Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 | Date : Sat Mar 13 04:53:30 2021 | Host : baby running 64-bit major release (build 9200) | Command : report_timing_summary -max_paths 10 -file ngFEC_top_timing_summary_routed.rpt -pb ngFEC_top_timing_summary_routed.pb -rpx ngFEC_top_timing_summary_routed.rpx -warn_on_violation | Design : ngFEC_top | Device : xcku115-flva2104 | Speed File : -1 PRODUCTION 1.26 12-04-2018 | Temperature Grade : C ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes check_timing report Table of Contents ----------------- 1. checking no_clock (0) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (0) 5. checking no_input_delay (35) 6. checking no_output_delay (28) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (0) 1. checking no_clock (0) ------------------------ There are 0 register/latch pins with no clock. 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (0) ------------------------------------------------ There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (35) ------------------------------- There are 35 input ports with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay (28) -------------------------------- There are 28 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (0) ---------------------------- There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 0.150 0.000 0 886738 0.024 0.000 0 886738 0.407 0.000 0 393787 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- DRPclk {0.000 10.000} 20.000 50.000 GBT_refclk0 {0.000 1.559} 3.119 320.616 gtwiz_userclk_rx_srcclk_out[0] {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_1 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_10 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_11 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_2 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_3 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_4 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_5 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_6 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_7 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_8 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_9 {0.000 4.159} 8.317 120.231 qpll0outclk_out[0] {0.000 0.097} 0.195 5129.849 qpll0outrefclk_out[0] {0.000 1.559} 3.119 320.616 txoutclk_out[0]_49 {0.000 1.559} 3.119 320.616 GBT_refclk1 {0.000 1.559} 3.119 320.616 gtwiz_userclk_rx_srcclk_out[0]_12 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_13 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_14 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_15 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_16 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_17 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_18 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_19 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_20 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_21 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_22 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_23 {0.000 4.159} 8.317 120.231 GBT_refclk2 {0.000 1.559} 3.119 320.616 gtwiz_userclk_rx_srcclk_out[0]_24 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_25 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_26 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_27 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_28 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_29 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_30 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_31 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_32 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_33 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_34 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_35 {0.000 4.159} 8.317 120.231 GBT_refclk3 {0.000 1.559} 3.119 320.616 gtwiz_userclk_rx_srcclk_out[0]_36 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_37 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_38 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_39 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_40 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_41 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_42 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_43 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_44 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_45 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_46 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_47 {0.000 4.159} 8.317 120.231 TTC_rx_refclk {0.000 1.559} 3.119 320.616 qpll1outclk_out[0] {0.000 0.097} 0.195 5129.849 rxoutclk_out[0]_1 {0.000 1.559} 3.119 320.616 qpll1outrefclk_out[0] {0.000 1.559} 3.119 320.616 TTC_rxusrclk {0.000 1.559} 3.119 320.616 fabric_clk_in {0.000 12.476} 24.952 40.077 CLKFBOUT {6.238 18.714} 24.952 40.077 fabric_clk_dcm {0.000 12.476} 24.952 40.077 tx_wordclk_dcm {0.000 4.159} 8.317 120.231 clk125 {0.000 4.000} 8.000 125.000 clk250 {0.000 2.000} 4.000 250.000 fabric_clk {0.000 12.476} 24.952 40.077 ipb_clk {0.000 16.000} 32.000 31.250 refclk125 {0.000 4.000} 8.000 125.000 DRPclk_dcm {0.000 10.000} 20.000 50.000 clk125_dcm {0.000 4.000} 8.000 125.000 clk250_dcm {0.000 2.000} 4.000 250.000 clk62_5_dcm {0.000 8.000} 16.000 62.500 ipb_clk_dcm {0.000 16.000} 32.000 31.250 rx_rcvclk {0.000 1.559} 3.119 320.616 tx_wordclk {0.000 4.159} 8.317 120.236 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- DRPclk 15.425 0.000 0 7776 0.030 0.000 0 7776 9.725 0.000 0 3888 gtwiz_userclk_rx_srcclk_out[0] 2.241 0.000 0 1308 0.031 0.000 0 1308 0.494 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_1 3.914 0.000 0 1308 0.042 0.000 0 1308 0.493 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_10 3.609 0.000 0 1308 0.036 0.000 0 1308 0.494 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_11 4.302 0.000 0 1308 0.033 0.000 0 1308 0.493 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_2 3.134 0.000 0 1308 0.035 0.000 0 1308 0.493 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_3 1.821 0.000 0 1308 0.031 0.000 0 1308 0.493 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_4 1.978 0.000 0 1308 0.039 0.000 0 1308 0.494 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_5 1.653 0.000 0 1308 0.036 0.000 0 1308 0.494 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_6 2.946 0.000 0 1308 0.034 0.000 0 1308 0.493 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_7 3.012 0.000 0 1308 0.033 0.000 0 1308 0.493 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_8 3.788 0.000 0 1308 0.037 0.000 0 1308 0.494 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_9 3.070 0.000 0 1308 0.037 0.000 0 1308 0.494 0.000 0 675 txoutclk_out[0]_49 0.656 0.000 0 1587 0.031 0.000 0 1587 0.407 0.000 0 540 gtwiz_userclk_rx_srcclk_out[0]_12 3.018 0.000 0 1308 0.034 0.000 0 1308 0.493 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_13 4.061 0.000 0 1308 0.031 0.000 0 1308 0.494 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_14 3.090 0.000 0 1307 0.035 0.000 0 1307 0.493 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_15 3.165 0.000 0 1307 0.043 0.000 0 1307 0.493 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_16 2.973 0.000 0 1307 0.030 0.000 0 1307 0.493 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_17 3.244 0.000 0 1308 0.035 0.000 0 1308 0.494 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_18 3.176 0.000 0 1308 0.030 0.000 0 1308 0.493 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_19 3.185 0.000 0 1307 0.039 0.000 0 1307 0.494 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_20 3.275 0.000 0 1308 0.045 0.000 0 1308 0.493 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_21 3.032 0.000 0 1307 0.038 0.000 0 1307 0.494 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_22 3.325 0.000 0 1308 0.041 0.000 0 1308 0.494 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_23 2.775 0.000 0 1308 0.036 0.000 0 1308 0.494 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_24 2.549 0.000 0 1308 0.035 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_25 3.157 0.000 0 1307 0.035 0.000 0 1307 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_26 3.276 0.000 0 1308 0.033 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_27 2.930 0.000 0 1308 0.031 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_28 4.215 0.000 0 1308 0.039 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_29 2.713 0.000 0 1308 0.036 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_30 2.431 0.000 0 1307 0.034 0.000 0 1307 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_31 3.220 0.000 0 1308 0.036 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_32 4.043 0.000 0 1308 0.042 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_33 2.793 0.000 0 1307 0.040 0.000 0 1307 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_34 3.873 0.000 0 1308 0.036 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_35 2.504 0.000 0 1308 0.033 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_36 3.184 0.000 0 1308 0.039 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_37 2.885 0.000 0 1308 0.036 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_38 2.468 0.000 0 1308 0.037 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_39 3.526 0.000 0 1308 0.034 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_40 3.965 0.000 0 1308 0.036 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_41 3.176 0.000 0 1308 0.033 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_42 3.224 0.000 0 1308 0.032 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_43 3.968 0.000 0 1308 0.035 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_44 2.774 0.000 0 1308 0.034 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_45 2.659 0.000 0 1308 0.034 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_46 3.024 0.000 0 1308 0.036 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_47 3.309 0.000 0 1308 0.031 0.000 0 1308 0.510 0.000 0 675 rxoutclk_out[0]_1 1.532 0.000 0 1 TTC_rxusrclk 0.160 0.000 0 3842 0.033 0.000 0 3842 0.407 0.000 0 1861 fabric_clk_in 17.640 0.000 0 862 0.045 0.000 0 862 6.238 0.000 0 792 CLKFBOUT 23.365 0.000 0 3 fabric_clk_dcm 23.365 0.000 0 2 tx_wordclk_dcm 6.730 0.000 0 2 clk125 1.074 0.000 0 8456 0.024 0.000 0 8456 2.200 0.000 0 3804 clk250 0.158 0.000 0 55713 0.042 0.000 0 55713 1.048 0.000 0 14395 fabric_clk 11.114 0.000 0 163569 0.030 0.000 0 163569 11.390 0.000 0 103803 ipb_clk 0.199 0.000 0 478451 0.030 0.000 0 478451 15.048 0.000 0 204776 refclk125 1.600 0.000 0 2 DRPclk_dcm 18.413 0.000 0 2 clk125_dcm 6.413 0.000 0 2 clk250_dcm 2.413 0.000 0 2 clk62_5_dcm 14.025 0.000 0 62 0.033 0.000 0 62 0.494 0.000 0 71 ipb_clk_dcm 30.413 0.000 0 2 tx_wordclk 0.181 0.000 0 54022 0.030 0.000 0 54022 0.495 0.000 0 27439 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ipb_clk clk250 0.900 0.000 0 34 0.055 0.000 0 34 clk250 ipb_clk 0.586 0.000 0 6912 0.030 0.000 0 6912 fabric_clk tx_wordclk 1.461 0.000 0 3937 0.030 0.000 0 3937 ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- **async_default** DRPclk DRPclk 15.473 0.000 0 240 0.222 0.000 0 240 **async_default** TTC_rxusrclk TTC_rxusrclk 0.150 0.000 0 1096 0.132 0.000 0 1096 **async_default** clk125 clk125 2.606 0.000 0 43 0.199 0.000 0 43 **async_default** fabric_clk fabric_clk 8.363 0.000 0 11472 0.136 0.000 0 11472 **async_default** gtwiz_userclk_rx_srcclk_out[0] gtwiz_userclk_rx_srcclk_out[0] 3.708 0.000 0 391 0.215 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 4.822 0.000 0 391 0.114 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_10 gtwiz_userclk_rx_srcclk_out[0]_10 5.268 0.000 0 391 0.136 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_11 gtwiz_userclk_rx_srcclk_out[0]_11 5.481 0.000 0 391 0.150 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_12 gtwiz_userclk_rx_srcclk_out[0]_12 4.590 0.000 0 391 0.138 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_13 gtwiz_userclk_rx_srcclk_out[0]_13 2.594 0.000 0 391 0.149 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_14 gtwiz_userclk_rx_srcclk_out[0]_14 4.428 0.000 0 391 0.227 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_15 gtwiz_userclk_rx_srcclk_out[0]_15 4.233 0.000 0 391 0.140 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_16 gtwiz_userclk_rx_srcclk_out[0]_16 4.940 0.000 0 391 0.177 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_17 gtwiz_userclk_rx_srcclk_out[0]_17 5.083 0.000 0 391 0.157 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_18 gtwiz_userclk_rx_srcclk_out[0]_18 4.426 0.000 0 391 0.137 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_19 gtwiz_userclk_rx_srcclk_out[0]_19 4.835 0.000 0 391 0.214 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 5.700 0.000 0 391 0.146 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_20 gtwiz_userclk_rx_srcclk_out[0]_20 4.552 0.000 0 391 0.113 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_21 gtwiz_userclk_rx_srcclk_out[0]_21 4.999 0.000 0 391 0.161 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_22 gtwiz_userclk_rx_srcclk_out[0]_22 5.126 0.000 0 391 0.206 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_23 gtwiz_userclk_rx_srcclk_out[0]_23 3.755 0.000 0 391 0.149 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_24 gtwiz_userclk_rx_srcclk_out[0]_24 3.383 0.000 0 391 0.142 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_25 gtwiz_userclk_rx_srcclk_out[0]_25 5.131 0.000 0 391 0.147 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_26 gtwiz_userclk_rx_srcclk_out[0]_26 4.278 0.000 0 391 0.141 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_27 gtwiz_userclk_rx_srcclk_out[0]_27 4.474 0.000 0 391 0.150 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_28 gtwiz_userclk_rx_srcclk_out[0]_28 6.277 0.000 0 391 0.141 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_29 gtwiz_userclk_rx_srcclk_out[0]_29 3.470 0.000 0 391 0.163 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 3.227 0.000 0 391 0.130 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_30 gtwiz_userclk_rx_srcclk_out[0]_30 3.477 0.000 0 391 0.112 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_31 gtwiz_userclk_rx_srcclk_out[0]_31 3.987 0.000 0 391 0.159 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_32 gtwiz_userclk_rx_srcclk_out[0]_32 5.181 0.000 0 391 0.116 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_33 gtwiz_userclk_rx_srcclk_out[0]_33 4.472 0.000 0 391 0.142 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_34 gtwiz_userclk_rx_srcclk_out[0]_34 4.906 0.000 0 391 0.115 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_35 gtwiz_userclk_rx_srcclk_out[0]_35 4.305 0.000 0 391 0.122 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_36 gtwiz_userclk_rx_srcclk_out[0]_36 3.370 0.000 0 391 0.100 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_37 gtwiz_userclk_rx_srcclk_out[0]_37 2.625 0.000 0 391 0.225 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_38 gtwiz_userclk_rx_srcclk_out[0]_38 1.785 0.000 0 391 0.153 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_39 gtwiz_userclk_rx_srcclk_out[0]_39 4.385 0.000 0 391 0.133 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 3.469 0.000 0 391 0.142 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_40 gtwiz_userclk_rx_srcclk_out[0]_40 5.554 0.000 0 391 0.146 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_41 gtwiz_userclk_rx_srcclk_out[0]_41 5.115 0.000 0 391 0.163 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_42 gtwiz_userclk_rx_srcclk_out[0]_42 4.363 0.000 0 391 0.093 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_43 gtwiz_userclk_rx_srcclk_out[0]_43 2.867 0.000 0 391 0.222 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_44 gtwiz_userclk_rx_srcclk_out[0]_44 2.878 0.000 0 391 0.096 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_45 gtwiz_userclk_rx_srcclk_out[0]_45 1.481 0.000 0 391 0.140 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_46 gtwiz_userclk_rx_srcclk_out[0]_46 2.839 0.000 0 391 0.136 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_47 gtwiz_userclk_rx_srcclk_out[0]_47 5.042 0.000 0 391 0.170 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 3.889 0.000 0 391 0.180 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 5.036 0.000 0 391 0.217 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 4.078 0.000 0 391 0.183 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 5.154 0.000 0 391 0.172 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 4.243 0.000 0 391 0.137 0.000 0 391 **async_default** ipb_clk ipb_clk 29.209 0.000 0 34 0.772 0.000 0 34 **async_default** tx_wordclk tx_wordclk 1.657 0.000 0 11044 0.117 0.000 0 11044 ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: DRPclk To Clock: DRPclk Setup : 0 Failing Endpoints, Worst Slack 15.425ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.030ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 9.725ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 15.425ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[23]/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[24]/CE (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 4.157ns (logic 0.333ns (8.011%) route 3.824ns (91.989%)) Logic Levels: 3 (LUT3=1 LUT5=1 LUT6=1) Clock Path Skew: -0.285ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.133ns = ( 23.133 - 20.000 ) Source Clock Delay (SCD): 3.549ns Clock Pessimism Removal (CPR): 0.131ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.549ns (routing 0.987ns, distribution 2.562ns) Clock Net Delay (Destination): 3.133ns (routing 0.904ns, distribution 2.229ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.549 3.549 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/DRPclk SLR Crossing[0->1] SLICE_X48Y539 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[23]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y539 FDRE (Prop_HFF_SLICEL_C_Q) 0.138 3.687 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[23]/Q net (fo=2, routed) 1.642 5.329 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[23] SLICE_X48Y540 LUT5 (Prop_G6LUT_SLICEL_I1_O) 0.089 5.418 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/tx_timer_sat_i_6__46/O net (fo=1, routed) 0.266 5.684 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/tx_timer_sat_i_6__46_n_0 SLICE_X49Y538 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.055 5.739 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/tx_timer_sat_i_2__46/O net (fo=3, routed) 0.327 6.066 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/tx_timer_sat_i_2__46_n_0 SLICE_X48Y540 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.051 6.117 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr[0]_i_1__46/O net (fo=25, routed) 1.589 7.706 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr SLICE_X48Y540 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[24]/CE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y114 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.133 23.133 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/DRPclk SLR Crossing[0->1] SLICE_X48Y540 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[24]/C clock pessimism 0.131 23.264 clock uncertainty -0.079 23.185 SLICE_X48Y540 FDRE (Setup_AFF_SLICEL_C_CE) -0.054 23.131 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[24] ------------------------------------------------------------------- required time 23.131 arrival time -7.706 ------------------------------------------------------------------- slack 15.425 Slack (MET) : 16.615ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/CE (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 3.169ns (logic 0.836ns (26.381%) route 2.333ns (73.619%)) Logic Levels: 3 (LUT3=1 LUT5=1 LUT6=1) Clock Path Skew: -0.082ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.020ns = ( 23.020 - 20.000 ) Source Clock Delay (SCD): 3.473ns Clock Pessimism Removal (CPR): 0.371ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.473ns (routing 0.987ns, distribution 2.486ns) Clock Net Delay (Destination): 3.020ns (routing 0.904ns, distribution 2.116ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.473 3.473 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk SLICE_X57Y180 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y180 FDCE (Prop_DFF_SLICEL_C_Q) 0.139 3.612 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/Q net (fo=2, routed) 0.291 3.903 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3] SLICE_X58Y182 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.244 4.147 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/O net (fo=1, routed) 0.463 4.610 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27_n_0 SLICE_X56Y182 LUT6 (Prop_H6LUT_SLICEL_I4_O) 0.218 4.828 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/O net (fo=2, routed) 0.579 5.407 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24_n_0 SLICE_X57Y183 LUT5 (Prop_E6LUT_SLICEL_I1_O) 0.235 5.642 r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/O net (fo=26, routed) 1.000 6.642 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27_n_0 SLICE_X57Y181 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/CE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y114 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.020 23.020 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk SLICE_X57Y181 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/C clock pessimism 0.371 23.391 clock uncertainty -0.079 23.312 SLICE_X57Y181 FDCE (Setup_EFF_SLICEL_C_CE) -0.055 23.257 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12] ------------------------------------------------------------------- required time 23.257 arrival time -6.642 ------------------------------------------------------------------- slack 16.615 Slack (MET) : 16.615ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[13]/CE (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 3.169ns (logic 0.836ns (26.381%) route 2.333ns (73.619%)) Logic Levels: 3 (LUT3=1 LUT5=1 LUT6=1) Clock Path Skew: -0.082ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.020ns = ( 23.020 - 20.000 ) Source Clock Delay (SCD): 3.473ns Clock Pessimism Removal (CPR): 0.371ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.473ns (routing 0.987ns, distribution 2.486ns) Clock Net Delay (Destination): 3.020ns (routing 0.904ns, distribution 2.116ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.473 3.473 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk SLICE_X57Y180 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y180 FDCE (Prop_DFF_SLICEL_C_Q) 0.139 3.612 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/Q net (fo=2, routed) 0.291 3.903 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3] SLICE_X58Y182 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.244 4.147 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/O net (fo=1, routed) 0.463 4.610 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27_n_0 SLICE_X56Y182 LUT6 (Prop_H6LUT_SLICEL_I4_O) 0.218 4.828 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/O net (fo=2, routed) 0.579 5.407 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24_n_0 SLICE_X57Y183 LUT5 (Prop_E6LUT_SLICEL_I1_O) 0.235 5.642 r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/O net (fo=26, routed) 1.000 6.642 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27_n_0 SLICE_X57Y181 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[13]/CE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y114 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.020 23.020 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk SLICE_X57Y181 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[13]/C clock pessimism 0.371 23.391 clock uncertainty -0.079 23.312 SLICE_X57Y181 FDCE (Setup_FFF_SLICEL_C_CE) -0.055 23.257 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[13] ------------------------------------------------------------------- required time 23.257 arrival time -6.642 ------------------------------------------------------------------- slack 16.615 Slack (MET) : 16.615ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[14]/CE (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 3.169ns (logic 0.836ns (26.381%) route 2.333ns (73.619%)) Logic Levels: 3 (LUT3=1 LUT5=1 LUT6=1) Clock Path Skew: -0.082ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.020ns = ( 23.020 - 20.000 ) Source Clock Delay (SCD): 3.473ns Clock Pessimism Removal (CPR): 0.371ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.473ns (routing 0.987ns, distribution 2.486ns) Clock Net Delay (Destination): 3.020ns (routing 0.904ns, distribution 2.116ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.473 3.473 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk SLICE_X57Y180 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y180 FDCE (Prop_DFF_SLICEL_C_Q) 0.139 3.612 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/Q net (fo=2, routed) 0.291 3.903 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3] SLICE_X58Y182 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.244 4.147 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/O net (fo=1, routed) 0.463 4.610 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27_n_0 SLICE_X56Y182 LUT6 (Prop_H6LUT_SLICEL_I4_O) 0.218 4.828 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/O net (fo=2, routed) 0.579 5.407 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24_n_0 SLICE_X57Y183 LUT5 (Prop_E6LUT_SLICEL_I1_O) 0.235 5.642 r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/O net (fo=26, routed) 1.000 6.642 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27_n_0 SLICE_X57Y181 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[14]/CE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y114 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.020 23.020 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk SLICE_X57Y181 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[14]/C clock pessimism 0.371 23.391 clock uncertainty -0.079 23.312 SLICE_X57Y181 FDCE (Setup_GFF_SLICEL_C_CE) -0.055 23.257 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[14] ------------------------------------------------------------------- required time 23.257 arrival time -6.642 ------------------------------------------------------------------- slack 16.615 Slack (MET) : 16.615ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[15]/CE (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 3.169ns (logic 0.836ns (26.381%) route 2.333ns (73.619%)) Logic Levels: 3 (LUT3=1 LUT5=1 LUT6=1) Clock Path Skew: -0.082ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.020ns = ( 23.020 - 20.000 ) Source Clock Delay (SCD): 3.473ns Clock Pessimism Removal (CPR): 0.371ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.473ns (routing 0.987ns, distribution 2.486ns) Clock Net Delay (Destination): 3.020ns (routing 0.904ns, distribution 2.116ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.473 3.473 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk SLICE_X57Y180 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y180 FDCE (Prop_DFF_SLICEL_C_Q) 0.139 3.612 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/Q net (fo=2, routed) 0.291 3.903 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3] SLICE_X58Y182 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.244 4.147 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/O net (fo=1, routed) 0.463 4.610 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27_n_0 SLICE_X56Y182 LUT6 (Prop_H6LUT_SLICEL_I4_O) 0.218 4.828 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/O net (fo=2, routed) 0.579 5.407 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24_n_0 SLICE_X57Y183 LUT5 (Prop_E6LUT_SLICEL_I1_O) 0.235 5.642 r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/O net (fo=26, routed) 1.000 6.642 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27_n_0 SLICE_X57Y181 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[15]/CE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y114 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.020 23.020 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk SLICE_X57Y181 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[15]/C clock pessimism 0.371 23.391 clock uncertainty -0.079 23.312 SLICE_X57Y181 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 23.257 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[15] ------------------------------------------------------------------- required time 23.257 arrival time -6.642 ------------------------------------------------------------------- slack 16.615 Slack (MET) : 16.622ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/CE (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 3.165ns (logic 0.836ns (26.414%) route 2.329ns (73.586%)) Logic Levels: 3 (LUT3=1 LUT5=1 LUT6=1) Clock Path Skew: -0.080ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.022ns = ( 23.022 - 20.000 ) Source Clock Delay (SCD): 3.473ns Clock Pessimism Removal (CPR): 0.371ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.473ns (routing 0.987ns, distribution 2.486ns) Clock Net Delay (Destination): 3.022ns (routing 0.904ns, distribution 2.118ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.473 3.473 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk SLICE_X57Y180 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y180 FDCE (Prop_DFF_SLICEL_C_Q) 0.139 3.612 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/Q net (fo=2, routed) 0.291 3.903 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3] SLICE_X58Y182 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.244 4.147 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/O net (fo=1, routed) 0.463 4.610 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27_n_0 SLICE_X56Y182 LUT6 (Prop_H6LUT_SLICEL_I4_O) 0.218 4.828 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/O net (fo=2, routed) 0.579 5.407 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24_n_0 SLICE_X57Y183 LUT5 (Prop_E6LUT_SLICEL_I1_O) 0.235 5.642 r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/O net (fo=26, routed) 0.996 6.638 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27_n_0 SLICE_X57Y181 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/CE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y114 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.022 23.022 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk SLICE_X57Y181 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/C clock pessimism 0.371 23.393 clock uncertainty -0.079 23.314 SLICE_X57Y181 FDCE (Setup_CFF_SLICEL_C_CE) -0.054 23.260 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10] ------------------------------------------------------------------- required time 23.260 arrival time -6.638 ------------------------------------------------------------------- slack 16.622 Slack (MET) : 16.622ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/CE (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 3.165ns (logic 0.836ns (26.414%) route 2.329ns (73.586%)) Logic Levels: 3 (LUT3=1 LUT5=1 LUT6=1) Clock Path Skew: -0.080ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.022ns = ( 23.022 - 20.000 ) Source Clock Delay (SCD): 3.473ns Clock Pessimism Removal (CPR): 0.371ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.473ns (routing 0.987ns, distribution 2.486ns) Clock Net Delay (Destination): 3.022ns (routing 0.904ns, distribution 2.118ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.473 3.473 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk SLICE_X57Y180 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y180 FDCE (Prop_DFF_SLICEL_C_Q) 0.139 3.612 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/Q net (fo=2, routed) 0.291 3.903 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3] SLICE_X58Y182 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.244 4.147 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/O net (fo=1, routed) 0.463 4.610 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27_n_0 SLICE_X56Y182 LUT6 (Prop_H6LUT_SLICEL_I4_O) 0.218 4.828 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/O net (fo=2, routed) 0.579 5.407 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24_n_0 SLICE_X57Y183 LUT5 (Prop_E6LUT_SLICEL_I1_O) 0.235 5.642 r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/O net (fo=26, routed) 0.996 6.638 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27_n_0 SLICE_X57Y181 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/CE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y114 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.022 23.022 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk SLICE_X57Y181 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/C clock pessimism 0.371 23.393 clock uncertainty -0.079 23.314 SLICE_X57Y181 FDCE (Setup_DFF_SLICEL_C_CE) -0.054 23.260 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11] ------------------------------------------------------------------- required time 23.260 arrival time -6.638 ------------------------------------------------------------------- slack 16.622 Slack (MET) : 16.622ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]/CE (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 3.165ns (logic 0.836ns (26.414%) route 2.329ns (73.586%)) Logic Levels: 3 (LUT3=1 LUT5=1 LUT6=1) Clock Path Skew: -0.080ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.022ns = ( 23.022 - 20.000 ) Source Clock Delay (SCD): 3.473ns Clock Pessimism Removal (CPR): 0.371ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.473ns (routing 0.987ns, distribution 2.486ns) Clock Net Delay (Destination): 3.022ns (routing 0.904ns, distribution 2.118ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.473 3.473 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk SLICE_X57Y180 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y180 FDCE (Prop_DFF_SLICEL_C_Q) 0.139 3.612 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/Q net (fo=2, routed) 0.291 3.903 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3] SLICE_X58Y182 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.244 4.147 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/O net (fo=1, routed) 0.463 4.610 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27_n_0 SLICE_X56Y182 LUT6 (Prop_H6LUT_SLICEL_I4_O) 0.218 4.828 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/O net (fo=2, routed) 0.579 5.407 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24_n_0 SLICE_X57Y183 LUT5 (Prop_E6LUT_SLICEL_I1_O) 0.235 5.642 r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/O net (fo=26, routed) 0.996 6.638 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27_n_0 SLICE_X57Y181 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]/CE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y114 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.022 23.022 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk SLICE_X57Y181 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]/C clock pessimism 0.371 23.393 clock uncertainty -0.079 23.314 SLICE_X57Y181 FDCE (Setup_AFF_SLICEL_C_CE) -0.054 23.260 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8] ------------------------------------------------------------------- required time 23.260 arrival time -6.638 ------------------------------------------------------------------- slack 16.622 Slack (MET) : 16.622ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[9]/CE (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 3.165ns (logic 0.836ns (26.414%) route 2.329ns (73.586%)) Logic Levels: 3 (LUT3=1 LUT5=1 LUT6=1) Clock Path Skew: -0.080ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.022ns = ( 23.022 - 20.000 ) Source Clock Delay (SCD): 3.473ns Clock Pessimism Removal (CPR): 0.371ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.473ns (routing 0.987ns, distribution 2.486ns) Clock Net Delay (Destination): 3.022ns (routing 0.904ns, distribution 2.118ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.473 3.473 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk SLICE_X57Y180 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y180 FDCE (Prop_DFF_SLICEL_C_Q) 0.139 3.612 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/Q net (fo=2, routed) 0.291 3.903 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3] SLICE_X58Y182 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.244 4.147 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/O net (fo=1, routed) 0.463 4.610 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27_n_0 SLICE_X56Y182 LUT6 (Prop_H6LUT_SLICEL_I4_O) 0.218 4.828 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/O net (fo=2, routed) 0.579 5.407 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24_n_0 SLICE_X57Y183 LUT5 (Prop_E6LUT_SLICEL_I1_O) 0.235 5.642 r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/O net (fo=26, routed) 0.996 6.638 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27_n_0 SLICE_X57Y181 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[9]/CE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y114 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.022 23.022 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk SLICE_X57Y181 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[9]/C clock pessimism 0.371 23.393 clock uncertainty -0.079 23.314 SLICE_X57Y181 FDCE (Setup_BFF_SLICEL_C_CE) -0.054 23.260 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[9] ------------------------------------------------------------------- required time 23.260 arrival time -6.638 ------------------------------------------------------------------- slack 16.622 Slack (MET) : 16.631ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/CE (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 3.234ns (logic 0.836ns (25.850%) route 2.398ns (74.150%)) Logic Levels: 3 (LUT3=1 LUT5=1 LUT6=1) Clock Path Skew: -0.002ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.022ns = ( 23.022 - 20.000 ) Source Clock Delay (SCD): 3.473ns Clock Pessimism Removal (CPR): 0.449ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.473ns (routing 0.987ns, distribution 2.486ns) Clock Net Delay (Destination): 3.022ns (routing 0.904ns, distribution 2.118ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.473 3.473 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk SLICE_X57Y180 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y180 FDCE (Prop_DFF_SLICEL_C_Q) 0.139 3.612 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/Q net (fo=2, routed) 0.291 3.903 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3] SLICE_X58Y182 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.244 4.147 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/O net (fo=1, routed) 0.463 4.610 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27_n_0 SLICE_X56Y182 LUT6 (Prop_H6LUT_SLICEL_I4_O) 0.218 4.828 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/O net (fo=2, routed) 0.579 5.407 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24_n_0 SLICE_X57Y183 LUT5 (Prop_E6LUT_SLICEL_I1_O) 0.235 5.642 r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/O net (fo=26, routed) 1.065 6.707 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27_n_0 SLICE_X57Y180 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y114 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.022 23.022 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk SLICE_X57Y180 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/C clock pessimism 0.449 23.471 clock uncertainty -0.079 23.392 SLICE_X57Y180 FDCE (Setup_AFF_SLICEL_C_CE) -0.054 23.338 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0] ------------------------------------------------------------------- required time 23.338 arrival time -6.707 ------------------------------------------------------------------- slack 16.631 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.030ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[5]/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[24]/D (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.235ns (logic 0.172ns (73.191%) route 0.063ns (26.809%)) Logic Levels: 4 (CARRY8=4) Clock Path Skew: 0.149ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.544ns Source Clock Delay (SCD): 1.326ns Clock Pessimism Removal (CPR): 0.069ns Clock Net Delay (Source): 1.326ns (routing 0.371ns, distribution 0.955ns) Clock Net Delay (Destination): 1.544ns (routing 0.412ns, distribution 1.132ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.326 1.326 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/DRPclk SLR Crossing[0->1] SLICE_X48Y537 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y537 FDRE (Prop_FFF_SLICEL_C_Q) 0.049 1.375 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[5]/Q net (fo=2, routed) 0.053 1.428 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[5] SLICE_X48Y537 CARRY8 (Prop_CARRY8_SLICEL_S[5]_CO[7]) 0.057 1.485 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[0]_i_2__46/CO[7] net (fo=1, routed) 0.000 1.485 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[0]_i_2__46_n_0 SLICE_X48Y538 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) 0.016 1.501 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[8]_i_1__46/CO[7] net (fo=1, routed) 0.000 1.501 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[8]_i_1__46_n_0 SLICE_X48Y539 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) 0.016 1.517 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[16]_i_1__46/CO[7] net (fo=1, routed) 0.000 1.517 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[16]_i_1__46_n_0 SLICE_X48Y540 CARRY8 (Prop_CARRY8_SLICEL_CI_O[0]) 0.034 1.551 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[24]_i_1__46/O[0] net (fo=1, routed) 0.010 1.561 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[24]_i_1__46_n_15 SLICE_X48Y540 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[24]/D ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.544 1.544 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/DRPclk SLR Crossing[0->1] SLICE_X48Y540 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[24]/C clock pessimism -0.069 1.475 SLICE_X48Y540 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.531 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[24] ------------------------------------------------------------------- required time -1.531 arrival time 1.561 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.032ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[3]/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[24]/D (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.250ns (logic 0.190ns (76.000%) route 0.060ns (24.000%)) Logic Levels: 4 (CARRY8=4) Clock Path Skew: 0.162ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.612ns Source Clock Delay (SCD): 1.381ns Clock Pessimism Removal (CPR): 0.069ns Clock Net Delay (Source): 1.381ns (routing 0.371ns, distribution 1.010ns) Clock Net Delay (Destination): 1.612ns (routing 0.412ns, distribution 1.200ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.381 1.381 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/DRPclk SLR Crossing[0->1] SLICE_X116Y537 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X116Y537 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.430 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[3]/Q net (fo=2, routed) 0.050 1.480 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[3] SLICE_X116Y537 CARRY8 (Prop_CARRY8_SLICEL_S[3]_CO[7]) 0.075 1.555 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[0]_i_2__20/CO[7] net (fo=1, routed) 0.000 1.555 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[0]_i_2__20_n_0 SLICE_X116Y538 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) 0.016 1.571 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[8]_i_1__20/CO[7] net (fo=1, routed) 0.000 1.571 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[8]_i_1__20_n_0 SLICE_X116Y539 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) 0.016 1.587 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[16]_i_1__20/CO[7] net (fo=1, routed) 0.000 1.587 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[16]_i_1__20_n_0 SLICE_X116Y540 CARRY8 (Prop_CARRY8_SLICEL_CI_O[0]) 0.034 1.621 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[24]_i_1__20/O[0] net (fo=1, routed) 0.010 1.631 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[24]_i_1__20_n_15 SLICE_X116Y540 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[24]/D ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.612 1.612 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/DRPclk SLR Crossing[0->1] SLICE_X116Y540 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[24]/C clock pessimism -0.069 1.543 SLICE_X116Y540 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.599 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[24] ------------------------------------------------------------------- required time -1.599 arrival time 1.631 ------------------------------------------------------------------- slack 0.032 Slack (MET) : 0.033ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/D (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.224ns (logic 0.164ns (73.214%) route 0.060ns (26.786%)) Logic Levels: 3 (CARRY8=3) Clock Path Skew: 0.135ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.505ns Source Clock Delay (SCD): 1.313ns Clock Pessimism Removal (CPR): 0.057ns Clock Net Delay (Source): 1.313ns (routing 0.371ns, distribution 0.942ns) Clock Net Delay (Destination): 1.505ns (routing 0.412ns, distribution 1.093ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.313 1.313 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk SLICE_X99Y118 FDCE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X99Y118 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 1.362 r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/Q net (fo=2, routed) 0.050 1.412 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11] SLICE_X99Y118 CARRY8 (Prop_CARRY8_SLICEL_S[3]_CO[7]) 0.065 1.477 r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__3/CO[7] net (fo=1, routed) 0.000 1.477 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__3_n_0 SLICE_X99Y119 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) 0.016 1.493 r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]_i_1__3/CO[7] net (fo=1, routed) 0.000 1.493 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]_i_1__3_n_0 SLICE_X99Y120 CARRY8 (Prop_CARRY8_SLICEL_CI_O[0]) 0.034 1.527 r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]_i_1__3/O[0] net (fo=1, routed) 0.010 1.537 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]_i_1__3_n_15 SLICE_X99Y120 FDCE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/D ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.505 1.505 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk SLICE_X99Y120 FDCE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/C clock pessimism -0.057 1.448 SLICE_X99Y120 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.504 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24] ------------------------------------------------------------------- required time -1.504 arrival time 1.537 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.033ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]/D (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.238ns (logic 0.194ns (81.513%) route 0.044ns (18.487%)) Logic Levels: 3 (CARRY8=2 LUT1=1) Clock Path Skew: 0.149ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.446ns Source Clock Delay (SCD): 1.249ns Clock Pessimism Removal (CPR): 0.048ns Clock Net Delay (Source): 1.249ns (routing 0.371ns, distribution 0.878ns) Clock Net Delay (Destination): 1.446ns (routing 0.412ns, distribution 1.034ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.249 1.249 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/DRPclk SLICE_X58Y179 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X58Y179 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.298 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/Q net (fo=2, routed) 0.033 1.331 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0] SLICE_X58Y179 LUT1 (Prop_A6LUT_SLICEM_I0_O) 0.015 1.346 r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_5__24/O net (fo=1, routed) 0.001 1.347 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_5__24_n_0 SLICE_X58Y179 CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[7]) 0.096 1.443 r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]_i_2__24/CO[7] net (fo=1, routed) 0.000 1.443 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]_i_2__24_n_0 SLICE_X58Y180 CARRY8 (Prop_CARRY8_SLICEM_CI_O[0]) 0.034 1.477 r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__24/O[0] net (fo=1, routed) 0.010 1.487 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__24_n_15 SLICE_X58Y180 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]/D ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.446 1.446 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/DRPclk SLICE_X58Y180 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]/C clock pessimism -0.048 1.398 SLICE_X58Y180 FDCE (Hold_AFF_SLICEM_C_D) 0.056 1.454 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8] ------------------------------------------------------------------- required time -1.454 arrival time 1.487 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.034ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[25]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genReset_s_reg/D (rising edge-triggered cell FDPE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.256ns (logic 0.113ns (44.141%) route 0.143ns (55.859%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.166ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.672ns Source Clock Delay (SCD): 1.446ns Clock Pessimism Removal (CPR): 0.060ns Clock Net Delay (Source): 1.446ns (routing 0.371ns, distribution 1.075ns) Clock Net Delay (Destination): 1.672ns (routing 0.412ns, distribution 1.260ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.446 1.446 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/DRPclk SLR Crossing[0->1] SLICE_X44Y480 FDCE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[25]/C ------------------------------------------------------------------- ------------------- SLICE_X44Y480 FDCE (Prop_BFF_SLICEM_C_Q) 0.049 1.495 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[25]/Q net (fo=3, routed) 0.127 1.622 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[25] SLICE_X45Y479 LUT6 (Prop_D6LUT_SLICEL_I5_O) 0.064 1.686 r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genReset_s_i_1__41/O net (fo=1, routed) 0.016 1.702 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genReset_s_i_1__41_n_0 SLICE_X45Y479 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genReset_s_reg/D ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.672 1.672 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/DRPclk SLR Crossing[0->1] SLICE_X45Y479 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genReset_s_reg/C clock pessimism -0.060 1.612 SLICE_X45Y479 FDPE (Hold_DFF_SLICEL_C_D) 0.056 1.668 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genReset_s_reg ------------------------------------------------------------------- required time -1.668 arrival time 1.702 ------------------------------------------------------------------- slack 0.034 Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genReset_s_reg/D (rising edge-triggered cell FDPE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.164ns (logic 0.065ns (39.634%) route 0.099ns (60.366%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.441ns Source Clock Delay (SCD): 1.231ns Clock Pessimism Removal (CPR): 0.138ns Clock Net Delay (Source): 1.231ns (routing 0.371ns, distribution 0.860ns) Clock Net Delay (Destination): 1.441ns (routing 0.412ns, distribution 1.029ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.231 1.231 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/DRPclk SLICE_X51Y264 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y264 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.280 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/Q net (fo=3, routed) 0.083 1.363 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24] SLICE_X52Y263 LUT6 (Prop_H6LUT_SLICEM_I4_O) 0.016 1.379 r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genReset_s_i_1__32/O net (fo=1, routed) 0.016 1.395 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genReset_s_i_1__32_n_0 SLICE_X52Y263 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genReset_s_reg/D ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.441 1.441 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/DRPclk SLICE_X52Y263 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genReset_s_reg/C clock pessimism -0.138 1.303 SLICE_X52Y263 FDPE (Hold_HFF_SLICEM_C_D) 0.056 1.359 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genReset_s_reg ------------------------------------------------------------------- required time -1.359 arrival time 1.395 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/D (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.246ns (logic 0.198ns (80.488%) route 0.048ns (19.512%)) Logic Levels: 3 (CARRY8=2 LUT1=1) Clock Path Skew: 0.149ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.446ns Source Clock Delay (SCD): 1.249ns Clock Pessimism Removal (CPR): 0.048ns Clock Net Delay (Source): 1.249ns (routing 0.371ns, distribution 0.878ns) Clock Net Delay (Destination): 1.446ns (routing 0.412ns, distribution 1.034ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.249 1.249 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/DRPclk SLICE_X58Y179 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X58Y179 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.298 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/Q net (fo=2, routed) 0.033 1.331 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0] SLICE_X58Y179 LUT1 (Prop_A6LUT_SLICEM_I0_O) 0.015 1.346 r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_5__24/O net (fo=1, routed) 0.001 1.347 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_5__24_n_0 SLICE_X58Y179 CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[7]) 0.096 1.443 r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]_i_2__24/CO[7] net (fo=1, routed) 0.000 1.443 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]_i_2__24_n_0 SLICE_X58Y180 CARRY8 (Prop_CARRY8_SLICEM_CI_O[2]) 0.038 1.481 r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__24/O[2] net (fo=1, routed) 0.014 1.495 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__24_n_13 SLICE_X58Y180 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/D ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.446 1.446 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/DRPclk SLICE_X58Y180 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/C clock pessimism -0.048 1.398 SLICE_X58Y180 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.454 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10] ------------------------------------------------------------------- required time -1.454 arrival time 1.495 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C (rising edge-triggered cell FDPE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/D (rising edge-triggered cell FDPE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.171ns (logic 0.048ns (28.070%) route 0.123ns (71.930%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.510ns Source Clock Delay (SCD): 1.296ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 1.296ns (routing 0.371ns, distribution 0.925ns) Clock Net Delay (Destination): 1.510ns (routing 0.412ns, distribution 1.098ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.296 1.296 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X112Y198 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C ------------------------------------------------------------------- ------------------- SLICE_X112Y198 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.344 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/Q net (fo=1, routed) 0.123 1.467 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3 SLICE_X110Y198 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/D ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.510 1.510 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X110Y198 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C clock pessimism -0.142 1.368 SLICE_X110Y198 FDPE (Hold_AFF_SLICEM_C_D) 0.056 1.424 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg ------------------------------------------------------------------- required time -1.424 arrival time 1.467 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/D (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.272ns (logic 0.209ns (76.838%) route 0.063ns (23.162%)) Logic Levels: 4 (CARRY8=4) Clock Path Skew: 0.172ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.667ns Source Clock Delay (SCD): 1.435ns Clock Pessimism Removal (CPR): 0.060ns Clock Net Delay (Source): 1.435ns (routing 0.371ns, distribution 1.064ns) Clock Net Delay (Destination): 1.667ns (routing 0.412ns, distribution 1.255ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.435 1.435 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/DRPclk SLR Crossing[0->1] SLICE_X44Y477 FDCE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X44Y477 FDCE (Prop_BFF_SLICEM_C_Q) 0.049 1.484 r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1]/Q net (fo=2, routed) 0.053 1.537 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1] SLICE_X44Y477 CARRY8 (Prop_CARRY8_SLICEM_S[1]_CO[7]) 0.094 1.631 r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]_i_2__41/CO[7] net (fo=1, routed) 0.000 1.631 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]_i_2__41_n_0 SLICE_X44Y478 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.016 1.647 r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__41/CO[7] net (fo=1, routed) 0.000 1.647 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__41_n_0 SLICE_X44Y479 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.016 1.663 r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]_i_1__41/CO[7] net (fo=1, routed) 0.000 1.663 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]_i_1__41_n_0 SLICE_X44Y480 CARRY8 (Prop_CARRY8_SLICEM_CI_O[0]) 0.034 1.697 r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]_i_1__41/O[0] net (fo=1, routed) 0.010 1.707 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]_i_1__41_n_15 SLICE_X44Y480 FDCE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/D ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.667 1.667 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/DRPclk SLR Crossing[0->1] SLICE_X44Y480 FDCE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/C clock pessimism -0.060 1.607 SLICE_X44Y480 FDCE (Hold_AFF_SLICEM_C_D) 0.056 1.663 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24] ------------------------------------------------------------------- required time -1.663 arrival time 1.707 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genReset_s_reg/D (rising edge-triggered cell FDPE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.171ns (logic 0.078ns (45.614%) route 0.093ns (54.386%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.599ns Source Clock Delay (SCD): 1.391ns Clock Pessimism Removal (CPR): 0.138ns Clock Net Delay (Source): 1.391ns (routing 0.371ns, distribution 1.020ns) Clock Net Delay (Destination): 1.599ns (routing 0.412ns, distribution 1.187ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.391 1.391 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/DRPclk SLR Crossing[0->1] SLICE_X112Y542 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y542 FDCE (Prop_CFF_SLICEM_C_Q) 0.048 1.439 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/Q net (fo=3, routed) 0.077 1.516 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18] SLICE_X111Y542 LUT6 (Prop_D6LUT_SLICEL_I1_O) 0.030 1.546 r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genReset_s_i_1__19/O net (fo=1, routed) 0.016 1.562 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genReset_s_i_1__19_n_0 SLICE_X111Y542 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genReset_s_reg/D ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.599 1.599 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/DRPclk SLR Crossing[0->1] SLICE_X111Y542 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genReset_s_reg/C clock pessimism -0.138 1.461 SLICE_X111Y542 FDPE (Hold_DFF_SLICEL_C_D) 0.056 1.517 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genReset_s_reg ------------------------------------------------------------------- required time -1.517 arrival time 1.562 ------------------------------------------------------------------- slack 0.045 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: DRPclk Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { i_DRPclk_bufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a FDPE/C n/a 0.550 20.000 19.450 SLICE_X67Y71 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genReset_s_reg/C Min Period n/a FDCE/C n/a 0.550 20.000 19.450 SLICE_X68Y68 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/C Min Period n/a FDCE/C n/a 0.550 20.000 19.450 SLICE_X68Y69 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/C Min Period n/a FDCE/C n/a 0.550 20.000 19.450 SLICE_X68Y69 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/C Min Period n/a FDCE/C n/a 0.550 20.000 19.450 SLICE_X68Y69 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/C Min Period n/a FDCE/C n/a 0.550 20.000 19.450 SLICE_X68Y69 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[13]/C Min Period n/a FDCE/C n/a 0.550 20.000 19.450 SLICE_X68Y69 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[14]/C Min Period n/a FDCE/C n/a 0.550 20.000 19.450 SLICE_X68Y69 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[15]/C Min Period n/a FDCE/C n/a 0.550 20.000 19.450 SLICE_X68Y70 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]/C Min Period n/a FDCE/C n/a 0.550 20.000 19.450 SLICE_X68Y70 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[17]/C Low Pulse Width Fast FDCE/C n/a 0.275 10.000 9.725 SLICE_X68Y68 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/C Low Pulse Width Fast FDCE/C n/a 0.275 10.000 9.725 SLICE_X68Y69 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/C Low Pulse Width Fast FDCE/C n/a 0.275 10.000 9.725 SLICE_X68Y69 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/C Low Pulse Width Slow FDCE/C n/a 0.275 10.000 9.725 SLICE_X68Y69 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/C Low Pulse Width Slow FDCE/C n/a 0.275 10.000 9.725 SLICE_X68Y69 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[13]/C Low Pulse Width Slow FDCE/C n/a 0.275 10.000 9.725 SLICE_X68Y69 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[14]/C Low Pulse Width Slow FDCE/C n/a 0.275 10.000 9.725 SLICE_X68Y69 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[15]/C Low Pulse Width Fast FDCE/C n/a 0.275 10.000 9.725 SLICE_X68Y70 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]/C Low Pulse Width Fast FDCE/C n/a 0.275 10.000 9.725 SLICE_X68Y70 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[17]/C Low Pulse Width Fast FDCE/C n/a 0.275 10.000 9.725 SLICE_X68Y70 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/C High Pulse Width Slow FDCE/C n/a 0.275 10.000 9.725 SLICE_X68Y69 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/C High Pulse Width Slow FDCE/C n/a 0.275 10.000 9.725 SLICE_X68Y69 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/C High Pulse Width Slow FDCE/C n/a 0.275 10.000 9.725 SLICE_X68Y70 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]/C High Pulse Width Slow FDCE/C n/a 0.275 10.000 9.725 SLICE_X68Y70 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[17]/C High Pulse Width Slow FDCE/C n/a 0.275 10.000 9.725 SLICE_X68Y70 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/C High Pulse Width Slow FDCE/C n/a 0.275 10.000 9.725 SLICE_X68Y70 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[19]/C High Pulse Width Slow FDCE/C n/a 0.275 10.000 9.725 SLICE_X68Y71 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/C High Pulse Width Slow FDCE/C n/a 0.275 10.000 9.725 SLICE_X68Y71 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[25]/C High Pulse Width Slow FDCE/C n/a 0.275 10.000 9.725 SLICE_X68Y69 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]/C High Pulse Width Slow FDCE/C n/a 0.275 10.000 9.725 SLICE_X68Y69 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[9]/C --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0] To Clock: gtwiz_userclk_rx_srcclk_out[0] Setup : 0 Failing Endpoints, Worst Slack 2.241ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.031ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.241ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 5.427ns (logic 1.559ns (28.727%) route 3.868ns (71.273%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.559ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.067ns = ( 11.384 - 8.317 ) Source Clock Delay (SCD): 3.914ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.439ns (routing 1.460ns, distribution 1.979ns) Clock Net Delay (Destination): 2.669ns (routing 1.334ns, distribution 1.335ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.439 3.914 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 5.000 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.084 8.084 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] SLICE_X87Y65 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.092 8.176 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/O net (fo=5, routed) 0.207 8.383 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X86Y65 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.235 8.618 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7/O net (fo=1, routed) 0.073 8.691 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7_n_0 SLICE_X86Y65 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.146 8.837 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1/O net (fo=2, routed) 0.504 9.341 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1_n_0 SLICE_X86Y65 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.669 11.384 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y65 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.288 11.672 clock uncertainty -0.035 11.637 SLICE_X86Y65 FDCE (Setup_GFF_SLICEL_C_CE) -0.055 11.582 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.582 arrival time -9.341 ------------------------------------------------------------------- slack 2.241 Slack (MET) : 2.241ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 5.427ns (logic 1.559ns (28.727%) route 3.868ns (71.273%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.559ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.067ns = ( 11.384 - 8.317 ) Source Clock Delay (SCD): 3.914ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.439ns (routing 1.460ns, distribution 1.979ns) Clock Net Delay (Destination): 2.669ns (routing 1.334ns, distribution 1.335ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.439 3.914 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 5.000 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.084 8.084 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] SLICE_X87Y65 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.092 8.176 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/O net (fo=5, routed) 0.207 8.383 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X86Y65 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.235 8.618 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7/O net (fo=1, routed) 0.073 8.691 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7_n_0 SLICE_X86Y65 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.146 8.837 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1/O net (fo=2, routed) 0.504 9.341 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1_n_0 SLICE_X86Y65 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.669 11.384 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y65 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.288 11.672 clock uncertainty -0.035 11.637 SLICE_X86Y65 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 11.582 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.582 arrival time -9.341 ------------------------------------------------------------------- slack 2.241 Slack (MET) : 2.516ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[0].rx_data_ngccm_reg[0][70]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 4.934ns (logic 0.305ns (6.182%) route 4.629ns (93.818%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.774ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.043ns = ( 11.360 - 8.317 ) Source Clock Delay (SCD): 4.020ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.545ns (routing 1.460ns, distribution 2.085ns) Clock Net Delay (Destination): 2.645ns (routing 1.334ns, distribution 1.311ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.545 4.020 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X130Y71 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y71 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.159 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.984 7.143 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X84Y68 LUT6 (Prop_B6LUT_SLICEL_I0_O) 0.166 7.309 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[0].rx_data_ngccm[0][83]_i_1/O net (fo=76, routed) 1.645 8.954 rx_data_ngccm[0] SLICE_X73Y58 FDCE r SFP_GEN[0].rx_data_ngccm_reg[0][70]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.645 11.360 RX_WORDCLK_O[0] SLICE_X73Y58 FDCE r SFP_GEN[0].rx_data_ngccm_reg[0][70]/C clock pessimism 0.203 11.563 clock uncertainty -0.035 11.528 SLICE_X73Y58 FDCE (Setup_EFF2_SLICEM_C_CE) -0.058 11.470 SFP_GEN[0].rx_data_ngccm_reg[0][70] ------------------------------------------------------------------- required time 11.470 arrival time -8.954 ------------------------------------------------------------------- slack 2.516 Slack (MET) : 2.522ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[0].rx_data_ngccm_reg[0][68]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 4.931ns (logic 0.305ns (6.185%) route 4.626ns (93.815%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.774ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.043ns = ( 11.360 - 8.317 ) Source Clock Delay (SCD): 4.020ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.545ns (routing 1.460ns, distribution 2.085ns) Clock Net Delay (Destination): 2.645ns (routing 1.334ns, distribution 1.311ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.545 4.020 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X130Y71 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y71 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.159 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.984 7.143 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X84Y68 LUT6 (Prop_B6LUT_SLICEL_I0_O) 0.166 7.309 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[0].rx_data_ngccm[0][83]_i_1/O net (fo=76, routed) 1.642 8.951 rx_data_ngccm[0] SLICE_X73Y58 FDCE r SFP_GEN[0].rx_data_ngccm_reg[0][68]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.645 11.360 RX_WORDCLK_O[0] SLICE_X73Y58 FDCE r SFP_GEN[0].rx_data_ngccm_reg[0][68]/C clock pessimism 0.203 11.563 clock uncertainty -0.035 11.528 SLICE_X73Y58 FDCE (Setup_EFF_SLICEM_C_CE) -0.055 11.473 SFP_GEN[0].rx_data_ngccm_reg[0][68] ------------------------------------------------------------------- required time 11.473 arrival time -8.951 ------------------------------------------------------------------- slack 2.522 Slack (MET) : 2.522ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[0].rx_data_ngccm_reg[0][71]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 4.931ns (logic 0.305ns (6.185%) route 4.626ns (93.815%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.774ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.043ns = ( 11.360 - 8.317 ) Source Clock Delay (SCD): 4.020ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.545ns (routing 1.460ns, distribution 2.085ns) Clock Net Delay (Destination): 2.645ns (routing 1.334ns, distribution 1.311ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.545 4.020 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X130Y71 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y71 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.159 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.984 7.143 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X84Y68 LUT6 (Prop_B6LUT_SLICEL_I0_O) 0.166 7.309 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[0].rx_data_ngccm[0][83]_i_1/O net (fo=76, routed) 1.642 8.951 rx_data_ngccm[0] SLICE_X73Y58 FDCE r SFP_GEN[0].rx_data_ngccm_reg[0][71]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.645 11.360 RX_WORDCLK_O[0] SLICE_X73Y58 FDCE r SFP_GEN[0].rx_data_ngccm_reg[0][71]/C clock pessimism 0.203 11.563 clock uncertainty -0.035 11.528 SLICE_X73Y58 FDCE (Setup_FFF_SLICEM_C_CE) -0.055 11.473 SFP_GEN[0].rx_data_ngccm_reg[0][71] ------------------------------------------------------------------- required time 11.473 arrival time -8.951 ------------------------------------------------------------------- slack 2.522 Slack (MET) : 2.541ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 5.099ns (logic 1.324ns (25.966%) route 3.775ns (74.034%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.584ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.042ns = ( 11.359 - 8.317 ) Source Clock Delay (SCD): 3.914ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.439ns (routing 1.460ns, distribution 1.979ns) Clock Net Delay (Destination): 2.644ns (routing 1.334ns, distribution 1.310ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.439 3.914 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 5.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.084 8.084 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] SLICE_X87Y65 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.092 8.176 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/O net (fo=5, routed) 0.261 8.437 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X86Y66 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.146 8.583 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__0/O net (fo=5, routed) 0.430 9.013 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 SLICE_X86Y67 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.644 11.359 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y67 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.288 11.647 clock uncertainty -0.035 11.612 SLICE_X86Y67 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 11.554 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.554 arrival time -9.013 ------------------------------------------------------------------- slack 2.541 Slack (MET) : 2.541ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 5.099ns (logic 1.324ns (25.966%) route 3.775ns (74.034%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.584ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.042ns = ( 11.359 - 8.317 ) Source Clock Delay (SCD): 3.914ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.439ns (routing 1.460ns, distribution 1.979ns) Clock Net Delay (Destination): 2.644ns (routing 1.334ns, distribution 1.310ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.439 3.914 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 5.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.084 8.084 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] SLICE_X87Y65 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.092 8.176 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/O net (fo=5, routed) 0.261 8.437 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X86Y66 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.146 8.583 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__0/O net (fo=5, routed) 0.430 9.013 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 SLICE_X86Y67 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.644 11.359 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y67 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.288 11.647 clock uncertainty -0.035 11.612 SLICE_X86Y67 FDRE (Setup_GFF2_SLICEL_C_CE) -0.058 11.554 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 11.554 arrival time -9.013 ------------------------------------------------------------------- slack 2.541 Slack (MET) : 2.548ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 5.095ns (logic 1.324ns (25.986%) route 3.771ns (74.014%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.584ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.042ns = ( 11.359 - 8.317 ) Source Clock Delay (SCD): 3.914ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.439ns (routing 1.460ns, distribution 1.979ns) Clock Net Delay (Destination): 2.644ns (routing 1.334ns, distribution 1.310ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.439 3.914 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 5.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.084 8.084 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] SLICE_X87Y65 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.092 8.176 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/O net (fo=5, routed) 0.261 8.437 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X86Y66 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.146 8.583 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__0/O net (fo=5, routed) 0.426 9.009 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 SLICE_X86Y67 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.644 11.359 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y67 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C clock pessimism 0.288 11.647 clock uncertainty -0.035 11.612 SLICE_X86Y67 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 11.557 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0] ------------------------------------------------------------------- required time 11.557 arrival time -9.009 ------------------------------------------------------------------- slack 2.548 Slack (MET) : 2.548ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 5.095ns (logic 1.324ns (25.986%) route 3.771ns (74.014%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.584ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.042ns = ( 11.359 - 8.317 ) Source Clock Delay (SCD): 3.914ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.439ns (routing 1.460ns, distribution 1.979ns) Clock Net Delay (Destination): 2.644ns (routing 1.334ns, distribution 1.310ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.439 3.914 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 5.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.084 8.084 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] SLICE_X87Y65 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.092 8.176 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/O net (fo=5, routed) 0.261 8.437 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X86Y66 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.146 8.583 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__0/O net (fo=5, routed) 0.426 9.009 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 SLICE_X86Y67 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.644 11.359 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y67 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C clock pessimism 0.288 11.647 clock uncertainty -0.035 11.612 SLICE_X86Y67 FDRE (Setup_GFF_SLICEL_C_CE) -0.055 11.557 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2] ------------------------------------------------------------------- required time 11.557 arrival time -9.009 ------------------------------------------------------------------- slack 2.548 Slack (MET) : 2.548ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 5.095ns (logic 1.324ns (25.986%) route 3.771ns (74.014%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.584ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.042ns = ( 11.359 - 8.317 ) Source Clock Delay (SCD): 3.914ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.439ns (routing 1.460ns, distribution 1.979ns) Clock Net Delay (Destination): 2.644ns (routing 1.334ns, distribution 1.310ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.439 3.914 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 5.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.084 8.084 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] SLICE_X87Y65 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.092 8.176 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/O net (fo=5, routed) 0.261 8.437 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X86Y66 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.146 8.583 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__0/O net (fo=5, routed) 0.426 9.009 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 SLICE_X86Y67 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.644 11.359 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y67 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism 0.288 11.647 clock uncertainty -0.035 11.612 SLICE_X86Y67 FDRE (Setup_FFF_SLICEL_C_CE) -0.055 11.557 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time 11.557 arrival time -9.009 ------------------------------------------------------------------- slack 2.548 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.031ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[0].rx_data_ngccm_reg[0][70]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.155ns (logic 0.048ns (30.968%) route 0.107ns (69.032%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.519ns Source Clock Delay (SCD): 1.284ns Clock Pessimism Removal (CPR): 0.166ns Clock Net Delay (Source): 1.166ns (routing 0.610ns, distribution 0.556ns) Clock Net Delay (Destination): 1.354ns (routing 0.687ns, distribution 0.667ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.166 1.284 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X71Y58 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X71Y58 FDRE (Prop_BFF2_SLICEM_C_Q) 0.048 1.332 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/Q net (fo=1, routed) 0.107 1.439 rx_data[0][70] SLICE_X73Y58 FDCE r SFP_GEN[0].rx_data_ngccm_reg[0][70]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.354 1.519 RX_WORDCLK_O[0] SLICE_X73Y58 FDCE r SFP_GEN[0].rx_data_ngccm_reg[0][70]/C clock pessimism -0.166 1.353 SLICE_X73Y58 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.408 SFP_GEN[0].rx_data_ngccm_reg[0][70] ------------------------------------------------------------------- required time -1.408 arrival time 1.439 ------------------------------------------------------------------- slack 0.031 Slack (MET) : 0.033ns (arrival time - required time) Source: SFP_GEN[0].rx_data_ngccm_reg[0][77]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[76]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.233ns (logic 0.103ns (44.206%) route 0.130ns (55.794%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.144ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.551ns Source Clock Delay (SCD): 1.283ns Clock Pessimism Removal (CPR): 0.124ns Clock Net Delay (Source): 1.165ns (routing 0.610ns, distribution 0.555ns) Clock Net Delay (Destination): 1.386ns (routing 0.687ns, distribution 0.699ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.165 1.283 RX_WORDCLK_O[0] SLICE_X72Y59 FDCE r SFP_GEN[0].rx_data_ngccm_reg[0][77]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y59 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 1.332 r SFP_GEN[0].rx_data_ngccm_reg[0][77]/Q net (fo=1, routed) 0.114 1.446 SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[83]_0[69] SLICE_X73Y60 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.054 1.500 r SFP_GEN[0].ngCCM_gbt/RX_Word_rx40[76]_i_1/O net (fo=1, routed) 0.016 1.516 SFP_GEN[0].ngCCM_gbt/RX_Word_rx40[76]_i_1_n_0 SLICE_X73Y60 FDCE r SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[76]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.386 1.551 SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X73Y60 FDCE r SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[76]/C clock pessimism -0.124 1.427 SLICE_X73Y60 FDCE (Hold_HFF_SLICEM_C_D) 0.056 1.483 SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[76] ------------------------------------------------------------------- required time -1.483 arrival time 1.516 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.038ns (arrival time - required time) Source: SFP_GEN[0].rx_data_ngccm_reg[0][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[2]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.199ns (logic 0.086ns (43.216%) route 0.113ns (56.784%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.105ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.554ns Source Clock Delay (SCD): 1.281ns Clock Pessimism Removal (CPR): 0.168ns Clock Net Delay (Source): 1.163ns (routing 0.610ns, distribution 0.553ns) Clock Net Delay (Destination): 1.389ns (routing 0.687ns, distribution 0.702ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.163 1.281 RX_WORDCLK_O[0] SLICE_X81Y64 FDCE r SFP_GEN[0].rx_data_ngccm_reg[0][3]/C ------------------------------------------------------------------- ------------------- SLICE_X81Y64 FDCE (Prop_EFF2_SLICEL_C_Q) 0.048 1.329 r SFP_GEN[0].rx_data_ngccm_reg[0][3]/Q net (fo=1, routed) 0.102 1.431 SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[83]_0[3] SLICE_X80Y65 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.038 1.469 r SFP_GEN[0].ngCCM_gbt/RX_Word_rx40[2]_i_1/O net (fo=1, routed) 0.011 1.480 SFP_GEN[0].ngCCM_gbt/RX_Word_rx40[2]_i_1_n_0 SLICE_X80Y65 FDCE r SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[2]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.389 1.554 SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y65 FDCE r SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[2]/C clock pessimism -0.168 1.386 SLICE_X80Y65 FDCE (Hold_DFF2_SLICEL_C_D) 0.056 1.442 SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[2] ------------------------------------------------------------------- required time -1.442 arrival time 1.480 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.186ns (logic 0.094ns (50.538%) route 0.092ns (49.462%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.540ns Source Clock Delay (SCD): 1.283ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 1.165ns (routing 0.610ns, distribution 0.555ns) Clock Net Delay (Destination): 1.375ns (routing 0.687ns, distribution 0.688ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.165 1.283 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X85Y64 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X85Y64 FDCE (Prop_AFF2_SLICEM_C_Q) 0.049 1.332 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Q net (fo=2, routed) 0.078 1.410 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_25_in SLICE_X84Y64 LUT3 (Prop_G6LUT_SLICEL_I0_O) 0.045 1.455 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1/O net (fo=1, routed) 0.014 1.469 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[13] SLICE_X84Y64 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.375 1.540 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X84Y64 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C clock pessimism -0.169 1.371 SLICE_X84Y64 FDRE (Hold_GFF_SLICEL_C_D) 0.056 1.427 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13] ------------------------------------------------------------------- required time -1.427 arrival time 1.469 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.045ns (arrival time - required time) Source: SFP_GEN[0].rx_data_ngccm_reg[0][79]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[78]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.177ns (logic 0.089ns (50.282%) route 0.088ns (49.718%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.551ns Source Clock Delay (SCD): 1.307ns Clock Pessimism Removal (CPR): 0.168ns Clock Net Delay (Source): 1.189ns (routing 0.610ns, distribution 0.579ns) Clock Net Delay (Destination): 1.386ns (routing 0.687ns, distribution 0.699ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.189 1.307 RX_WORDCLK_O[0] SLICE_X72Y60 FDCE r SFP_GEN[0].rx_data_ngccm_reg[0][79]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y60 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.356 r SFP_GEN[0].rx_data_ngccm_reg[0][79]/Q net (fo=1, routed) 0.076 1.432 SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[83]_0[71] SLICE_X73Y60 LUT3 (Prop_H5LUT_SLICEM_I0_O) 0.040 1.472 r SFP_GEN[0].ngCCM_gbt/RX_Word_rx40[78]_i_1/O net (fo=1, routed) 0.012 1.484 SFP_GEN[0].ngCCM_gbt/RX_Word_rx40[78]_i_1_n_0 SLICE_X73Y60 FDCE r SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[78]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.386 1.551 SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X73Y60 FDCE r SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[78]/C clock pessimism -0.168 1.383 SLICE_X73Y60 FDCE (Hold_HFF2_SLICEM_C_D) 0.056 1.439 SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[78] ------------------------------------------------------------------- required time -1.439 arrival time 1.484 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.143ns (logic 0.094ns (65.734%) route 0.049ns (34.266%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.544ns Source Clock Delay (SCD): 1.290ns Clock Pessimism Removal (CPR): 0.213ns Clock Net Delay (Source): 1.172ns (routing 0.610ns, distribution 0.562ns) Clock Net Delay (Destination): 1.379ns (routing 0.687ns, distribution 0.692ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.172 1.290 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X83Y64 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X83Y64 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.339 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.037 1.376 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/feedbackRegister[0] SLICE_X83Y64 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.045 1.421 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1/O net (fo=1, routed) 0.012 1.433 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[0] SLICE_X83Y64 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.379 1.544 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X83Y64 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C clock pessimism -0.213 1.331 SLICE_X83Y64 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.387 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19] ------------------------------------------------------------------- required time -1.387 arrival time 1.433 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.145ns (logic 0.094ns (64.828%) route 0.051ns (35.172%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.539ns Source Clock Delay (SCD): 1.286ns Clock Pessimism Removal (CPR): 0.212ns Clock Net Delay (Source): 1.168ns (routing 0.610ns, distribution 0.558ns) Clock Net Delay (Destination): 1.374ns (routing 0.687ns, distribution 0.687ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.168 1.286 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X85Y65 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X85Y65 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.335 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Q net (fo=2, routed) 0.035 1.370 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_3_in SLICE_X85Y65 LUT3 (Prop_C6LUT_SLICEM_I2_O) 0.045 1.415 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1/O net (fo=1, routed) 0.016 1.431 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[0] SLICE_X85Y65 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.374 1.539 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X85Y65 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.212 1.327 SLICE_X85Y65 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.383 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -1.383 arrival time 1.431 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: SFP_GEN[0].ngccm_status_reg_reg[0][23]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[0].ngccm_status_reg_reg[0][23]/D (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.109ns (logic 0.064ns (58.716%) route 0.045ns (41.284%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.534ns Source Clock Delay (SCD): 1.287ns Clock Pessimism Removal (CPR): 0.242ns Clock Net Delay (Source): 1.169ns (routing 0.610ns, distribution 0.559ns) Clock Net Delay (Destination): 1.369ns (routing 0.687ns, distribution 0.682ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.169 1.287 RX_WORDCLK_O[0] SLICE_X83Y118 FDPE r SFP_GEN[0].ngccm_status_reg_reg[0][23]/C ------------------------------------------------------------------- ------------------- SLICE_X83Y118 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.336 r SFP_GEN[0].ngccm_status_reg_reg[0][23]/Q net (fo=2, routed) 0.033 1.369 SFP_GEN[0].ngCCM_gbt/SFP_GEN[0].ngccm_status_reg_reg[0][24]_0[7] SLICE_X83Y118 LUT2 (Prop_A6LUT_SLICEM_I0_O) 0.015 1.384 r SFP_GEN[0].ngCCM_gbt/SFP_GEN[0].ngccm_status_reg[0][23]_i_1/O net (fo=1, routed) 0.012 1.396 p_3_out[23] SLICE_X83Y118 FDPE r SFP_GEN[0].ngccm_status_reg_reg[0][23]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.369 1.534 RX_WORDCLK_O[0] SLICE_X83Y118 FDPE r SFP_GEN[0].ngccm_status_reg_reg[0][23]/C clock pessimism -0.242 1.292 SLICE_X83Y118 FDPE (Hold_AFF_SLICEM_C_D) 0.056 1.348 SFP_GEN[0].ngccm_status_reg_reg[0][23] ------------------------------------------------------------------- required time -1.348 arrival time 1.396 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.147ns (logic 0.064ns (43.537%) route 0.083ns (56.463%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.558ns Source Clock Delay (SCD): 1.313ns Clock Pessimism Removal (CPR): 0.204ns Clock Net Delay (Source): 1.195ns (routing 0.610ns, distribution 0.585ns) Clock Net Delay (Destination): 1.393ns (routing 0.687ns, distribution 0.706ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.195 1.313 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X72Y63 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y63 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 1.362 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.069 1.431 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/O84[0] SLICE_X71Y62 LUT3 (Prop_G6LUT_SLICEM_I2_O) 0.015 1.446 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1/O net (fo=1, routed) 0.014 1.460 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] SLICE_X71Y62 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.393 1.558 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X71Y62 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.204 1.354 SLICE_X71Y62 FDRE (Hold_GFF_SLICEM_C_D) 0.056 1.410 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.410 arrival time 1.460 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.111ns (logic 0.064ns (57.658%) route 0.047ns (42.342%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.526ns Source Clock Delay (SCD): 1.279ns Clock Pessimism Removal (CPR): 0.242ns Clock Net Delay (Source): 1.161ns (routing 0.610ns, distribution 0.551ns) Clock Net Delay (Destination): 1.361ns (routing 0.687ns, distribution 0.674ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.161 1.279 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y68 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y68 FDRE (Prop_AFF_SLICEL_C_Q) 0.049 1.328 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]/Q net (fo=2, routed) 0.035 1.363 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/timer[5] SLICE_X88Y68 LUT6 (Prop_A6LUT_SLICEL_I0_O) 0.015 1.378 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__0/O net (fo=1, routed) 0.012 1.390 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__0_n_0 SLICE_X88Y68 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.361 1.526 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y68 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C clock pessimism -0.242 1.284 SLICE_X88Y68 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.340 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5] ------------------------------------------------------------------- required time -1.340 arrival time 1.390 ------------------------------------------------------------------- slack 0.050 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0] Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y43 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y65 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X60Y65 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X82Y67 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X82Y67 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X82Y67 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y66 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X72Y65 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y73 SFP_GEN[0].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X53Y65 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X53Y65 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X60Y65 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X82Y67 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X82Y67 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X60Y65 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X60Y65 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[48]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X60Y65 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[50]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X62Y66 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[66]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X60Y65 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[68]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X60Y64 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[70]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_1 To Clock: gtwiz_userclk_rx_srcclk_out[0]_1 Setup : 0 Failing Endpoints, Worst Slack 3.914ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.042ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.493ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.914ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 4.308ns (logic 1.649ns (38.278%) route 2.659ns (61.722%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.006ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.339ns = ( 10.656 - 8.317 ) Source Clock Delay (SCD): 2.575ns Clock Pessimism Removal (CPR): 0.230ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.100ns (routing 0.632ns, distribution 1.468ns) Clock Net Delay (Destination): 1.941ns (routing 0.573ns, distribution 1.368ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.100 2.575 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.659 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.903 5.562 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X123Y223 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.146 5.708 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/O net (fo=5, routed) 0.280 5.988 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X122Y224 LUT4 (Prop_B5LUT_SLICEL_I2_O) 0.272 6.260 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__9/O net (fo=1, routed) 0.142 6.402 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__9_n_0 SLICE_X122Y224 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 6.549 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__9/O net (fo=2, routed) 0.334 6.883 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__9_n_0 SLICE_X122Y222 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.941 10.656 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X122Y222 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.230 10.887 clock uncertainty -0.035 10.851 SLICE_X122Y222 FDCE (Setup_AFF_SLICEL_C_CE) -0.054 10.797 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.797 arrival time -6.883 ------------------------------------------------------------------- slack 3.914 Slack (MET) : 3.914ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 4.308ns (logic 1.649ns (38.278%) route 2.659ns (61.722%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.006ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.339ns = ( 10.656 - 8.317 ) Source Clock Delay (SCD): 2.575ns Clock Pessimism Removal (CPR): 0.230ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.100ns (routing 0.632ns, distribution 1.468ns) Clock Net Delay (Destination): 1.941ns (routing 0.573ns, distribution 1.368ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.100 2.575 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.659 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.903 5.562 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X123Y223 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.146 5.708 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/O net (fo=5, routed) 0.280 5.988 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X122Y224 LUT4 (Prop_B5LUT_SLICEL_I2_O) 0.272 6.260 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__9/O net (fo=1, routed) 0.142 6.402 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__9_n_0 SLICE_X122Y224 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 6.549 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__9/O net (fo=2, routed) 0.334 6.883 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__9_n_0 SLICE_X122Y222 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.941 10.656 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X122Y222 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.230 10.887 clock uncertainty -0.035 10.851 SLICE_X122Y222 FDCE (Setup_BFF_SLICEL_C_CE) -0.054 10.797 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.797 arrival time -6.883 ------------------------------------------------------------------- slack 3.914 Slack (MET) : 4.066ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[10].rx_data_ngccm_reg[10][77]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 3.828ns (logic 0.286ns (7.471%) route 3.542ns (92.529%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.333ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.221ns = ( 10.538 - 8.317 ) Source Clock Delay (SCD): 2.766ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.291ns (routing 0.632ns, distribution 1.659ns) Clock Net Delay (Destination): 1.823ns (routing 0.573ns, distribution 1.250ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.291 2.766 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X140Y214 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X140Y214 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.906 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.959 4.865 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X117Y222 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.146 5.011 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/SFP_GEN[10].rx_data_ngccm[10][83]_i_1/O net (fo=76, routed) 1.583 6.594 rx_data_ngccm[10] SLICE_X110Y204 FDCE r SFP_GEN[10].rx_data_ngccm_reg[10][77]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.823 10.538 RX_WORDCLK_O[10] SLICE_X110Y204 FDCE r SFP_GEN[10].rx_data_ngccm_reg[10][77]/C clock pessimism 0.212 10.750 clock uncertainty -0.035 10.715 SLICE_X110Y204 FDCE (Setup_EFF_SLICEM_C_CE) -0.055 10.660 SFP_GEN[10].rx_data_ngccm_reg[10][77] ------------------------------------------------------------------- required time 10.660 arrival time -6.594 ------------------------------------------------------------------- slack 4.066 Slack (MET) : 4.178ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 4.040ns (logic 1.320ns (32.673%) route 2.720ns (67.327%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.006ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.339ns = ( 10.656 - 8.317 ) Source Clock Delay (SCD): 2.575ns Clock Pessimism Removal (CPR): 0.230ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.100ns (routing 0.632ns, distribution 1.468ns) Clock Net Delay (Destination): 1.941ns (routing 0.573ns, distribution 1.368ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.100 2.575 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.659 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.903 5.562 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X123Y223 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.146 5.708 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/O net (fo=5, routed) 0.387 6.095 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X122Y223 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.090 6.185 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__10/O net (fo=3, routed) 0.430 6.615 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecFalseHeaders0 SLICE_X122Y224 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.941 10.656 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X122Y224 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.230 10.887 clock uncertainty -0.035 10.851 SLICE_X122Y224 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 10.793 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 10.793 arrival time -6.615 ------------------------------------------------------------------- slack 4.178 Slack (MET) : 4.185ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 4.036ns (logic 1.320ns (32.706%) route 2.716ns (67.294%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.006ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.339ns = ( 10.656 - 8.317 ) Source Clock Delay (SCD): 2.575ns Clock Pessimism Removal (CPR): 0.230ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.100ns (routing 0.632ns, distribution 1.468ns) Clock Net Delay (Destination): 1.941ns (routing 0.573ns, distribution 1.368ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.100 2.575 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.659 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.903 5.562 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X123Y223 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.146 5.708 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/O net (fo=5, routed) 0.387 6.095 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X122Y223 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.090 6.185 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__10/O net (fo=3, routed) 0.426 6.611 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecFalseHeaders0 SLICE_X122Y224 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.941 10.656 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X122Y224 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.230 10.887 clock uncertainty -0.035 10.851 SLICE_X122Y224 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 10.796 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 10.796 arrival time -6.611 ------------------------------------------------------------------- slack 4.185 Slack (MET) : 4.185ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 4.036ns (logic 1.320ns (32.706%) route 2.716ns (67.294%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.006ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.339ns = ( 10.656 - 8.317 ) Source Clock Delay (SCD): 2.575ns Clock Pessimism Removal (CPR): 0.230ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.100ns (routing 0.632ns, distribution 1.468ns) Clock Net Delay (Destination): 1.941ns (routing 0.573ns, distribution 1.368ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.100 2.575 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.659 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.903 5.562 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X123Y223 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.146 5.708 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/O net (fo=5, routed) 0.387 6.095 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X122Y223 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.090 6.185 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__10/O net (fo=3, routed) 0.426 6.611 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecFalseHeaders0 SLICE_X122Y224 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.941 10.656 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X122Y224 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C clock pessimism 0.230 10.887 clock uncertainty -0.035 10.851 SLICE_X122Y224 FDRE (Setup_EFF_SLICEL_C_CE) -0.055 10.796 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2] ------------------------------------------------------------------- required time 10.796 arrival time -6.611 ------------------------------------------------------------------- slack 4.185 Slack (MET) : 4.202ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[10].rx_data_ngccm_reg[10][69]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 3.691ns (logic 0.286ns (7.749%) route 3.405ns (92.251%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.331ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.223ns = ( 10.540 - 8.317 ) Source Clock Delay (SCD): 2.766ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.291ns (routing 0.632ns, distribution 1.659ns) Clock Net Delay (Destination): 1.825ns (routing 0.573ns, distribution 1.252ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.291 2.766 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X140Y214 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X140Y214 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.906 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.959 4.865 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X117Y222 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.146 5.011 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/SFP_GEN[10].rx_data_ngccm[10][83]_i_1/O net (fo=76, routed) 1.446 6.457 rx_data_ngccm[10] SLICE_X114Y204 FDCE r SFP_GEN[10].rx_data_ngccm_reg[10][69]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.825 10.540 RX_WORDCLK_O[10] SLICE_X114Y204 FDCE r SFP_GEN[10].rx_data_ngccm_reg[10][69]/C clock pessimism 0.212 10.752 clock uncertainty -0.035 10.717 SLICE_X114Y204 FDCE (Setup_EFF2_SLICEL_C_CE) -0.058 10.659 SFP_GEN[10].rx_data_ngccm_reg[10][69] ------------------------------------------------------------------- required time 10.659 arrival time -6.457 ------------------------------------------------------------------- slack 4.202 Slack (MET) : 4.202ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[10].rx_data_ngccm_reg[10][71]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 3.691ns (logic 0.286ns (7.749%) route 3.405ns (92.251%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.331ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.223ns = ( 10.540 - 8.317 ) Source Clock Delay (SCD): 2.766ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.291ns (routing 0.632ns, distribution 1.659ns) Clock Net Delay (Destination): 1.825ns (routing 0.573ns, distribution 1.252ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.291 2.766 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X140Y214 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X140Y214 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.906 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.959 4.865 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X117Y222 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.146 5.011 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/SFP_GEN[10].rx_data_ngccm[10][83]_i_1/O net (fo=76, routed) 1.446 6.457 rx_data_ngccm[10] SLICE_X114Y204 FDCE r SFP_GEN[10].rx_data_ngccm_reg[10][71]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.825 10.540 RX_WORDCLK_O[10] SLICE_X114Y204 FDCE r SFP_GEN[10].rx_data_ngccm_reg[10][71]/C clock pessimism 0.212 10.752 clock uncertainty -0.035 10.717 SLICE_X114Y204 FDCE (Setup_FFF2_SLICEL_C_CE) -0.058 10.659 SFP_GEN[10].rx_data_ngccm_reg[10][71] ------------------------------------------------------------------- required time 10.659 arrival time -6.457 ------------------------------------------------------------------- slack 4.202 Slack (MET) : 4.202ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[10].rx_data_ngccm_reg[10][73]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 3.691ns (logic 0.286ns (7.749%) route 3.405ns (92.251%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.331ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.223ns = ( 10.540 - 8.317 ) Source Clock Delay (SCD): 2.766ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.291ns (routing 0.632ns, distribution 1.659ns) Clock Net Delay (Destination): 1.825ns (routing 0.573ns, distribution 1.252ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.291 2.766 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X140Y214 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X140Y214 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.906 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.959 4.865 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X117Y222 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.146 5.011 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/SFP_GEN[10].rx_data_ngccm[10][83]_i_1/O net (fo=76, routed) 1.446 6.457 rx_data_ngccm[10] SLICE_X114Y204 FDCE r SFP_GEN[10].rx_data_ngccm_reg[10][73]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.825 10.540 RX_WORDCLK_O[10] SLICE_X114Y204 FDCE r SFP_GEN[10].rx_data_ngccm_reg[10][73]/C clock pessimism 0.212 10.752 clock uncertainty -0.035 10.717 SLICE_X114Y204 FDCE (Setup_GFF2_SLICEL_C_CE) -0.058 10.659 SFP_GEN[10].rx_data_ngccm_reg[10][73] ------------------------------------------------------------------- required time 10.659 arrival time -6.457 ------------------------------------------------------------------- slack 4.202 Slack (MET) : 4.202ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[10].rx_data_ngccm_reg[10][75]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 3.691ns (logic 0.286ns (7.749%) route 3.405ns (92.251%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.331ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.223ns = ( 10.540 - 8.317 ) Source Clock Delay (SCD): 2.766ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.291ns (routing 0.632ns, distribution 1.659ns) Clock Net Delay (Destination): 1.825ns (routing 0.573ns, distribution 1.252ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.291 2.766 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X140Y214 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X140Y214 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.906 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.959 4.865 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X117Y222 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.146 5.011 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/SFP_GEN[10].rx_data_ngccm[10][83]_i_1/O net (fo=76, routed) 1.446 6.457 rx_data_ngccm[10] SLICE_X114Y204 FDCE r SFP_GEN[10].rx_data_ngccm_reg[10][75]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.825 10.540 RX_WORDCLK_O[10] SLICE_X114Y204 FDCE r SFP_GEN[10].rx_data_ngccm_reg[10][75]/C clock pessimism 0.212 10.752 clock uncertainty -0.035 10.717 SLICE_X114Y204 FDCE (Setup_HFF2_SLICEL_C_CE) -0.058 10.659 SFP_GEN[10].rx_data_ngccm_reg[10][75] ------------------------------------------------------------------- required time 10.659 arrival time -6.457 ------------------------------------------------------------------- slack 4.202 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[10].rx_data_ngccm_reg[10][4]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.049ns (34.028%) route 0.095ns (65.972%)) Logic Levels: 0 Clock Path Skew: 0.046ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.097ns Source Clock Delay (SCD): 0.891ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.773ns (routing 0.275ns, distribution 0.498ns) Clock Net Delay (Destination): 0.932ns (routing 0.312ns, distribution 0.620ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.773 0.891 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X114Y213 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X114Y213 FDRE (Prop_FFF_SLICEL_C_Q) 0.049 0.940 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/Q net (fo=1, routed) 0.095 1.035 rx_data[10][4] SLICE_X114Y212 FDCE r SFP_GEN[10].rx_data_ngccm_reg[10][4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.932 1.097 RX_WORDCLK_O[10] SLICE_X114Y212 FDCE r SFP_GEN[10].rx_data_ngccm_reg[10][4]/C clock pessimism -0.160 0.937 SLICE_X114Y212 FDCE (Hold_BFF2_SLICEL_C_D) 0.056 0.993 SFP_GEN[10].rx_data_ngccm_reg[10][4] ------------------------------------------------------------------- required time -0.993 arrival time 1.035 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.094ns (64.828%) route 0.051ns (35.172%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.112ns Source Clock Delay (SCD): 0.902ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 0.784ns (routing 0.275ns, distribution 0.509ns) Clock Net Delay (Destination): 0.947ns (routing 0.312ns, distribution 0.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.784 0.902 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X113Y217 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y217 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 0.951 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Q net (fo=2, routed) 0.035 0.986 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_29_in SLICE_X113Y217 LUT3 (Prop_C6LUT_SLICEM_I2_O) 0.045 1.031 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__9/O net (fo=1, routed) 0.016 1.047 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[13] SLICE_X113Y217 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.947 1.112 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X113Y217 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C clock pessimism -0.169 0.943 SLICE_X113Y217 FDRE (Hold_CFF_SLICEM_C_D) 0.056 0.999 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13] ------------------------------------------------------------------- required time -0.999 arrival time 1.047 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.141ns (logic 0.094ns (66.667%) route 0.047ns (33.333%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.096ns Source Clock Delay (SCD): 0.893ns Clock Pessimism Removal (CPR): 0.168ns Clock Net Delay (Source): 0.775ns (routing 0.275ns, distribution 0.500ns) Clock Net Delay (Destination): 0.931ns (routing 0.312ns, distribution 0.619ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.775 0.893 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X114Y213 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X114Y213 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 0.942 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Q net (fo=2, routed) 0.035 0.977 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_11_in SLICE_X114Y213 LUT3 (Prop_F6LUT_SLICEL_I2_O) 0.045 1.022 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__9/O net (fo=1, routed) 0.012 1.034 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[4] SLICE_X114Y213 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.931 1.096 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X114Y213 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.168 0.928 SLICE_X114Y213 FDRE (Hold_FFF_SLICEL_C_D) 0.056 0.984 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -0.984 arrival time 1.034 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[10].rx_data_ngccm_reg[10][53]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.049ns (33.333%) route 0.098ns (66.667%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.094ns Source Clock Delay (SCD): 0.893ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.775ns (routing 0.275ns, distribution 0.500ns) Clock Net Delay (Destination): 0.929ns (routing 0.312ns, distribution 0.617ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.775 0.893 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X117Y207 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y207 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 0.942 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/Q net (fo=1, routed) 0.098 1.040 rx_data[10][53] SLICE_X117Y205 FDCE r SFP_GEN[10].rx_data_ngccm_reg[10][53]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.929 1.094 RX_WORDCLK_O[10] SLICE_X117Y205 FDCE r SFP_GEN[10].rx_data_ngccm_reg[10][53]/C clock pessimism -0.160 0.934 SLICE_X117Y205 FDCE (Hold_GFF_SLICEL_C_D) 0.056 0.990 SFP_GEN[10].rx_data_ngccm_reg[10][53] ------------------------------------------------------------------- required time -0.990 arrival time 1.040 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.094ns (66.197%) route 0.048ns (33.803%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.096ns Source Clock Delay (SCD): 0.893ns Clock Pessimism Removal (CPR): 0.168ns Clock Net Delay (Source): 0.775ns (routing 0.275ns, distribution 0.500ns) Clock Net Delay (Destination): 0.931ns (routing 0.312ns, distribution 0.619ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.775 0.893 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X114Y213 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X114Y213 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 0.942 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Q net (fo=1, routed) 0.034 0.976 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] SLICE_X114Y213 LUT3 (Prop_G6LUT_SLICEL_I0_O) 0.045 1.021 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__9/O net (fo=1, routed) 0.014 1.035 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[1] SLICE_X114Y213 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.931 1.096 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X114Y213 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.168 0.928 SLICE_X114Y213 FDRE (Hold_GFF_SLICEL_C_D) 0.056 0.984 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -0.984 arrival time 1.035 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[10].rx_data_ngccm_reg[10][7]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.048ns (31.169%) route 0.106ns (68.831%)) Logic Levels: 0 Clock Path Skew: 0.046ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.097ns Source Clock Delay (SCD): 0.891ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.773ns (routing 0.275ns, distribution 0.498ns) Clock Net Delay (Destination): 0.932ns (routing 0.312ns, distribution 0.620ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.773 0.891 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X114Y213 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X114Y213 FDRE (Prop_EFF2_SLICEL_C_Q) 0.048 0.939 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/Q net (fo=1, routed) 0.106 1.045 rx_data[10][7] SLICE_X114Y212 FDCE r SFP_GEN[10].rx_data_ngccm_reg[10][7]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.932 1.097 RX_WORDCLK_O[10] SLICE_X114Y212 FDCE r SFP_GEN[10].rx_data_ngccm_reg[10][7]/C clock pessimism -0.160 0.937 SLICE_X114Y212 FDCE (Hold_DFF_SLICEL_C_D) 0.056 0.993 SFP_GEN[10].rx_data_ngccm_reg[10][7] ------------------------------------------------------------------- required time -0.993 arrival time 1.045 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.113ns (logic 0.064ns (56.637%) route 0.049ns (43.363%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.148ns Source Clock Delay (SCD): 0.942ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 0.824ns (routing 0.275ns, distribution 0.549ns) Clock Net Delay (Destination): 0.983ns (routing 0.312ns, distribution 0.671ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.824 0.942 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X122Y222 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X122Y222 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 0.991 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/Q net (fo=9, routed) 0.037 1.028 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/Q[1] SLICE_X122Y222 LUT6 (Prop_A6LUT_SLICEL_I0_O) 0.015 1.043 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[0]_i_1__9/O net (fo=1, routed) 0.012 1.055 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/D[0] SLICE_X122Y222 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.983 1.148 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X122Y222 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism -0.201 0.947 SLICE_X122Y222 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.003 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time -1.003 arrival time 1.055 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/bitSlipCmd_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.112ns (logic 0.063ns (56.250%) route 0.049ns (43.750%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.004ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.145ns Source Clock Delay (SCD): 0.945ns Clock Pessimism Removal (CPR): 0.196ns Clock Net Delay (Source): 0.827ns (routing 0.275ns, distribution 0.552ns) Clock Net Delay (Destination): 0.980ns (routing 0.312ns, distribution 0.668ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.827 0.945 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X123Y223 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/bitSlipCmd_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y223 FDCE (Prop_HFF_SLICEL_C_Q) 0.048 0.993 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/bitSlipCmd_reg/Q net (fo=10, routed) 0.035 1.028 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/bitSlipCmd_to_bitSlipCtrller_10 SLICE_X123Y223 LUT3 (Prop_G6LUT_SLICEL_I0_O) 0.015 1.043 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_i_1__9/O net (fo=1, routed) 0.014 1.057 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_i_1__9_n_0 SLICE_X123Y223 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.980 1.145 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X123Y223 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_reg/C clock pessimism -0.196 0.949 SLICE_X123Y223 FDCE (Hold_GFF_SLICEL_C_D) 0.056 1.005 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_reg ------------------------------------------------------------------- required time -1.005 arrival time 1.057 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.053ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.150ns (logic 0.104ns (69.333%) route 0.046ns (30.667%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.112ns Source Clock Delay (SCD): 0.902ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 0.784ns (routing 0.275ns, distribution 0.509ns) Clock Net Delay (Destination): 0.947ns (routing 0.312ns, distribution 0.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.784 0.902 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X113Y217 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y217 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 0.951 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Q net (fo=2, routed) 0.035 0.986 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_29_in SLICE_X113Y217 LUT3 (Prop_C5LUT_SLICEM_I0_O) 0.055 1.041 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__9/O net (fo=1, routed) 0.011 1.052 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[15] SLICE_X113Y217 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.947 1.112 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X113Y217 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C clock pessimism -0.169 0.943 SLICE_X113Y217 FDRE (Hold_CFF2_SLICEM_C_D) 0.056 0.999 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15] ------------------------------------------------------------------- required time -0.999 arrival time 1.052 ------------------------------------------------------------------- slack 0.053 Slack (MET) : 0.053ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.114ns (logic 0.064ns (56.140%) route 0.050ns (43.860%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.149ns Source Clock Delay (SCD): 0.942ns Clock Pessimism Removal (CPR): 0.202ns Clock Net Delay (Source): 0.824ns (routing 0.275ns, distribution 0.549ns) Clock Net Delay (Destination): 0.984ns (routing 0.312ns, distribution 0.672ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.824 0.942 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] SLICE_X120Y226 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/C ------------------------------------------------------------------- ------------------- SLICE_X120Y226 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 0.991 r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/Q net (fo=5, routed) 0.035 1.026 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gbtBank_Clk_gen[10].cnt_reg[10][7]_0[7] SLICE_X120Y226 LUT6 (Prop_B6LUT_SLICEL_I4_O) 0.015 1.041 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gbtBank_Clk_gen[10].cnt[10][7]_i_2/O net (fo=1, routed) 0.015 1.056 g_gbt_bank[0].gbtbank/i_gbt_bank_n_354 SLICE_X120Y226 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.984 1.149 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] SLICE_X120Y226 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/C clock pessimism -0.202 0.947 SLICE_X120Y226 FDCE (Hold_BFF_SLICEL_C_D) 0.056 1.003 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7] ------------------------------------------------------------------- required time -1.003 arrival time 1.056 ------------------------------------------------------------------- slack 0.053 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_1 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y89 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X119Y227 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X119Y225 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X119Y225 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X119Y225 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X119Y226 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X119Y226 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X120Y226 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X119Y227 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X119Y225 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X119Y225 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X119Y225 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X119Y226 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X119Y226 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X113Y213 g_gbt_bank[0].gbtbank/i_gbt_bank/g_rx_data_good[10].rx_data_good_reg[10]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X119Y218 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/READY_O_reg/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X117Y211 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X114Y213 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X114Y213 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X114Y213 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.037 0.493 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.037 1.292 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_10 To Clock: gtwiz_userclk_rx_srcclk_out[0]_10 Setup : 0 Failing Endpoints, Worst Slack 3.609ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.036ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.609ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 4.434ns (logic 1.488ns (33.559%) route 2.946ns (66.441%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.184ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.244ns = ( 10.561 - 8.317 ) Source Clock Delay (SCD): 2.641ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.166ns (routing 0.633ns, distribution 1.533ns) Clock Net Delay (Destination): 1.846ns (routing 0.572ns, distribution 1.274ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.166 2.641 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.727 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.077 5.804 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X116Y188 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.970 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/O net (fo=5, routed) 0.110 6.080 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X116Y188 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.147 6.227 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__7/O net (fo=1, routed) 0.269 6.496 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__7_n_0 SLICE_X116Y188 LUT6 (Prop_H6LUT_SLICEL_I5_O) 0.089 6.585 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__7/O net (fo=2, routed) 0.490 7.075 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__7_n_0 SLICE_X115Y188 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.846 10.561 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X115Y188 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.213 10.775 clock uncertainty -0.035 10.739 SLICE_X115Y188 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 10.684 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.684 arrival time -7.075 ------------------------------------------------------------------- slack 3.609 Slack (MET) : 3.844ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 4.201ns (logic 1.488ns (35.420%) route 2.713ns (64.580%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.183ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.245ns = ( 10.562 - 8.317 ) Source Clock Delay (SCD): 2.641ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.166ns (routing 0.633ns, distribution 1.533ns) Clock Net Delay (Destination): 1.847ns (routing 0.572ns, distribution 1.275ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.166 2.641 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.727 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.077 5.804 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X116Y188 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.970 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/O net (fo=5, routed) 0.110 6.080 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X116Y188 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.147 6.227 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__7/O net (fo=1, routed) 0.269 6.496 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__7_n_0 SLICE_X116Y188 LUT6 (Prop_H6LUT_SLICEL_I5_O) 0.089 6.585 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__7/O net (fo=2, routed) 0.257 6.842 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__7_n_0 SLICE_X115Y188 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.847 10.562 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X115Y188 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.213 10.776 clock uncertainty -0.035 10.740 SLICE_X115Y188 FDCE (Setup_DFF_SLICEM_C_CE) -0.054 10.686 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.686 arrival time -6.842 ------------------------------------------------------------------- slack 3.844 Slack (MET) : 3.876ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 4.156ns (logic 1.303ns (31.352%) route 2.853ns (68.648%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.195ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.233ns = ( 10.550 - 8.317 ) Source Clock Delay (SCD): 2.641ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.166ns (routing 0.633ns, distribution 1.533ns) Clock Net Delay (Destination): 1.835ns (routing 0.572ns, distribution 1.263ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.166 2.641 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.727 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.077 5.804 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X116Y188 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.970 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/O net (fo=5, routed) 0.111 6.081 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X116Y188 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.051 6.132 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/O net (fo=7, routed) 0.665 6.797 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X116Y187 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.835 10.550 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X116Y187 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.213 10.764 clock uncertainty -0.035 10.728 SLICE_X116Y187 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 10.673 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 10.673 arrival time -6.797 ------------------------------------------------------------------- slack 3.876 Slack (MET) : 3.881ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 4.152ns (logic 1.303ns (31.382%) route 2.849ns (68.618%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.195ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.233ns = ( 10.550 - 8.317 ) Source Clock Delay (SCD): 2.641ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.166ns (routing 0.633ns, distribution 1.533ns) Clock Net Delay (Destination): 1.835ns (routing 0.572ns, distribution 1.263ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.166 2.641 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.727 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.077 5.804 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X116Y188 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.970 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/O net (fo=5, routed) 0.111 6.081 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X116Y188 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.051 6.132 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/O net (fo=7, routed) 0.661 6.793 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X116Y187 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.835 10.550 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X116Y187 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.213 10.764 clock uncertainty -0.035 10.728 SLICE_X116Y187 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 10.674 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 10.674 arrival time -6.793 ------------------------------------------------------------------- slack 3.881 Slack (MET) : 3.881ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 4.152ns (logic 1.303ns (31.382%) route 2.849ns (68.618%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.195ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.233ns = ( 10.550 - 8.317 ) Source Clock Delay (SCD): 2.641ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.166ns (routing 0.633ns, distribution 1.533ns) Clock Net Delay (Destination): 1.835ns (routing 0.572ns, distribution 1.263ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.166 2.641 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.727 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.077 5.804 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X116Y188 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.970 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/O net (fo=5, routed) 0.111 6.081 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X116Y188 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.051 6.132 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/O net (fo=7, routed) 0.661 6.793 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X116Y187 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.835 10.550 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X116Y187 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.213 10.764 clock uncertainty -0.035 10.728 SLICE_X116Y187 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 10.674 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 10.674 arrival time -6.793 ------------------------------------------------------------------- slack 3.881 Slack (MET) : 4.033ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 4.017ns (logic 1.399ns (34.827%) route 2.618ns (65.173%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.174ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.254ns = ( 10.571 - 8.317 ) Source Clock Delay (SCD): 2.641ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.166ns (routing 0.633ns, distribution 1.533ns) Clock Net Delay (Destination): 1.856ns (routing 0.572ns, distribution 1.284ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.166 2.641 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.727 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.077 5.804 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X116Y188 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.970 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/O net (fo=5, routed) 0.109 6.079 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X116Y188 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 6.226 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__8/O net (fo=3, routed) 0.432 6.658 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecFalseHeaders0 SLICE_X116Y189 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.856 10.571 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X116Y189 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.213 10.785 clock uncertainty -0.035 10.749 SLICE_X116Y189 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 10.691 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 10.691 arrival time -6.658 ------------------------------------------------------------------- slack 4.033 Slack (MET) : 4.040ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 4.013ns (logic 1.399ns (34.862%) route 2.614ns (65.138%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.174ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.254ns = ( 10.571 - 8.317 ) Source Clock Delay (SCD): 2.641ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.166ns (routing 0.633ns, distribution 1.533ns) Clock Net Delay (Destination): 1.856ns (routing 0.572ns, distribution 1.284ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.166 2.641 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.727 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.077 5.804 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X116Y188 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.970 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/O net (fo=5, routed) 0.109 6.079 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X116Y188 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 6.226 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__8/O net (fo=3, routed) 0.428 6.654 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecFalseHeaders0 SLICE_X116Y189 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.856 10.571 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X116Y189 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.213 10.785 clock uncertainty -0.035 10.749 SLICE_X116Y189 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 10.694 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 10.694 arrival time -6.654 ------------------------------------------------------------------- slack 4.040 Slack (MET) : 4.040ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 4.013ns (logic 1.399ns (34.862%) route 2.614ns (65.138%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.174ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.254ns = ( 10.571 - 8.317 ) Source Clock Delay (SCD): 2.641ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.166ns (routing 0.633ns, distribution 1.533ns) Clock Net Delay (Destination): 1.856ns (routing 0.572ns, distribution 1.284ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.166 2.641 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.727 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.077 5.804 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X116Y188 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.970 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/O net (fo=5, routed) 0.109 6.079 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X116Y188 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 6.226 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__8/O net (fo=3, routed) 0.428 6.654 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecFalseHeaders0 SLICE_X116Y189 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.856 10.571 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X116Y189 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C clock pessimism 0.213 10.785 clock uncertainty -0.035 10.749 SLICE_X116Y189 FDRE (Setup_EFF_SLICEL_C_CE) -0.055 10.694 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2] ------------------------------------------------------------------- required time 10.694 arrival time -6.654 ------------------------------------------------------------------- slack 4.040 Slack (MET) : 4.047ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 4.008ns (logic 1.303ns (32.510%) route 2.705ns (67.490%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.172ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.256ns = ( 10.573 - 8.317 ) Source Clock Delay (SCD): 2.641ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.166ns (routing 0.633ns, distribution 1.533ns) Clock Net Delay (Destination): 1.858ns (routing 0.572ns, distribution 1.286ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.166 2.641 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.727 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.077 5.804 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X116Y188 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.970 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/O net (fo=5, routed) 0.111 6.081 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X116Y188 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.051 6.132 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/O net (fo=7, routed) 0.517 6.649 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X116Y189 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.858 10.573 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X116Y189 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.213 10.787 clock uncertainty -0.035 10.751 SLICE_X116Y189 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 10.696 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 10.696 arrival time -6.649 ------------------------------------------------------------------- slack 4.047 Slack (MET) : 4.047ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 4.008ns (logic 1.303ns (32.510%) route 2.705ns (67.490%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.172ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.256ns = ( 10.573 - 8.317 ) Source Clock Delay (SCD): 2.641ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.166ns (routing 0.633ns, distribution 1.533ns) Clock Net Delay (Destination): 1.858ns (routing 0.572ns, distribution 1.286ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.166 2.641 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.727 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.077 5.804 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X116Y188 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.970 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/O net (fo=5, routed) 0.111 6.081 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X116Y188 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.051 6.132 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/O net (fo=7, routed) 0.517 6.649 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X116Y189 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.858 10.573 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X116Y189 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.213 10.787 clock uncertainty -0.035 10.751 SLICE_X116Y189 FDRE (Setup_BFF2_SLICEL_C_CE) -0.055 10.696 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 10.696 arrival time -6.649 ------------------------------------------------------------------- slack 4.047 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[8].rx_data_ngccm_reg[8][68]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.161ns (logic 0.049ns (30.435%) route 0.112ns (69.565%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.118ns Source Clock Delay (SCD): 0.920ns Clock Pessimism Removal (CPR): 0.129ns Clock Net Delay (Source): 0.802ns (routing 0.275ns, distribution 0.527ns) Clock Net Delay (Destination): 0.953ns (routing 0.314ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.802 0.920 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X106Y181 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y181 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 0.969 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/Q net (fo=1, routed) 0.112 1.081 rx_data[8][68] SLICE_X105Y181 FDCE r SFP_GEN[8].rx_data_ngccm_reg[8][68]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.953 1.118 RX_WORDCLK_O[8] SLICE_X105Y181 FDCE r SFP_GEN[8].rx_data_ngccm_reg[8][68]/C clock pessimism -0.129 0.989 SLICE_X105Y181 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.045 SFP_GEN[8].rx_data_ngccm_reg[8][68] ------------------------------------------------------------------- required time -1.045 arrival time 1.081 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.093ns (65.035%) route 0.050ns (34.965%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.131ns Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.174ns Clock Net Delay (Source): 0.797ns (routing 0.275ns, distribution 0.522ns) Clock Net Delay (Destination): 0.966ns (routing 0.314ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.797 0.915 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X108Y187 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y187 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 0.963 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Q net (fo=2, routed) 0.034 0.997 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_13_in SLICE_X108Y187 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.045 1.042 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__7/O net (fo=1, routed) 0.016 1.058 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[5] SLICE_X108Y187 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.966 1.131 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X108Y187 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism -0.174 0.957 SLICE_X108Y187 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.013 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time -1.013 arrival time 1.058 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[8].rx_data_ngccm_reg[8][7]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.166ns (logic 0.048ns (28.916%) route 0.118ns (71.084%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.112ns Source Clock Delay (SCD): 0.918ns Clock Pessimism Removal (CPR): 0.129ns Clock Net Delay (Source): 0.800ns (routing 0.275ns, distribution 0.525ns) Clock Net Delay (Destination): 0.947ns (routing 0.314ns, distribution 0.633ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.800 0.918 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X110Y186 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y186 FDRE (Prop_CFF2_SLICEM_C_Q) 0.048 0.966 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/Q net (fo=1, routed) 0.118 1.084 rx_data[8][7] SLICE_X109Y186 FDCE r SFP_GEN[8].rx_data_ngccm_reg[8][7]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.947 1.112 RX_WORDCLK_O[8] SLICE_X109Y186 FDCE r SFP_GEN[8].rx_data_ngccm_reg[8][7]/C clock pessimism -0.129 0.983 SLICE_X109Y186 FDCE (Hold_GFF2_SLICEM_C_D) 0.056 1.039 SFP_GEN[8].rx_data_ngccm_reg[8][7] ------------------------------------------------------------------- required time -1.039 arrival time 1.084 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.139ns (logic 0.093ns (66.906%) route 0.046ns (33.094%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.128ns Source Clock Delay (SCD): 0.918ns Clock Pessimism Removal (CPR): 0.173ns Clock Net Delay (Source): 0.800ns (routing 0.275ns, distribution 0.525ns) Clock Net Delay (Destination): 0.963ns (routing 0.314ns, distribution 0.649ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.800 0.918 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X108Y185 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y185 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 0.966 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Q net (fo=2, routed) 0.034 1.000 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_11_in SLICE_X108Y185 LUT3 (Prop_F6LUT_SLICEL_I2_O) 0.045 1.045 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__7/O net (fo=1, routed) 0.012 1.057 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[4] SLICE_X108Y185 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.963 1.128 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X108Y185 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.173 0.955 SLICE_X108Y185 FDRE (Hold_FFF_SLICEL_C_D) 0.056 1.011 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.011 arrival time 1.057 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: SFP_GEN[8].rx_data_ngccm_reg[8][53]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[52]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.170ns (logic 0.079ns (46.471%) route 0.091ns (53.529%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.115ns Source Clock Delay (SCD): 0.918ns Clock Pessimism Removal (CPR): 0.129ns Clock Net Delay (Source): 0.800ns (routing 0.275ns, distribution 0.525ns) Clock Net Delay (Destination): 0.950ns (routing 0.314ns, distribution 0.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.800 0.918 RX_WORDCLK_O[8] SLICE_X108Y182 FDCE r SFP_GEN[8].rx_data_ngccm_reg[8][53]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y182 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 0.967 r SFP_GEN[8].rx_data_ngccm_reg[8][53]/Q net (fo=1, routed) 0.075 1.042 SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[83]_0[45] SLICE_X109Y182 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.030 1.072 r SFP_GEN[8].ngCCM_gbt/RX_Word_rx40[52]_i_1/O net (fo=1, routed) 0.016 1.088 SFP_GEN[8].ngCCM_gbt/RX_Word_rx40[52]_i_1_n_0 SLICE_X109Y182 FDCE r SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[52]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.950 1.115 SFP_GEN[8].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y182 FDCE r SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[52]/C clock pessimism -0.129 0.986 SLICE_X109Y182 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.042 SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[52] ------------------------------------------------------------------- required time -1.042 arrival time 1.088 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[8].rx_data_ngccm_reg[8][79]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.048ns (33.566%) route 0.095ns (66.434%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.114ns Source Clock Delay (SCD): 0.913ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.795ns (routing 0.275ns, distribution 0.520ns) Clock Net Delay (Destination): 0.949ns (routing 0.314ns, distribution 0.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.795 0.913 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X105Y183 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X105Y183 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 0.961 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/Q net (fo=1, routed) 0.095 1.056 rx_data[8][79] SLICE_X105Y184 FDCE r SFP_GEN[8].rx_data_ngccm_reg[8][79]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.949 1.114 RX_WORDCLK_O[8] SLICE_X105Y184 FDCE r SFP_GEN[8].rx_data_ngccm_reg[8][79]/C clock pessimism -0.160 0.954 SLICE_X105Y184 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.009 SFP_GEN[8].rx_data_ngccm_reg[8][79] ------------------------------------------------------------------- required time -1.009 arrival time 1.056 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/psAddress_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/bitSlipCmd_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.151ns (logic 0.063ns (41.722%) route 0.088ns (58.278%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.048ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.110ns Source Clock Delay (SCD): 0.902ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.784ns (routing 0.275ns, distribution 0.509ns) Clock Net Delay (Destination): 0.945ns (routing 0.314ns, distribution 0.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.784 0.902 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X117Y188 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/psAddress_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y188 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 0.950 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/psAddress_reg[1]/Q net (fo=8, routed) 0.072 1.022 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/psAddress[1] SLICE_X117Y189 LUT6 (Prop_D6LUT_SLICEL_I4_O) 0.015 1.037 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/bitSlipCmd_i_1__7/O net (fo=1, routed) 0.016 1.053 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/bitSlipCmd SLICE_X117Y189 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/bitSlipCmd_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.945 1.110 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X117Y189 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/bitSlipCmd_reg/C clock pessimism -0.160 0.950 SLICE_X117Y189 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.006 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/bitSlipCmd_reg ------------------------------------------------------------------- required time -1.006 arrival time 1.053 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[38]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[8].ngCCM_gbt/pwr_good_pre_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.178ns (logic 0.048ns (26.966%) route 0.130ns (73.034%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.121ns Source Clock Delay (SCD): 0.918ns Clock Pessimism Removal (CPR): 0.129ns Clock Net Delay (Source): 0.800ns (routing 0.275ns, distribution 0.525ns) Clock Net Delay (Destination): 0.956ns (routing 0.314ns, distribution 0.642ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.800 0.918 SFP_GEN[8].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y186 FDCE r SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[38]/C ------------------------------------------------------------------- ------------------- SLICE_X107Y186 FDCE (Prop_GFF2_SLICEM_C_Q) 0.048 0.966 r SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[38]/Q net (fo=3, routed) 0.130 1.096 SFP_GEN[8].ngCCM_gbt/GBT_Word_to_ngCCM_Pins_bkp_pwr_good SLICE_X106Y186 FDCE r SFP_GEN[8].ngCCM_gbt/pwr_good_pre_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.956 1.121 SFP_GEN[8].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y186 FDCE r SFP_GEN[8].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.129 0.992 SLICE_X106Y186 FDCE (Hold_EFF_SLICEM_C_D) 0.056 1.048 SFP_GEN[8].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.048 arrival time 1.096 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.087ns (50.289%) route 0.086ns (49.711%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.117ns Source Clock Delay (SCD): 0.920ns Clock Pessimism Removal (CPR): 0.129ns Clock Net Delay (Source): 0.802ns (routing 0.275ns, distribution 0.527ns) Clock Net Delay (Destination): 0.952ns (routing 0.314ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.802 0.920 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X106Y183 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y183 FDCE (Prop_AFF2_SLICEM_C_Q) 0.049 0.969 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.075 1.044 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/O85[1] SLICE_X105Y183 LUT3 (Prop_C5LUT_SLICEL_I2_O) 0.038 1.082 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__7/O net (fo=1, routed) 0.011 1.093 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[18] SLICE_X105Y183 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.952 1.117 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X105Y183 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C clock pessimism -0.129 0.988 SLICE_X105Y183 FDRE (Hold_CFF2_SLICEL_C_D) 0.056 1.044 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18] ------------------------------------------------------------------- required time -1.044 arrival time 1.093 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[8].rx_data_ngccm_reg[8][72]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.048ns (31.169%) route 0.106ns (68.831%)) Logic Levels: 0 Clock Path Skew: 0.049ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.118ns Source Clock Delay (SCD): 0.909ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.791ns (routing 0.275ns, distribution 0.516ns) Clock Net Delay (Destination): 0.953ns (routing 0.314ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.791 0.909 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X105Y182 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X105Y182 FDRE (Prop_CFF2_SLICEL_C_Q) 0.048 0.957 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/Q net (fo=1, routed) 0.106 1.063 rx_data[8][72] SLICE_X105Y181 FDCE r SFP_GEN[8].rx_data_ngccm_reg[8][72]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.953 1.118 RX_WORDCLK_O[8] SLICE_X105Y181 FDCE r SFP_GEN[8].rx_data_ngccm_reg[8][72]/C clock pessimism -0.160 0.958 SLICE_X105Y181 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.014 SFP_GEN[8].rx_data_ngccm_reg[8][72] ------------------------------------------------------------------- required time -1.014 arrival time 1.063 ------------------------------------------------------------------- slack 0.049 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_10 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y91 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X98Y238 g_clock_rate_din[8].ngccm_status_cnt_reg[8][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X98Y238 g_clock_rate_din[8].ngccm_status_cnt_reg[8][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X98Y237 g_clock_rate_din[8].ngccm_status_cnt_reg[8][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X98Y237 g_clock_rate_din[8].ngccm_status_cnt_reg[8][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X98Y237 g_clock_rate_din[8].ngccm_status_cnt_reg[8][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X98Y238 g_clock_rate_din[8].ngccm_status_cnt_reg[8][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X107Y232 g_clock_rate_din[8].ngccm_status_cnt_reg[8][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X98Y238 g_clock_rate_din[8].ngccm_status_cnt_reg[8][0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X98Y238 g_clock_rate_din[8].ngccm_status_cnt_reg[8][1]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X98Y238 g_clock_rate_din[8].ngccm_status_cnt_reg[8][5]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X107Y232 g_clock_rate_din[8].ngccm_status_cnt_reg[8][6]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X107Y232 g_clock_rate_din[8].ngccm_status_cnt_reg[8][6]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X105Y191 g_clock_rate_din[8].rx_frameclk_div2_reg[8]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X98Y238 g_clock_rate_din[8].ngccm_status_cnt_reg[8][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X98Y238 g_clock_rate_din[8].ngccm_status_cnt_reg[8][1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X98Y237 g_clock_rate_din[8].ngccm_status_cnt_reg[8][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X98Y237 g_clock_rate_din[8].ngccm_status_cnt_reg[8][3]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X98Y237 g_clock_rate_din[8].ngccm_status_cnt_reg[8][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X98Y238 g_clock_rate_din[8].ngccm_status_cnt_reg[8][5]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_11 To Clock: gtwiz_userclk_rx_srcclk_out[0]_11 Setup : 0 Failing Endpoints, Worst Slack 4.302ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.033ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.493ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.302ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[67]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 3.964ns (logic 1.119ns (28.229%) route 2.845ns (71.771%)) Logic Levels: 0 Clock Path Skew: -0.078ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.318ns = ( 10.635 - 8.317 ) Source Clock Delay (SCD): 2.618ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.143ns (routing 0.632ns, distribution 1.511ns) Clock Net Delay (Destination): 1.920ns (routing 0.572ns, distribution 1.348ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.143 2.618 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[7]) 1.119 3.737 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[7] net (fo=6, routed) 2.845 6.582 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/D[7] SLICE_X121Y198 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[67]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.920 10.635 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X121Y198 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[67]/C clock pessimism 0.222 10.857 clock uncertainty -0.035 10.822 SLICE_X121Y198 FDCE (Setup_BFF_SLICEL_C_D) 0.062 10.884 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[67] ------------------------------------------------------------------- required time 10.884 arrival time -6.582 ------------------------------------------------------------------- slack 4.302 Slack (MET) : 4.331ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[92]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 3.747ns (logic 0.881ns (23.512%) route 2.866ns (76.488%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.267ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.231ns = ( 10.548 - 8.317 ) Source Clock Delay (SCD): 2.710ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.235ns (routing 0.632ns, distribution 1.603ns) Clock Net Delay (Destination): 1.833ns (routing 0.572ns, distribution 1.261ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.235 2.710 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X120Y199 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[92]/C ------------------------------------------------------------------- ------------------- SLICE_X120Y199 FDCE (Prop_CFF2_SLICEL_C_Q) 0.139 2.849 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[92]/Q net (fo=9, routed) 0.323 3.172 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxencdata_s[9]_53[27] SLICE_X122Y201 LUT6 (Prop_F6LUT_SLICEL_I1_O) 0.221 3.393 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/syndromes/i___77_i_3__8/O net (fo=1, routed) 0.652 4.045 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/syndromes/i___77_i_3__8_n_0 SLICE_X119Y201 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.223 4.268 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/syndromes/i___77_i_2__8/O net (fo=49, routed) 1.576 5.844 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[92]_0[1] SLICE_X110Y192 LUT4 (Prop_B6LUT_SLICEM_I2_O) 0.243 6.087 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_3__8/O net (fo=1, routed) 0.280 6.367 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_3__8_n_0 SLICE_X110Y192 LUT6 (Prop_H6LUT_SLICEM_I2_O) 0.055 6.422 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__18/O net (fo=1, routed) 0.035 6.457 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg_3 SLICE_X110Y192 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.833 10.548 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/CLK SLICE_X110Y192 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C clock pessimism 0.212 10.761 clock uncertainty -0.035 10.725 SLICE_X110Y192 FDRE (Setup_HFF_SLICEM_C_D) 0.063 10.788 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg ------------------------------------------------------------------- required time 10.788 arrival time -6.457 ------------------------------------------------------------------- slack 4.331 Slack (MET) : 4.473ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[87]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 3.800ns (logic 1.119ns (29.447%) route 2.681ns (70.553%)) Logic Levels: 0 Clock Path Skew: -0.072ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.325ns = ( 10.642 - 8.317 ) Source Clock Delay (SCD): 2.618ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.143ns (routing 0.632ns, distribution 1.511ns) Clock Net Delay (Destination): 1.927ns (routing 0.572ns, distribution 1.355ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.143 2.618 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[7]) 1.119 3.737 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[7] net (fo=6, routed) 2.681 6.418 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/D[7] SLICE_X121Y199 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[87]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.927 10.642 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X121Y199 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[87]/C clock pessimism 0.221 10.864 clock uncertainty -0.035 10.828 SLICE_X121Y199 FDCE (Setup_DFF_SLICEL_C_D) 0.063 10.891 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[87] ------------------------------------------------------------------- required time 10.891 arrival time -6.418 ------------------------------------------------------------------- slack 4.473 Slack (MET) : 4.495ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].rx_data_ngccm_reg[9][63]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 3.456ns (logic 0.285ns (8.247%) route 3.171ns (91.753%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.276ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.236ns = ( 10.553 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.249ns (routing 0.632ns, distribution 1.617ns) Clock Net Delay (Destination): 1.838ns (routing 0.572ns, distribution 1.266ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.249 2.724 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y203 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y203 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.863 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.253 4.116 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X113Y203 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.146 4.262 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[9].rx_data_ngccm[9][83]_i_1/O net (fo=76, routed) 1.918 6.180 rx_data_ngccm[9] SLICE_X114Y192 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][63]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.838 10.553 RX_WORDCLK_O[9] SLICE_X114Y192 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][63]/C clock pessimism 0.212 10.766 clock uncertainty -0.035 10.730 SLICE_X114Y192 FDCE (Setup_EFF_SLICEL_C_CE) -0.055 10.675 SFP_GEN[9].rx_data_ngccm_reg[9][63] ------------------------------------------------------------------- required time 10.675 arrival time -6.180 ------------------------------------------------------------------- slack 4.495 Slack (MET) : 4.557ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].rx_data_ngccm_reg[9][69]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 3.410ns (logic 0.285ns (8.358%) route 3.125ns (91.642%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.260ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.252ns = ( 10.569 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.249ns (routing 0.632ns, distribution 1.617ns) Clock Net Delay (Destination): 1.854ns (routing 0.572ns, distribution 1.282ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.249 2.724 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y203 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y203 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.863 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.253 4.116 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X113Y203 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.146 4.262 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[9].rx_data_ngccm[9][83]_i_1/O net (fo=76, routed) 1.872 6.134 rx_data_ngccm[9] SLICE_X113Y193 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][69]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.854 10.569 RX_WORDCLK_O[9] SLICE_X113Y193 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][69]/C clock pessimism 0.212 10.781 clock uncertainty -0.035 10.746 SLICE_X113Y193 FDCE (Setup_AFF2_SLICEM_C_CE) -0.055 10.691 SFP_GEN[9].rx_data_ngccm_reg[9][69] ------------------------------------------------------------------- required time 10.691 arrival time -6.134 ------------------------------------------------------------------- slack 4.557 Slack (MET) : 4.561ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].rx_data_ngccm_reg[9][68]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 3.407ns (logic 0.285ns (8.365%) route 3.122ns (91.635%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.260ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.252ns = ( 10.569 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.249ns (routing 0.632ns, distribution 1.617ns) Clock Net Delay (Destination): 1.854ns (routing 0.572ns, distribution 1.282ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.249 2.724 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y203 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y203 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.863 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.253 4.116 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X113Y203 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.146 4.262 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[9].rx_data_ngccm[9][83]_i_1/O net (fo=76, routed) 1.869 6.131 rx_data_ngccm[9] SLICE_X113Y193 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][68]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.854 10.569 RX_WORDCLK_O[9] SLICE_X113Y193 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][68]/C clock pessimism 0.212 10.781 clock uncertainty -0.035 10.746 SLICE_X113Y193 FDCE (Setup_AFF_SLICEM_C_CE) -0.054 10.692 SFP_GEN[9].rx_data_ngccm_reg[9][68] ------------------------------------------------------------------- required time 10.692 arrival time -6.131 ------------------------------------------------------------------- slack 4.561 Slack (MET) : 4.561ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].rx_data_ngccm_reg[9][70]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 3.407ns (logic 0.285ns (8.365%) route 3.122ns (91.635%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.260ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.252ns = ( 10.569 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.249ns (routing 0.632ns, distribution 1.617ns) Clock Net Delay (Destination): 1.854ns (routing 0.572ns, distribution 1.282ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.249 2.724 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y203 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y203 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.863 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.253 4.116 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X113Y203 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.146 4.262 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[9].rx_data_ngccm[9][83]_i_1/O net (fo=76, routed) 1.869 6.131 rx_data_ngccm[9] SLICE_X113Y193 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][70]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.854 10.569 RX_WORDCLK_O[9] SLICE_X113Y193 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][70]/C clock pessimism 0.212 10.781 clock uncertainty -0.035 10.746 SLICE_X113Y193 FDCE (Setup_BFF_SLICEM_C_CE) -0.054 10.692 SFP_GEN[9].rx_data_ngccm_reg[9][70] ------------------------------------------------------------------- required time 10.692 arrival time -6.131 ------------------------------------------------------------------- slack 4.561 Slack (MET) : 4.562ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[7]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 3.606ns (logic 1.119ns (31.032%) route 2.487ns (68.968%)) Logic Levels: 0 Clock Path Skew: -0.177ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.228ns = ( 10.545 - 8.317 ) Source Clock Delay (SCD): 2.618ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.143ns (routing 0.632ns, distribution 1.511ns) Clock Net Delay (Destination): 1.830ns (routing 0.572ns, distribution 1.258ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.143 2.618 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[7]) 1.119 3.737 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[7] net (fo=6, routed) 2.487 6.224 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/D[7] SLICE_X117Y203 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[7]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.830 10.545 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X117Y203 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[7]/C clock pessimism 0.213 10.758 clock uncertainty -0.035 10.723 SLICE_X117Y203 FDCE (Setup_CFF_SLICEL_C_D) 0.063 10.786 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[7] ------------------------------------------------------------------- required time 10.786 arrival time -6.224 ------------------------------------------------------------------- slack 4.562 Slack (MET) : 4.567ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_clock_rate_din[9].ngccm_status_cnt_reg[9][5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 3.570ns (logic 0.387ns (10.840%) route 3.183ns (89.160%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: -0.211ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.268ns = ( 10.585 - 8.317 ) Source Clock Delay (SCD): 2.691ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.216ns (routing 0.632ns, distribution 1.584ns) Clock Net Delay (Destination): 1.870ns (routing 0.572ns, distribution 1.298ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.216 2.691 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X119Y203 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C ------------------------------------------------------------------- ------------------- SLICE_X119Y203 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.831 r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/Q net (fo=137, routed) 2.398 5.229 SFP_GEN[9].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X97Y237 LUT4 (Prop_G5LUT_SLICEM_I2_O) 0.247 5.476 r SFP_GEN[9].ngCCM_gbt/g_clock_rate_din[9].ngccm_status_cnt[9][5]_i_1/O net (fo=1, routed) 0.785 6.261 SFP_GEN[9].ngCCM_gbt_n_412 SLICE_X97Y237 FDRE r g_clock_rate_din[9].ngccm_status_cnt_reg[9][5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.870 10.585 RX_WORDCLK_O[9] SLICE_X97Y237 FDRE r g_clock_rate_din[9].ngccm_status_cnt_reg[9][5]/C clock pessimism 0.212 10.798 clock uncertainty -0.035 10.762 SLICE_X97Y237 FDRE (Setup_CFF2_SLICEM_C_D) 0.066 10.828 g_clock_rate_din[9].ngccm_status_cnt_reg[9][5] ------------------------------------------------------------------- required time 10.828 arrival time -6.261 ------------------------------------------------------------------- slack 4.567 Slack (MET) : 4.568ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].rx_data_ngccm_reg[9][58]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 3.399ns (logic 0.285ns (8.385%) route 3.114ns (91.615%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.260ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.252ns = ( 10.569 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.249ns (routing 0.632ns, distribution 1.617ns) Clock Net Delay (Destination): 1.854ns (routing 0.572ns, distribution 1.282ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.249 2.724 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y203 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y203 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.863 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.253 4.116 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X113Y203 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.146 4.262 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[9].rx_data_ngccm[9][83]_i_1/O net (fo=76, routed) 1.861 6.123 rx_data_ngccm[9] SLICE_X115Y192 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][58]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.854 10.569 RX_WORDCLK_O[9] SLICE_X115Y192 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][58]/C clock pessimism 0.212 10.781 clock uncertainty -0.035 10.746 SLICE_X115Y192 FDCE (Setup_AFF2_SLICEM_C_CE) -0.055 10.691 SFP_GEN[9].rx_data_ngccm_reg[9][58] ------------------------------------------------------------------- required time 10.691 arrival time -6.123 ------------------------------------------------------------------- slack 4.568 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.033ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].rx_data_ngccm_reg[9][76]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.048ns (33.566%) route 0.095ns (66.434%)) Logic Levels: 0 Clock Path Skew: 0.054ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.116ns Source Clock Delay (SCD): 0.902ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.784ns (routing 0.274ns, distribution 0.510ns) Clock Net Delay (Destination): 0.951ns (routing 0.313ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.784 0.902 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X116Y196 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X116Y196 FDRE (Prop_GFF_SLICEL_C_Q) 0.048 0.950 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/Q net (fo=1, routed) 0.095 1.045 rx_data[9][76] SLICE_X116Y195 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][76]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.951 1.116 RX_WORDCLK_O[9] SLICE_X116Y195 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][76]/C clock pessimism -0.160 0.956 SLICE_X116Y195 FDCE (Hold_BFF2_SLICEL_C_D) 0.056 1.012 SFP_GEN[9].rx_data_ngccm_reg[9][76] ------------------------------------------------------------------- required time -1.012 arrival time 1.045 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.103ns (66.883%) route 0.051ns (33.117%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.119ns Source Clock Delay (SCD): 0.903ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.785ns (routing 0.274ns, distribution 0.511ns) Clock Net Delay (Destination): 0.954ns (routing 0.313ns, distribution 0.641ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.785 0.903 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X113Y196 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y196 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 0.952 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Q net (fo=1, routed) 0.035 0.987 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] SLICE_X113Y195 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.054 1.041 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__8/O net (fo=1, routed) 0.016 1.057 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[0] SLICE_X113Y195 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.954 1.119 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X113Y195 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.160 0.959 SLICE_X113Y195 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.015 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -1.015 arrival time 1.057 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].rx_data_ngccm_reg[9][44]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.162ns (logic 0.049ns (30.247%) route 0.113ns (69.753%)) Logic Levels: 0 Clock Path Skew: 0.062ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.115ns Source Clock Delay (SCD): 0.893ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.775ns (routing 0.274ns, distribution 0.501ns) Clock Net Delay (Destination): 0.950ns (routing 0.313ns, distribution 0.637ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.775 0.893 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X114Y197 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X114Y197 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 0.942 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/Q net (fo=1, routed) 0.113 1.055 rx_data[9][44] SLICE_X114Y195 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][44]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.950 1.115 RX_WORDCLK_O[9] SLICE_X114Y195 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][44]/C clock pessimism -0.160 0.955 SLICE_X114Y195 FDCE (Hold_FFF_SLICEL_C_D) 0.056 1.011 SFP_GEN[9].rx_data_ngccm_reg[9][44] ------------------------------------------------------------------- required time -1.011 arrival time 1.055 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].rx_data_ngccm_reg[9][48]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.141ns (logic 0.048ns (34.043%) route 0.093ns (65.957%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.118ns Source Clock Delay (SCD): 0.907ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.789ns (routing 0.274ns, distribution 0.515ns) Clock Net Delay (Destination): 0.953ns (routing 0.313ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.789 0.907 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X113Y194 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y194 FDRE (Prop_FFF2_SLICEM_C_Q) 0.048 0.955 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/Q net (fo=1, routed) 0.093 1.048 rx_data[9][48] SLICE_X114Y194 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][48]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.953 1.118 RX_WORDCLK_O[9] SLICE_X114Y194 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][48]/C clock pessimism -0.171 0.947 SLICE_X114Y194 FDCE (Hold_BFF2_SLICEL_C_D) 0.056 1.003 SFP_GEN[9].rx_data_ngccm_reg[9][48] ------------------------------------------------------------------- required time -1.003 arrival time 1.048 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.164ns (logic 0.080ns (48.780%) route 0.084ns (51.220%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.063ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.112ns Source Clock Delay (SCD): 0.889ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.771ns (routing 0.274ns, distribution 0.497ns) Clock Net Delay (Destination): 0.947ns (routing 0.313ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.771 0.889 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X116Y197 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X116Y197 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 0.938 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Q net (fo=2, routed) 0.068 1.006 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_23_in SLICE_X116Y196 LUT3 (Prop_H6LUT_SLICEL_I2_O) 0.031 1.037 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__8/O net (fo=1, routed) 0.016 1.053 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[10] SLICE_X116Y196 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.947 1.112 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X116Y196 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C clock pessimism -0.160 0.952 SLICE_X116Y196 FDRE (Hold_HFF_SLICEL_C_D) 0.056 1.008 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10] ------------------------------------------------------------------- required time -1.008 arrival time 1.053 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: SFP_GEN[9].rx_data_ngccm_reg[9][44]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[44]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.118ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.172ns Clock Net Delay (Source): 0.786ns (routing 0.274ns, distribution 0.512ns) Clock Net Delay (Destination): 0.953ns (routing 0.313ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 RX_WORDCLK_O[9] SLICE_X114Y195 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][44]/C ------------------------------------------------------------------- ------------------- SLICE_X114Y195 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 0.953 r SFP_GEN[9].rx_data_ngccm_reg[9][44]/Q net (fo=1, routed) 0.034 0.987 SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[83]_0[36] SLICE_X114Y195 LUT3 (Prop_D6LUT_SLICEL_I1_O) 0.045 1.032 r SFP_GEN[9].ngCCM_gbt/RX_Word_rx40[44]_i_1/O net (fo=1, routed) 0.016 1.048 SFP_GEN[9].ngCCM_gbt/RX_Word_rx40[44]_i_1_n_0 SLICE_X114Y195 FDCE r SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[44]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.953 1.118 SFP_GEN[9].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X114Y195 FDCE r SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[44]/C clock pessimism -0.172 0.946 SLICE_X114Y195 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.002 SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[44] ------------------------------------------------------------------- required time -1.002 arrival time 1.048 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[36]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.228ns (logic 0.114ns (50.000%) route 0.114ns (50.000%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.126ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.151ns Source Clock Delay (SCD): 0.896ns Clock Pessimism Removal (CPR): 0.129ns Clock Net Delay (Source): 0.778ns (routing 0.274ns, distribution 0.504ns) Clock Net Delay (Destination): 0.986ns (routing 0.313ns, distribution 0.673ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.778 0.896 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X118Y200 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y200 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 0.945 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/Q net (fo=29, routed) 0.099 1.044 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0] SLICE_X119Y200 LUT5 (Prop_B6LUT_SLICEM_I2_O) 0.065 1.109 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0[36]_i_1__4/O net (fo=1, routed) 0.015 1.124 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg00[36] SLICE_X119Y200 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[36]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.986 1.151 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X119Y200 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[36]/C clock pessimism -0.129 1.022 SLICE_X119Y200 FDCE (Hold_BFF_SLICEM_C_D) 0.056 1.078 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[36] ------------------------------------------------------------------- required time -1.078 arrival time 1.124 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[33]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[33]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.049ns (34.266%) route 0.094ns (65.734%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.140ns Source Clock Delay (SCD): 0.935ns Clock Pessimism Removal (CPR): 0.164ns Clock Net Delay (Source): 0.817ns (routing 0.274ns, distribution 0.543ns) Clock Net Delay (Destination): 0.975ns (routing 0.313ns, distribution 0.662ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.817 0.935 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X120Y200 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[33]/C ------------------------------------------------------------------- ------------------- SLICE_X120Y200 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 0.984 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[33]/Q net (fo=1, routed) 0.094 1.078 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0[33] SLICE_X120Y199 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[33]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.975 1.140 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X120Y199 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[33]/C clock pessimism -0.164 0.976 SLICE_X120Y199 FDCE (Hold_HFF2_SLICEL_C_D) 0.056 1.032 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[33] ------------------------------------------------------------------- required time -1.032 arrival time 1.078 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].rx_data_ngccm_reg[9][77]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.049ns (31.613%) route 0.106ns (68.387%)) Logic Levels: 0 Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.116ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.786ns (routing 0.274ns, distribution 0.512ns) Clock Net Delay (Destination): 0.951ns (routing 0.313ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X116Y196 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X116Y196 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 0.953 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/Q net (fo=1, routed) 0.106 1.059 rx_data[9][77] SLICE_X116Y195 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][77]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.951 1.116 RX_WORDCLK_O[9] SLICE_X116Y195 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][77]/C clock pessimism -0.159 0.956 SLICE_X116Y195 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.013 SFP_GEN[9].rx_data_ngccm_reg[9][77] ------------------------------------------------------------------- required time -1.012 arrival time 1.059 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.094ns (64.384%) route 0.052ns (35.616%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.113ns Source Clock Delay (SCD): 0.900ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.782ns (routing 0.274ns, distribution 0.508ns) Clock Net Delay (Destination): 0.948ns (routing 0.313ns, distribution 0.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.782 0.900 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X114Y200 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X114Y200 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 0.949 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Q net (fo=2, routed) 0.036 0.985 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_7_in SLICE_X114Y200 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.045 1.030 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__8/O net (fo=1, routed) 0.016 1.046 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[4] SLICE_X114Y200 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.948 1.113 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X114Y200 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.171 0.942 SLICE_X114Y200 FDRE (Hold_DFF_SLICEL_C_D) 0.056 0.998 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -0.998 arrival time 1.046 ------------------------------------------------------------------- slack 0.048 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_11 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y93 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X97Y237 g_clock_rate_din[9].ngccm_status_cnt_reg[9][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X97Y237 g_clock_rate_din[9].ngccm_status_cnt_reg[9][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X97Y237 g_clock_rate_din[9].ngccm_status_cnt_reg[9][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X97Y237 g_clock_rate_din[9].ngccm_status_cnt_reg[9][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X97Y237 g_clock_rate_din[9].ngccm_status_cnt_reg[9][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X97Y237 g_clock_rate_din[9].ngccm_status_cnt_reg[9][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X113Y235 g_clock_rate_din[9].ngccm_status_cnt_reg[9][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X97Y237 g_clock_rate_din[9].ngccm_status_cnt_reg[9][0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X97Y237 g_clock_rate_din[9].ngccm_status_cnt_reg[9][0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X97Y237 g_clock_rate_din[9].ngccm_status_cnt_reg[9][1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X97Y237 g_clock_rate_din[9].ngccm_status_cnt_reg[9][1]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X97Y237 g_clock_rate_din[9].ngccm_status_cnt_reg[9][2]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X97Y237 g_clock_rate_din[9].ngccm_status_cnt_reg[9][2]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X119Y203 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X119Y203 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X119Y203 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X119Y203 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X119Y199 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X119Y199 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.037 0.493 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.037 1.292 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_2 To Clock: gtwiz_userclk_rx_srcclk_out[0]_2 Setup : 0 Failing Endpoints, Worst Slack 3.134ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.035ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.493ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.134ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 4.961ns (logic 1.791ns (36.102%) route 3.170ns (63.898%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.133ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.382ns = ( 10.699 - 8.317 ) Source Clock Delay (SCD): 2.651ns Clock Pessimism Removal (CPR): 0.136ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.176ns (routing 0.630ns, distribution 1.546ns) Clock Net Delay (Destination): 1.984ns (routing 0.571ns, distribution 1.413ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.176 2.651 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.812 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.106 5.918 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X120Y242 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.156 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/O net (fo=5, routed) 0.346 6.502 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X119Y241 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.224 6.726 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__10/O net (fo=1, routed) 0.079 6.805 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__10_n_0 SLICE_X119Y241 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.168 6.973 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__10/O net (fo=2, routed) 0.639 7.612 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__10_n_0 SLICE_X120Y241 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.984 10.699 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X120Y241 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.136 10.835 clock uncertainty -0.035 10.800 SLICE_X120Y241 FDCE (Setup_CFF_SLICEL_C_CE) -0.054 10.746 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.746 arrival time -7.612 ------------------------------------------------------------------- slack 3.134 Slack (MET) : 3.134ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 4.961ns (logic 1.791ns (36.102%) route 3.170ns (63.898%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.133ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.382ns = ( 10.699 - 8.317 ) Source Clock Delay (SCD): 2.651ns Clock Pessimism Removal (CPR): 0.136ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.176ns (routing 0.630ns, distribution 1.546ns) Clock Net Delay (Destination): 1.984ns (routing 0.571ns, distribution 1.413ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.176 2.651 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.812 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.106 5.918 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X120Y242 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.156 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/O net (fo=5, routed) 0.346 6.502 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X119Y241 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.224 6.726 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__10/O net (fo=1, routed) 0.079 6.805 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__10_n_0 SLICE_X119Y241 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.168 6.973 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__10/O net (fo=2, routed) 0.639 7.612 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__10_n_0 SLICE_X120Y241 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.984 10.699 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X120Y241 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.136 10.835 clock uncertainty -0.035 10.800 SLICE_X120Y241 FDCE (Setup_DFF_SLICEL_C_CE) -0.054 10.746 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.746 arrival time -7.612 ------------------------------------------------------------------- slack 3.134 Slack (MET) : 3.468ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 4.603ns (logic 1.625ns (35.303%) route 2.978ns (64.697%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.153ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.362ns = ( 10.679 - 8.317 ) Source Clock Delay (SCD): 2.651ns Clock Pessimism Removal (CPR): 0.136ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.176ns (routing 0.630ns, distribution 1.546ns) Clock Net Delay (Destination): 1.964ns (routing 0.571ns, distribution 1.393ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.176 2.651 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.812 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.106 5.918 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X120Y242 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.156 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/O net (fo=5, routed) 0.277 6.433 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X119Y241 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.226 6.659 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/O net (fo=7, routed) 0.595 7.254 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 SLICE_X119Y244 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.964 10.679 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X119Y244 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.136 10.815 clock uncertainty -0.035 10.780 SLICE_X119Y244 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 10.722 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 10.722 arrival time -7.254 ------------------------------------------------------------------- slack 3.468 Slack (MET) : 3.474ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 4.600ns (logic 1.625ns (35.326%) route 2.975ns (64.674%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.153ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.362ns = ( 10.679 - 8.317 ) Source Clock Delay (SCD): 2.651ns Clock Pessimism Removal (CPR): 0.136ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.176ns (routing 0.630ns, distribution 1.546ns) Clock Net Delay (Destination): 1.964ns (routing 0.571ns, distribution 1.393ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.176 2.651 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.812 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.106 5.918 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X120Y242 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.156 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/O net (fo=5, routed) 0.277 6.433 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X119Y241 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.226 6.659 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/O net (fo=7, routed) 0.592 7.251 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 SLICE_X119Y244 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.964 10.679 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X119Y244 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.136 10.815 clock uncertainty -0.035 10.780 SLICE_X119Y244 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 10.725 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 10.725 arrival time -7.251 ------------------------------------------------------------------- slack 3.474 Slack (MET) : 3.565ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 4.515ns (logic 1.636ns (36.235%) route 2.879ns (63.765%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.371ns = ( 10.688 - 8.317 ) Source Clock Delay (SCD): 2.651ns Clock Pessimism Removal (CPR): 0.136ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.176ns (routing 0.630ns, distribution 1.546ns) Clock Net Delay (Destination): 1.973ns (routing 0.571ns, distribution 1.402ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.176 2.651 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.812 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.106 5.918 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X120Y242 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.156 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/O net (fo=5, routed) 0.182 6.338 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X120Y241 LUT6 (Prop_B6LUT_SLICEL_I5_O) 0.237 6.575 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__11/O net (fo=3, routed) 0.591 7.166 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 SLICE_X119Y240 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.973 10.688 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X119Y240 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.136 10.824 clock uncertainty -0.035 10.789 SLICE_X119Y240 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 10.731 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 10.731 arrival time -7.166 ------------------------------------------------------------------- slack 3.565 Slack (MET) : 3.571ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 4.512ns (logic 1.636ns (36.259%) route 2.876ns (63.741%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.371ns = ( 10.688 - 8.317 ) Source Clock Delay (SCD): 2.651ns Clock Pessimism Removal (CPR): 0.136ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.176ns (routing 0.630ns, distribution 1.546ns) Clock Net Delay (Destination): 1.973ns (routing 0.571ns, distribution 1.402ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.176 2.651 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.812 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.106 5.918 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X120Y242 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.156 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/O net (fo=5, routed) 0.182 6.338 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X120Y241 LUT6 (Prop_B6LUT_SLICEL_I5_O) 0.237 6.575 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__11/O net (fo=3, routed) 0.588 7.163 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 SLICE_X119Y240 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.973 10.688 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X119Y240 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.136 10.824 clock uncertainty -0.035 10.789 SLICE_X119Y240 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 10.734 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 10.734 arrival time -7.163 ------------------------------------------------------------------- slack 3.571 Slack (MET) : 3.632ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 4.447ns (logic 1.625ns (36.541%) route 2.822ns (63.459%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.370ns = ( 10.687 - 8.317 ) Source Clock Delay (SCD): 2.651ns Clock Pessimism Removal (CPR): 0.136ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.176ns (routing 0.630ns, distribution 1.546ns) Clock Net Delay (Destination): 1.972ns (routing 0.571ns, distribution 1.401ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.176 2.651 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.812 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.106 5.918 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X120Y242 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.156 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/O net (fo=5, routed) 0.277 6.433 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X119Y241 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.226 6.659 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/O net (fo=7, routed) 0.439 7.098 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 SLICE_X119Y242 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.972 10.687 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X119Y242 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.136 10.823 clock uncertainty -0.035 10.788 SLICE_X119Y242 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 10.730 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 10.730 arrival time -7.098 ------------------------------------------------------------------- slack 3.632 Slack (MET) : 3.638ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 4.444ns (logic 1.625ns (36.566%) route 2.819ns (63.434%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.370ns = ( 10.687 - 8.317 ) Source Clock Delay (SCD): 2.651ns Clock Pessimism Removal (CPR): 0.136ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.176ns (routing 0.630ns, distribution 1.546ns) Clock Net Delay (Destination): 1.972ns (routing 0.571ns, distribution 1.401ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.176 2.651 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.812 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.106 5.918 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X120Y242 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.156 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/O net (fo=5, routed) 0.277 6.433 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X119Y241 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.226 6.659 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/O net (fo=7, routed) 0.436 7.095 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 SLICE_X119Y242 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.972 10.687 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X119Y242 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.136 10.823 clock uncertainty -0.035 10.788 SLICE_X119Y242 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 10.733 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 10.733 arrival time -7.095 ------------------------------------------------------------------- slack 3.638 Slack (MET) : 3.638ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 4.444ns (logic 1.625ns (36.566%) route 2.819ns (63.434%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.370ns = ( 10.687 - 8.317 ) Source Clock Delay (SCD): 2.651ns Clock Pessimism Removal (CPR): 0.136ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.176ns (routing 0.630ns, distribution 1.546ns) Clock Net Delay (Destination): 1.972ns (routing 0.571ns, distribution 1.401ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.176 2.651 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.812 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.106 5.918 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X120Y242 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.156 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/O net (fo=5, routed) 0.277 6.433 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X119Y241 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.226 6.659 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/O net (fo=7, routed) 0.436 7.095 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 SLICE_X119Y242 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.972 10.687 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X119Y242 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.136 10.823 clock uncertainty -0.035 10.788 SLICE_X119Y242 FDRE (Setup_GFF_SLICEM_C_CE) -0.055 10.733 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 10.733 arrival time -7.095 ------------------------------------------------------------------- slack 3.638 Slack (MET) : 3.742ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 4.346ns (logic 1.625ns (37.391%) route 2.721ns (62.609%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.379ns = ( 10.696 - 8.317 ) Source Clock Delay (SCD): 2.651ns Clock Pessimism Removal (CPR): 0.136ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.176ns (routing 0.630ns, distribution 1.546ns) Clock Net Delay (Destination): 1.981ns (routing 0.571ns, distribution 1.410ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.176 2.651 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.812 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.106 5.918 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X120Y242 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.156 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/O net (fo=5, routed) 0.277 6.433 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X119Y241 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.226 6.659 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/O net (fo=7, routed) 0.338 6.997 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 SLICE_X119Y241 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.981 10.696 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X119Y241 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.136 10.832 clock uncertainty -0.035 10.797 SLICE_X119Y241 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 10.739 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 10.739 arrival time -6.997 ------------------------------------------------------------------- slack 3.742 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.035ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.240ns (logic 0.102ns (42.500%) route 0.138ns (57.500%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.149ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.137ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.084ns Clock Net Delay (Source): 0.786ns (routing 0.275ns, distribution 0.511ns) Clock Net Delay (Destination): 0.972ns (routing 0.312ns, distribution 0.660ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X117Y239 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y239 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 0.953 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Q net (fo=2, routed) 0.122 1.075 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_11_in SLICE_X117Y240 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.053 1.128 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__10/O net (fo=1, routed) 0.016 1.144 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[4] SLICE_X117Y240 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.137 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X117Y240 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.084 1.053 SLICE_X117Y240 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.109 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.109 arrival time 1.144 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[39]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[39]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.241ns (logic 0.048ns (19.917%) route 0.193ns (80.083%)) Logic Levels: 0 Clock Path Skew: 0.149ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.184ns Source Clock Delay (SCD): 0.951ns Clock Pessimism Removal (CPR): 0.084ns Clock Net Delay (Source): 0.833ns (routing 0.275ns, distribution 0.558ns) Clock Net Delay (Destination): 1.019ns (routing 0.312ns, distribution 0.707ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.833 0.951 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X122Y239 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[39]/C ------------------------------------------------------------------- ------------------- SLICE_X122Y239 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 0.999 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[39]/Q net (fo=1, routed) 0.193 1.192 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[39] SLICE_X122Y240 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[39]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.019 1.184 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X122Y240 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[39]/C clock pessimism -0.084 1.100 SLICE_X122Y240 FDCE (Hold_DFF2_SLICEL_C_D) 0.056 1.156 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[39] ------------------------------------------------------------------- required time -1.156 arrival time 1.192 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.039ns (arrival time - required time) Source: SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[23]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[11].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[7]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.230ns (logic 0.049ns (21.304%) route 0.181ns (78.696%)) Logic Levels: 0 Clock Path Skew: 0.135ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.133ns Source Clock Delay (SCD): 0.914ns Clock Pessimism Removal (CPR): 0.084ns Clock Net Delay (Source): 0.796ns (routing 0.275ns, distribution 0.521ns) Clock Net Delay (Destination): 0.968ns (routing 0.312ns, distribution 0.656ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.796 0.914 SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X115Y237 FDCE r SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[23]/C ------------------------------------------------------------------- ------------------- SLICE_X115Y237 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 0.963 r SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[23]/Q net (fo=5, routed) 0.181 1.144 SFP_GEN[11].ngCCM_gbt/gbt_rx_checker/Q[7] SLICE_X113Y240 FDRE r SFP_GEN[11].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[7]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.968 1.133 SFP_GEN[11].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X113Y240 FDRE r SFP_GEN[11].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[7]/C clock pessimism -0.084 1.049 SLICE_X113Y240 FDRE (Hold_GFF2_SLICEM_C_D) 0.056 1.105 SFP_GEN[11].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[7] ------------------------------------------------------------------- required time -1.105 arrival time 1.144 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[11].rx_data_ngccm_reg[11][34]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.192ns (logic 0.048ns (25.000%) route 0.144ns (75.000%)) Logic Levels: 0 Clock Path Skew: 0.097ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.105ns Source Clock Delay (SCD): 0.924ns Clock Pessimism Removal (CPR): 0.084ns Clock Net Delay (Source): 0.806ns (routing 0.275ns, distribution 0.531ns) Clock Net Delay (Destination): 0.940ns (routing 0.312ns, distribution 0.628ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.806 0.924 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X117Y241 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y241 FDRE (Prop_HFF_SLICEL_C_Q) 0.048 0.972 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/Q net (fo=1, routed) 0.144 1.116 rx_data[11][34] SLICE_X117Y239 FDCE r SFP_GEN[11].rx_data_ngccm_reg[11][34]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.940 1.105 RX_WORDCLK_O[11] SLICE_X117Y239 FDCE r SFP_GEN[11].rx_data_ngccm_reg[11][34]/C clock pessimism -0.084 1.021 SLICE_X117Y239 FDCE (Hold_FFF_SLICEL_C_D) 0.056 1.077 SFP_GEN[11].rx_data_ngccm_reg[11][34] ------------------------------------------------------------------- required time -1.077 arrival time 1.116 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[23]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[23]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.179ns (logic 0.049ns (27.374%) route 0.130ns (72.626%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.173ns Source Clock Delay (SCD): 0.955ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.837ns (routing 0.275ns, distribution 0.562ns) Clock Net Delay (Destination): 1.008ns (routing 0.312ns, distribution 0.696ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.837 0.955 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X123Y237 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[23]/C ------------------------------------------------------------------- ------------------- SLICE_X123Y237 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 1.004 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[23]/Q net (fo=1, routed) 0.130 1.134 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[23] SLICE_X122Y237 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.173 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X122Y237 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[23]/C clock pessimism -0.134 1.039 SLICE_X122Y237 FDCE (Hold_HFF2_SLICEL_C_D) 0.056 1.095 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[23] ------------------------------------------------------------------- required time -1.095 arrival time 1.134 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.245ns (logic 0.112ns (45.714%) route 0.133ns (54.286%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.149ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.137ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.084ns Clock Net Delay (Source): 0.786ns (routing 0.275ns, distribution 0.511ns) Clock Net Delay (Destination): 0.972ns (routing 0.312ns, distribution 0.660ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X117Y239 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y239 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 0.953 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Q net (fo=2, routed) 0.122 1.075 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_11_in SLICE_X117Y240 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.063 1.138 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__10/O net (fo=1, routed) 0.011 1.149 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[6] SLICE_X117Y240 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.137 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X117Y240 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C clock pessimism -0.084 1.053 SLICE_X117Y240 FDRE (Hold_DFF2_SLICEL_C_D) 0.056 1.109 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6] ------------------------------------------------------------------- required time -1.109 arrival time 1.149 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.242ns (logic 0.119ns (49.174%) route 0.123ns (50.826%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.146ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.134ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.084ns Clock Net Delay (Source): 0.786ns (routing 0.275ns, distribution 0.511ns) Clock Net Delay (Destination): 0.969ns (routing 0.312ns, distribution 0.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X117Y239 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y239 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.953 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.109 1.062 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_35_in SLICE_X117Y240 LUT3 (Prop_G6LUT_SLICEL_I2_O) 0.070 1.132 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__10/O net (fo=1, routed) 0.014 1.146 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[16] SLICE_X117Y240 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.969 1.134 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X117Y240 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.084 1.050 SLICE_X117Y240 FDRE (Hold_GFF_SLICEL_C_D) 0.056 1.106 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.106 arrival time 1.146 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[54]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[54]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.235ns (logic 0.048ns (20.426%) route 0.187ns (79.574%)) Logic Levels: 0 Clock Path Skew: 0.137ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.174ns Source Clock Delay (SCD): 0.953ns Clock Pessimism Removal (CPR): 0.084ns Clock Net Delay (Source): 0.835ns (routing 0.275ns, distribution 0.560ns) Clock Net Delay (Destination): 1.009ns (routing 0.312ns, distribution 0.697ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.835 0.953 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X124Y239 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[54]/C ------------------------------------------------------------------- ------------------- SLICE_X124Y239 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 1.001 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[54]/Q net (fo=1, routed) 0.187 1.188 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[54] SLICE_X123Y243 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[54]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.009 1.174 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X123Y243 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[54]/C clock pessimism -0.084 1.090 SLICE_X123Y243 FDCE (Hold_BFF_SLICEL_C_D) 0.056 1.146 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[54] ------------------------------------------------------------------- required time -1.146 arrival time 1.188 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.165ns (logic 0.078ns (47.273%) route 0.087ns (52.727%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.126ns Source Clock Delay (SCD): 0.928ns Clock Pessimism Removal (CPR): 0.131ns Clock Net Delay (Source): 0.810ns (routing 0.275ns, distribution 0.535ns) Clock Net Delay (Destination): 0.961ns (routing 0.312ns, distribution 0.649ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.810 0.928 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X118Y241 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y241 FDCE (Prop_FFF2_SLICEM_C_Q) 0.048 0.976 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.075 1.051 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/feedbackRegister[1] SLICE_X117Y241 LUT3 (Prop_F6LUT_SLICEL_I0_O) 0.030 1.081 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[20]_i_2__10/O net (fo=1, routed) 0.012 1.093 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[1] SLICE_X117Y241 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.961 1.126 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X117Y241 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C clock pessimism -0.131 0.995 SLICE_X117Y241 FDRE (Hold_FFF_SLICEL_C_D) 0.056 1.051 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20] ------------------------------------------------------------------- required time -1.051 arrival time 1.093 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[11].rx_data_ngccm_reg[11][39]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.193ns (logic 0.048ns (24.870%) route 0.145ns (75.130%)) Logic Levels: 0 Clock Path Skew: 0.093ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.105ns Source Clock Delay (SCD): 0.928ns Clock Pessimism Removal (CPR): 0.084ns Clock Net Delay (Source): 0.810ns (routing 0.275ns, distribution 0.535ns) Clock Net Delay (Destination): 0.940ns (routing 0.312ns, distribution 0.628ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.810 0.928 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X117Y240 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y240 FDRE (Prop_GFF2_SLICEL_C_Q) 0.048 0.976 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/Q net (fo=1, routed) 0.145 1.121 rx_data[11][39] SLICE_X117Y239 FDCE r SFP_GEN[11].rx_data_ngccm_reg[11][39]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.940 1.105 RX_WORDCLK_O[11] SLICE_X117Y239 FDCE r SFP_GEN[11].rx_data_ngccm_reg[11][39]/C clock pessimism -0.084 1.021 SLICE_X117Y239 FDCE (Hold_HFF2_SLICEL_C_D) 0.056 1.077 SFP_GEN[11].rx_data_ngccm_reg[11][39] ------------------------------------------------------------------- required time -1.077 arrival time 1.121 ------------------------------------------------------------------- slack 0.044 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_2 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y88 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X119Y239 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X119Y239 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X119Y238 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X119Y238 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X119Y240 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X119Y238 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X119Y238 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X119Y238 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X119Y238 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X119Y238 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X122Y238 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X122Y238 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X122Y238 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X122Y238 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X122Y238 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X122Y238 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X122Y238 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X128Y233 g_gbt_bank[0].gbtbank/i_gbt_bank/g_rx_data_good[11].rx_data_good_cntr_reg[11][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X128Y233 g_gbt_bank[0].gbtbank/i_gbt_bank/g_rx_data_good[11].rx_data_good_cntr_reg[11][1]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.037 0.493 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.037 1.292 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_3 To Clock: gtwiz_userclk_rx_srcclk_out[0]_3 Setup : 0 Failing Endpoints, Worst Slack 1.821ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.031ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.493ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.821ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 5.848ns (logic 1.563ns (26.727%) route 4.285ns (73.273%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.559ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.039ns = ( 11.356 - 8.317 ) Source Clock Delay (SCD): 3.888ns Clock Pessimism Removal (CPR): 0.290ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.413ns (routing 1.459ns, distribution 1.954ns) Clock Net Delay (Destination): 2.641ns (routing 1.332ns, distribution 1.309ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.413 3.888 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.974 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.366 8.340 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X84Y82 LUT4 (Prop_C6LUT_SLICEL_I0_O) 0.235 8.575 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/O net (fo=5, routed) 0.345 8.920 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y82 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.092 9.012 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__0/O net (fo=1, routed) 0.162 9.174 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__0_n_0 SLICE_X85Y83 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.150 9.324 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__0/O net (fo=2, routed) 0.412 9.736 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__0_n_0 SLICE_X84Y82 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.641 11.356 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y82 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.290 11.646 clock uncertainty -0.035 11.611 SLICE_X84Y82 FDCE (Setup_AFF_SLICEL_C_CE) -0.054 11.557 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.557 arrival time -9.736 ------------------------------------------------------------------- slack 1.821 Slack (MET) : 1.821ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 5.848ns (logic 1.563ns (26.727%) route 4.285ns (73.273%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.559ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.039ns = ( 11.356 - 8.317 ) Source Clock Delay (SCD): 3.888ns Clock Pessimism Removal (CPR): 0.290ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.413ns (routing 1.459ns, distribution 1.954ns) Clock Net Delay (Destination): 2.641ns (routing 1.332ns, distribution 1.309ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.413 3.888 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.974 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.366 8.340 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X84Y82 LUT4 (Prop_C6LUT_SLICEL_I0_O) 0.235 8.575 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/O net (fo=5, routed) 0.345 8.920 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y82 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.092 9.012 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__0/O net (fo=1, routed) 0.162 9.174 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__0_n_0 SLICE_X85Y83 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.150 9.324 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__0/O net (fo=2, routed) 0.412 9.736 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__0_n_0 SLICE_X84Y82 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.641 11.356 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y82 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.290 11.646 clock uncertainty -0.035 11.611 SLICE_X84Y82 FDCE (Setup_DFF_SLICEL_C_CE) -0.054 11.557 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.557 arrival time -9.736 ------------------------------------------------------------------- slack 1.821 Slack (MET) : 1.867ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[1].rx_data_ngccm_reg[1][42]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 5.695ns (logic 0.383ns (6.725%) route 5.312ns (93.275%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.665ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.047ns = ( 11.364 - 8.317 ) Source Clock Delay (SCD): 4.002ns Clock Pessimism Removal (CPR): 0.290ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.527ns (routing 1.459ns, distribution 2.068ns) Clock Net Delay (Destination): 2.649ns (routing 1.332ns, distribution 1.317ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.527 4.002 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y82 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y82 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.141 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.308 7.449 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X85Y85 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 7.693 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[1].rx_data_ngccm[1][83]_i_1/O net (fo=76, routed) 2.004 9.697 rx_data_ngccm[1] SLICE_X74Y74 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][42]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.649 11.364 RX_WORDCLK_O[1] SLICE_X74Y74 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][42]/C clock pessimism 0.290 11.654 clock uncertainty -0.035 11.619 SLICE_X74Y74 FDCE (Setup_EFF_SLICEL_C_CE) -0.055 11.564 SFP_GEN[1].rx_data_ngccm_reg[1][42] ------------------------------------------------------------------- required time 11.564 arrival time -9.697 ------------------------------------------------------------------- slack 1.867 Slack (MET) : 1.908ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[1].rx_data_ngccm_reg[1][43]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 5.662ns (logic 0.383ns (6.764%) route 5.279ns (93.236%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.657ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.055ns = ( 11.372 - 8.317 ) Source Clock Delay (SCD): 4.002ns Clock Pessimism Removal (CPR): 0.290ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.527ns (routing 1.459ns, distribution 2.068ns) Clock Net Delay (Destination): 2.657ns (routing 1.332ns, distribution 1.325ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.527 4.002 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y82 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y82 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.141 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.308 7.449 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X85Y85 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 7.693 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[1].rx_data_ngccm[1][83]_i_1/O net (fo=76, routed) 1.971 9.664 rx_data_ngccm[1] SLICE_X72Y75 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][43]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.657 11.372 RX_WORDCLK_O[1] SLICE_X72Y75 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][43]/C clock pessimism 0.290 11.662 clock uncertainty -0.035 11.627 SLICE_X72Y75 FDCE (Setup_EFF_SLICEL_C_CE) -0.055 11.572 SFP_GEN[1].rx_data_ngccm_reg[1][43] ------------------------------------------------------------------- required time 11.572 arrival time -9.664 ------------------------------------------------------------------- slack 1.908 Slack (MET) : 1.966ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[1].rx_data_ngccm_reg[1][47]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 5.619ns (logic 0.383ns (6.816%) route 5.236ns (93.184%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.639ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.074ns = ( 11.391 - 8.317 ) Source Clock Delay (SCD): 4.002ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.527ns (routing 1.459ns, distribution 2.068ns) Clock Net Delay (Destination): 2.676ns (routing 1.332ns, distribution 1.344ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.527 4.002 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y82 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y82 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.141 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.308 7.449 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X85Y85 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 7.693 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[1].rx_data_ngccm[1][83]_i_1/O net (fo=76, routed) 1.928 9.621 rx_data_ngccm[1] SLICE_X72Y70 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][47]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.676 11.391 RX_WORDCLK_O[1] SLICE_X72Y70 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][47]/C clock pessimism 0.289 11.681 clock uncertainty -0.035 11.645 SLICE_X72Y70 FDCE (Setup_EFF2_SLICEL_C_CE) -0.058 11.587 SFP_GEN[1].rx_data_ngccm_reg[1][47] ------------------------------------------------------------------- required time 11.587 arrival time -9.621 ------------------------------------------------------------------- slack 1.966 Slack (MET) : 1.966ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[1].rx_data_ngccm_reg[1][51]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 5.619ns (logic 0.383ns (6.816%) route 5.236ns (93.184%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.639ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.074ns = ( 11.391 - 8.317 ) Source Clock Delay (SCD): 4.002ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.527ns (routing 1.459ns, distribution 2.068ns) Clock Net Delay (Destination): 2.676ns (routing 1.332ns, distribution 1.344ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.527 4.002 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y82 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y82 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.141 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.308 7.449 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X85Y85 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 7.693 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[1].rx_data_ngccm[1][83]_i_1/O net (fo=76, routed) 1.928 9.621 rx_data_ngccm[1] SLICE_X72Y70 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][51]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.676 11.391 RX_WORDCLK_O[1] SLICE_X72Y70 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][51]/C clock pessimism 0.289 11.681 clock uncertainty -0.035 11.645 SLICE_X72Y70 FDCE (Setup_FFF2_SLICEL_C_CE) -0.058 11.587 SFP_GEN[1].rx_data_ngccm_reg[1][51] ------------------------------------------------------------------- required time 11.587 arrival time -9.621 ------------------------------------------------------------------- slack 1.966 Slack (MET) : 1.966ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[1].rx_data_ngccm_reg[1][72]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 5.619ns (logic 0.383ns (6.816%) route 5.236ns (93.184%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.639ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.074ns = ( 11.391 - 8.317 ) Source Clock Delay (SCD): 4.002ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.527ns (routing 1.459ns, distribution 2.068ns) Clock Net Delay (Destination): 2.676ns (routing 1.332ns, distribution 1.344ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.527 4.002 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y82 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y82 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.141 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.308 7.449 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X85Y85 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 7.693 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[1].rx_data_ngccm[1][83]_i_1/O net (fo=76, routed) 1.928 9.621 rx_data_ngccm[1] SLICE_X72Y70 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][72]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.676 11.391 RX_WORDCLK_O[1] SLICE_X72Y70 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][72]/C clock pessimism 0.289 11.681 clock uncertainty -0.035 11.645 SLICE_X72Y70 FDCE (Setup_GFF2_SLICEL_C_CE) -0.058 11.587 SFP_GEN[1].rx_data_ngccm_reg[1][72] ------------------------------------------------------------------- required time 11.587 arrival time -9.621 ------------------------------------------------------------------- slack 1.966 Slack (MET) : 1.966ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[1].rx_data_ngccm_reg[1][75]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 5.619ns (logic 0.383ns (6.816%) route 5.236ns (93.184%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.639ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.074ns = ( 11.391 - 8.317 ) Source Clock Delay (SCD): 4.002ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.527ns (routing 1.459ns, distribution 2.068ns) Clock Net Delay (Destination): 2.676ns (routing 1.332ns, distribution 1.344ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.527 4.002 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y82 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y82 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.141 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.308 7.449 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X85Y85 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 7.693 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[1].rx_data_ngccm[1][83]_i_1/O net (fo=76, routed) 1.928 9.621 rx_data_ngccm[1] SLICE_X72Y70 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][75]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.676 11.391 RX_WORDCLK_O[1] SLICE_X72Y70 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][75]/C clock pessimism 0.289 11.681 clock uncertainty -0.035 11.645 SLICE_X72Y70 FDCE (Setup_HFF2_SLICEL_C_CE) -0.058 11.587 SFP_GEN[1].rx_data_ngccm_reg[1][75] ------------------------------------------------------------------- required time 11.587 arrival time -9.621 ------------------------------------------------------------------- slack 1.966 Slack (MET) : 1.972ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[1].rx_data_ngccm_reg[1][46]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 5.616ns (logic 0.383ns (6.820%) route 5.233ns (93.180%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.639ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.074ns = ( 11.391 - 8.317 ) Source Clock Delay (SCD): 4.002ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.527ns (routing 1.459ns, distribution 2.068ns) Clock Net Delay (Destination): 2.676ns (routing 1.332ns, distribution 1.344ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.527 4.002 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y82 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y82 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.141 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.308 7.449 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X85Y85 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 7.693 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[1].rx_data_ngccm[1][83]_i_1/O net (fo=76, routed) 1.925 9.618 rx_data_ngccm[1] SLICE_X72Y70 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][46]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.676 11.391 RX_WORDCLK_O[1] SLICE_X72Y70 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][46]/C clock pessimism 0.289 11.681 clock uncertainty -0.035 11.645 SLICE_X72Y70 FDCE (Setup_EFF_SLICEL_C_CE) -0.055 11.590 SFP_GEN[1].rx_data_ngccm_reg[1][46] ------------------------------------------------------------------- required time 11.590 arrival time -9.618 ------------------------------------------------------------------- slack 1.972 Slack (MET) : 1.972ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[1].rx_data_ngccm_reg[1][50]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 5.616ns (logic 0.383ns (6.820%) route 5.233ns (93.180%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.639ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.074ns = ( 11.391 - 8.317 ) Source Clock Delay (SCD): 4.002ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.527ns (routing 1.459ns, distribution 2.068ns) Clock Net Delay (Destination): 2.676ns (routing 1.332ns, distribution 1.344ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.527 4.002 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y82 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y82 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.141 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.308 7.449 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X85Y85 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 7.693 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[1].rx_data_ngccm[1][83]_i_1/O net (fo=76, routed) 1.925 9.618 rx_data_ngccm[1] SLICE_X72Y70 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][50]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.676 11.391 RX_WORDCLK_O[1] SLICE_X72Y70 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][50]/C clock pessimism 0.289 11.681 clock uncertainty -0.035 11.645 SLICE_X72Y70 FDCE (Setup_FFF_SLICEL_C_CE) -0.055 11.590 SFP_GEN[1].rx_data_ngccm_reg[1][50] ------------------------------------------------------------------- required time 11.590 arrival time -9.618 ------------------------------------------------------------------- slack 1.972 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.031ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[1].rx_data_ngccm_reg[1][69]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.141ns (logic 0.048ns (34.043%) route 0.093ns (65.957%)) Logic Levels: 0 Clock Path Skew: 0.054ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.545ns Source Clock Delay (SCD): 1.292ns Clock Pessimism Removal (CPR): 0.199ns Clock Net Delay (Source): 1.174ns (routing 0.610ns, distribution 0.564ns) Clock Net Delay (Destination): 1.380ns (routing 0.686ns, distribution 0.694ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.174 1.292 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X74Y69 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X74Y69 FDRE (Prop_GFF2_SLICEL_C_Q) 0.048 1.340 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/Q net (fo=1, routed) 0.093 1.433 rx_data[1][69] SLICE_X74Y70 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][69]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.380 1.545 RX_WORDCLK_O[1] SLICE_X74Y70 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][69]/C clock pessimism -0.199 1.346 SLICE_X74Y70 FDCE (Hold_BFF2_SLICEL_C_D) 0.056 1.402 SFP_GEN[1].rx_data_ngccm_reg[1][69] ------------------------------------------------------------------- required time -1.402 arrival time 1.433 ------------------------------------------------------------------- slack 0.031 Slack (MET) : 0.032ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[35]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.177ns (logic 0.078ns (44.068%) route 0.099ns (55.932%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.533ns Source Clock Delay (SCD): 1.276ns Clock Pessimism Removal (CPR): 0.168ns Clock Net Delay (Source): 1.158ns (routing 0.610ns, distribution 0.548ns) Clock Net Delay (Destination): 1.368ns (routing 0.686ns, distribution 0.682ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.158 1.276 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X79Y77 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y77 FDCE (Prop_GFF_SLICEM_C_Q) 0.048 1.324 f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Q net (fo=27, routed) 0.087 1.411 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] SLICE_X78Y77 LUT5 (Prop_E6LUT_SLICEL_I1_O) 0.030 1.441 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[35]_i_1/O net (fo=1, routed) 0.012 1.453 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg00[35] SLICE_X78Y77 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[35]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.368 1.533 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X78Y77 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[35]/C clock pessimism -0.168 1.365 SLICE_X78Y77 FDCE (Hold_EFF_SLICEL_C_D) 0.056 1.421 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[35] ------------------------------------------------------------------- required time -1.421 arrival time 1.453 ------------------------------------------------------------------- slack 0.032 Slack (MET) : 0.033ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[34]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.178ns (logic 0.078ns (43.820%) route 0.100ns (56.180%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.533ns Source Clock Delay (SCD): 1.276ns Clock Pessimism Removal (CPR): 0.168ns Clock Net Delay (Source): 1.158ns (routing 0.610ns, distribution 0.548ns) Clock Net Delay (Destination): 1.368ns (routing 0.686ns, distribution 0.682ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.158 1.276 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X79Y77 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y77 FDCE (Prop_GFF_SLICEM_C_Q) 0.048 1.324 f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Q net (fo=27, routed) 0.088 1.412 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] SLICE_X78Y77 LUT5 (Prop_F6LUT_SLICEL_I1_O) 0.030 1.442 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[34]_i_1/O net (fo=1, routed) 0.012 1.454 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg00[34] SLICE_X78Y77 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[34]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.368 1.533 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X78Y77 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[34]/C clock pessimism -0.168 1.365 SLICE_X78Y77 FDCE (Hold_FFF_SLICEL_C_D) 0.056 1.421 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[34] ------------------------------------------------------------------- required time -1.421 arrival time 1.454 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[23]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.185ns (logic 0.079ns (42.703%) route 0.106ns (57.297%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.533ns Source Clock Delay (SCD): 1.276ns Clock Pessimism Removal (CPR): 0.168ns Clock Net Delay (Source): 1.158ns (routing 0.610ns, distribution 0.548ns) Clock Net Delay (Destination): 1.368ns (routing 0.686ns, distribution 0.682ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.158 1.276 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X79Y77 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y77 FDCE (Prop_GFF_SLICEM_C_Q) 0.048 1.324 f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Q net (fo=27, routed) 0.090 1.414 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] SLICE_X78Y77 LUT5 (Prop_H6LUT_SLICEL_I1_O) 0.031 1.445 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[23]_i_1/O net (fo=1, routed) 0.016 1.461 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg00[23] SLICE_X78Y77 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[23]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.368 1.533 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X78Y77 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[23]/C clock pessimism -0.168 1.365 SLICE_X78Y77 FDCE (Hold_HFF_SLICEL_C_D) 0.056 1.421 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[23] ------------------------------------------------------------------- required time -1.421 arrival time 1.461 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.041ns (arrival time - required time) Source: SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.164ns (logic 0.049ns (29.878%) route 0.115ns (70.122%)) Logic Levels: 0 Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.503ns Source Clock Delay (SCD): 1.268ns Clock Pessimism Removal (CPR): 0.168ns Clock Net Delay (Source): 1.150ns (routing 0.610ns, distribution 0.540ns) Clock Net Delay (Destination): 1.338ns (routing 0.686ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.150 1.268 SFP_GEN[1].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X83Y80 FDCE r SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X83Y80 FDCE (Prop_AFF2_SLICEM_C_Q) 0.049 1.317 r SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[18]/Q net (fo=5, routed) 0.115 1.432 SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/Q[2] SLICE_X85Y80 FDRE r SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.338 1.503 SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y80 FDRE r SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/C clock pessimism -0.168 1.335 SLICE_X85Y80 FDRE (Hold_DFF2_SLICEM_C_D) 0.056 1.391 SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2] ------------------------------------------------------------------- required time -1.391 arrival time 1.432 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[30]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.156ns (logic 0.063ns (40.385%) route 0.093ns (59.615%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.057ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.533ns Source Clock Delay (SCD): 1.276ns Clock Pessimism Removal (CPR): 0.200ns Clock Net Delay (Source): 1.158ns (routing 0.610ns, distribution 0.548ns) Clock Net Delay (Destination): 1.368ns (routing 0.686ns, distribution 0.682ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.158 1.276 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X79Y77 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y77 FDCE (Prop_HFF_SLICEM_C_Q) 0.048 1.324 f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/Q net (fo=28, routed) 0.079 1.403 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] SLICE_X79Y78 LUT5 (Prop_G6LUT_SLICEM_I0_O) 0.015 1.418 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[30]_i_1/O net (fo=1, routed) 0.014 1.432 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg00[30] SLICE_X79Y78 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[30]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.368 1.533 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X79Y78 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[30]/C clock pessimism -0.200 1.333 SLICE_X79Y78 FDCE (Hold_GFF_SLICEM_C_D) 0.056 1.389 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[30] ------------------------------------------------------------------- required time -1.389 arrival time 1.432 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.045ns (arrival time - required time) Source: SFP_GEN[1].rx_data_ngccm_reg[1][35]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[34]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.088ns (50.867%) route 0.085ns (49.133%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.509ns Source Clock Delay (SCD): 1.269ns Clock Pessimism Removal (CPR): 0.168ns Clock Net Delay (Source): 1.151ns (routing 0.610ns, distribution 0.541ns) Clock Net Delay (Destination): 1.344ns (routing 0.686ns, distribution 0.658ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.151 1.269 RX_WORDCLK_O[1] SLICE_X81Y79 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][35]/C ------------------------------------------------------------------- ------------------- SLICE_X81Y79 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 1.317 r SFP_GEN[1].rx_data_ngccm_reg[1][35]/Q net (fo=1, routed) 0.073 1.390 SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[83]_0[27] SLICE_X82Y79 LUT3 (Prop_D5LUT_SLICEM_I0_O) 0.040 1.430 r SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[34]_i_1/O net (fo=1, routed) 0.012 1.442 SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[34]_i_1_n_0 SLICE_X82Y79 FDCE r SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[34]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.344 1.509 SFP_GEN[1].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y79 FDCE r SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[34]/C clock pessimism -0.168 1.341 SLICE_X82Y79 FDCE (Hold_DFF2_SLICEM_C_D) 0.056 1.397 SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[34] ------------------------------------------------------------------- required time -1.397 arrival time 1.442 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: SFP_GEN[1].rx_data_ngccm_reg[1][48]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[48]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.103ns (66.883%) route 0.051ns (33.117%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.546ns Source Clock Delay (SCD): 1.294ns Clock Pessimism Removal (CPR): 0.199ns Clock Net Delay (Source): 1.176ns (routing 0.610ns, distribution 0.566ns) Clock Net Delay (Destination): 1.381ns (routing 0.686ns, distribution 0.695ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.176 1.294 RX_WORDCLK_O[1] SLICE_X71Y71 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][48]/C ------------------------------------------------------------------- ------------------- SLICE_X71Y71 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.343 r SFP_GEN[1].rx_data_ngccm_reg[1][48]/Q net (fo=1, routed) 0.035 1.378 SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[83]_0[40] SLICE_X71Y70 LUT3 (Prop_D6LUT_SLICEM_I1_O) 0.054 1.432 r SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[48]_i_1/O net (fo=1, routed) 0.016 1.448 SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[48]_i_1_n_0 SLICE_X71Y70 FDCE r SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[48]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.381 1.546 SFP_GEN[1].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X71Y70 FDCE r SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[48]/C clock pessimism -0.199 1.347 SLICE_X71Y70 FDCE (Hold_DFF_SLICEM_C_D) 0.056 1.403 SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[48] ------------------------------------------------------------------- required time -1.403 arrival time 1.448 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.545ns Source Clock Delay (SCD): 1.291ns Clock Pessimism Removal (CPR): 0.212ns Clock Net Delay (Source): 1.173ns (routing 0.610ns, distribution 0.563ns) Clock Net Delay (Destination): 1.380ns (routing 0.686ns, distribution 0.694ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.173 1.291 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X74Y72 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X74Y72 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.340 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.034 1.374 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_35_in SLICE_X74Y72 LUT3 (Prop_C6LUT_SLICEL_I2_O) 0.045 1.419 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__0/O net (fo=1, routed) 0.016 1.435 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] SLICE_X74Y72 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.380 1.545 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X74Y72 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.212 1.333 SLICE_X74Y72 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.389 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.389 arrival time 1.435 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.188ns (logic 0.094ns (50.000%) route 0.094ns (50.000%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.545ns Source Clock Delay (SCD): 1.293ns Clock Pessimism Removal (CPR): 0.167ns Clock Net Delay (Source): 1.175ns (routing 0.610ns, distribution 0.565ns) Clock Net Delay (Destination): 1.380ns (routing 0.686ns, distribution 0.694ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.175 1.293 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X73Y72 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X73Y72 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.342 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Q net (fo=2, routed) 0.078 1.420 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_25_in SLICE_X72Y72 LUT3 (Prop_C6LUT_SLICEL_I2_O) 0.045 1.465 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__0/O net (fo=1, routed) 0.016 1.481 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[11] SLICE_X72Y72 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.380 1.545 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X72Y72 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C clock pessimism -0.167 1.378 SLICE_X72Y72 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.434 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11] ------------------------------------------------------------------- required time -1.434 arrival time 1.481 ------------------------------------------------------------------- slack 0.047 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_3 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y45 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X83Y86 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X83Y86 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X83Y87 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X83Y87 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X83Y87 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X83Y87 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X83Y88 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y86 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y86 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y87 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y87 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y87 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y87 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/C High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y86 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y88 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y88 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X81Y88 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y86 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][5]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X71Y78 g_gbt_bank[0].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][0]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.037 0.493 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.037 1.291 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_4 To Clock: gtwiz_userclk_rx_srcclk_out[0]_4 Setup : 0 Failing Endpoints, Worst Slack 1.978ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.039ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.978ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 5.676ns (logic 1.657ns (29.193%) route 4.019ns (70.807%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.573ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.033ns = ( 11.350 - 8.317 ) Source Clock Delay (SCD): 3.895ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.420ns (routing 1.458ns, distribution 1.962ns) Clock Net Delay (Destination): 2.635ns (routing 1.333ns, distribution 1.302ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.420 3.895 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.981 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.189 8.170 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X79Y93 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.171 8.341 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/O net (fo=5, routed) 0.276 8.617 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X80Y92 LUT4 (Prop_B5LUT_SLICEL_I2_O) 0.253 8.870 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__1/O net (fo=1, routed) 0.142 9.012 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__1_n_0 SLICE_X80Y92 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 9.159 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__1/O net (fo=2, routed) 0.412 9.571 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__1_n_0 SLICE_X80Y93 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.635 11.350 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y93 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.289 11.639 clock uncertainty -0.035 11.604 SLICE_X80Y93 FDCE (Setup_GFF_SLICEL_C_CE) -0.055 11.549 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.549 arrival time -9.571 ------------------------------------------------------------------- slack 1.978 Slack (MET) : 1.978ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 5.676ns (logic 1.657ns (29.193%) route 4.019ns (70.807%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.573ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.033ns = ( 11.350 - 8.317 ) Source Clock Delay (SCD): 3.895ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.420ns (routing 1.458ns, distribution 1.962ns) Clock Net Delay (Destination): 2.635ns (routing 1.333ns, distribution 1.302ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.420 3.895 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.981 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.189 8.170 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X79Y93 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.171 8.341 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/O net (fo=5, routed) 0.276 8.617 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X80Y92 LUT4 (Prop_B5LUT_SLICEL_I2_O) 0.253 8.870 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__1/O net (fo=1, routed) 0.142 9.012 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__1_n_0 SLICE_X80Y92 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 9.159 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__1/O net (fo=2, routed) 0.412 9.571 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__1_n_0 SLICE_X80Y93 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.635 11.350 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y93 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.289 11.639 clock uncertainty -0.035 11.604 SLICE_X80Y93 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 11.549 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.549 arrival time -9.571 ------------------------------------------------------------------- slack 1.978 Slack (MET) : 2.179ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 5.459ns (logic 1.476ns (27.038%) route 3.983ns (72.962%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.589ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.017ns = ( 11.334 - 8.317 ) Source Clock Delay (SCD): 3.895ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.420ns (routing 1.458ns, distribution 1.962ns) Clock Net Delay (Destination): 2.619ns (routing 1.333ns, distribution 1.286ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.420 3.895 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.981 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.189 8.170 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X79Y93 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.171 8.341 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/O net (fo=5, routed) 0.275 8.616 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X80Y92 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.219 8.835 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__2/O net (fo=7, routed) 0.519 9.354 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X82Y93 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.619 11.334 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y93 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.289 11.623 clock uncertainty -0.035 11.588 SLICE_X82Y93 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 11.533 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.533 arrival time -9.354 ------------------------------------------------------------------- slack 2.179 Slack (MET) : 2.179ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 5.459ns (logic 1.476ns (27.038%) route 3.983ns (72.962%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.589ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.017ns = ( 11.334 - 8.317 ) Source Clock Delay (SCD): 3.895ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.420ns (routing 1.458ns, distribution 1.962ns) Clock Net Delay (Destination): 2.619ns (routing 1.333ns, distribution 1.286ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.420 3.895 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.981 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.189 8.170 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X79Y93 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.171 8.341 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/O net (fo=5, routed) 0.275 8.616 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X80Y92 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.219 8.835 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__2/O net (fo=7, routed) 0.519 9.354 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X82Y93 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.619 11.334 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y93 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.289 11.623 clock uncertainty -0.035 11.588 SLICE_X82Y93 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 11.533 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.533 arrival time -9.354 ------------------------------------------------------------------- slack 2.179 Slack (MET) : 2.183ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 5.456ns (logic 1.476ns (27.053%) route 3.980ns (72.947%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.589ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.017ns = ( 11.334 - 8.317 ) Source Clock Delay (SCD): 3.895ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.420ns (routing 1.458ns, distribution 1.962ns) Clock Net Delay (Destination): 2.619ns (routing 1.333ns, distribution 1.286ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.420 3.895 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.981 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.189 8.170 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X79Y93 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.171 8.341 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/O net (fo=5, routed) 0.275 8.616 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X80Y92 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.219 8.835 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__2/O net (fo=7, routed) 0.516 9.351 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X82Y93 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.619 11.334 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y93 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.289 11.623 clock uncertainty -0.035 11.588 SLICE_X82Y93 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 11.534 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 11.534 arrival time -9.351 ------------------------------------------------------------------- slack 2.183 Slack (MET) : 2.183ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 5.456ns (logic 1.476ns (27.053%) route 3.980ns (72.947%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.589ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.017ns = ( 11.334 - 8.317 ) Source Clock Delay (SCD): 3.895ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.420ns (routing 1.458ns, distribution 1.962ns) Clock Net Delay (Destination): 2.619ns (routing 1.333ns, distribution 1.286ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.420 3.895 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.981 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.189 8.170 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X79Y93 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.171 8.341 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/O net (fo=5, routed) 0.275 8.616 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X80Y92 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.219 8.835 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__2/O net (fo=7, routed) 0.516 9.351 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X82Y93 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.619 11.334 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y93 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.289 11.623 clock uncertainty -0.035 11.588 SLICE_X82Y93 FDRE (Setup_BFF_SLICEM_C_CE) -0.054 11.534 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 11.534 arrival time -9.351 ------------------------------------------------------------------- slack 2.183 Slack (MET) : 2.183ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 5.456ns (logic 1.476ns (27.053%) route 3.980ns (72.947%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.589ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.017ns = ( 11.334 - 8.317 ) Source Clock Delay (SCD): 3.895ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.420ns (routing 1.458ns, distribution 1.962ns) Clock Net Delay (Destination): 2.619ns (routing 1.333ns, distribution 1.286ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.420 3.895 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.981 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.189 8.170 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X79Y93 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.171 8.341 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/O net (fo=5, routed) 0.275 8.616 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X80Y92 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.219 8.835 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__2/O net (fo=7, routed) 0.516 9.351 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X82Y93 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.619 11.334 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y93 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.289 11.623 clock uncertainty -0.035 11.588 SLICE_X82Y93 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 11.534 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.534 arrival time -9.351 ------------------------------------------------------------------- slack 2.183 Slack (MET) : 2.373ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 5.263ns (logic 1.409ns (26.772%) route 3.854ns (73.228%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.588ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.018ns = ( 11.335 - 8.317 ) Source Clock Delay (SCD): 3.895ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.420ns (routing 1.458ns, distribution 1.962ns) Clock Net Delay (Destination): 2.620ns (routing 1.333ns, distribution 1.287ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.420 3.895 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.981 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.189 8.170 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X79Y93 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.171 8.341 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/O net (fo=5, routed) 0.177 8.518 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X79Y92 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.152 8.670 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__2/O net (fo=5, routed) 0.488 9.158 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecCorrectHeaders0 SLICE_X81Y92 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.620 11.335 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X81Y92 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.289 11.624 clock uncertainty -0.035 11.589 SLICE_X81Y92 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 11.531 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.531 arrival time -9.158 ------------------------------------------------------------------- slack 2.373 Slack (MET) : 2.373ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 5.263ns (logic 1.409ns (26.772%) route 3.854ns (73.228%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.588ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.018ns = ( 11.335 - 8.317 ) Source Clock Delay (SCD): 3.895ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.420ns (routing 1.458ns, distribution 1.962ns) Clock Net Delay (Destination): 2.620ns (routing 1.333ns, distribution 1.287ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.420 3.895 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.981 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.189 8.170 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X79Y93 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.171 8.341 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/O net (fo=5, routed) 0.177 8.518 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X79Y92 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.152 8.670 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__2/O net (fo=5, routed) 0.488 9.158 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecCorrectHeaders0 SLICE_X81Y92 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.620 11.335 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X81Y92 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.289 11.624 clock uncertainty -0.035 11.589 SLICE_X81Y92 FDRE (Setup_GFF2_SLICEL_C_CE) -0.058 11.531 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 11.531 arrival time -9.158 ------------------------------------------------------------------- slack 2.373 Slack (MET) : 2.380ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 5.259ns (logic 1.409ns (26.792%) route 3.850ns (73.208%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.588ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.018ns = ( 11.335 - 8.317 ) Source Clock Delay (SCD): 3.895ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.420ns (routing 1.458ns, distribution 1.962ns) Clock Net Delay (Destination): 2.620ns (routing 1.333ns, distribution 1.287ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.420 3.895 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.981 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.189 8.170 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X79Y93 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.171 8.341 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/O net (fo=5, routed) 0.177 8.518 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X79Y92 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.152 8.670 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__2/O net (fo=5, routed) 0.484 9.154 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecCorrectHeaders0 SLICE_X81Y92 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.620 11.335 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X81Y92 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C clock pessimism 0.289 11.624 clock uncertainty -0.035 11.589 SLICE_X81Y92 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 11.534 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0] ------------------------------------------------------------------- required time 11.534 arrival time -9.154 ------------------------------------------------------------------- slack 2.380 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.167ns (logic 0.078ns (46.707%) route 0.089ns (53.293%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.498ns Source Clock Delay (SCD): 1.255ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 1.137ns (routing 0.607ns, distribution 0.530ns) Clock Net Delay (Destination): 1.333ns (routing 0.684ns, distribution 0.649ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.137 1.255 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X76Y91 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X76Y91 FDCE (Prop_BFF2_SLICEM_C_Q) 0.048 1.303 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Q net (fo=2, routed) 0.074 1.377 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_5_in SLICE_X75Y91 LUT3 (Prop_B6LUT_SLICEL_I2_O) 0.030 1.407 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__1/O net (fo=1, routed) 0.015 1.422 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[1] SLICE_X75Y91 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.333 1.498 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X75Y91 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.171 1.327 SLICE_X75Y91 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.383 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.383 arrival time 1.422 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.526ns Source Clock Delay (SCD): 1.270ns Clock Pessimism Removal (CPR): 0.212ns Clock Net Delay (Source): 1.152ns (routing 0.607ns, distribution 0.545ns) Clock Net Delay (Destination): 1.361ns (routing 0.684ns, distribution 0.677ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.152 1.270 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X72Y83 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y83 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.319 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Q net (fo=2, routed) 0.034 1.353 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_3_in SLICE_X72Y83 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.045 1.398 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__1/O net (fo=1, routed) 0.016 1.414 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[0] SLICE_X72Y83 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.361 1.526 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X72Y83 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.212 1.314 SLICE_X72Y83 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.370 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -1.370 arrival time 1.414 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.044ns (arrival time - required time) Source: SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[27]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[2].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.161ns (logic 0.049ns (30.435%) route 0.112ns (69.565%)) Logic Levels: 0 Clock Path Skew: 0.061ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.485ns Source Clock Delay (SCD): 1.253ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 1.135ns (routing 0.607ns, distribution 0.528ns) Clock Net Delay (Destination): 1.320ns (routing 0.684ns, distribution 0.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.135 1.253 SFP_GEN[2].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X78Y88 FDCE r SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y88 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 1.302 r SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[27]/Q net (fo=2, routed) 0.112 1.414 SFP_GEN[2].ngCCM_gbt/gbt_rx_checker/Q[11] SLICE_X79Y88 FDRE r SFP_GEN[2].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.320 1.485 SFP_GEN[2].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X79Y88 FDRE r SFP_GEN[2].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/C clock pessimism -0.171 1.314 SLICE_X79Y88 FDRE (Hold_GFF2_SLICEM_C_D) 0.056 1.370 SFP_GEN[2].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11] ------------------------------------------------------------------- required time -1.370 arrival time 1.414 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/shiftPsAddr_reg_inv/D (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.152ns (logic 0.064ns (42.105%) route 0.088ns (57.895%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.051ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.505ns Source Clock Delay (SCD): 1.252ns Clock Pessimism Removal (CPR): 0.202ns Clock Net Delay (Source): 1.134ns (routing 0.607ns, distribution 0.527ns) Clock Net Delay (Destination): 1.340ns (routing 0.684ns, distribution 0.656ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.134 1.252 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y94 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y94 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.301 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[2]/Q net (fo=6, routed) 0.073 1.374 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/bitSlipCnt[2] SLICE_X80Y93 LUT6 (Prop_B6LUT_SLICEL_I4_O) 0.015 1.389 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/shiftPsAddr_inv_i_1__2/O net (fo=1, routed) 0.015 1.404 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/shiftPsAddr3_out SLICE_X80Y93 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/shiftPsAddr_reg_inv/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.340 1.505 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y93 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/shiftPsAddr_reg_inv/C clock pessimism -0.202 1.303 SLICE_X80Y93 FDPE (Hold_BFF_SLICEL_C_D) 0.056 1.359 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/shiftPsAddr_reg_inv ------------------------------------------------------------------- required time -1.359 arrival time 1.404 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.086ns (49.711%) route 0.087ns (50.289%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.498ns Source Clock Delay (SCD): 1.255ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 1.137ns (routing 0.607ns, distribution 0.530ns) Clock Net Delay (Destination): 1.333ns (routing 0.684ns, distribution 0.649ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.137 1.255 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X76Y91 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X76Y91 FDCE (Prop_BFF2_SLICEM_C_Q) 0.048 1.303 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Q net (fo=2, routed) 0.074 1.377 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_5_in SLICE_X75Y91 LUT3 (Prop_B5LUT_SLICEL_I0_O) 0.038 1.415 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[3]_i_1__1/O net (fo=1, routed) 0.013 1.428 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[3] SLICE_X75Y91 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.333 1.498 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X75Y91 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C clock pessimism -0.171 1.327 SLICE_X75Y91 FDRE (Hold_BFF2_SLICEL_C_D) 0.056 1.383 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3] ------------------------------------------------------------------- required time -1.383 arrival time 1.428 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.048ns (arrival time - required time) Source: SFP_GEN[2].ngccm_status_reg_reg[2][24]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[2].ngccm_status_reg_reg[2][24]/D (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.109ns (logic 0.064ns (58.716%) route 0.045ns (41.284%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.517ns Source Clock Delay (SCD): 1.265ns Clock Pessimism Removal (CPR): 0.247ns Clock Net Delay (Source): 1.147ns (routing 0.607ns, distribution 0.540ns) Clock Net Delay (Destination): 1.352ns (routing 0.684ns, distribution 0.668ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.147 1.265 RX_WORDCLK_O[2] SLICE_X83Y117 FDPE r SFP_GEN[2].ngccm_status_reg_reg[2][24]/C ------------------------------------------------------------------- ------------------- SLICE_X83Y117 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.314 r SFP_GEN[2].ngccm_status_reg_reg[2][24]/Q net (fo=2, routed) 0.033 1.347 SFP_GEN[2].ngCCM_gbt/SFP_GEN[2].ngccm_status_reg_reg[2][24]_0[8] SLICE_X83Y117 LUT2 (Prop_A6LUT_SLICEM_I0_O) 0.015 1.362 r SFP_GEN[2].ngCCM_gbt/SFP_GEN[2].ngccm_status_reg[2][24]_i_2/O net (fo=1, routed) 0.012 1.374 SFP_GEN[2].ngCCM_gbt_n_393 SLICE_X83Y117 FDPE r SFP_GEN[2].ngccm_status_reg_reg[2][24]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.352 1.517 RX_WORDCLK_O[2] SLICE_X83Y117 FDPE r SFP_GEN[2].ngccm_status_reg_reg[2][24]/C clock pessimism -0.247 1.270 SLICE_X83Y117 FDPE (Hold_AFF_SLICEM_C_D) 0.056 1.326 SFP_GEN[2].ngccm_status_reg_reg[2][24] ------------------------------------------------------------------- required time -1.326 arrival time 1.374 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.104ns (69.799%) route 0.045ns (30.201%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.526ns Source Clock Delay (SCD): 1.270ns Clock Pessimism Removal (CPR): 0.212ns Clock Net Delay (Source): 1.152ns (routing 0.607ns, distribution 0.545ns) Clock Net Delay (Destination): 1.361ns (routing 0.684ns, distribution 0.677ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.152 1.270 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X72Y83 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y83 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.319 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Q net (fo=2, routed) 0.034 1.353 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_3_in SLICE_X72Y83 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.055 1.408 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__1/O net (fo=1, routed) 0.011 1.419 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[2] SLICE_X72Y83 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.361 1.526 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X72Y83 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C clock pessimism -0.212 1.314 SLICE_X72Y83 FDRE (Hold_DFF2_SLICEL_C_D) 0.056 1.370 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[2] ------------------------------------------------------------------- required time -1.370 arrival time 1.419 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.193ns (logic 0.095ns (49.223%) route 0.098ns (50.777%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.513ns Source Clock Delay (SCD): 1.254ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 1.136ns (routing 0.607ns, distribution 0.529ns) Clock Net Delay (Destination): 1.348ns (routing 0.684ns, distribution 0.664ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.136 1.254 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X76Y91 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X76Y91 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.303 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.082 1.385 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_35_in SLICE_X77Y91 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.046 1.431 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__1/O net (fo=1, routed) 0.016 1.447 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[16] SLICE_X77Y91 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.348 1.513 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X77Y91 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.171 1.342 SLICE_X77Y91 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.398 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.398 arrival time 1.447 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.111ns (logic 0.064ns (57.658%) route 0.047ns (42.342%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.505ns Source Clock Delay (SCD): 1.258ns Clock Pessimism Removal (CPR): 0.242ns Clock Net Delay (Source): 1.140ns (routing 0.607ns, distribution 0.533ns) Clock Net Delay (Destination): 1.340ns (routing 0.684ns, distribution 0.656ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.140 1.258 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y93 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y93 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.307 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_reg/Q net (fo=2, routed) 0.035 1.342 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/ready_from_bitSlipCtrller_2 SLICE_X80Y93 LUT3 (Prop_A6LUT_SLICEL_I2_O) 0.015 1.357 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_i_1__1/O net (fo=1, routed) 0.012 1.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_i_1__1_n_0 SLICE_X80Y93 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.340 1.505 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y93 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_reg/C clock pessimism -0.242 1.263 SLICE_X80Y93 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.319 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_reg ------------------------------------------------------------------- required time -1.319 arrival time 1.369 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[71]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[71]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.201ns (logic 0.048ns (23.881%) route 0.153ns (76.119%)) Logic Levels: 0 Clock Path Skew: 0.095ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.519ns Source Clock Delay (SCD): 1.253ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 1.135ns (routing 0.607ns, distribution 0.528ns) Clock Net Delay (Destination): 1.354ns (routing 0.684ns, distribution 0.670ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.135 1.253 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X75Y92 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[71]/C ------------------------------------------------------------------- ------------------- SLICE_X75Y92 FDCE (Prop_GFF_SLICEL_C_Q) 0.048 1.301 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[71]/Q net (fo=1, routed) 0.153 1.454 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[71] SLICE_X74Y92 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[71]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.354 1.519 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X74Y92 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[71]/C clock pessimism -0.171 1.348 SLICE_X74Y92 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 1.404 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[71] ------------------------------------------------------------------- required time -1.404 arrival time 1.454 ------------------------------------------------------------------- slack 0.050 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_4 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y41 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X84Y117 g_clock_rate_din[2].ngccm_status_cnt_reg[2][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X84Y117 g_clock_rate_din[2].ngccm_status_cnt_reg[2][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X84Y117 g_clock_rate_din[2].ngccm_status_cnt_reg[2][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X84Y117 g_clock_rate_din[2].ngccm_status_cnt_reg[2][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X84Y117 g_clock_rate_din[2].ngccm_status_cnt_reg[2][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X84Y117 g_clock_rate_din[2].ngccm_status_cnt_reg[2][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X85Y117 g_clock_rate_din[2].ngccm_status_cnt_reg[2][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X77Y79 SFP_GEN[2].rx_data_ngccm_reg[2][76]/C Low Pulse Width Slow FDPE/C n/a 0.275 4.159 3.884 SLICE_X80Y83 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X71Y92 SFP_GEN[2].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X84Y117 g_clock_rate_din[2].ngccm_status_cnt_reg[2][0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X84Y117 g_clock_rate_din[2].ngccm_status_cnt_reg[2][1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X84Y117 g_clock_rate_din[2].ngccm_status_cnt_reg[2][2]/C High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X84Y117 g_clock_rate_din[2].ngccm_status_cnt_reg[2][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X84Y117 g_clock_rate_din[2].ngccm_status_cnt_reg[2][1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X84Y117 g_clock_rate_din[2].ngccm_status_cnt_reg[2][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X84Y117 g_clock_rate_din[2].ngccm_status_cnt_reg[2][3]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X84Y117 g_clock_rate_din[2].ngccm_status_cnt_reg[2][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X84Y117 g_clock_rate_din[2].ngccm_status_cnt_reg[2][5]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_5 To Clock: gtwiz_userclk_rx_srcclk_out[0]_5 Setup : 0 Failing Endpoints, Worst Slack 1.653ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.036ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.653ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 5.998ns (logic 1.758ns (29.310%) route 4.240ns (70.690%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.576ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.664ns = ( 10.981 - 8.317 ) Source Clock Delay (SCD): 3.501ns Clock Pessimism Removal (CPR): 0.261ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.026ns (routing 1.103ns, distribution 1.923ns) Clock Net Delay (Destination): 2.266ns (routing 1.003ns, distribution 1.263ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.026 3.501 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.605 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.288 7.893 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X81Y102 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.238 8.131 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/O net (fo=5, routed) 0.408 8.539 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X79Y101 LUT4 (Prop_B6LUT_SLICEM_I2_O) 0.243 8.782 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__2/O net (fo=1, routed) 0.086 8.868 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__2_n_0 SLICE_X79Y101 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 9.041 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__2/O net (fo=2, routed) 0.458 9.499 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__2_n_0 SLICE_X81Y101 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.266 10.981 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X81Y101 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.261 11.242 clock uncertainty -0.035 11.207 SLICE_X81Y101 FDCE (Setup_GFF_SLICEL_C_CE) -0.055 11.152 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.152 arrival time -9.499 ------------------------------------------------------------------- slack 1.653 Slack (MET) : 1.653ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 5.998ns (logic 1.758ns (29.310%) route 4.240ns (70.690%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.576ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.664ns = ( 10.981 - 8.317 ) Source Clock Delay (SCD): 3.501ns Clock Pessimism Removal (CPR): 0.261ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.026ns (routing 1.103ns, distribution 1.923ns) Clock Net Delay (Destination): 2.266ns (routing 1.003ns, distribution 1.263ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.026 3.501 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.605 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.288 7.893 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X81Y102 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.238 8.131 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/O net (fo=5, routed) 0.408 8.539 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X79Y101 LUT4 (Prop_B6LUT_SLICEM_I2_O) 0.243 8.782 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__2/O net (fo=1, routed) 0.086 8.868 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__2_n_0 SLICE_X79Y101 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 9.041 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__2/O net (fo=2, routed) 0.458 9.499 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__2_n_0 SLICE_X81Y101 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.266 10.981 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X81Y101 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.261 11.242 clock uncertainty -0.035 11.207 SLICE_X81Y101 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 11.152 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.152 arrival time -9.499 ------------------------------------------------------------------- slack 1.653 Slack (MET) : 1.879ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 5.762ns (logic 1.488ns (25.824%) route 4.274ns (74.176%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.586ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.654ns = ( 10.971 - 8.317 ) Source Clock Delay (SCD): 3.501ns Clock Pessimism Removal (CPR): 0.261ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.026ns (routing 1.103ns, distribution 1.923ns) Clock Net Delay (Destination): 2.256ns (routing 1.003ns, distribution 1.253ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.026 3.501 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.605 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.288 7.893 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X81Y102 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.238 8.131 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/O net (fo=5, routed) 0.398 8.529 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X79Y101 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.146 8.675 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__3/O net (fo=7, routed) 0.588 9.263 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 SLICE_X82Y102 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.256 10.971 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y102 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.261 11.232 clock uncertainty -0.035 11.197 SLICE_X82Y102 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 11.142 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.142 arrival time -9.263 ------------------------------------------------------------------- slack 1.879 Slack (MET) : 1.879ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 5.762ns (logic 1.488ns (25.824%) route 4.274ns (74.176%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.586ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.654ns = ( 10.971 - 8.317 ) Source Clock Delay (SCD): 3.501ns Clock Pessimism Removal (CPR): 0.261ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.026ns (routing 1.103ns, distribution 1.923ns) Clock Net Delay (Destination): 2.256ns (routing 1.003ns, distribution 1.253ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.026 3.501 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.605 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.288 7.893 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X81Y102 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.238 8.131 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/O net (fo=5, routed) 0.398 8.529 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X79Y101 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.146 8.675 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__3/O net (fo=7, routed) 0.588 9.263 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 SLICE_X82Y102 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.256 10.971 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y102 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.261 11.232 clock uncertainty -0.035 11.197 SLICE_X82Y102 FDRE (Setup_BFF2_SLICEM_C_CE) -0.055 11.142 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.142 arrival time -9.263 ------------------------------------------------------------------- slack 1.879 Slack (MET) : 1.883ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 5.759ns (logic 1.488ns (25.838%) route 4.271ns (74.162%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.586ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.654ns = ( 10.971 - 8.317 ) Source Clock Delay (SCD): 3.501ns Clock Pessimism Removal (CPR): 0.261ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.026ns (routing 1.103ns, distribution 1.923ns) Clock Net Delay (Destination): 2.256ns (routing 1.003ns, distribution 1.253ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.026 3.501 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.605 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.288 7.893 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X81Y102 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.238 8.131 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/O net (fo=5, routed) 0.398 8.529 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X79Y101 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.146 8.675 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__3/O net (fo=7, routed) 0.585 9.260 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 SLICE_X82Y102 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.256 10.971 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y102 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.261 11.232 clock uncertainty -0.035 11.197 SLICE_X82Y102 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 11.143 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 11.143 arrival time -9.260 ------------------------------------------------------------------- slack 1.883 Slack (MET) : 1.883ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 5.759ns (logic 1.488ns (25.838%) route 4.271ns (74.162%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.586ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.654ns = ( 10.971 - 8.317 ) Source Clock Delay (SCD): 3.501ns Clock Pessimism Removal (CPR): 0.261ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.026ns (routing 1.103ns, distribution 1.923ns) Clock Net Delay (Destination): 2.256ns (routing 1.003ns, distribution 1.253ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.026 3.501 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.605 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.288 7.893 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X81Y102 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.238 8.131 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/O net (fo=5, routed) 0.398 8.529 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X79Y101 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.146 8.675 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__3/O net (fo=7, routed) 0.585 9.260 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 SLICE_X82Y102 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.256 10.971 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y102 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.261 11.232 clock uncertainty -0.035 11.197 SLICE_X82Y102 FDRE (Setup_AFF_SLICEM_C_CE) -0.054 11.143 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 11.143 arrival time -9.260 ------------------------------------------------------------------- slack 1.883 Slack (MET) : 1.883ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 5.759ns (logic 1.488ns (25.838%) route 4.271ns (74.162%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.586ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.654ns = ( 10.971 - 8.317 ) Source Clock Delay (SCD): 3.501ns Clock Pessimism Removal (CPR): 0.261ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.026ns (routing 1.103ns, distribution 1.923ns) Clock Net Delay (Destination): 2.256ns (routing 1.003ns, distribution 1.253ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.026 3.501 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.605 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.288 7.893 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X81Y102 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.238 8.131 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/O net (fo=5, routed) 0.398 8.529 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X79Y101 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.146 8.675 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__3/O net (fo=7, routed) 0.585 9.260 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 SLICE_X82Y102 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.256 10.971 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y102 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.261 11.232 clock uncertainty -0.035 11.197 SLICE_X82Y102 FDRE (Setup_BFF_SLICEM_C_CE) -0.054 11.143 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.143 arrival time -9.260 ------------------------------------------------------------------- slack 1.883 Slack (MET) : 2.055ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 5.615ns (logic 1.489ns (26.518%) route 4.126ns (73.482%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.554ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.686ns = ( 11.003 - 8.317 ) Source Clock Delay (SCD): 3.501ns Clock Pessimism Removal (CPR): 0.261ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.026ns (routing 1.103ns, distribution 1.923ns) Clock Net Delay (Destination): 2.288ns (routing 1.003ns, distribution 1.285ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.026 3.501 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.605 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.288 7.893 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X81Y102 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.238 8.131 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/O net (fo=5, routed) 0.299 8.430 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X80Y101 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 8.577 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__3/O net (fo=5, routed) 0.539 9.116 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecCorrectHeaders0 SLICE_X80Y101 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.288 11.003 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y101 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.261 11.264 clock uncertainty -0.035 11.229 SLICE_X80Y101 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 11.171 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.171 arrival time -9.116 ------------------------------------------------------------------- slack 2.055 Slack (MET) : 2.062ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 5.611ns (logic 1.489ns (26.537%) route 4.122ns (73.463%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.554ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.686ns = ( 11.003 - 8.317 ) Source Clock Delay (SCD): 3.501ns Clock Pessimism Removal (CPR): 0.261ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.026ns (routing 1.103ns, distribution 1.923ns) Clock Net Delay (Destination): 2.288ns (routing 1.003ns, distribution 1.285ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.026 3.501 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.605 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.288 7.893 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X81Y102 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.238 8.131 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/O net (fo=5, routed) 0.299 8.430 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X80Y101 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 8.577 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__3/O net (fo=5, routed) 0.535 9.112 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecCorrectHeaders0 SLICE_X80Y101 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.288 11.003 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y101 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C clock pessimism 0.261 11.264 clock uncertainty -0.035 11.229 SLICE_X80Y101 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 11.174 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0] ------------------------------------------------------------------- required time 11.174 arrival time -9.112 ------------------------------------------------------------------- slack 2.062 Slack (MET) : 2.141ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 5.516ns (logic 1.488ns (26.976%) route 4.028ns (73.024%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.570ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.670ns = ( 10.987 - 8.317 ) Source Clock Delay (SCD): 3.501ns Clock Pessimism Removal (CPR): 0.261ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.026ns (routing 1.103ns, distribution 1.923ns) Clock Net Delay (Destination): 2.272ns (routing 1.003ns, distribution 1.269ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.026 3.501 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.605 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.288 7.893 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X81Y102 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.238 8.131 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/O net (fo=5, routed) 0.398 8.529 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X79Y101 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.146 8.675 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__3/O net (fo=7, routed) 0.342 9.017 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 SLICE_X80Y100 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.272 10.987 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y100 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.261 11.248 clock uncertainty -0.035 11.213 SLICE_X80Y100 FDRE (Setup_EFF_SLICEL_C_CE) -0.055 11.158 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 11.158 arrival time -9.017 ------------------------------------------------------------------- slack 2.141 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.165ns (logic 0.078ns (47.273%) route 0.087ns (52.727%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.379ns Source Clock Delay (SCD): 1.147ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 1.029ns (routing 0.471ns, distribution 0.558ns) Clock Net Delay (Destination): 1.214ns (routing 0.533ns, distribution 0.681ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.029 1.147 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X70Y99 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X70Y99 FDCE (Prop_CFF_SLICEM_C_Q) 0.048 1.195 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Q net (fo=2, routed) 0.075 1.270 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_13_in SLICE_X69Y99 LUT3 (Prop_A6LUT_SLICEL_I2_O) 0.030 1.300 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__2/O net (fo=1, routed) 0.012 1.312 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[5] SLICE_X69Y99 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.214 1.379 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X69Y99 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism -0.159 1.220 SLICE_X69Y99 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.276 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time -1.276 arrival time 1.312 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[3].rx_data_ngccm_reg[3][28]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.141ns (logic 0.048ns (34.043%) route 0.093ns (65.957%)) Logic Levels: 0 Clock Path Skew: 0.046ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.337ns Source Clock Delay (SCD): 1.106ns Clock Pessimism Removal (CPR): 0.185ns Clock Net Delay (Source): 0.988ns (routing 0.471ns, distribution 0.517ns) Clock Net Delay (Destination): 1.172ns (routing 0.533ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.988 1.106 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X75Y107 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X75Y107 FDRE (Prop_FFF2_SLICEL_C_Q) 0.048 1.154 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/Q net (fo=1, routed) 0.093 1.247 rx_data[3][28] SLICE_X75Y108 FDCE r SFP_GEN[3].rx_data_ngccm_reg[3][28]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.172 1.337 RX_WORDCLK_O[3] SLICE_X75Y108 FDCE r SFP_GEN[3].rx_data_ngccm_reg[3][28]/C clock pessimism -0.185 1.152 SLICE_X75Y108 FDCE (Hold_AFF2_SLICEL_C_D) 0.056 1.208 SFP_GEN[3].rx_data_ngccm_reg[3][28] ------------------------------------------------------------------- required time -1.208 arrival time 1.247 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[3].rx_data_ngccm_reg[3][58]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.205ns (logic 0.049ns (23.902%) route 0.156ns (76.098%)) Logic Levels: 0 Clock Path Skew: 0.109ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.378ns Source Clock Delay (SCD): 1.116ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 0.998ns (routing 0.471ns, distribution 0.527ns) Clock Net Delay (Destination): 1.213ns (routing 0.533ns, distribution 0.680ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.116 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X71Y97 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X71Y97 FDRE (Prop_BFF_SLICEM_C_Q) 0.049 1.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/Q net (fo=1, routed) 0.156 1.321 rx_data[3][58] SLICE_X70Y97 FDCE r SFP_GEN[3].rx_data_ngccm_reg[3][58]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.213 1.378 RX_WORDCLK_O[3] SLICE_X70Y97 FDCE r SFP_GEN[3].rx_data_ngccm_reg[3][58]/C clock pessimism -0.153 1.225 SLICE_X70Y97 FDCE (Hold_BFF_SLICEM_C_D) 0.056 1.281 SFP_GEN[3].rx_data_ngccm_reg[3][58] ------------------------------------------------------------------- required time -1.281 arrival time 1.321 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.171ns (logic 0.080ns (46.784%) route 0.091ns (53.216%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.376ns Source Clock Delay (SCD): 1.142ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 1.024ns (routing 0.471ns, distribution 0.553ns) Clock Net Delay (Destination): 1.211ns (routing 0.533ns, distribution 0.678ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.024 1.142 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X69Y97 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y97 FDCE (Prop_EFF2_SLICEL_C_Q) 0.048 1.190 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Q net (fo=2, routed) 0.075 1.265 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_27_in SLICE_X70Y97 LUT3 (Prop_H6LUT_SLICEM_I2_O) 0.032 1.297 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__2/O net (fo=1, routed) 0.016 1.313 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[12] SLICE_X70Y97 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.211 1.376 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X70Y97 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C clock pessimism -0.159 1.217 SLICE_X70Y97 FDRE (Hold_HFF_SLICEM_C_D) 0.056 1.273 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12] ------------------------------------------------------------------- required time -1.273 arrival time 1.313 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.175ns (logic 0.088ns (50.286%) route 0.087ns (49.714%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.376ns Source Clock Delay (SCD): 1.142ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 1.024ns (routing 0.471ns, distribution 0.553ns) Clock Net Delay (Destination): 1.211ns (routing 0.533ns, distribution 0.678ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.024 1.142 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X69Y97 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y97 FDCE (Prop_EFF2_SLICEL_C_Q) 0.048 1.190 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Q net (fo=2, routed) 0.075 1.265 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_27_in SLICE_X70Y97 LUT3 (Prop_H5LUT_SLICEM_I0_O) 0.040 1.305 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__2/O net (fo=1, routed) 0.012 1.317 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[14] SLICE_X70Y97 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.211 1.376 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X70Y97 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C clock pessimism -0.159 1.217 SLICE_X70Y97 FDRE (Hold_HFF2_SLICEM_C_D) 0.056 1.273 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14] ------------------------------------------------------------------- required time -1.273 arrival time 1.317 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.153ns (logic 0.064ns (41.830%) route 0.089ns (58.170%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.350ns Source Clock Delay (SCD): 1.113ns Clock Pessimism Removal (CPR): 0.185ns Clock Net Delay (Source): 0.995ns (routing 0.471ns, distribution 0.524ns) Clock Net Delay (Destination): 1.185ns (routing 0.533ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.995 1.113 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X72Y108 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y108 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.162 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.074 1.236 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_33_in SLICE_X72Y107 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.015 1.251 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__2/O net (fo=1, routed) 0.015 1.266 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[17] SLICE_X72Y107 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.185 1.350 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X72Y107 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.185 1.165 SLICE_X72Y107 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.221 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.221 arrival time 1.266 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.175ns (logic 0.086ns (49.143%) route 0.089ns (50.857%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.379ns Source Clock Delay (SCD): 1.147ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 1.029ns (routing 0.471ns, distribution 0.558ns) Clock Net Delay (Destination): 1.214ns (routing 0.533ns, distribution 0.681ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.029 1.147 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X70Y99 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X70Y99 FDCE (Prop_CFF_SLICEM_C_Q) 0.048 1.195 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Q net (fo=2, routed) 0.075 1.270 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_13_in SLICE_X69Y99 LUT3 (Prop_A5LUT_SLICEL_I0_O) 0.038 1.308 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[7]_i_1__2/O net (fo=1, routed) 0.014 1.322 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[7] SLICE_X69Y99 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.214 1.379 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X69Y99 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C clock pessimism -0.159 1.220 SLICE_X69Y99 FDRE (Hold_AFF2_SLICEL_C_D) 0.056 1.276 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7] ------------------------------------------------------------------- required time -1.276 arrival time 1.322 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: SFP_GEN[3].rx_data_ngccm_reg[3][58]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[58]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.174ns (logic 0.087ns (50.000%) route 0.087ns (50.000%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.376ns Source Clock Delay (SCD): 1.145ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 1.027ns (routing 0.471ns, distribution 0.556ns) Clock Net Delay (Destination): 1.211ns (routing 0.533ns, distribution 0.678ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.027 1.145 RX_WORDCLK_O[3] SLICE_X70Y97 FDCE r SFP_GEN[3].rx_data_ngccm_reg[3][58]/C ------------------------------------------------------------------- ------------------- SLICE_X70Y97 FDCE (Prop_BFF_SLICEM_C_Q) 0.049 1.194 r SFP_GEN[3].rx_data_ngccm_reg[3][58]/Q net (fo=1, routed) 0.076 1.270 SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[83]_0[50] SLICE_X69Y97 LUT3 (Prop_C5LUT_SLICEL_I1_O) 0.038 1.308 r SFP_GEN[3].ngCCM_gbt/RX_Word_rx40[58]_i_1/O net (fo=1, routed) 0.011 1.319 SFP_GEN[3].ngCCM_gbt/RX_Word_rx40[58]_i_1_n_0 SLICE_X69Y97 FDCE r SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[58]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.211 1.376 SFP_GEN[3].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y97 FDCE r SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[58]/C clock pessimism -0.159 1.217 SLICE_X69Y97 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 1.273 SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[58] ------------------------------------------------------------------- required time -1.273 arrival time 1.319 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.094ns (66.197%) route 0.048ns (33.803%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.352ns Source Clock Delay (SCD): 1.120ns Clock Pessimism Removal (CPR): 0.194ns Clock Net Delay (Source): 1.002ns (routing 0.471ns, distribution 0.531ns) Clock Net Delay (Destination): 1.187ns (routing 0.533ns, distribution 0.654ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.002 1.120 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X73Y107 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X73Y107 FDCE (Prop_BFF2_SLICEM_C_Q) 0.048 1.168 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Q net (fo=2, routed) 0.036 1.204 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_27_in SLICE_X73Y107 LUT3 (Prop_F6LUT_SLICEM_I2_O) 0.046 1.250 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__2/O net (fo=1, routed) 0.012 1.262 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[12] SLICE_X73Y107 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.187 1.352 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X73Y107 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C clock pessimism -0.194 1.158 SLICE_X73Y107 FDRE (Hold_FFF_SLICEM_C_D) 0.056 1.214 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12] ------------------------------------------------------------------- required time -1.214 arrival time 1.262 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.094ns (66.197%) route 0.048ns (33.803%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.352ns Source Clock Delay (SCD): 1.120ns Clock Pessimism Removal (CPR): 0.194ns Clock Net Delay (Source): 1.002ns (routing 0.471ns, distribution 0.531ns) Clock Net Delay (Destination): 1.187ns (routing 0.533ns, distribution 0.654ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.002 1.120 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X73Y107 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X73Y107 FDCE (Prop_DFF_SLICEM_C_Q) 0.049 1.169 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Q net (fo=2, routed) 0.036 1.205 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_11_in SLICE_X73Y107 LUT3 (Prop_E6LUT_SLICEM_I2_O) 0.045 1.250 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__2/O net (fo=1, routed) 0.012 1.262 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[4] SLICE_X73Y107 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.187 1.352 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X73Y107 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.194 1.158 SLICE_X73Y107 FDRE (Hold_EFF_SLICEM_C_D) 0.056 1.214 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.214 arrival time 1.262 ------------------------------------------------------------------- slack 0.048 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_5 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y40 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X71Y116 SFP_GEN[3].ngccm_rx_down_cnt_reg[3]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X81Y117 SFP_GEN[3].ngccm_status_reg_reg[3][0]/C Min Period n/a FDPE/C n/a 0.550 8.317 7.767 SLICE_X82Y117 SFP_GEN[3].ngccm_status_reg_reg[3][16]/C Min Period n/a FDPE/C n/a 0.550 8.317 7.767 SLICE_X81Y117 SFP_GEN[3].ngccm_status_reg_reg[3][17]/C Min Period n/a FDPE/C n/a 0.550 8.317 7.767 SLICE_X81Y117 SFP_GEN[3].ngccm_status_reg_reg[3][18]/C Min Period n/a FDPE/C n/a 0.550 8.317 7.767 SLICE_X81Y117 SFP_GEN[3].ngccm_status_reg_reg[3][19]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X81Y117 SFP_GEN[3].ngccm_status_reg_reg[3][1]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X71Y116 SFP_GEN[3].ngccm_rx_down_cnt_reg[3]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X81Y117 SFP_GEN[3].ngccm_status_reg_reg[3][0]/C Low Pulse Width Fast FDPE/C n/a 0.275 4.159 3.884 SLICE_X81Y117 SFP_GEN[3].ngccm_status_reg_reg[3][17]/C Low Pulse Width Fast FDPE/C n/a 0.275 4.159 3.884 SLICE_X81Y117 SFP_GEN[3].ngccm_status_reg_reg[3][18]/C Low Pulse Width Fast FDPE/C n/a 0.275 4.159 3.884 SLICE_X81Y117 SFP_GEN[3].ngccm_status_reg_reg[3][19]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X81Y117 SFP_GEN[3].ngccm_status_reg_reg[3][1]/C High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X71Y116 SFP_GEN[3].ngccm_rx_down_cnt_reg[3]/C High Pulse Width Slow FDPE/C n/a 0.275 4.159 3.884 SLICE_X82Y117 SFP_GEN[3].ngccm_status_reg_reg[3][16]/C High Pulse Width Slow FDPE/C n/a 0.275 4.159 3.884 SLICE_X82Y117 SFP_GEN[3].ngccm_status_reg_reg[3][23]/C High Pulse Width Slow FDPE/C n/a 0.275 4.159 3.884 SLICE_X82Y117 SFP_GEN[3].ngccm_status_reg_reg[3][24]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X72Y101 SFP_GEN[3].rx_data_ngccm_reg[3][1]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X73Y108 SFP_GEN[3].rx_data_ngccm_reg[3][21]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_6 To Clock: gtwiz_userclk_rx_srcclk_out[0]_6 Setup : 0 Failing Endpoints, Worst Slack 2.946ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.034ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.493ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.946ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 5.384ns (logic 1.348ns (25.037%) route 4.036ns (74.963%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.103ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.599ns = ( 10.916 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.244ns (routing 0.667ns, distribution 1.577ns) Clock Net Delay (Destination): 2.201ns (routing 0.604ns, distribution 1.597ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.244 2.719 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.805 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.082 6.887 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X92Y128 LUT4 (Prop_H6LUT_SLICEM_I0_O) 0.173 7.060 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/O net (fo=5, routed) 0.433 7.493 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X94Y128 LUT5 (Prop_B6LUT_SLICEL_I3_O) 0.089 7.582 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__4/O net (fo=7, routed) 0.521 8.103 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X93Y127 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.201 10.916 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y127 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.223 11.139 clock uncertainty -0.035 11.104 SLICE_X93Y127 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 11.049 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.049 arrival time -8.103 ------------------------------------------------------------------- slack 2.946 Slack (MET) : 2.947ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 5.387ns (logic 1.348ns (25.023%) route 4.039ns (74.977%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.107ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.603ns = ( 10.920 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.244ns (routing 0.667ns, distribution 1.577ns) Clock Net Delay (Destination): 2.205ns (routing 0.604ns, distribution 1.601ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.244 2.719 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.805 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.082 6.887 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X92Y128 LUT4 (Prop_H6LUT_SLICEM_I0_O) 0.173 7.060 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/O net (fo=5, routed) 0.433 7.493 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X94Y128 LUT5 (Prop_B6LUT_SLICEL_I3_O) 0.089 7.582 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__4/O net (fo=7, routed) 0.524 8.106 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X92Y127 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.205 10.920 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X92Y127 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.223 11.143 clock uncertainty -0.035 11.108 SLICE_X92Y127 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 11.053 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.053 arrival time -8.106 ------------------------------------------------------------------- slack 2.947 Slack (MET) : 2.951ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 5.384ns (logic 1.348ns (25.037%) route 4.036ns (74.963%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.107ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.603ns = ( 10.920 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.244ns (routing 0.667ns, distribution 1.577ns) Clock Net Delay (Destination): 2.205ns (routing 0.604ns, distribution 1.601ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.244 2.719 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.805 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.082 6.887 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X92Y128 LUT4 (Prop_H6LUT_SLICEM_I0_O) 0.173 7.060 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/O net (fo=5, routed) 0.433 7.493 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X94Y128 LUT5 (Prop_B6LUT_SLICEL_I3_O) 0.089 7.582 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__4/O net (fo=7, routed) 0.521 8.103 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X92Y127 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.205 10.920 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X92Y127 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.223 11.143 clock uncertainty -0.035 11.108 SLICE_X92Y127 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 11.054 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 11.054 arrival time -8.103 ------------------------------------------------------------------- slack 2.951 Slack (MET) : 2.951ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 5.380ns (logic 1.348ns (25.056%) route 4.032ns (74.944%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.103ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.599ns = ( 10.916 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.244ns (routing 0.667ns, distribution 1.577ns) Clock Net Delay (Destination): 2.201ns (routing 0.604ns, distribution 1.597ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.244 2.719 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.805 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.082 6.887 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X92Y128 LUT4 (Prop_H6LUT_SLICEM_I0_O) 0.173 7.060 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/O net (fo=5, routed) 0.433 7.493 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X94Y128 LUT5 (Prop_B6LUT_SLICEL_I3_O) 0.089 7.582 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__4/O net (fo=7, routed) 0.517 8.099 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X93Y127 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.201 10.916 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y127 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.223 11.139 clock uncertainty -0.035 11.104 SLICE_X93Y127 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 11.050 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 11.050 arrival time -8.099 ------------------------------------------------------------------- slack 2.951 Slack (MET) : 2.951ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 5.380ns (logic 1.348ns (25.056%) route 4.032ns (74.944%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.103ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.599ns = ( 10.916 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.244ns (routing 0.667ns, distribution 1.577ns) Clock Net Delay (Destination): 2.201ns (routing 0.604ns, distribution 1.597ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.244 2.719 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.805 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.082 6.887 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X92Y128 LUT4 (Prop_H6LUT_SLICEM_I0_O) 0.173 7.060 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/O net (fo=5, routed) 0.433 7.493 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X94Y128 LUT5 (Prop_B6LUT_SLICEL_I3_O) 0.089 7.582 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__4/O net (fo=7, routed) 0.517 8.099 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X93Y127 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.201 10.916 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y127 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.223 11.139 clock uncertainty -0.035 11.104 SLICE_X93Y127 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 11.050 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.050 arrival time -8.099 ------------------------------------------------------------------- slack 2.951 Slack (MET) : 2.959ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 5.369ns (logic 1.475ns (27.473%) route 3.894ns (72.527%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.101ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.597ns = ( 10.914 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.244ns (routing 0.667ns, distribution 1.577ns) Clock Net Delay (Destination): 2.199ns (routing 0.604ns, distribution 1.595ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.244 2.719 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.805 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.082 6.887 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X92Y128 LUT4 (Prop_H6LUT_SLICEM_I0_O) 0.173 7.060 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/O net (fo=5, routed) 0.189 7.249 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X93Y128 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.165 7.414 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__3/O net (fo=1, routed) 0.222 7.636 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__3_n_0 SLICE_X94Y128 LUT6 (Prop_C6LUT_SLICEL_I5_O) 0.051 7.687 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__3/O net (fo=2, routed) 0.401 8.088 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__3_n_0 SLICE_X93Y128 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.199 10.914 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y128 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.223 11.137 clock uncertainty -0.035 11.102 SLICE_X93Y128 FDCE (Setup_GFF_SLICEL_C_CE) -0.055 11.047 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.047 arrival time -8.088 ------------------------------------------------------------------- slack 2.959 Slack (MET) : 2.959ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 5.369ns (logic 1.475ns (27.473%) route 3.894ns (72.527%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.101ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.597ns = ( 10.914 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.244ns (routing 0.667ns, distribution 1.577ns) Clock Net Delay (Destination): 2.199ns (routing 0.604ns, distribution 1.595ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.244 2.719 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.805 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.082 6.887 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X92Y128 LUT4 (Prop_H6LUT_SLICEM_I0_O) 0.173 7.060 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/O net (fo=5, routed) 0.189 7.249 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X93Y128 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.165 7.414 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__3/O net (fo=1, routed) 0.222 7.636 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__3_n_0 SLICE_X94Y128 LUT6 (Prop_C6LUT_SLICEL_I5_O) 0.051 7.687 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__3/O net (fo=2, routed) 0.401 8.088 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__3_n_0 SLICE_X93Y128 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.199 10.914 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y128 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.223 11.137 clock uncertainty -0.035 11.102 SLICE_X93Y128 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 11.047 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.047 arrival time -8.088 ------------------------------------------------------------------- slack 2.959 Slack (MET) : 3.076ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 5.257ns (logic 1.348ns (25.642%) route 3.909ns (74.358%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.106ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.602ns = ( 10.919 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.244ns (routing 0.667ns, distribution 1.577ns) Clock Net Delay (Destination): 2.204ns (routing 0.604ns, distribution 1.600ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.244 2.719 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.805 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.082 6.887 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X92Y128 LUT4 (Prop_H6LUT_SLICEM_I0_O) 0.173 7.060 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/O net (fo=5, routed) 0.433 7.493 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X94Y128 LUT5 (Prop_B6LUT_SLICEL_I3_O) 0.089 7.582 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__4/O net (fo=7, routed) 0.394 7.976 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X92Y128 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.204 10.919 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X92Y128 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.223 11.142 clock uncertainty -0.035 11.107 SLICE_X92Y128 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 11.052 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 11.052 arrival time -7.976 ------------------------------------------------------------------- slack 3.076 Slack (MET) : 3.076ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 5.257ns (logic 1.348ns (25.642%) route 3.909ns (74.358%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.106ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.602ns = ( 10.919 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.244ns (routing 0.667ns, distribution 1.577ns) Clock Net Delay (Destination): 2.204ns (routing 0.604ns, distribution 1.600ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.244 2.719 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.805 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.082 6.887 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X92Y128 LUT4 (Prop_H6LUT_SLICEM_I0_O) 0.173 7.060 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/O net (fo=5, routed) 0.433 7.493 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X94Y128 LUT5 (Prop_B6LUT_SLICEL_I3_O) 0.089 7.582 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__4/O net (fo=7, routed) 0.394 7.976 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X92Y128 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.204 10.919 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X92Y128 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.223 11.142 clock uncertainty -0.035 11.107 SLICE_X92Y128 FDRE (Setup_GFF_SLICEM_C_CE) -0.055 11.052 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 11.052 arrival time -7.976 ------------------------------------------------------------------- slack 3.076 Slack (MET) : 3.101ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 5.229ns (logic 1.427ns (27.290%) route 3.802ns (72.710%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.106ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.602ns = ( 10.919 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.244ns (routing 0.667ns, distribution 1.577ns) Clock Net Delay (Destination): 2.204ns (routing 0.604ns, distribution 1.600ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.244 2.719 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.805 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.082 6.887 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X92Y128 LUT4 (Prop_H6LUT_SLICEM_I0_O) 0.173 7.060 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/O net (fo=5, routed) 0.371 7.431 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X92Y128 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.168 7.599 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__4/O net (fo=5, routed) 0.349 7.948 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 SLICE_X92Y127 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.204 10.919 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X92Y127 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.223 11.142 clock uncertainty -0.035 11.107 SLICE_X92Y127 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 11.049 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.049 arrival time -7.948 ------------------------------------------------------------------- slack 3.101 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.034ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[4].rx_data_ngccm_reg[4][74]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.048ns (33.566%) route 0.095ns (66.434%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.330ns Source Clock Delay (SCD): 1.096ns Clock Pessimism Removal (CPR): 0.181ns Clock Net Delay (Source): 0.978ns (routing 0.303ns, distribution 0.675ns) Clock Net Delay (Destination): 1.165ns (routing 0.344ns, distribution 0.821ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.978 1.096 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X84Y124 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y124 FDRE (Prop_GFF_SLICEL_C_Q) 0.048 1.144 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/Q net (fo=1, routed) 0.095 1.239 rx_data[4][74] SLICE_X84Y123 FDCE r SFP_GEN[4].rx_data_ngccm_reg[4][74]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.165 1.330 RX_WORDCLK_O[4] SLICE_X84Y123 FDCE r SFP_GEN[4].rx_data_ngccm_reg[4][74]/C clock pessimism -0.181 1.149 SLICE_X84Y123 FDCE (Hold_BFF2_SLICEL_C_D) 0.056 1.205 SFP_GEN[4].rx_data_ngccm_reg[4][74] ------------------------------------------------------------------- required time -1.205 arrival time 1.239 ------------------------------------------------------------------- slack 0.034 Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[4].rx_data_ngccm_reg[4][57]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.167ns (logic 0.048ns (28.743%) route 0.119ns (71.257%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.324ns Source Clock Delay (SCD): 1.098ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.980ns (routing 0.303ns, distribution 0.677ns) Clock Net Delay (Destination): 1.159ns (routing 0.344ns, distribution 0.815ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.980 1.098 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X84Y125 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y125 FDRE (Prop_CFF2_SLICEL_C_Q) 0.048 1.146 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/Q net (fo=1, routed) 0.119 1.265 rx_data[4][57] SLICE_X85Y125 FDCE r SFP_GEN[4].rx_data_ngccm_reg[4][57]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.159 1.324 RX_WORDCLK_O[4] SLICE_X85Y125 FDCE r SFP_GEN[4].rx_data_ngccm_reg[4][57]/C clock pessimism -0.151 1.173 SLICE_X85Y125 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.229 SFP_GEN[4].rx_data_ngccm_reg[4][57] ------------------------------------------------------------------- required time -1.229 arrival time 1.265 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[4].rx_data_ngccm_reg[4][19]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.183ns (logic 0.049ns (26.776%) route 0.134ns (73.224%)) Logic Levels: 0 Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.333ns Source Clock Delay (SCD): 1.093ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.975ns (routing 0.303ns, distribution 0.672ns) Clock Net Delay (Destination): 1.168ns (routing 0.344ns, distribution 0.824ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.975 1.093 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X87Y134 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X87Y134 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 1.142 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/Q net (fo=1, routed) 0.134 1.276 rx_data[4][19] SLICE_X86Y135 FDCE r SFP_GEN[4].rx_data_ngccm_reg[4][19]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.168 1.333 RX_WORDCLK_O[4] SLICE_X86Y135 FDCE r SFP_GEN[4].rx_data_ngccm_reg[4][19]/C clock pessimism -0.151 1.182 SLICE_X86Y135 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.237 SFP_GEN[4].rx_data_ngccm_reg[4][19] ------------------------------------------------------------------- required time -1.237 arrival time 1.276 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[4].rx_data_ngccm_reg[4][25]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.185ns (logic 0.049ns (26.486%) route 0.136ns (73.514%)) Logic Levels: 0 Clock Path Skew: 0.090ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.334ns Source Clock Delay (SCD): 1.093ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.975ns (routing 0.303ns, distribution 0.672ns) Clock Net Delay (Destination): 1.169ns (routing 0.344ns, distribution 0.825ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.975 1.093 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X87Y134 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X87Y134 FDRE (Prop_BFF_SLICEM_C_Q) 0.049 1.142 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/Q net (fo=1, routed) 0.136 1.278 rx_data[4][25] SLICE_X85Y134 FDCE r SFP_GEN[4].rx_data_ngccm_reg[4][25]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.169 1.334 RX_WORDCLK_O[4] SLICE_X85Y134 FDCE r SFP_GEN[4].rx_data_ngccm_reg[4][25]/C clock pessimism -0.151 1.183 SLICE_X85Y134 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.238 SFP_GEN[4].rx_data_ngccm_reg[4][25] ------------------------------------------------------------------- required time -1.238 arrival time 1.278 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[4].rx_data_ngccm_reg[4][55]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.171ns (logic 0.048ns (28.070%) route 0.123ns (71.930%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.324ns Source Clock Delay (SCD): 1.098ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.980ns (routing 0.303ns, distribution 0.677ns) Clock Net Delay (Destination): 1.159ns (routing 0.344ns, distribution 0.815ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.980 1.098 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X84Y125 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y125 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 1.146 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/Q net (fo=1, routed) 0.123 1.269 rx_data[4][55] SLICE_X85Y125 FDCE r SFP_GEN[4].rx_data_ngccm_reg[4][55]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.159 1.324 RX_WORDCLK_O[4] SLICE_X85Y125 FDCE r SFP_GEN[4].rx_data_ngccm_reg[4][55]/C clock pessimism -0.151 1.173 SLICE_X85Y125 FDCE (Hold_BFF_SLICEM_C_D) 0.056 1.229 SFP_GEN[4].rx_data_ngccm_reg[4][55] ------------------------------------------------------------------- required time -1.229 arrival time 1.269 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.175ns (logic 0.086ns (49.143%) route 0.089ns (50.857%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.327ns Source Clock Delay (SCD): 1.098ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.980ns (routing 0.303ns, distribution 0.677ns) Clock Net Delay (Destination): 1.162ns (routing 0.344ns, distribution 0.818ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.980 1.098 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X85Y125 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X85Y125 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.146 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/Q net (fo=2, routed) 0.077 1.223 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_17_in SLICE_X84Y125 LUT3 (Prop_G5LUT_SLICEL_I2_O) 0.038 1.261 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[7]_i_1__3/O net (fo=1, routed) 0.012 1.273 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[7] SLICE_X84Y125 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.162 1.327 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X84Y125 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C clock pessimism -0.151 1.176 SLICE_X84Y125 FDRE (Hold_GFF2_SLICEL_C_D) 0.056 1.232 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7] ------------------------------------------------------------------- required time -1.232 arrival time 1.273 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.041ns (arrival time - required time) Source: SFP_GEN[4].rx_data_ngccm_reg[4][24]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[24]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.198ns (logic 0.049ns (24.747%) route 0.149ns (75.253%)) Logic Levels: 0 Clock Path Skew: 0.101ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.336ns Source Clock Delay (SCD): 1.084ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.966ns (routing 0.303ns, distribution 0.663ns) Clock Net Delay (Destination): 1.171ns (routing 0.344ns, distribution 0.827ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.966 1.084 RX_WORDCLK_O[4] SLICE_X88Y135 FDCE r SFP_GEN[4].rx_data_ngccm_reg[4][24]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y135 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 1.133 r SFP_GEN[4].rx_data_ngccm_reg[4][24]/Q net (fo=1, routed) 0.149 1.282 SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[83]_0[16] SLICE_X86Y135 FDCE r SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[24]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.171 1.336 SFP_GEN[4].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y135 FDCE r SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[24]/C clock pessimism -0.151 1.185 SLICE_X86Y135 FDCE (Hold_BFF_SLICEL_C_D) 0.056 1.241 SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[24] ------------------------------------------------------------------- required time -1.241 arrival time 1.282 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.158ns (logic 0.078ns (49.367%) route 0.080ns (50.633%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.059ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.322ns Source Clock Delay (SCD): 1.082ns Clock Pessimism Removal (CPR): 0.181ns Clock Net Delay (Source): 0.964ns (routing 0.303ns, distribution 0.661ns) Clock Net Delay (Destination): 1.157ns (routing 0.344ns, distribution 0.813ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.964 1.082 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X88Y135 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y135 FDCE (Prop_GFF2_SLICEL_C_Q) 0.048 1.130 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Q net (fo=2, routed) 0.066 1.196 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_13_in SLICE_X88Y134 LUT3 (Prop_G6LUT_SLICEL_I2_O) 0.030 1.226 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__3/O net (fo=1, routed) 0.014 1.240 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[5] SLICE_X88Y134 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.157 1.322 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X88Y134 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism -0.181 1.141 SLICE_X88Y134 FDRE (Hold_GFF_SLICEL_C_D) 0.056 1.197 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time -1.197 arrival time 1.240 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.044ns (arrival time - required time) Source: SFP_GEN[4].rx_data_ngccm_reg[4][28]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[28]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.200ns (logic 0.048ns (24.000%) route 0.152ns (76.000%)) Logic Levels: 0 Clock Path Skew: 0.100ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.335ns Source Clock Delay (SCD): 1.084ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.966ns (routing 0.303ns, distribution 0.663ns) Clock Net Delay (Destination): 1.170ns (routing 0.344ns, distribution 0.826ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.966 1.084 RX_WORDCLK_O[4] SLICE_X88Y135 FDCE r SFP_GEN[4].rx_data_ngccm_reg[4][28]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y135 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.132 r SFP_GEN[4].rx_data_ngccm_reg[4][28]/Q net (fo=1, routed) 0.152 1.284 SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[83]_0[20] SLICE_X85Y135 FDCE r SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[28]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.170 1.335 SFP_GEN[4].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y135 FDCE r SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[28]/C clock pessimism -0.151 1.184 SLICE_X85Y135 FDCE (Hold_AFF_SLICEM_C_D) 0.056 1.240 SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[28] ------------------------------------------------------------------- required time -1.240 arrival time 1.284 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.177ns (logic 0.079ns (44.633%) route 0.098ns (55.367%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.306ns Source Clock Delay (SCD): 1.078ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.960ns (routing 0.303ns, distribution 0.657ns) Clock Net Delay (Destination): 1.141ns (routing 0.344ns, distribution 0.797ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.960 1.078 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X90Y133 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X90Y133 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.127 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Q net (fo=2, routed) 0.082 1.209 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_25_in SLICE_X89Y133 LUT3 (Prop_C6LUT_SLICEM_I2_O) 0.030 1.239 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__3/O net (fo=1, routed) 0.016 1.255 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[11] SLICE_X89Y133 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.141 1.306 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X89Y133 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C clock pessimism -0.151 1.155 SLICE_X89Y133 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.211 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11] ------------------------------------------------------------------- required time -1.211 arrival time 1.255 ------------------------------------------------------------------- slack 0.044 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_6 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y65 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X93Y131 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X93Y131 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X93Y131 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X93Y131 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X92Y129 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X92Y129 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X93Y129 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X93Y131 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X93Y131 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X92Y129 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X92Y129 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X93Y131 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X93Y131 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X93Y131 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X93Y131 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X93Y131 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X92Y129 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X92Y129 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X92Y129 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][5]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.037 0.493 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.037 1.291 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_7 To Clock: gtwiz_userclk_rx_srcclk_out[0]_7 Setup : 0 Failing Endpoints, Worst Slack 3.012ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.033ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.493ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.012ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[3]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 5.513ns (logic 1.161ns (21.059%) route 4.352ns (78.941%)) Logic Levels: 0 Clock Path Skew: 0.180ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.659ns = ( 10.976 - 8.317 ) Source Clock Delay (SCD): 2.699ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.224ns (routing 0.665ns, distribution 1.559ns) Clock Net Delay (Destination): 2.261ns (routing 0.604ns, distribution 1.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.224 2.699 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.860 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 4.352 8.212 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/D[3] SLICE_X75Y137 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.261 10.976 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X75Y137 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[3]/C clock pessimism 0.220 11.197 clock uncertainty -0.035 11.161 SLICE_X75Y137 FDCE (Setup_FFF_SLICEL_C_D) 0.063 11.224 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[3] ------------------------------------------------------------------- required time 11.224 arrival time -8.212 ------------------------------------------------------------------- slack 3.012 Slack (MET) : 3.081ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[23]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 5.455ns (logic 1.307ns (23.960%) route 4.148ns (76.040%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.191ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.670ns = ( 10.987 - 8.317 ) Source Clock Delay (SCD): 2.699ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.224ns (routing 0.665ns, distribution 1.559ns) Clock Net Delay (Destination): 2.272ns (routing 0.604ns, distribution 1.668ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.224 2.699 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.860 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 4.113 7.973 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/D[3] SLICE_X80Y139 LUT5 (Prop_D6LUT_SLICEL_I3_O) 0.146 8.119 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0[23]_i_1__8/O net (fo=1, routed) 0.035 8.154 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg00[23] SLICE_X80Y139 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[23]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.272 10.987 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X80Y139 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[23]/C clock pessimism 0.220 11.208 clock uncertainty -0.035 11.172 SLICE_X80Y139 FDCE (Setup_DFF_SLICEL_C_D) 0.063 11.235 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[23] ------------------------------------------------------------------- required time 11.235 arrival time -8.154 ------------------------------------------------------------------- slack 3.081 Slack (MET) : 3.203ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[5].rx_data_ngccm_reg[5][67]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 5.095ns (logic 0.291ns (5.711%) route 4.804ns (94.289%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.659ns = ( 10.976 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.665ns, distribution 1.668ns) Clock Net Delay (Destination): 2.261ns (routing 0.604ns, distribution 1.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y141 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.662 5.609 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X85Y145 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.152 5.761 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[5].rx_data_ngccm[5][83]_i_1/O net (fo=76, routed) 2.142 7.903 rx_data_ngccm[5] SLICE_X73Y126 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][67]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.261 10.976 RX_WORDCLK_O[5] SLICE_X73Y126 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][67]/C clock pessimism 0.220 11.196 clock uncertainty -0.035 11.161 SLICE_X73Y126 FDCE (Setup_AFF2_SLICEM_C_CE) -0.055 11.106 SFP_GEN[5].rx_data_ngccm_reg[5][67] ------------------------------------------------------------------- required time 11.106 arrival time -7.903 ------------------------------------------------------------------- slack 3.203 Slack (MET) : 3.203ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[5].rx_data_ngccm_reg[5][72]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 5.095ns (logic 0.291ns (5.711%) route 4.804ns (94.289%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.659ns = ( 10.976 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.665ns, distribution 1.668ns) Clock Net Delay (Destination): 2.261ns (routing 0.604ns, distribution 1.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y141 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.662 5.609 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X85Y145 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.152 5.761 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[5].rx_data_ngccm[5][83]_i_1/O net (fo=76, routed) 2.142 7.903 rx_data_ngccm[5] SLICE_X73Y126 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][72]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.261 10.976 RX_WORDCLK_O[5] SLICE_X73Y126 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][72]/C clock pessimism 0.220 11.196 clock uncertainty -0.035 11.161 SLICE_X73Y126 FDCE (Setup_BFF2_SLICEM_C_CE) -0.055 11.106 SFP_GEN[5].rx_data_ngccm_reg[5][72] ------------------------------------------------------------------- required time 11.106 arrival time -7.903 ------------------------------------------------------------------- slack 3.203 Slack (MET) : 3.203ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[5].rx_data_ngccm_reg[5][75]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 5.095ns (logic 0.291ns (5.711%) route 4.804ns (94.289%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.659ns = ( 10.976 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.665ns, distribution 1.668ns) Clock Net Delay (Destination): 2.261ns (routing 0.604ns, distribution 1.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y141 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.662 5.609 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X85Y145 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.152 5.761 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[5].rx_data_ngccm[5][83]_i_1/O net (fo=76, routed) 2.142 7.903 rx_data_ngccm[5] SLICE_X73Y126 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][75]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.261 10.976 RX_WORDCLK_O[5] SLICE_X73Y126 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][75]/C clock pessimism 0.220 11.196 clock uncertainty -0.035 11.161 SLICE_X73Y126 FDCE (Setup_CFF2_SLICEM_C_CE) -0.055 11.106 SFP_GEN[5].rx_data_ngccm_reg[5][75] ------------------------------------------------------------------- required time 11.106 arrival time -7.903 ------------------------------------------------------------------- slack 3.203 Slack (MET) : 3.203ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[5].rx_data_ngccm_reg[5][77]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 5.095ns (logic 0.291ns (5.711%) route 4.804ns (94.289%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.659ns = ( 10.976 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.665ns, distribution 1.668ns) Clock Net Delay (Destination): 2.261ns (routing 0.604ns, distribution 1.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y141 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.662 5.609 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X85Y145 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.152 5.761 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[5].rx_data_ngccm[5][83]_i_1/O net (fo=76, routed) 2.142 7.903 rx_data_ngccm[5] SLICE_X73Y126 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][77]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.261 10.976 RX_WORDCLK_O[5] SLICE_X73Y126 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][77]/C clock pessimism 0.220 11.196 clock uncertainty -0.035 11.161 SLICE_X73Y126 FDCE (Setup_DFF2_SLICEM_C_CE) -0.055 11.106 SFP_GEN[5].rx_data_ngccm_reg[5][77] ------------------------------------------------------------------- required time 11.106 arrival time -7.903 ------------------------------------------------------------------- slack 3.203 Slack (MET) : 3.205ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[5].rx_data_ngccm_reg[5][58]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 5.114ns (logic 0.291ns (5.690%) route 4.823ns (94.310%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.095ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.683ns = ( 11.000 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.665ns, distribution 1.668ns) Clock Net Delay (Destination): 2.285ns (routing 0.604ns, distribution 1.681ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y141 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.662 5.609 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X85Y145 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.152 5.761 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[5].rx_data_ngccm[5][83]_i_1/O net (fo=76, routed) 2.161 7.922 rx_data_ngccm[5] SLICE_X72Y127 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][58]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.285 11.000 RX_WORDCLK_O[5] SLICE_X72Y127 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][58]/C clock pessimism 0.220 11.220 clock uncertainty -0.035 11.185 SLICE_X72Y127 FDCE (Setup_EFF2_SLICEL_C_CE) -0.058 11.127 SFP_GEN[5].rx_data_ngccm_reg[5][58] ------------------------------------------------------------------- required time 11.127 arrival time -7.922 ------------------------------------------------------------------- slack 3.205 Slack (MET) : 3.205ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[5].rx_data_ngccm_reg[5][60]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 5.114ns (logic 0.291ns (5.690%) route 4.823ns (94.310%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.095ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.683ns = ( 11.000 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.665ns, distribution 1.668ns) Clock Net Delay (Destination): 2.285ns (routing 0.604ns, distribution 1.681ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y141 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.662 5.609 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X85Y145 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.152 5.761 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[5].rx_data_ngccm[5][83]_i_1/O net (fo=76, routed) 2.161 7.922 rx_data_ngccm[5] SLICE_X72Y127 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][60]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.285 11.000 RX_WORDCLK_O[5] SLICE_X72Y127 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][60]/C clock pessimism 0.220 11.220 clock uncertainty -0.035 11.185 SLICE_X72Y127 FDCE (Setup_FFF2_SLICEL_C_CE) -0.058 11.127 SFP_GEN[5].rx_data_ngccm_reg[5][60] ------------------------------------------------------------------- required time 11.127 arrival time -7.922 ------------------------------------------------------------------- slack 3.205 Slack (MET) : 3.205ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[5].rx_data_ngccm_reg[5][62]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 5.114ns (logic 0.291ns (5.690%) route 4.823ns (94.310%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.095ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.683ns = ( 11.000 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.665ns, distribution 1.668ns) Clock Net Delay (Destination): 2.285ns (routing 0.604ns, distribution 1.681ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y141 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.662 5.609 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X85Y145 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.152 5.761 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[5].rx_data_ngccm[5][83]_i_1/O net (fo=76, routed) 2.161 7.922 rx_data_ngccm[5] SLICE_X72Y127 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][62]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.285 11.000 RX_WORDCLK_O[5] SLICE_X72Y127 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][62]/C clock pessimism 0.220 11.220 clock uncertainty -0.035 11.185 SLICE_X72Y127 FDCE (Setup_GFF2_SLICEL_C_CE) -0.058 11.127 SFP_GEN[5].rx_data_ngccm_reg[5][62] ------------------------------------------------------------------- required time 11.127 arrival time -7.922 ------------------------------------------------------------------- slack 3.205 Slack (MET) : 3.205ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[5].rx_data_ngccm_reg[5][69]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 5.114ns (logic 0.291ns (5.690%) route 4.823ns (94.310%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.095ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.683ns = ( 11.000 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.665ns, distribution 1.668ns) Clock Net Delay (Destination): 2.285ns (routing 0.604ns, distribution 1.681ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y141 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.662 5.609 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X85Y145 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.152 5.761 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[5].rx_data_ngccm[5][83]_i_1/O net (fo=76, routed) 2.161 7.922 rx_data_ngccm[5] SLICE_X72Y127 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][69]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.285 11.000 RX_WORDCLK_O[5] SLICE_X72Y127 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][69]/C clock pessimism 0.220 11.220 clock uncertainty -0.035 11.185 SLICE_X72Y127 FDCE (Setup_HFF2_SLICEL_C_CE) -0.058 11.127 SFP_GEN[5].rx_data_ngccm_reg[5][69] ------------------------------------------------------------------- required time 11.127 arrival time -7.922 ------------------------------------------------------------------- slack 3.205 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.033ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[5].rx_data_ngccm_reg[5][60]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.048ns (33.333%) route 0.096ns (66.667%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.368ns Source Clock Delay (SCD): 1.125ns Clock Pessimism Removal (CPR): 0.187ns Clock Net Delay (Source): 1.007ns (routing 0.300ns, distribution 0.707ns) Clock Net Delay (Destination): 1.203ns (routing 0.344ns, distribution 0.859ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.125 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X72Y128 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y128 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 1.173 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/Q net (fo=1, routed) 0.096 1.269 rx_data[5][60] SLICE_X72Y127 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][60]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.203 1.368 RX_WORDCLK_O[5] SLICE_X72Y127 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][60]/C clock pessimism -0.187 1.181 SLICE_X72Y127 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.236 SFP_GEN[5].rx_data_ngccm_reg[5][60] ------------------------------------------------------------------- required time -1.236 arrival time 1.269 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.087ns (50.289%) route 0.086ns (49.711%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.131ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 1.013ns (routing 0.300ns, distribution 0.713ns) Clock Net Delay (Destination): 1.194ns (routing 0.344ns, distribution 0.850ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.013 1.131 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X73Y128 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X73Y128 FDCE (Prop_FFF2_SLICEM_C_Q) 0.048 1.179 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.074 1.253 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/O84[1] SLICE_X72Y128 LUT3 (Prop_H5LUT_SLICEL_I2_O) 0.039 1.292 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__4/O net (fo=1, routed) 0.012 1.304 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[18] SLICE_X72Y128 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.194 1.359 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X72Y128 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C clock pessimism -0.153 1.206 SLICE_X72Y128 FDRE (Hold_HFF2_SLICEL_C_D) 0.056 1.262 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18] ------------------------------------------------------------------- required time -1.262 arrival time 1.304 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.170ns (logic 0.079ns (46.471%) route 0.091ns (53.529%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.356ns Source Clock Delay (SCD): 1.131ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 1.013ns (routing 0.300ns, distribution 0.713ns) Clock Net Delay (Destination): 1.191ns (routing 0.344ns, distribution 0.847ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.013 1.131 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X72Y127 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y127 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.179 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Q net (fo=2, routed) 0.075 1.254 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_3_in SLICE_X73Y127 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.031 1.285 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__4/O net (fo=1, routed) 0.016 1.301 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[0] SLICE_X73Y127 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.191 1.356 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X73Y127 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.153 1.203 SLICE_X73Y127 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.259 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -1.259 arrival time 1.301 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/psAddress_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.152ns (logic 0.063ns (41.447%) route 0.089ns (58.553%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.338ns Source Clock Delay (SCD): 1.101ns Clock Pessimism Removal (CPR): 0.184ns Clock Net Delay (Source): 0.983ns (routing 0.300ns, distribution 0.683ns) Clock Net Delay (Destination): 1.173ns (routing 0.344ns, distribution 0.829ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.983 1.101 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y140 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/psAddress_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X86Y140 FDCE (Prop_HFF_SLICEL_C_Q) 0.048 1.149 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/psAddress_reg[1]/Q net (fo=8, routed) 0.073 1.222 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/psAddress[1] SLICE_X86Y141 LUT6 (Prop_H6LUT_SLICEL_I4_O) 0.015 1.237 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_i_1__4/O net (fo=1, routed) 0.016 1.253 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd SLICE_X86Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.173 1.338 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_reg/C clock pessimism -0.184 1.154 SLICE_X86Y141 FDCE (Hold_HFF_SLICEL_C_D) 0.056 1.210 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_reg ------------------------------------------------------------------- required time -1.210 arrival time 1.253 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[31]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[31]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.048ns (33.566%) route 0.095ns (66.434%)) Logic Levels: 0 Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.346ns Source Clock Delay (SCD): 1.116ns Clock Pessimism Removal (CPR): 0.187ns Clock Net Delay (Source): 0.998ns (routing 0.300ns, distribution 0.698ns) Clock Net Delay (Destination): 1.181ns (routing 0.344ns, distribution 0.837ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.116 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X78Y139 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[31]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y139 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 1.164 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[31]/Q net (fo=1, routed) 0.095 1.259 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0[31] SLICE_X78Y140 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.181 1.346 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X78Y140 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[31]/C clock pessimism -0.187 1.159 SLICE_X78Y140 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.214 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[31] ------------------------------------------------------------------- required time -1.214 arrival time 1.259 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[5].rx_data_ngccm_reg[5][48]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.049ns (31.613%) route 0.106ns (68.387%)) Logic Levels: 0 Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.361ns Source Clock Delay (SCD): 1.122ns Clock Pessimism Removal (CPR): 0.187ns Clock Net Delay (Source): 1.004ns (routing 0.300ns, distribution 0.704ns) Clock Net Delay (Destination): 1.196ns (routing 0.344ns, distribution 0.852ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.004 1.122 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X72Y132 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y132 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.171 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/Q net (fo=1, routed) 0.106 1.277 rx_data[5][48] SLICE_X72Y131 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][48]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.196 1.361 RX_WORDCLK_O[5] SLICE_X72Y131 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][48]/C clock pessimism -0.187 1.174 SLICE_X72Y131 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.230 SFP_GEN[5].rx_data_ngccm_reg[5][48] ------------------------------------------------------------------- required time -1.230 arrival time 1.277 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.175ns (logic 0.088ns (50.286%) route 0.087ns (49.714%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.356ns Source Clock Delay (SCD): 1.131ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 1.013ns (routing 0.300ns, distribution 0.713ns) Clock Net Delay (Destination): 1.191ns (routing 0.344ns, distribution 0.847ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.013 1.131 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X72Y127 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y127 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.179 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Q net (fo=2, routed) 0.075 1.254 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_3_in SLICE_X73Y127 LUT3 (Prop_D5LUT_SLICEM_I0_O) 0.040 1.294 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__4/O net (fo=1, routed) 0.012 1.306 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[2] SLICE_X73Y127 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.191 1.356 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X73Y127 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C clock pessimism -0.153 1.203 SLICE_X73Y127 FDRE (Hold_DFF2_SLICEM_C_D) 0.056 1.259 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2] ------------------------------------------------------------------- required time -1.259 arrival time 1.306 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[73]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[73]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.048ns (30.968%) route 0.107ns (69.032%)) Logic Levels: 0 Clock Path Skew: 0.049ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.346ns Source Clock Delay (SCD): 1.110ns Clock Pessimism Removal (CPR): 0.187ns Clock Net Delay (Source): 0.992ns (routing 0.300ns, distribution 0.692ns) Clock Net Delay (Destination): 1.181ns (routing 0.344ns, distribution 0.837ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.992 1.110 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X75Y138 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[73]/C ------------------------------------------------------------------- ------------------- SLICE_X75Y138 FDCE (Prop_HFF_SLICEL_C_Q) 0.048 1.158 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[73]/Q net (fo=1, routed) 0.107 1.265 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0[73] SLICE_X75Y137 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[73]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.181 1.346 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X75Y137 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[73]/C clock pessimism -0.187 1.159 SLICE_X75Y137 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.215 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[73] ------------------------------------------------------------------- required time -1.215 arrival time 1.265 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.179ns (logic 0.078ns (43.575%) route 0.101ns (56.425%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.340ns Source Clock Delay (SCD): 1.113ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.995ns (routing 0.300ns, distribution 0.695ns) Clock Net Delay (Destination): 1.175ns (routing 0.344ns, distribution 0.831ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.995 1.113 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X77Y143 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X77Y143 FDCE (Prop_CFF2_SLICEM_C_Q) 0.048 1.161 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/Q net (fo=2, routed) 0.085 1.246 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_9_in SLICE_X76Y143 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.030 1.276 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__4/O net (fo=1, routed) 0.016 1.292 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[5] SLICE_X76Y143 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.175 1.340 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X76Y143 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism -0.154 1.186 SLICE_X76Y143 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.242 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time -1.242 arrival time 1.292 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[5].rx_data_ngccm_reg[5][44]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.159ns (logic 0.049ns (30.818%) route 0.110ns (69.182%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.361ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.187ns Clock Net Delay (Source): 1.003ns (routing 0.300ns, distribution 0.703ns) Clock Net Delay (Destination): 1.196ns (routing 0.344ns, distribution 0.852ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.003 1.121 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X72Y133 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y133 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.170 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/Q net (fo=1, routed) 0.110 1.280 rx_data[5][44] SLICE_X72Y131 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][44]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.196 1.361 RX_WORDCLK_O[5] SLICE_X72Y131 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][44]/C clock pessimism -0.187 1.174 SLICE_X72Y131 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.230 SFP_GEN[5].rx_data_ngccm_reg[5][44] ------------------------------------------------------------------- required time -1.230 arrival time 1.280 ------------------------------------------------------------------- slack 0.050 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_7 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y69 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X83Y179 g_clock_rate_din[5].ngccm_status_cnt_reg[5][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X83Y179 g_clock_rate_din[5].ngccm_status_cnt_reg[5][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X83Y179 g_clock_rate_din[5].ngccm_status_cnt_reg[5][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X83Y179 g_clock_rate_din[5].ngccm_status_cnt_reg[5][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X83Y179 g_clock_rate_din[5].ngccm_status_cnt_reg[5][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X83Y179 g_clock_rate_din[5].ngccm_status_cnt_reg[5][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X82Y177 g_clock_rate_din[5].ngccm_status_cnt_reg[5][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X82Y177 g_clock_rate_din[5].ngccm_status_cnt_reg[5][6]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X84Y146 g_clock_rate_din[5].rx_frameclk_div2_reg[5]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X82Y177 g_clock_rate_din[5].rx_test_comm_cnt_reg[5]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X85Y142 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X85Y141 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X85Y141 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X83Y179 g_clock_rate_din[5].ngccm_status_cnt_reg[5][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X83Y179 g_clock_rate_din[5].ngccm_status_cnt_reg[5][1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X83Y179 g_clock_rate_din[5].ngccm_status_cnt_reg[5][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X83Y179 g_clock_rate_din[5].ngccm_status_cnt_reg[5][3]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X83Y179 g_clock_rate_din[5].ngccm_status_cnt_reg[5][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X83Y179 g_clock_rate_din[5].ngccm_status_cnt_reg[5][5]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.037 0.493 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.037 1.291 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_8 To Clock: gtwiz_userclk_rx_srcclk_out[0]_8 Setup : 0 Failing Endpoints, Worst Slack 3.788ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.037ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.788ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 4.201ns (logic 1.552ns (36.944%) route 2.649ns (63.056%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.239ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.259ns = ( 10.576 - 8.317 ) Source Clock Delay (SCD): 2.713ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.238ns (routing 0.664ns, distribution 1.574ns) Clock Net Delay (Destination): 1.861ns (routing 0.602ns, distribution 1.259ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.238 2.713 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.799 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.848 5.647 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X106Y147 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.149 5.796 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/O net (fo=5, routed) 0.309 6.105 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X106Y146 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.171 6.276 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__5/O net (fo=1, routed) 0.075 6.351 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__5_n_0 SLICE_X106Y146 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 6.497 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__5/O net (fo=2, routed) 0.417 6.914 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__5_n_0 SLICE_X105Y148 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.861 10.576 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y148 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.215 10.791 clock uncertainty -0.035 10.756 SLICE_X105Y148 FDCE (Setup_CFF_SLICEL_C_CE) -0.054 10.702 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.702 arrival time -6.914 ------------------------------------------------------------------- slack 3.788 Slack (MET) : 3.788ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 4.201ns (logic 1.552ns (36.944%) route 2.649ns (63.056%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.239ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.259ns = ( 10.576 - 8.317 ) Source Clock Delay (SCD): 2.713ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.238ns (routing 0.664ns, distribution 1.574ns) Clock Net Delay (Destination): 1.861ns (routing 0.602ns, distribution 1.259ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.238 2.713 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.799 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.848 5.647 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X106Y147 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.149 5.796 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/O net (fo=5, routed) 0.309 6.105 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X106Y146 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.171 6.276 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__5/O net (fo=1, routed) 0.075 6.351 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__5_n_0 SLICE_X106Y146 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 6.497 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__5/O net (fo=2, routed) 0.417 6.914 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__5_n_0 SLICE_X105Y148 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.861 10.576 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y148 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.215 10.791 clock uncertainty -0.035 10.756 SLICE_X105Y148 FDCE (Setup_DFF_SLICEL_C_CE) -0.054 10.702 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.702 arrival time -6.914 ------------------------------------------------------------------- slack 3.788 Slack (MET) : 4.026ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[42]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 4.101ns (logic 1.084ns (26.433%) route 3.017ns (73.567%)) Logic Levels: 0 Clock Path Skew: -0.218ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.280ns = ( 10.597 - 8.317 ) Source Clock Delay (SCD): 2.713ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.238ns (routing 0.664ns, distribution 1.574ns) Clock Net Delay (Destination): 1.882ns (routing 0.602ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.238 2.713 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.797 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.017 6.814 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/D[2] SLICE_X102Y131 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[42]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.882 10.597 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X102Y131 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[42]/C clock pessimism 0.215 10.812 clock uncertainty -0.035 10.777 SLICE_X102Y131 FDCE (Setup_DFF_SLICEL_C_D) 0.063 10.840 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[42] ------------------------------------------------------------------- required time 10.840 arrival time -6.814 ------------------------------------------------------------------- slack 4.026 Slack (MET) : 4.035ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[64]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 4.098ns (logic 1.188ns (28.990%) route 2.910ns (71.010%)) Logic Levels: 0 Clock Path Skew: -0.212ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.286ns = ( 10.603 - 8.317 ) Source Clock Delay (SCD): 2.713ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.238ns (routing 0.664ns, distribution 1.574ns) Clock Net Delay (Destination): 1.888ns (routing 0.602ns, distribution 1.286ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.238 2.713 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[4]) 1.188 3.901 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[4] net (fo=6, routed) 2.910 6.811 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/D[4] SLICE_X101Y134 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[64]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.888 10.603 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X101Y134 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[64]/C clock pessimism 0.215 10.818 clock uncertainty -0.035 10.783 SLICE_X101Y134 FDCE (Setup_DFF_SLICEM_C_D) 0.063 10.846 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[64] ------------------------------------------------------------------- required time 10.846 arrival time -6.811 ------------------------------------------------------------------- slack 4.035 Slack (MET) : 4.066ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 3.919ns (logic 1.385ns (35.341%) route 2.534ns (64.659%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.239ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.259ns = ( 10.576 - 8.317 ) Source Clock Delay (SCD): 2.713ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.238ns (routing 0.664ns, distribution 1.574ns) Clock Net Delay (Destination): 1.861ns (routing 0.602ns, distribution 1.259ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.238 2.713 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.799 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.848 5.647 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X106Y147 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.149 5.796 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/O net (fo=5, routed) 0.172 5.968 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X106Y146 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.150 6.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/O net (fo=7, routed) 0.514 6.632 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 SLICE_X105Y147 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.861 10.576 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y147 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.215 10.791 clock uncertainty -0.035 10.756 SLICE_X105Y147 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 10.698 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 10.698 arrival time -6.632 ------------------------------------------------------------------- slack 4.066 Slack (MET) : 4.137ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[51]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 3.986ns (logic 1.088ns (27.296%) route 2.898ns (72.704%)) Logic Levels: 0 Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.276ns = ( 10.593 - 8.317 ) Source Clock Delay (SCD): 2.713ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.238ns (routing 0.664ns, distribution 1.574ns) Clock Net Delay (Destination): 1.878ns (routing 0.602ns, distribution 1.276ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.238 2.713 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[9]) 1.088 3.801 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[9] net (fo=6, routed) 2.898 6.699 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/D[11] SLICE_X103Y132 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[51]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.878 10.593 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X103Y132 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[51]/C clock pessimism 0.215 10.808 clock uncertainty -0.035 10.773 SLICE_X103Y132 FDCE (Setup_FFF_SLICEM_C_D) 0.063 10.836 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[51] ------------------------------------------------------------------- required time 10.836 arrival time -6.699 ------------------------------------------------------------------- slack 4.137 Slack (MET) : 4.158ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 3.826ns (logic 1.385ns (36.200%) route 2.441ns (63.800%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.243ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.255ns = ( 10.572 - 8.317 ) Source Clock Delay (SCD): 2.713ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.238ns (routing 0.664ns, distribution 1.574ns) Clock Net Delay (Destination): 1.857ns (routing 0.602ns, distribution 1.255ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.238 2.713 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.799 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.848 5.647 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X106Y147 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.149 5.796 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/O net (fo=5, routed) 0.172 5.968 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X106Y146 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.150 6.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/O net (fo=7, routed) 0.421 6.539 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 SLICE_X105Y146 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.857 10.572 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y146 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.215 10.787 clock uncertainty -0.035 10.752 SLICE_X105Y146 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 10.697 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 10.697 arrival time -6.539 ------------------------------------------------------------------- slack 4.158 Slack (MET) : 4.163ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 3.822ns (logic 1.385ns (36.238%) route 2.437ns (63.762%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.243ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.255ns = ( 10.572 - 8.317 ) Source Clock Delay (SCD): 2.713ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.238ns (routing 0.664ns, distribution 1.574ns) Clock Net Delay (Destination): 1.857ns (routing 0.602ns, distribution 1.255ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.238 2.713 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.799 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.848 5.647 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X106Y147 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.149 5.796 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/O net (fo=5, routed) 0.172 5.968 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X106Y146 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.150 6.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/O net (fo=7, routed) 0.417 6.535 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 SLICE_X105Y146 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.857 10.572 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y146 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.215 10.787 clock uncertainty -0.035 10.752 SLICE_X105Y146 FDRE (Setup_BFF_SLICEL_C_CE) -0.054 10.698 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 10.698 arrival time -6.535 ------------------------------------------------------------------- slack 4.163 Slack (MET) : 4.163ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 3.822ns (logic 1.385ns (36.238%) route 2.437ns (63.762%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.243ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.255ns = ( 10.572 - 8.317 ) Source Clock Delay (SCD): 2.713ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.238ns (routing 0.664ns, distribution 1.574ns) Clock Net Delay (Destination): 1.857ns (routing 0.602ns, distribution 1.255ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.238 2.713 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.799 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.848 5.647 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X106Y147 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.149 5.796 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/O net (fo=5, routed) 0.172 5.968 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X106Y146 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.150 6.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/O net (fo=7, routed) 0.417 6.535 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 SLICE_X105Y146 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.857 10.572 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y146 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.215 10.787 clock uncertainty -0.035 10.752 SLICE_X105Y146 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 10.698 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 10.698 arrival time -6.535 ------------------------------------------------------------------- slack 4.163 Slack (MET) : 4.196ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[83]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 3.929ns (logic 1.161ns (29.550%) route 2.768ns (70.451%)) Logic Levels: 0 Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.278ns = ( 10.595 - 8.317 ) Source Clock Delay (SCD): 2.713ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.238ns (routing 0.664ns, distribution 1.574ns) Clock Net Delay (Destination): 1.880ns (routing 0.602ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.238 2.713 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.874 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.768 6.642 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/D[3] SLICE_X103Y132 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[83]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.880 10.595 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X103Y132 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[83]/C clock pessimism 0.215 10.810 clock uncertainty -0.035 10.775 SLICE_X103Y132 FDCE (Setup_CFF_SLICEM_C_D) 0.063 10.838 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[83] ------------------------------------------------------------------- required time 10.838 arrival time -6.642 ------------------------------------------------------------------- slack 4.196 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.037ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[6].rx_data_ngccm_reg[6][24]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.048ns (27.746%) route 0.125ns (72.254%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.154ns Source Clock Delay (SCD): 0.942ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.824ns (routing 0.301ns, distribution 0.523ns) Clock Net Delay (Destination): 0.989ns (routing 0.342ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.824 0.942 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X96Y143 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y143 FDRE (Prop_CFF2_SLICEL_C_Q) 0.048 0.990 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/Q net (fo=1, routed) 0.125 1.115 rx_data[6][24] SLICE_X97Y143 FDCE r SFP_GEN[6].rx_data_ngccm_reg[6][24]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.154 RX_WORDCLK_O[6] SLICE_X97Y143 FDCE r SFP_GEN[6].rx_data_ngccm_reg[6][24]/C clock pessimism -0.132 1.022 SLICE_X97Y143 FDCE (Hold_BFF_SLICEM_C_D) 0.056 1.078 SFP_GEN[6].rx_data_ngccm_reg[6][24] ------------------------------------------------------------------- required time -1.078 arrival time 1.115 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.037ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[6].rx_data_ngccm_reg[6][35]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.048ns (33.803%) route 0.094ns (66.197%)) Logic Levels: 0 Clock Path Skew: 0.049ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.151ns Source Clock Delay (SCD): 0.939ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 0.821ns (routing 0.301ns, distribution 0.520ns) Clock Net Delay (Destination): 0.986ns (routing 0.342ns, distribution 0.644ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.821 0.939 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X98Y143 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X98Y143 FDRE (Prop_CFF2_SLICEL_C_Q) 0.048 0.987 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/Q net (fo=1, routed) 0.094 1.081 rx_data[6][35] SLICE_X98Y142 FDCE r SFP_GEN[6].rx_data_ngccm_reg[6][35]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.986 1.151 RX_WORDCLK_O[6] SLICE_X98Y142 FDCE r SFP_GEN[6].rx_data_ngccm_reg[6][35]/C clock pessimism -0.163 0.988 SLICE_X98Y142 FDCE (Hold_GFF2_SLICEL_C_D) 0.056 1.044 SFP_GEN[6].rx_data_ngccm_reg[6][35] ------------------------------------------------------------------- required time -1.044 arrival time 1.081 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.040ns (arrival time - required time) Source: SFP_GEN[6].rx_data_ngccm_reg[6][59]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[58]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.087ns (50.289%) route 0.086ns (49.711%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.147ns Source Clock Delay (SCD): 0.938ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.820ns (routing 0.301ns, distribution 0.519ns) Clock Net Delay (Destination): 0.982ns (routing 0.342ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.820 0.938 RX_WORDCLK_O[6] SLICE_X100Y127 FDCE r SFP_GEN[6].rx_data_ngccm_reg[6][59]/C ------------------------------------------------------------------- ------------------- SLICE_X100Y127 FDCE (Prop_BFF_SLICEM_C_Q) 0.049 0.987 r SFP_GEN[6].rx_data_ngccm_reg[6][59]/Q net (fo=1, routed) 0.075 1.062 SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[83]_0[51] SLICE_X99Y127 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.038 1.100 r SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[58]_i_1/O net (fo=1, routed) 0.011 1.111 SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[58]_i_1_n_0 SLICE_X99Y127 FDCE r SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[58]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.982 1.147 SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X99Y127 FDCE r SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[58]/C clock pessimism -0.132 1.015 SLICE_X99Y127 FDCE (Hold_DFF2_SLICEL_C_D) 0.056 1.071 SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[58] ------------------------------------------------------------------- required time -1.071 arrival time 1.111 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[6].rx_data_ngccm_reg[6][37]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.048ns (33.103%) route 0.097ns (66.897%)) Logic Levels: 0 Clock Path Skew: 0.046ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.146ns Source Clock Delay (SCD): 0.937ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 0.819ns (routing 0.301ns, distribution 0.518ns) Clock Net Delay (Destination): 0.981ns (routing 0.342ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.819 0.937 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X98Y141 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X98Y141 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 0.985 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/Q net (fo=1, routed) 0.097 1.082 rx_data[6][37] SLICE_X98Y139 FDCE r SFP_GEN[6].rx_data_ngccm_reg[6][37]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.981 1.146 RX_WORDCLK_O[6] SLICE_X98Y139 FDCE r SFP_GEN[6].rx_data_ngccm_reg[6][37]/C clock pessimism -0.163 0.983 SLICE_X98Y139 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.038 SFP_GEN[6].rx_data_ngccm_reg[6][37] ------------------------------------------------------------------- required time -1.038 arrival time 1.082 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[6].rx_data_ngccm_reg[6][4]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.048ns (33.333%) route 0.096ns (66.667%)) Logic Levels: 0 Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.146ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 0.822ns (routing 0.301ns, distribution 0.521ns) Clock Net Delay (Destination): 0.981ns (routing 0.342ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.822 0.940 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X98Y140 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X98Y140 FDRE (Prop_GFF_SLICEL_C_Q) 0.048 0.988 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/Q net (fo=1, routed) 0.096 1.084 rx_data[6][4] SLICE_X98Y139 FDCE r SFP_GEN[6].rx_data_ngccm_reg[6][4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.981 1.146 RX_WORDCLK_O[6] SLICE_X98Y139 FDCE r SFP_GEN[6].rx_data_ngccm_reg[6][4]/C clock pessimism -0.163 0.983 SLICE_X98Y139 FDCE (Hold_GFF2_SLICEL_C_D) 0.056 1.039 SFP_GEN[6].rx_data_ngccm_reg[6][4] ------------------------------------------------------------------- required time -1.039 arrival time 1.084 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.048ns (arrival time - required time) Source: SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[26]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[6].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.180ns (logic 0.049ns (27.222%) route 0.131ns (72.778%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.148ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.822ns (routing 0.301ns, distribution 0.521ns) Clock Net Delay (Destination): 0.983ns (routing 0.342ns, distribution 0.641ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.822 0.940 SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X98Y142 FDCE r SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[26]/C ------------------------------------------------------------------- ------------------- SLICE_X98Y142 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 0.989 r SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[26]/Q net (fo=2, routed) 0.131 1.120 SFP_GEN[6].ngCCM_gbt/gbt_rx_checker/Q[10] SLICE_X96Y143 FDRE r SFP_GEN[6].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.983 1.148 SFP_GEN[6].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y143 FDRE r SFP_GEN[6].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]/C clock pessimism -0.132 1.016 SLICE_X96Y143 FDRE (Hold_HFF2_SLICEL_C_D) 0.056 1.072 SFP_GEN[6].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10] ------------------------------------------------------------------- required time -1.072 arrival time 1.120 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.050ns (arrival time - required time) Source: SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[29]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[6].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.182ns (logic 0.048ns (26.374%) route 0.134ns (73.626%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.148ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.822ns (routing 0.301ns, distribution 0.521ns) Clock Net Delay (Destination): 0.983ns (routing 0.342ns, distribution 0.641ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.822 0.940 SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X98Y142 FDCE r SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[29]/C ------------------------------------------------------------------- ------------------- SLICE_X98Y142 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 0.988 r SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[29]/Q net (fo=2, routed) 0.134 1.122 SFP_GEN[6].ngCCM_gbt/gbt_rx_checker/Q[13] SLICE_X96Y143 FDRE r SFP_GEN[6].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.983 1.148 SFP_GEN[6].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y143 FDRE r SFP_GEN[6].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/C clock pessimism -0.132 1.016 SLICE_X96Y143 FDRE (Hold_GFF2_SLICEL_C_D) 0.056 1.072 SFP_GEN[6].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13] ------------------------------------------------------------------- required time -1.072 arrival time 1.122 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[6].rx_data_ngccm_reg[6][76]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.183ns (logic 0.048ns (26.229%) route 0.135ns (73.770%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.146ns Source Clock Delay (SCD): 0.937ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.819ns (routing 0.301ns, distribution 0.518ns) Clock Net Delay (Destination): 0.981ns (routing 0.342ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.819 0.937 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X100Y128 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X100Y128 FDRE (Prop_HFF_SLICEM_C_Q) 0.048 0.985 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/Q net (fo=1, routed) 0.135 1.120 rx_data[6][76] SLICE_X99Y129 FDCE r SFP_GEN[6].rx_data_ngccm_reg[6][76]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.981 1.146 RX_WORDCLK_O[6] SLICE_X99Y129 FDCE r SFP_GEN[6].rx_data_ngccm_reg[6][76]/C clock pessimism -0.132 1.014 SLICE_X99Y129 FDCE (Hold_AFF2_SLICEL_C_D) 0.056 1.070 SFP_GEN[6].rx_data_ngccm_reg[6][76] ------------------------------------------------------------------- required time -1.070 arrival time 1.120 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[29]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[29]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.159ns (logic 0.049ns (30.818%) route 0.110ns (69.182%)) Logic Levels: 0 Clock Path Skew: 0.051ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.152ns Source Clock Delay (SCD): 0.938ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 0.820ns (routing 0.301ns, distribution 0.519ns) Clock Net Delay (Destination): 0.987ns (routing 0.342ns, distribution 0.645ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.820 0.938 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X101Y140 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[29]/C ------------------------------------------------------------------- ------------------- SLICE_X101Y140 FDCE (Prop_BFF_SLICEM_C_Q) 0.049 0.987 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[29]/Q net (fo=1, routed) 0.110 1.097 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[29] SLICE_X101Y138 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.987 1.152 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X101Y138 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[29]/C clock pessimism -0.163 0.989 SLICE_X101Y138 FDCE (Hold_GFF2_SLICEM_C_D) 0.056 1.045 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[29] ------------------------------------------------------------------- required time -1.045 arrival time 1.097 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[20]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.161ns (logic 0.063ns (39.130%) route 0.098ns (60.870%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.151ns Source Clock Delay (SCD): 0.935ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 0.817ns (routing 0.301ns, distribution 0.516ns) Clock Net Delay (Destination): 0.986ns (routing 0.342ns, distribution 0.644ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.817 0.935 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X102Y142 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X102Y142 FDCE (Prop_CFF2_SLICEL_C_Q) 0.048 0.983 f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/Q net (fo=28, routed) 0.082 1.065 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] SLICE_X102Y140 LUT5 (Prop_C6LUT_SLICEL_I0_O) 0.015 1.080 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[20]_i_1__7/O net (fo=1, routed) 0.016 1.096 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg00[20] SLICE_X102Y140 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.986 1.151 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X102Y140 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[20]/C clock pessimism -0.163 0.988 SLICE_X102Y140 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.044 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[20] ------------------------------------------------------------------- required time -1.044 arrival time 1.096 ------------------------------------------------------------------- slack 0.052 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_8 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y64 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X88Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X88Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X88Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X90Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X90Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X90Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X99Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X88Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X88Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X88Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][2]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X90Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][3]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X90Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][4]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X90Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][5]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X95Y123 g_clock_rate_din[6].rx_wordclk_div2_reg[6]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X102Y150 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X102Y150 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X101Y150 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X101Y150 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/C High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X102Y125 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_9 To Clock: gtwiz_userclk_rx_srcclk_out[0]_9 Setup : 0 Failing Endpoints, Worst Slack 3.070ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.037ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.070ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 5.291ns (logic 1.507ns (28.482%) route 3.784ns (71.518%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.133ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.660ns = ( 10.977 - 8.317 ) Source Clock Delay (SCD): 2.750ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.275ns (routing 0.683ns, distribution 1.592ns) Clock Net Delay (Destination): 2.262ns (routing 0.619ns, distribution 1.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.275 2.750 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.854 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.967 6.821 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X84Y151 LUT4 (Prop_C6LUT_SLICEL_I1_O) 0.146 6.967 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/O net (fo=5, routed) 0.270 7.237 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X84Y154 LUT4 (Prop_H6LUT_SLICEL_I2_O) 0.167 7.404 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__6/O net (fo=1, routed) 0.073 7.477 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__6_n_0 SLICE_X84Y154 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.090 7.567 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__6/O net (fo=2, routed) 0.474 8.041 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__6_n_0 SLICE_X84Y151 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.262 10.977 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y151 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.223 11.200 clock uncertainty -0.035 11.165 SLICE_X84Y151 FDCE (Setup_BFF_SLICEL_C_CE) -0.054 11.111 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.111 arrival time -8.041 ------------------------------------------------------------------- slack 3.070 Slack (MET) : 3.070ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 5.291ns (logic 1.507ns (28.482%) route 3.784ns (71.518%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.133ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.660ns = ( 10.977 - 8.317 ) Source Clock Delay (SCD): 2.750ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.275ns (routing 0.683ns, distribution 1.592ns) Clock Net Delay (Destination): 2.262ns (routing 0.619ns, distribution 1.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.275 2.750 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.854 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.967 6.821 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X84Y151 LUT4 (Prop_C6LUT_SLICEL_I1_O) 0.146 6.967 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/O net (fo=5, routed) 0.270 7.237 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X84Y154 LUT4 (Prop_H6LUT_SLICEL_I2_O) 0.167 7.404 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__6/O net (fo=1, routed) 0.073 7.477 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__6_n_0 SLICE_X84Y154 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.090 7.567 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__6/O net (fo=2, routed) 0.474 8.041 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__6_n_0 SLICE_X84Y151 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.262 10.977 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y151 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.223 11.200 clock uncertainty -0.035 11.165 SLICE_X84Y151 FDCE (Setup_DFF_SLICEL_C_CE) -0.054 11.111 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.111 arrival time -8.041 ------------------------------------------------------------------- slack 3.070 Slack (MET) : 3.089ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].rx_data_ngccm_reg[7][69]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 5.187ns (logic 0.287ns (5.533%) route 4.900ns (94.467%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.690ns = ( 11.007 - 8.317 ) Source Clock Delay (SCD): 2.860ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.385ns (routing 0.683ns, distribution 1.702ns) Clock Net Delay (Destination): 2.292ns (routing 0.619ns, distribution 1.673ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.385 2.860 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y171 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.999 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.690 5.689 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X83Y160 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.148 5.837 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[7].rx_data_ngccm[7][83]_i_1/O net (fo=76, routed) 2.210 8.047 rx_data_ngccm[7] SLICE_X74Y145 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][69]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.292 11.007 RX_WORDCLK_O[7] SLICE_X74Y145 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][69]/C clock pessimism 0.223 11.230 clock uncertainty -0.035 11.194 SLICE_X74Y145 FDCE (Setup_EFF2_SLICEL_C_CE) -0.058 11.136 SFP_GEN[7].rx_data_ngccm_reg[7][69] ------------------------------------------------------------------- required time 11.136 arrival time -8.047 ------------------------------------------------------------------- slack 3.089 Slack (MET) : 3.091ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].rx_data_ngccm_reg[7][49]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 5.190ns (logic 0.287ns (5.530%) route 4.903ns (94.470%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.058ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.695ns = ( 11.012 - 8.317 ) Source Clock Delay (SCD): 2.860ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.385ns (routing 0.683ns, distribution 1.702ns) Clock Net Delay (Destination): 2.297ns (routing 0.619ns, distribution 1.678ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.385 2.860 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y171 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.999 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.690 5.689 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X83Y160 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.148 5.837 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[7].rx_data_ngccm[7][83]_i_1/O net (fo=76, routed) 2.213 8.050 rx_data_ngccm[7] SLICE_X73Y145 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][49]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.297 11.012 RX_WORDCLK_O[7] SLICE_X73Y145 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][49]/C clock pessimism 0.223 11.235 clock uncertainty -0.035 11.199 SLICE_X73Y145 FDCE (Setup_EFF2_SLICEM_C_CE) -0.058 11.141 SFP_GEN[7].rx_data_ngccm_reg[7][49] ------------------------------------------------------------------- required time 11.141 arrival time -8.050 ------------------------------------------------------------------- slack 3.091 Slack (MET) : 3.091ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].rx_data_ngccm_reg[7][51]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 5.190ns (logic 0.287ns (5.530%) route 4.903ns (94.470%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.058ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.695ns = ( 11.012 - 8.317 ) Source Clock Delay (SCD): 2.860ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.385ns (routing 0.683ns, distribution 1.702ns) Clock Net Delay (Destination): 2.297ns (routing 0.619ns, distribution 1.678ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.385 2.860 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y171 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.999 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.690 5.689 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X83Y160 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.148 5.837 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[7].rx_data_ngccm[7][83]_i_1/O net (fo=76, routed) 2.213 8.050 rx_data_ngccm[7] SLICE_X73Y145 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][51]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.297 11.012 RX_WORDCLK_O[7] SLICE_X73Y145 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][51]/C clock pessimism 0.223 11.235 clock uncertainty -0.035 11.199 SLICE_X73Y145 FDCE (Setup_FFF2_SLICEM_C_CE) -0.058 11.141 SFP_GEN[7].rx_data_ngccm_reg[7][51] ------------------------------------------------------------------- required time 11.141 arrival time -8.050 ------------------------------------------------------------------- slack 3.091 Slack (MET) : 3.095ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].rx_data_ngccm_reg[7][58]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 5.184ns (logic 0.287ns (5.536%) route 4.897ns (94.464%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.690ns = ( 11.007 - 8.317 ) Source Clock Delay (SCD): 2.860ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.385ns (routing 0.683ns, distribution 1.702ns) Clock Net Delay (Destination): 2.292ns (routing 0.619ns, distribution 1.673ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.385 2.860 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y171 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.999 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.690 5.689 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X83Y160 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.148 5.837 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[7].rx_data_ngccm[7][83]_i_1/O net (fo=76, routed) 2.207 8.044 rx_data_ngccm[7] SLICE_X74Y145 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][58]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.292 11.007 RX_WORDCLK_O[7] SLICE_X74Y145 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][58]/C clock pessimism 0.223 11.230 clock uncertainty -0.035 11.194 SLICE_X74Y145 FDCE (Setup_EFF_SLICEL_C_CE) -0.055 11.139 SFP_GEN[7].rx_data_ngccm_reg[7][58] ------------------------------------------------------------------- required time 11.139 arrival time -8.044 ------------------------------------------------------------------- slack 3.095 Slack (MET) : 3.095ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].rx_data_ngccm_reg[7][71]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 5.184ns (logic 0.287ns (5.536%) route 4.897ns (94.464%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.690ns = ( 11.007 - 8.317 ) Source Clock Delay (SCD): 2.860ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.385ns (routing 0.683ns, distribution 1.702ns) Clock Net Delay (Destination): 2.292ns (routing 0.619ns, distribution 1.673ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.385 2.860 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y171 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.999 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.690 5.689 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X83Y160 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.148 5.837 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[7].rx_data_ngccm[7][83]_i_1/O net (fo=76, routed) 2.207 8.044 rx_data_ngccm[7] SLICE_X74Y145 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][71]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.292 11.007 RX_WORDCLK_O[7] SLICE_X74Y145 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][71]/C clock pessimism 0.223 11.230 clock uncertainty -0.035 11.194 SLICE_X74Y145 FDCE (Setup_FFF_SLICEL_C_CE) -0.055 11.139 SFP_GEN[7].rx_data_ngccm_reg[7][71] ------------------------------------------------------------------- required time 11.139 arrival time -8.044 ------------------------------------------------------------------- slack 3.095 Slack (MET) : 3.097ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].rx_data_ngccm_reg[7][48]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 5.187ns (logic 0.287ns (5.533%) route 4.900ns (94.467%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.058ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.695ns = ( 11.012 - 8.317 ) Source Clock Delay (SCD): 2.860ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.385ns (routing 0.683ns, distribution 1.702ns) Clock Net Delay (Destination): 2.297ns (routing 0.619ns, distribution 1.678ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.385 2.860 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y171 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.999 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.690 5.689 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X83Y160 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.148 5.837 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[7].rx_data_ngccm[7][83]_i_1/O net (fo=76, routed) 2.210 8.047 rx_data_ngccm[7] SLICE_X73Y145 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][48]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.297 11.012 RX_WORDCLK_O[7] SLICE_X73Y145 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][48]/C clock pessimism 0.223 11.235 clock uncertainty -0.035 11.199 SLICE_X73Y145 FDCE (Setup_EFF_SLICEM_C_CE) -0.055 11.144 SFP_GEN[7].rx_data_ngccm_reg[7][48] ------------------------------------------------------------------- required time 11.144 arrival time -8.047 ------------------------------------------------------------------- slack 3.097 Slack (MET) : 3.097ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].rx_data_ngccm_reg[7][50]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 5.187ns (logic 0.287ns (5.533%) route 4.900ns (94.467%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.058ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.695ns = ( 11.012 - 8.317 ) Source Clock Delay (SCD): 2.860ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.385ns (routing 0.683ns, distribution 1.702ns) Clock Net Delay (Destination): 2.297ns (routing 0.619ns, distribution 1.678ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.385 2.860 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y171 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.999 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.690 5.689 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X83Y160 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.148 5.837 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[7].rx_data_ngccm[7][83]_i_1/O net (fo=76, routed) 2.210 8.047 rx_data_ngccm[7] SLICE_X73Y145 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][50]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.297 11.012 RX_WORDCLK_O[7] SLICE_X73Y145 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][50]/C clock pessimism 0.223 11.235 clock uncertainty -0.035 11.199 SLICE_X73Y145 FDCE (Setup_FFF_SLICEM_C_CE) -0.055 11.144 SFP_GEN[7].rx_data_ngccm_reg[7][50] ------------------------------------------------------------------- required time 11.144 arrival time -8.047 ------------------------------------------------------------------- slack 3.097 Slack (MET) : 3.097ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].rx_data_ngccm_reg[7][59]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 5.187ns (logic 0.287ns (5.533%) route 4.900ns (94.467%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.058ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.695ns = ( 11.012 - 8.317 ) Source Clock Delay (SCD): 2.860ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.385ns (routing 0.683ns, distribution 1.702ns) Clock Net Delay (Destination): 2.297ns (routing 0.619ns, distribution 1.678ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.385 2.860 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y171 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.999 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.690 5.689 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X83Y160 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.148 5.837 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[7].rx_data_ngccm[7][83]_i_1/O net (fo=76, routed) 2.210 8.047 rx_data_ngccm[7] SLICE_X73Y145 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][59]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.297 11.012 RX_WORDCLK_O[7] SLICE_X73Y145 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][59]/C clock pessimism 0.223 11.235 clock uncertainty -0.035 11.199 SLICE_X73Y145 FDCE (Setup_GFF_SLICEM_C_CE) -0.055 11.144 SFP_GEN[7].rx_data_ngccm_reg[7][59] ------------------------------------------------------------------- required time 11.144 arrival time -8.047 ------------------------------------------------------------------- slack 3.097 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.037ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[38]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[38]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.049ns (34.507%) route 0.093ns (65.493%)) Logic Levels: 0 Clock Path Skew: 0.049ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.377ns Source Clock Delay (SCD): 1.139ns Clock Pessimism Removal (CPR): 0.189ns Clock Net Delay (Source): 1.021ns (routing 0.306ns, distribution 0.715ns) Clock Net Delay (Destination): 1.212ns (routing 0.352ns, distribution 0.860ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.021 1.139 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X74Y154 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[38]/C ------------------------------------------------------------------- ------------------- SLICE_X74Y154 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 1.188 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[38]/Q net (fo=1, routed) 0.093 1.281 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0[38] SLICE_X74Y155 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[38]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.212 1.377 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X74Y155 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[38]/C clock pessimism -0.189 1.188 SLICE_X74Y155 FDCE (Hold_GFF2_SLICEL_C_D) 0.056 1.244 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[38] ------------------------------------------------------------------- required time -1.244 arrival time 1.281 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].rx_data_ngccm_reg[7][38]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.172ns (logic 0.049ns (28.488%) route 0.123ns (71.512%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.364ns Source Clock Delay (SCD): 1.132ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.014ns (routing 0.306ns, distribution 0.708ns) Clock Net Delay (Destination): 1.199ns (routing 0.352ns, distribution 0.847ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.132 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X75Y158 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X75Y158 FDRE (Prop_BFF_SLICEL_C_Q) 0.049 1.181 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/Q net (fo=1, routed) 0.123 1.304 rx_data[7][38] SLICE_X76Y158 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][38]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.199 1.364 RX_WORDCLK_O[7] SLICE_X76Y158 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][38]/C clock pessimism -0.156 1.208 SLICE_X76Y158 FDCE (Hold_BFF_SLICEM_C_D) 0.056 1.264 SFP_GEN[7].rx_data_ngccm_reg[7][38] ------------------------------------------------------------------- required time -1.264 arrival time 1.304 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.043ns (arrival time - required time) Source: SFP_GEN[7].rx_data_ngccm_reg[7][18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[18]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.160ns (logic 0.048ns (30.000%) route 0.112ns (70.000%)) Logic Levels: 0 Clock Path Skew: 0.061ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.353ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.018ns (routing 0.306ns, distribution 0.712ns) Clock Net Delay (Destination): 1.188ns (routing 0.352ns, distribution 0.836ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.018 1.136 RX_WORDCLK_O[7] SLICE_X78Y158 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][18]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y158 FDCE (Prop_EFF2_SLICEL_C_Q) 0.048 1.184 r SFP_GEN[7].rx_data_ngccm_reg[7][18]/Q net (fo=1, routed) 0.112 1.296 SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[83]_0[10] SLICE_X79Y158 FDCE r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[18]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.188 1.353 SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X79Y158 FDCE r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[18]/C clock pessimism -0.156 1.197 SLICE_X79Y158 FDCE (Hold_AFF2_SLICEM_C_D) 0.056 1.253 SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[18] ------------------------------------------------------------------- required time -1.253 arrival time 1.296 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.044ns (arrival time - required time) Source: SFP_GEN[7].rx_data_ngccm_reg[7][47]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[46]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.192ns (logic 0.104ns (54.167%) route 0.088ns (45.833%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.092ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.370ns Source Clock Delay (SCD): 1.122ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.004ns (routing 0.306ns, distribution 0.698ns) Clock Net Delay (Destination): 1.205ns (routing 0.352ns, distribution 0.853ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.004 1.122 RX_WORDCLK_O[7] SLICE_X72Y147 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][47]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y147 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.171 r SFP_GEN[7].rx_data_ngccm_reg[7][47]/Q net (fo=1, routed) 0.077 1.248 SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[83]_0[39] SLICE_X74Y147 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.055 1.303 r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40[46]_i_1/O net (fo=1, routed) 0.011 1.314 SFP_GEN[7].ngCCM_gbt/RX_Word_rx40[46]_i_1_n_0 SLICE_X74Y147 FDCE r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[46]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.205 1.370 SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X74Y147 FDCE r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[46]/C clock pessimism -0.156 1.214 SLICE_X74Y147 FDCE (Hold_DFF2_SLICEL_C_D) 0.056 1.270 SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[46] ------------------------------------------------------------------- required time -1.270 arrival time 1.314 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.178ns (logic 0.088ns (49.438%) route 0.090ns (50.562%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.129ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.011ns (routing 0.306ns, distribution 0.705ns) Clock Net Delay (Destination): 1.194ns (routing 0.352ns, distribution 0.842ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.011 1.129 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X75Y147 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X75Y147 FDCE (Prop_HFF_SLICEL_C_Q) 0.048 1.177 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/Q net (fo=2, routed) 0.078 1.255 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_15_in SLICE_X76Y147 LUT3 (Prop_H5LUT_SLICEM_I2_O) 0.040 1.295 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__6/O net (fo=1, routed) 0.012 1.307 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[6] SLICE_X76Y147 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.194 1.359 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X76Y147 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C clock pessimism -0.156 1.203 SLICE_X76Y147 FDRE (Hold_HFF2_SLICEM_C_D) 0.056 1.259 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6] ------------------------------------------------------------------- required time -1.259 arrival time 1.307 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].rx_data_ngccm_reg[7][21]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.164ns (logic 0.049ns (29.878%) route 0.115ns (70.122%)) Logic Levels: 0 Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.378ns Source Clock Delay (SCD): 1.130ns Clock Pessimism Removal (CPR): 0.188ns Clock Net Delay (Source): 1.012ns (routing 0.306ns, distribution 0.706ns) Clock Net Delay (Destination): 1.213ns (routing 0.352ns, distribution 0.861ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.012 1.130 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X77Y157 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X77Y157 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 1.179 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/Q net (fo=1, routed) 0.115 1.294 rx_data[7][21] SLICE_X77Y158 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][21]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.213 1.378 RX_WORDCLK_O[7] SLICE_X77Y158 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][21]/C clock pessimism -0.188 1.190 SLICE_X77Y158 FDCE (Hold_AFF_SLICEM_C_D) 0.056 1.246 SFP_GEN[7].rx_data_ngccm_reg[7][21] ------------------------------------------------------------------- required time -1.246 arrival time 1.294 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].rx_data_ngccm_reg[7][30]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.191ns (logic 0.049ns (25.654%) route 0.142ns (74.346%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.374ns Source Clock Delay (SCD): 1.132ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 1.014ns (routing 0.306ns, distribution 0.708ns) Clock Net Delay (Destination): 1.209ns (routing 0.352ns, distribution 0.857ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.132 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X75Y158 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X75Y158 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.181 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/Q net (fo=1, routed) 0.142 1.323 rx_data[7][30] SLICE_X78Y158 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][30]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.209 1.374 RX_WORDCLK_O[7] SLICE_X78Y158 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][30]/C clock pessimism -0.155 1.219 SLICE_X78Y158 FDCE (Hold_HFF2_SLICEL_C_D) 0.056 1.275 SFP_GEN[7].rx_data_ngccm_reg[7][30] ------------------------------------------------------------------- required time -1.275 arrival time 1.323 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: SFP_GEN[7].rx_data_ngccm_reg[7][71]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[70]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.104ns (69.799%) route 0.045ns (30.201%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.373ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.196ns Clock Net Delay (Source): 1.015ns (routing 0.306ns, distribution 0.709ns) Clock Net Delay (Destination): 1.208ns (routing 0.352ns, distribution 0.856ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.015 1.133 RX_WORDCLK_O[7] SLICE_X74Y145 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][71]/C ------------------------------------------------------------------- ------------------- SLICE_X74Y145 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.182 r SFP_GEN[7].rx_data_ngccm_reg[7][71]/Q net (fo=1, routed) 0.034 1.216 SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[83]_0[63] SLICE_X74Y145 LUT3 (Prop_C5LUT_SLICEL_I0_O) 0.055 1.271 r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40[70]_i_1/O net (fo=1, routed) 0.011 1.282 SFP_GEN[7].ngCCM_gbt/RX_Word_rx40[70]_i_1_n_0 SLICE_X74Y145 FDCE r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[70]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.208 1.373 SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X74Y145 FDCE r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[70]/C clock pessimism -0.196 1.177 SLICE_X74Y145 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 1.233 SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[70] ------------------------------------------------------------------- required time -1.233 arrival time 1.282 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[22]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[22]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.049ns (34.028%) route 0.095ns (65.972%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.129ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 1.011ns (routing 0.306ns, distribution 0.705ns) Clock Net Delay (Destination): 1.194ns (routing 0.352ns, distribution 0.842ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.011 1.129 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X72Y153 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y153 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 1.178 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[22]/Q net (fo=1, routed) 0.095 1.273 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0[22] SLICE_X72Y154 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.194 1.359 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X72Y154 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[22]/C clock pessimism -0.190 1.169 SLICE_X72Y154 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.224 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[22] ------------------------------------------------------------------- required time -1.224 arrival time 1.273 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].rx_data_ngccm_reg[7][27]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.165ns (logic 0.048ns (29.091%) route 0.117ns (70.909%)) Logic Levels: 0 Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.378ns Source Clock Delay (SCD): 1.130ns Clock Pessimism Removal (CPR): 0.188ns Clock Net Delay (Source): 1.012ns (routing 0.306ns, distribution 0.706ns) Clock Net Delay (Destination): 1.213ns (routing 0.352ns, distribution 0.861ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.012 1.130 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X77Y157 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X77Y157 FDRE (Prop_BFF2_SLICEM_C_Q) 0.048 1.178 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/Q net (fo=1, routed) 0.117 1.295 rx_data[7][27] SLICE_X77Y158 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][27]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.213 1.378 RX_WORDCLK_O[7] SLICE_X77Y158 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][27]/C clock pessimism -0.188 1.190 SLICE_X77Y158 FDCE (Hold_BFF_SLICEM_C_D) 0.056 1.246 SFP_GEN[7].rx_data_ngccm_reg[7][27] ------------------------------------------------------------------- required time -1.246 arrival time 1.295 ------------------------------------------------------------------- slack 0.049 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_9 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y67 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y177 g_clock_rate_din[7].ngccm_status_cnt_reg[7][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X82Y179 g_clock_rate_din[7].ngccm_status_cnt_reg[7][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X82Y179 g_clock_rate_din[7].ngccm_status_cnt_reg[7][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X81Y177 g_clock_rate_din[7].ngccm_status_cnt_reg[7][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X81Y177 g_clock_rate_din[7].ngccm_status_cnt_reg[7][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X82Y179 g_clock_rate_din[7].ngccm_status_cnt_reg[7][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X82Y179 g_clock_rate_din[7].ngccm_status_cnt_reg[7][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y177 g_clock_rate_din[7].ngccm_status_cnt_reg[7][0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X81Y177 g_clock_rate_din[7].ngccm_status_cnt_reg[7][3]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X81Y177 g_clock_rate_din[7].ngccm_status_cnt_reg[7][4]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y156 g_clock_rate_din[7].rx_frameclk_div2_reg[7]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X92Y122 g_clock_rate_din[7].rx_wordclk_div2_reg[7]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X84Y157 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X84Y158 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y156 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y156 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y156 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][5]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y150 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y150 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: txoutclk_out[0]_49 To Clock: txoutclk_out[0]_49 Setup : 0 Failing Endpoints, Worst Slack 0.656ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.031ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.407ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.656ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/prbs_generator/data_o_reg[150]/R (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (txoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 2.283ns (logic 0.376ns (16.470%) route 1.907ns (83.530%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.048ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.139ns = ( 5.258 - 3.119 ) Source Clock Delay (SCD): 2.469ns Clock Pessimism Removal (CPR): 0.282ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.994ns (routing 0.501ns, distribution 1.493ns) Clock Net Delay (Destination): 1.741ns (routing 0.453ns, distribution 1.288ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.091 0.091 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.994 2.469 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 SLICE_X138Y36 FDCE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y36 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.608 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/Q net (fo=273, routed) 0.733 3.341 ctrl_regs_inst/gtwiz_reset_tx_done_in[0] SLICE_X133Y57 LUT3 (Prop_B6LUT_SLICEL_I2_O) 0.237 3.578 r ctrl_regs_inst/data_o[233]_i_1__0/O net (fo=234, routed) 1.174 4.752 i_tcds2_if/prbs_generator/SR[0] SLICE_X139Y46 FDRE r i_tcds2_if/prbs_generator/data_o_reg[150]/R ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 3.119 3.119 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.052 3.171 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 3.517 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.741 5.258 i_tcds2_if/prbs_generator/CLK SLICE_X139Y46 FDRE r i_tcds2_if/prbs_generator/data_o_reg[150]/C clock pessimism 0.282 5.540 clock uncertainty -0.035 5.504 SLICE_X139Y46 FDRE (Setup_DFF_SLICEL_C_R) -0.096 5.408 i_tcds2_if/prbs_generator/data_o_reg[150] ------------------------------------------------------------------- required time 5.408 arrival time -4.752 ------------------------------------------------------------------- slack 0.656 Slack (MET) : 0.656ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/prbs_generator/data_o_reg[184]/R (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (txoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 2.283ns (logic 0.376ns (16.470%) route 1.907ns (83.530%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.048ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.139ns = ( 5.258 - 3.119 ) Source Clock Delay (SCD): 2.469ns Clock Pessimism Removal (CPR): 0.282ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.994ns (routing 0.501ns, distribution 1.493ns) Clock Net Delay (Destination): 1.741ns (routing 0.453ns, distribution 1.288ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.091 0.091 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.994 2.469 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 SLICE_X138Y36 FDCE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y36 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.608 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/Q net (fo=273, routed) 0.733 3.341 ctrl_regs_inst/gtwiz_reset_tx_done_in[0] SLICE_X133Y57 LUT3 (Prop_B6LUT_SLICEL_I2_O) 0.237 3.578 r ctrl_regs_inst/data_o[233]_i_1__0/O net (fo=234, routed) 1.174 4.752 i_tcds2_if/prbs_generator/SR[0] SLICE_X139Y46 FDRE r i_tcds2_if/prbs_generator/data_o_reg[184]/R ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 3.119 3.119 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.052 3.171 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 3.517 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.741 5.258 i_tcds2_if/prbs_generator/CLK SLICE_X139Y46 FDRE r i_tcds2_if/prbs_generator/data_o_reg[184]/C clock pessimism 0.282 5.540 clock uncertainty -0.035 5.504 SLICE_X139Y46 FDRE (Setup_CFF_SLICEL_C_R) -0.096 5.408 i_tcds2_if/prbs_generator/data_o_reg[184] ------------------------------------------------------------------- required time 5.408 arrival time -4.752 ------------------------------------------------------------------- slack 0.656 Slack (MET) : 0.661ns (required time - arrival time) Source: i_tcds2_if/tx_strobe_reg/C (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[43]/CE (rising edge-triggered cell FDSE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (txoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 2.152ns (logic 0.137ns (6.366%) route 2.015ns (93.634%)) Logic Levels: 0 Clock Path Skew: -0.217ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.172ns = ( 5.291 - 3.119 ) Source Clock Delay (SCD): 2.514ns Clock Pessimism Removal (CPR): 0.125ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.039ns (routing 0.501ns, distribution 1.538ns) Clock Net Delay (Destination): 1.774ns (routing 0.453ns, distribution 1.321ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.091 0.091 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 2.039 2.514 i_tcds2_if/txusrclk_out SLICE_X135Y47 FDRE r i_tcds2_if/tx_strobe_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y47 FDRE (Prop_HFF2_SLICEL_C_Q) 0.137 2.651 r i_tcds2_if/tx_strobe_reg/Q net (fo=492, routed) 2.015 4.666 i_tcds2_if/txdatapath_inst/UPS/FEC5L0/E[0] SLICE_X139Y60 FDSE r i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[43]/CE ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 3.119 3.119 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.052 3.171 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 3.517 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.774 5.291 i_tcds2_if/txdatapath_inst/UPS/FEC5L0/CLK SLICE_X139Y60 FDSE r i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[43]/C clock pessimism 0.125 5.416 clock uncertainty -0.035 5.381 SLICE_X139Y60 FDSE (Setup_DFF_SLICEL_C_CE) -0.054 5.327 i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[43] ------------------------------------------------------------------- required time 5.327 arrival time -4.666 ------------------------------------------------------------------- slack 0.661 Slack (MET) : 0.661ns (required time - arrival time) Source: i_tcds2_if/tx_strobe_reg/C (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[4]/CE (rising edge-triggered cell FDSE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (txoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 2.152ns (logic 0.137ns (6.366%) route 2.015ns (93.634%)) Logic Levels: 0 Clock Path Skew: -0.217ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.172ns = ( 5.291 - 3.119 ) Source Clock Delay (SCD): 2.514ns Clock Pessimism Removal (CPR): 0.125ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.039ns (routing 0.501ns, distribution 1.538ns) Clock Net Delay (Destination): 1.774ns (routing 0.453ns, distribution 1.321ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.091 0.091 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 2.039 2.514 i_tcds2_if/txusrclk_out SLICE_X135Y47 FDRE r i_tcds2_if/tx_strobe_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y47 FDRE (Prop_HFF2_SLICEL_C_Q) 0.137 2.651 r i_tcds2_if/tx_strobe_reg/Q net (fo=492, routed) 2.015 4.666 i_tcds2_if/txdatapath_inst/UPS/FEC5L0/E[0] SLICE_X139Y60 FDSE r i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 3.119 3.119 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.052 3.171 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 3.517 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.774 5.291 i_tcds2_if/txdatapath_inst/UPS/FEC5L0/CLK SLICE_X139Y60 FDSE r i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[4]/C clock pessimism 0.125 5.416 clock uncertainty -0.035 5.381 SLICE_X139Y60 FDSE (Setup_CFF_SLICEL_C_CE) -0.054 5.327 i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[4] ------------------------------------------------------------------- required time 5.327 arrival time -4.666 ------------------------------------------------------------------- slack 0.661 Slack (MET) : 0.664ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/prbs_generator/data_o_reg[147]/R (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (txoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 2.270ns (logic 0.376ns (16.564%) route 1.894ns (83.436%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.132ns = ( 5.251 - 3.119 ) Source Clock Delay (SCD): 2.469ns Clock Pessimism Removal (CPR): 0.282ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.994ns (routing 0.501ns, distribution 1.493ns) Clock Net Delay (Destination): 1.734ns (routing 0.453ns, distribution 1.281ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.091 0.091 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.994 2.469 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 SLICE_X138Y36 FDCE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y36 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.608 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/Q net (fo=273, routed) 0.733 3.341 ctrl_regs_inst/gtwiz_reset_tx_done_in[0] SLICE_X133Y57 LUT3 (Prop_B6LUT_SLICEL_I2_O) 0.237 3.578 r ctrl_regs_inst/data_o[233]_i_1__0/O net (fo=234, routed) 1.161 4.739 i_tcds2_if/prbs_generator/SR[0] SLICE_X138Y46 FDRE r i_tcds2_if/prbs_generator/data_o_reg[147]/R ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 3.119 3.119 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.052 3.171 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 3.517 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.734 5.251 i_tcds2_if/prbs_generator/CLK SLICE_X138Y46 FDRE r i_tcds2_if/prbs_generator/data_o_reg[147]/C clock pessimism 0.282 5.533 clock uncertainty -0.035 5.498 SLICE_X138Y46 FDRE (Setup_HFF_SLICEL_C_R) -0.095 5.403 i_tcds2_if/prbs_generator/data_o_reg[147] ------------------------------------------------------------------- required time 5.403 arrival time -4.739 ------------------------------------------------------------------- slack 0.664 Slack (MET) : 0.664ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/prbs_generator/data_o_reg[153]/R (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (txoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 2.270ns (logic 0.376ns (16.564%) route 1.894ns (83.436%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.132ns = ( 5.251 - 3.119 ) Source Clock Delay (SCD): 2.469ns Clock Pessimism Removal (CPR): 0.282ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.994ns (routing 0.501ns, distribution 1.493ns) Clock Net Delay (Destination): 1.734ns (routing 0.453ns, distribution 1.281ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.091 0.091 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.994 2.469 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 SLICE_X138Y36 FDCE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y36 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.608 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/Q net (fo=273, routed) 0.733 3.341 ctrl_regs_inst/gtwiz_reset_tx_done_in[0] SLICE_X133Y57 LUT3 (Prop_B6LUT_SLICEL_I2_O) 0.237 3.578 r ctrl_regs_inst/data_o[233]_i_1__0/O net (fo=234, routed) 1.161 4.739 i_tcds2_if/prbs_generator/SR[0] SLICE_X138Y46 FDRE r i_tcds2_if/prbs_generator/data_o_reg[153]/R ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 3.119 3.119 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.052 3.171 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 3.517 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.734 5.251 i_tcds2_if/prbs_generator/CLK SLICE_X138Y46 FDRE r i_tcds2_if/prbs_generator/data_o_reg[153]/C clock pessimism 0.282 5.533 clock uncertainty -0.035 5.498 SLICE_X138Y46 FDRE (Setup_GFF_SLICEL_C_R) -0.095 5.403 i_tcds2_if/prbs_generator/data_o_reg[153] ------------------------------------------------------------------- required time 5.403 arrival time -4.739 ------------------------------------------------------------------- slack 0.664 Slack (MET) : 0.664ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/prbs_generator/data_o_reg[187]/R (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (txoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 2.270ns (logic 0.376ns (16.564%) route 1.894ns (83.436%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.132ns = ( 5.251 - 3.119 ) Source Clock Delay (SCD): 2.469ns Clock Pessimism Removal (CPR): 0.282ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.994ns (routing 0.501ns, distribution 1.493ns) Clock Net Delay (Destination): 1.734ns (routing 0.453ns, distribution 1.281ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.091 0.091 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.994 2.469 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 SLICE_X138Y36 FDCE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y36 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.608 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/Q net (fo=273, routed) 0.733 3.341 ctrl_regs_inst/gtwiz_reset_tx_done_in[0] SLICE_X133Y57 LUT3 (Prop_B6LUT_SLICEL_I2_O) 0.237 3.578 r ctrl_regs_inst/data_o[233]_i_1__0/O net (fo=234, routed) 1.161 4.739 i_tcds2_if/prbs_generator/SR[0] SLICE_X138Y46 FDRE r i_tcds2_if/prbs_generator/data_o_reg[187]/R ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 3.119 3.119 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.052 3.171 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 3.517 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.734 5.251 i_tcds2_if/prbs_generator/CLK SLICE_X138Y46 FDRE r i_tcds2_if/prbs_generator/data_o_reg[187]/C clock pessimism 0.282 5.533 clock uncertainty -0.035 5.498 SLICE_X138Y46 FDRE (Setup_FFF_SLICEL_C_R) -0.095 5.403 i_tcds2_if/prbs_generator/data_o_reg[187] ------------------------------------------------------------------- required time 5.403 arrival time -4.739 ------------------------------------------------------------------- slack 0.664 Slack (MET) : 0.664ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/prbs_generator/data_o_reg[220]/R (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (txoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 2.207ns (logic 0.376ns (17.037%) route 1.831ns (82.963%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.143ns = ( 5.262 - 3.119 ) Source Clock Delay (SCD): 2.469ns Clock Pessimism Removal (CPR): 0.209ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.994ns (routing 0.501ns, distribution 1.493ns) Clock Net Delay (Destination): 1.745ns (routing 0.453ns, distribution 1.292ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.091 0.091 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.994 2.469 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 SLICE_X138Y36 FDCE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y36 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.608 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/Q net (fo=273, routed) 0.733 3.341 ctrl_regs_inst/gtwiz_reset_tx_done_in[0] SLICE_X133Y57 LUT3 (Prop_B6LUT_SLICEL_I2_O) 0.237 3.578 r ctrl_regs_inst/data_o[233]_i_1__0/O net (fo=234, routed) 1.098 4.676 i_tcds2_if/prbs_generator/SR[0] SLICE_X131Y49 FDRE r i_tcds2_if/prbs_generator/data_o_reg[220]/R ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 3.119 3.119 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.052 3.171 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 3.517 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.745 5.262 i_tcds2_if/prbs_generator/CLK SLICE_X131Y49 FDRE r i_tcds2_if/prbs_generator/data_o_reg[220]/C clock pessimism 0.209 5.471 clock uncertainty -0.035 5.436 SLICE_X131Y49 FDRE (Setup_BFF_SLICEL_C_R) -0.096 5.340 i_tcds2_if/prbs_generator/data_o_reg[220] ------------------------------------------------------------------- required time 5.340 arrival time -4.676 ------------------------------------------------------------------- slack 0.664 Slack (MET) : 0.667ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/prbs_generator/data_o_reg[135]/R (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (txoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 2.209ns (logic 0.376ns (17.021%) route 1.833ns (82.979%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.112ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.148ns = ( 5.267 - 3.119 ) Source Clock Delay (SCD): 2.469ns Clock Pessimism Removal (CPR): 0.209ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.994ns (routing 0.501ns, distribution 1.493ns) Clock Net Delay (Destination): 1.750ns (routing 0.453ns, distribution 1.297ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.091 0.091 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.994 2.469 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 SLICE_X138Y36 FDCE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y36 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.608 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/Q net (fo=273, routed) 0.733 3.341 ctrl_regs_inst/gtwiz_reset_tx_done_in[0] SLICE_X133Y57 LUT3 (Prop_B6LUT_SLICEL_I2_O) 0.237 3.578 r ctrl_regs_inst/data_o[233]_i_1__0/O net (fo=234, routed) 1.100 4.678 i_tcds2_if/prbs_generator/SR[0] SLICE_X132Y49 FDRE r i_tcds2_if/prbs_generator/data_o_reg[135]/R ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 3.119 3.119 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.052 3.171 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 3.517 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.750 5.267 i_tcds2_if/prbs_generator/CLK SLICE_X132Y49 FDRE r i_tcds2_if/prbs_generator/data_o_reg[135]/C clock pessimism 0.209 5.476 clock uncertainty -0.035 5.441 SLICE_X132Y49 FDRE (Setup_DFF_SLICEL_C_R) -0.096 5.345 i_tcds2_if/prbs_generator/data_o_reg[135] ------------------------------------------------------------------- required time 5.345 arrival time -4.678 ------------------------------------------------------------------- slack 0.667 Slack (MET) : 0.667ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/prbs_generator/data_o_reg[175]/R (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (txoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 2.209ns (logic 0.376ns (17.021%) route 1.833ns (82.979%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.112ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.148ns = ( 5.267 - 3.119 ) Source Clock Delay (SCD): 2.469ns Clock Pessimism Removal (CPR): 0.209ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.994ns (routing 0.501ns, distribution 1.493ns) Clock Net Delay (Destination): 1.750ns (routing 0.453ns, distribution 1.297ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.091 0.091 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.994 2.469 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 SLICE_X138Y36 FDCE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y36 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.608 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/Q net (fo=273, routed) 0.733 3.341 ctrl_regs_inst/gtwiz_reset_tx_done_in[0] SLICE_X133Y57 LUT3 (Prop_B6LUT_SLICEL_I2_O) 0.237 3.578 r ctrl_regs_inst/data_o[233]_i_1__0/O net (fo=234, routed) 1.100 4.678 i_tcds2_if/prbs_generator/SR[0] SLICE_X132Y49 FDRE r i_tcds2_if/prbs_generator/data_o_reg[175]/R ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 3.119 3.119 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.052 3.171 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 3.517 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.750 5.267 i_tcds2_if/prbs_generator/CLK SLICE_X132Y49 FDRE r i_tcds2_if/prbs_generator/data_o_reg[175]/C clock pessimism 0.209 5.476 clock uncertainty -0.035 5.441 SLICE_X132Y49 FDRE (Setup_CFF_SLICEL_C_R) -0.096 5.345 i_tcds2_if/prbs_generator/data_o_reg[175] ------------------------------------------------------------------- required time 5.345 arrival time -4.678 ------------------------------------------------------------------- slack 0.667 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.031ns (arrival time - required time) Source: i_tcds2_if/txgearbox_inst/dataWord_reg[3]/C (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[3] (rising edge-triggered cell GTHE3_CHANNEL clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 0.174ns (logic 0.049ns (28.161%) route 0.125ns (71.839%)) Logic Levels: 0 Clock Path Skew: -0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.991ns Source Clock Delay (SCD): 0.851ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.733ns (routing 0.215ns, distribution 0.518ns) Clock Net Delay (Destination): 0.826ns (routing 0.247ns, distribution 0.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.018 0.018 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.733 0.851 i_tcds2_if/txgearbox_inst/CLK SLICE_X142Y51 FDRE r i_tcds2_if/txgearbox_inst/dataWord_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X142Y51 FDRE (Prop_BFF_SLICEM_C_Q) 0.049 0.900 r i_tcds2_if/txgearbox_inst/dataWord_reg[3]/Q net (fo=1, routed) 0.125 1.025 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[3] GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[3] ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.035 0.035 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.826 0.991 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 clock pessimism -0.154 0.837 GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL (Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[3]) 0.157 0.994 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST ------------------------------------------------------------------- required time -0.994 arrival time 1.025 ------------------------------------------------------------------- slack 0.031 Slack (MET) : 0.032ns (arrival time - required time) Source: i_tcds2_if/txgearbox_inst/dataWord_reg[21]/C (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[21] (rising edge-triggered cell GTHE3_CHANNEL clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.991ns Source Clock Delay (SCD): 0.851ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.733ns (routing 0.215ns, distribution 0.518ns) Clock Net Delay (Destination): 0.826ns (routing 0.247ns, distribution 0.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.018 0.018 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.733 0.851 i_tcds2_if/txgearbox_inst/CLK SLICE_X141Y55 FDRE r i_tcds2_if/txgearbox_inst/dataWord_reg[21]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y55 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 0.900 r i_tcds2_if/txgearbox_inst/dataWord_reg[21]/Q net (fo=1, routed) 0.175 1.075 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[21] GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[21] ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.035 0.035 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.826 0.991 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 clock pessimism -0.128 0.863 GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL (Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[21]) 0.180 1.043 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST ------------------------------------------------------------------- required time -1.043 arrival time 1.075 ------------------------------------------------------------------- slack 0.032 Slack (MET) : 0.038ns (arrival time - required time) Source: i_tcds2_if/prbs_generator/data_o_reg[7]/C (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[46]/D (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 0.159ns (logic 0.064ns (40.252%) route 0.095ns (59.748%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.052ns Source Clock Delay (SCD): 0.859ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.741ns (routing 0.215ns, distribution 0.526ns) Clock Net Delay (Destination): 0.887ns (routing 0.247ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.018 0.018 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.741 0.859 i_tcds2_if/prbs_generator/CLK SLICE_X135Y54 FDRE r i_tcds2_if/prbs_generator/data_o_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X135Y54 FDRE (Prop_AFF2_SLICEL_C_Q) 0.049 0.908 r i_tcds2_if/prbs_generator/data_o_reg[7]/Q net (fo=2, routed) 0.079 0.987 i_tcds2_if/txdatapath_inst/UPS/FEC5L0/Q[7] SLICE_X137Y54 LUT6 (Prop_C6LUT_SLICEL_I1_O) 0.015 1.002 r i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData[46]_i_1__2/O net (fo=1, routed) 0.016 1.018 i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData[46]_i_1__2_n_0 SLICE_X137Y54 FDRE r i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[46]/D ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.035 0.035 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.887 1.052 i_tcds2_if/txdatapath_inst/UPS/FEC5L0/CLK SLICE_X137Y54 FDRE r i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[46]/C clock pessimism -0.128 0.924 SLICE_X137Y54 FDRE (Hold_CFF_SLICEL_C_D) 0.056 0.980 i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[46] ------------------------------------------------------------------- required time -0.980 arrival time 1.018 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.038ns (arrival time - required time) Source: i_tcds2_if/txgearbox_inst/dataWord_reg[19]/C (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[19] (rising edge-triggered cell GTHE3_CHANNEL clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 0.188ns (logic 0.049ns (26.064%) route 0.139ns (73.936%)) Logic Levels: 0 Clock Path Skew: -0.019ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.991ns Source Clock Delay (SCD): 0.856ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.738ns (routing 0.215ns, distribution 0.523ns) Clock Net Delay (Destination): 0.826ns (routing 0.247ns, distribution 0.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.018 0.018 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.738 0.856 i_tcds2_if/txgearbox_inst/CLK SLICE_X142Y56 FDRE r i_tcds2_if/txgearbox_inst/dataWord_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X142Y56 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 0.905 r i_tcds2_if/txgearbox_inst/dataWord_reg[19]/Q net (fo=1, routed) 0.139 1.044 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[19] GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[19] ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.035 0.035 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.826 0.991 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 clock pessimism -0.154 0.837 GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL (Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[19]) 0.169 1.006 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST ------------------------------------------------------------------- required time -1.006 arrival time 1.044 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.038ns (arrival time - required time) Source: i_tcds2_if/txgearbox_inst/dataWord_reg[12]/C (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[12] (rising edge-triggered cell GTHE3_CHANNEL clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 0.225ns (logic 0.049ns (21.778%) route 0.176ns (78.222%)) Logic Levels: 0 Clock Path Skew: 0.001ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.991ns Source Clock Delay (SCD): 0.862ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.744ns (routing 0.215ns, distribution 0.529ns) Clock Net Delay (Destination): 0.826ns (routing 0.247ns, distribution 0.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.018 0.018 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.744 0.862 i_tcds2_if/txgearbox_inst/CLK SLICE_X139Y51 FDRE r i_tcds2_if/txgearbox_inst/dataWord_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X139Y51 FDRE (Prop_BFF_SLICEL_C_Q) 0.049 0.911 r i_tcds2_if/txgearbox_inst/dataWord_reg[12]/Q net (fo=1, routed) 0.176 1.087 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[12] GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[12] ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.035 0.035 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.826 0.991 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 clock pessimism -0.128 0.863 GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL (Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[12]) 0.186 1.049 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST ------------------------------------------------------------------- required time -1.049 arrival time 1.087 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.038ns (arrival time - required time) Source: i_tcds2_if/txgearbox_inst/dataWord_reg[10]/C (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[10] (rising edge-triggered cell GTHE3_CHANNEL clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 0.178ns (logic 0.049ns (27.528%) route 0.129ns (72.472%)) Logic Levels: 0 Clock Path Skew: 0.001ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.991ns Source Clock Delay (SCD): 0.862ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.744ns (routing 0.215ns, distribution 0.529ns) Clock Net Delay (Destination): 0.826ns (routing 0.247ns, distribution 0.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.018 0.018 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.744 0.862 i_tcds2_if/txgearbox_inst/CLK SLICE_X141Y50 FDRE r i_tcds2_if/txgearbox_inst/dataWord_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y50 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 0.911 r i_tcds2_if/txgearbox_inst/dataWord_reg[10]/Q net (fo=1, routed) 0.129 1.040 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[10] GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[10] ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.035 0.035 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.826 0.991 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 clock pessimism -0.128 0.863 GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL (Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[10]) 0.139 1.002 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST ------------------------------------------------------------------- required time -1.002 arrival time 1.040 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.038ns (arrival time - required time) Source: i_tcds2_if/txgearbox_inst/dataWord_reg[27]/C (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[27] (rising edge-triggered cell GTHE3_CHANNEL clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 0.228ns (logic 0.048ns (21.053%) route 0.180ns (78.947%)) Logic Levels: 0 Clock Path Skew: 0.003ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.991ns Source Clock Delay (SCD): 0.860ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.742ns (routing 0.215ns, distribution 0.527ns) Clock Net Delay (Destination): 0.826ns (routing 0.247ns, distribution 0.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.018 0.018 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.742 0.860 i_tcds2_if/txgearbox_inst/CLK SLICE_X139Y52 FDRE r i_tcds2_if/txgearbox_inst/dataWord_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X139Y52 FDRE (Prop_HFF_SLICEL_C_Q) 0.048 0.908 r i_tcds2_if/txgearbox_inst/dataWord_reg[27]/Q net (fo=1, routed) 0.180 1.088 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[27] GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[27] ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.035 0.035 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.826 0.991 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 clock pessimism -0.128 0.863 GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL (Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[27]) 0.187 1.050 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST ------------------------------------------------------------------- required time -1.050 arrival time 1.088 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.040ns (arrival time - required time) Source: i_tcds2_if/txgearbox_inst/dataWord_reg[8]/C (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[8] (rising edge-triggered cell GTHE3_CHANNEL clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 0.200ns (logic 0.048ns (24.000%) route 0.152ns (76.000%)) Logic Levels: 0 Clock Path Skew: 0.003ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.991ns Source Clock Delay (SCD): 0.860ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.742ns (routing 0.215ns, distribution 0.527ns) Clock Net Delay (Destination): 0.826ns (routing 0.247ns, distribution 0.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.018 0.018 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.742 0.860 i_tcds2_if/txgearbox_inst/CLK SLICE_X141Y50 FDRE r i_tcds2_if/txgearbox_inst/dataWord_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y50 FDRE (Prop_HFF_SLICEL_C_Q) 0.048 0.908 r i_tcds2_if/txgearbox_inst/dataWord_reg[8]/Q net (fo=1, routed) 0.152 1.060 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[8] GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[8] ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.035 0.035 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.826 0.991 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 clock pessimism -0.128 0.863 GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL (Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[8]) 0.157 1.020 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST ------------------------------------------------------------------- required time -1.020 arrival time 1.060 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.041ns (arrival time - required time) Source: i_tcds2_if/txgearbox_inst/gearboxCounter_reg[2]/C (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/txgearbox_inst/dataWord_reg[8]/D (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 0.183ns (logic 0.068ns (37.158%) route 0.115ns (62.842%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.064ns Source Clock Delay (SCD): 0.850ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.732ns (routing 0.215ns, distribution 0.517ns) Clock Net Delay (Destination): 0.899ns (routing 0.247ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.018 0.018 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.732 0.850 i_tcds2_if/txgearbox_inst/CLK SLICE_X142Y50 FDRE r i_tcds2_if/txgearbox_inst/gearboxCounter_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X142Y50 FDRE (Prop_HFF2_SLICEM_C_Q) 0.048 0.898 r i_tcds2_if/txgearbox_inst/gearboxCounter_reg[2]/Q net (fo=34, routed) 0.102 1.000 i_tcds2_if/txdatapath_inst/UPS/FEC5L1/dataWord_reg[0][2] SLICE_X141Y50 MUXF7 (Prop_F7MUX_GH_SLICEL_S_O) 0.020 1.020 r i_tcds2_if/txdatapath_inst/UPS/FEC5L1/dataWord_reg[8]_i_1/O net (fo=1, routed) 0.013 1.033 i_tcds2_if/txgearbox_inst/D[8] SLICE_X141Y50 FDRE r i_tcds2_if/txgearbox_inst/dataWord_reg[8]/D ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.035 0.035 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.899 1.064 i_tcds2_if/txgearbox_inst/CLK SLICE_X141Y50 FDRE r i_tcds2_if/txgearbox_inst/dataWord_reg[8]/C clock pessimism -0.128 0.936 SLICE_X141Y50 FDRE (Hold_HFF_SLICEL_C_D) 0.056 0.992 i_tcds2_if/txgearbox_inst/dataWord_reg[8] ------------------------------------------------------------------- required time -0.992 arrival time 1.033 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.043ns (arrival time - required time) Source: i_tcds2_if/txgearbox_inst/dataWord_reg[23]/C (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[23] (rising edge-triggered cell GTHE3_CHANNEL clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 0.208ns (logic 0.049ns (23.558%) route 0.159ns (76.442%)) Logic Levels: 0 Clock Path Skew: -0.019ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.991ns Source Clock Delay (SCD): 0.856ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.738ns (routing 0.215ns, distribution 0.523ns) Clock Net Delay (Destination): 0.826ns (routing 0.247ns, distribution 0.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.018 0.018 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.738 0.856 i_tcds2_if/txgearbox_inst/CLK SLICE_X142Y53 FDRE r i_tcds2_if/txgearbox_inst/dataWord_reg[23]/C ------------------------------------------------------------------- ------------------- SLICE_X142Y53 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 0.905 r i_tcds2_if/txgearbox_inst/dataWord_reg[23]/Q net (fo=1, routed) 0.159 1.064 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[23] GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[23] ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.035 0.035 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.826 0.991 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 clock pessimism -0.154 0.837 GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL (Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[23]) 0.184 1.021 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST ------------------------------------------------------------------- required time -1.021 arrival time 1.064 ------------------------------------------------------------------- slack 0.043 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: txoutclk_out[0]_49 Waveform(ns): { 0.000 1.559 } Period(ns): 3.119 Sources: { i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/TXUSRCLK n/a 2.560 3.119 0.559 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Min Period n/a GTHE3_CHANNEL/TXUSRCLK2 n/a 2.560 3.119 0.559 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 3.119 1.532 BUFG_GT_X1Y3 i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X138Y36 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_meta_reg/C Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X138Y36 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X138Y36 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync1_reg/C Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X138Y36 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync2_reg/C Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X138Y36 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg/C Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X141Y13 i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_meta_reg/C Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X141Y13 i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_sync_reg/C Low Pulse Width Fast GTHE3_CHANNEL/TXUSRCLK n/a 1.152 1.559 0.407 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/TXUSRCLK2 n/a 1.152 1.559 0.407 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/TXUSRCLK n/a 1.152 1.560 0.408 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/TXUSRCLK2 n/a 1.152 1.560 0.408 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 1.559 1.284 SLICE_X135Y56 i_tcds2_if/prbs_generator/data_o_reg[101]/C Low Pulse Width Slow FDRE/C n/a 0.275 1.559 1.284 SLICE_X135Y56 i_tcds2_if/prbs_generator/data_o_reg[109]/C Low Pulse Width Slow FDRE/C n/a 0.275 1.559 1.284 SLICE_X137Y60 i_tcds2_if/prbs_generator/data_o_reg[113]/C Low Pulse Width Fast FDRE/C n/a 0.275 1.559 1.284 SLICE_X132Y50 i_tcds2_if/prbs_generator/data_o_reg[120]/C Low Pulse Width Fast FDRE/C n/a 0.275 1.559 1.284 SLICE_X139Y50 i_tcds2_if/prbs_generator/data_o_reg[158]/C Low Pulse Width Slow FDRE/C n/a 0.275 1.559 1.284 SLICE_X133Y54 i_tcds2_if/prbs_generator/data_o_reg[161]/C High Pulse Width Slow GTHE3_CHANNEL/TXUSRCLK n/a 1.152 1.559 0.407 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/TXUSRCLK2 n/a 1.152 1.559 0.407 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/TXUSRCLK n/a 1.152 1.560 0.408 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/TXUSRCLK2 n/a 1.152 1.560 0.408 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 High Pulse Width Slow FDCE/C n/a 0.275 1.559 1.284 SLICE_X138Y36 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_meta_reg/C High Pulse Width Slow FDCE/C n/a 0.275 1.559 1.284 SLICE_X138Y36 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync1_reg/C High Pulse Width Slow FDCE/C n/a 0.275 1.559 1.284 SLICE_X138Y36 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync2_reg/C High Pulse Width Slow FDCE/C n/a 0.275 1.559 1.284 SLICE_X138Y36 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg/C High Pulse Width Slow FDRE/C n/a 0.275 1.559 1.284 SLICE_X137Y53 i_tcds2_if/prbs_generator/data_o_reg[103]/C High Pulse Width Slow FDRE/C n/a 0.275 1.559 1.284 SLICE_X135Y54 i_tcds2_if/prbs_generator/data_o_reg[105]/C Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.021 0.499 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Slow GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.613 0.045 0.568 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Slow GTHE3_CHANNEL/TXUSRCLK2 GTHE3_CHANNEL/TXUSRCLK 0.864 0.045 0.819 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 Max Skew Fast GTHE3_CHANNEL/TXUSRCLK2 GTHE3_CHANNEL/TXUSRCLK 0.914 0.021 0.893 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_12 To Clock: gtwiz_userclk_rx_srcclk_out[0]_12 Setup : 0 Failing Endpoints, Worst Slack 3.018ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.034ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.493ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.018ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 5.334ns (logic 1.637ns (30.690%) route 3.697ns (69.310%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.124ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.620ns = ( 10.937 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.244ns (routing 0.667ns, distribution 1.577ns) Clock Net Delay (Destination): 2.222ns (routing 0.604ns, distribution 1.618ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.244 2.719 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.803 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.818 6.621 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[2] SLICE_X88Y423 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.235 6.856 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/O net (fo=5, routed) 0.330 7.186 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X87Y423 LUT4 (Prop_D5LUT_SLICEM_I2_O) 0.265 7.451 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__11/O net (fo=1, routed) 0.301 7.752 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__11_n_0 SLICE_X88Y423 LUT6 (Prop_H6LUT_SLICEL_I5_O) 0.053 7.805 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__11/O net (fo=2, routed) 0.248 8.053 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__11_n_0 SLICE_X88Y423 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.222 10.937 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK SLICE_X88Y423 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.223 11.160 clock uncertainty -0.035 11.125 SLICE_X88Y423 FDCE (Setup_AFF_SLICEL_C_CE) -0.054 11.071 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.071 arrival time -8.053 ------------------------------------------------------------------- slack 3.018 Slack (MET) : 3.018ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 5.334ns (logic 1.637ns (30.690%) route 3.697ns (69.310%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.124ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.620ns = ( 10.937 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.244ns (routing 0.667ns, distribution 1.577ns) Clock Net Delay (Destination): 2.222ns (routing 0.604ns, distribution 1.618ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.244 2.719 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.803 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.818 6.621 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[2] SLICE_X88Y423 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.235 6.856 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/O net (fo=5, routed) 0.330 7.186 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X87Y423 LUT4 (Prop_D5LUT_SLICEM_I2_O) 0.265 7.451 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__11/O net (fo=1, routed) 0.301 7.752 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__11_n_0 SLICE_X88Y423 LUT6 (Prop_H6LUT_SLICEL_I5_O) 0.053 7.805 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__11/O net (fo=2, routed) 0.248 8.053 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__11_n_0 SLICE_X88Y423 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.222 10.937 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK SLICE_X88Y423 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.223 11.160 clock uncertainty -0.035 11.125 SLICE_X88Y423 FDCE (Setup_DFF_SLICEL_C_CE) -0.054 11.071 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.071 arrival time -8.053 ------------------------------------------------------------------- slack 3.018 Slack (MET) : 3.424ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 4.914ns (logic 1.465ns (29.813%) route 3.449ns (70.187%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.610ns = ( 10.927 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.244ns (routing 0.667ns, distribution 1.577ns) Clock Net Delay (Destination): 2.212ns (routing 0.604ns, distribution 1.608ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.244 2.719 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.803 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.818 6.621 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[2] SLICE_X88Y423 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.235 6.856 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/O net (fo=5, routed) 0.194 7.050 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X86Y423 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.146 7.196 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__12/O net (fo=3, routed) 0.437 7.633 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecFalseHeaders0 SLICE_X88Y422 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.212 10.927 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK SLICE_X88Y422 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.223 11.150 clock uncertainty -0.035 11.115 SLICE_X88Y422 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 11.057 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 11.057 arrival time -7.633 ------------------------------------------------------------------- slack 3.424 Slack (MET) : 3.425ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 4.918ns (logic 1.465ns (29.789%) route 3.453ns (70.211%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.611ns = ( 10.928 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.244ns (routing 0.667ns, distribution 1.577ns) Clock Net Delay (Destination): 2.213ns (routing 0.604ns, distribution 1.609ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.244 2.719 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.803 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.818 6.621 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[2] SLICE_X88Y423 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.235 6.856 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/O net (fo=5, routed) 0.088 6.944 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X88Y423 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.146 7.090 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__12/O net (fo=7, routed) 0.547 7.637 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 SLICE_X87Y421 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.213 10.928 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK SLICE_X87Y421 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.223 11.151 clock uncertainty -0.035 11.116 SLICE_X87Y421 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 11.062 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 11.062 arrival time -7.637 ------------------------------------------------------------------- slack 3.425 Slack (MET) : 3.425ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 4.918ns (logic 1.465ns (29.789%) route 3.453ns (70.211%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.612ns = ( 10.929 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.244ns (routing 0.667ns, distribution 1.577ns) Clock Net Delay (Destination): 2.214ns (routing 0.604ns, distribution 1.610ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.244 2.719 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.803 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.818 6.621 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[2] SLICE_X88Y423 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.235 6.856 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/O net (fo=5, routed) 0.088 6.944 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X88Y423 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.146 7.090 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__12/O net (fo=7, routed) 0.547 7.637 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 SLICE_X88Y421 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.214 10.929 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK SLICE_X88Y421 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.223 11.152 clock uncertainty -0.035 11.117 SLICE_X88Y421 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 11.062 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.062 arrival time -7.637 ------------------------------------------------------------------- slack 3.425 Slack (MET) : 3.430ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 4.914ns (logic 1.465ns (29.813%) route 3.449ns (70.187%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.612ns = ( 10.929 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.244ns (routing 0.667ns, distribution 1.577ns) Clock Net Delay (Destination): 2.214ns (routing 0.604ns, distribution 1.610ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.244 2.719 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.803 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.818 6.621 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[2] SLICE_X88Y423 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.235 6.856 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/O net (fo=5, routed) 0.088 6.944 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X88Y423 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.146 7.090 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__12/O net (fo=7, routed) 0.543 7.633 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 SLICE_X88Y421 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.214 10.929 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK SLICE_X88Y421 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.223 11.152 clock uncertainty -0.035 11.117 SLICE_X88Y421 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 11.063 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.063 arrival time -7.633 ------------------------------------------------------------------- slack 3.430 Slack (MET) : 3.431ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 4.910ns (logic 1.465ns (29.837%) route 3.445ns (70.163%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.610ns = ( 10.927 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.244ns (routing 0.667ns, distribution 1.577ns) Clock Net Delay (Destination): 2.212ns (routing 0.604ns, distribution 1.608ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.244 2.719 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.803 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.818 6.621 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[2] SLICE_X88Y423 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.235 6.856 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/O net (fo=5, routed) 0.194 7.050 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X86Y423 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.146 7.196 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__12/O net (fo=3, routed) 0.433 7.629 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecFalseHeaders0 SLICE_X88Y422 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.212 10.927 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK SLICE_X88Y422 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.223 11.150 clock uncertainty -0.035 11.115 SLICE_X88Y422 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 11.060 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 11.060 arrival time -7.629 ------------------------------------------------------------------- slack 3.431 Slack (MET) : 3.431ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 4.910ns (logic 1.465ns (29.837%) route 3.445ns (70.163%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.610ns = ( 10.927 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.244ns (routing 0.667ns, distribution 1.577ns) Clock Net Delay (Destination): 2.212ns (routing 0.604ns, distribution 1.608ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.244 2.719 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.803 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.818 6.621 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[2] SLICE_X88Y423 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.235 6.856 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/O net (fo=5, routed) 0.194 7.050 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X86Y423 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.146 7.196 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__12/O net (fo=3, routed) 0.433 7.629 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecFalseHeaders0 SLICE_X88Y422 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.212 10.927 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK SLICE_X88Y422 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C clock pessimism 0.223 11.150 clock uncertainty -0.035 11.115 SLICE_X88Y422 FDRE (Setup_EFF_SLICEL_C_CE) -0.055 11.060 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2] ------------------------------------------------------------------- required time 11.060 arrival time -7.629 ------------------------------------------------------------------- slack 3.431 Slack (MET) : 3.529ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 4.822ns (logic 1.466ns (30.402%) route 3.356ns (69.598%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.124ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.620ns = ( 10.937 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.244ns (routing 0.667ns, distribution 1.577ns) Clock Net Delay (Destination): 2.222ns (routing 0.604ns, distribution 1.618ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.244 2.719 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.803 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.818 6.621 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[2] SLICE_X88Y423 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.235 6.856 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/O net (fo=5, routed) 0.195 7.051 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X86Y423 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 7.198 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__12/O net (fo=5, routed) 0.343 7.541 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 SLICE_X86Y422 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.222 10.937 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK SLICE_X86Y422 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.223 11.160 clock uncertainty -0.035 11.125 SLICE_X86Y422 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 11.070 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.070 arrival time -7.541 ------------------------------------------------------------------- slack 3.529 Slack (MET) : 3.529ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 4.822ns (logic 1.466ns (30.402%) route 3.356ns (69.598%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.124ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.620ns = ( 10.937 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.244ns (routing 0.667ns, distribution 1.577ns) Clock Net Delay (Destination): 2.222ns (routing 0.604ns, distribution 1.618ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.244 2.719 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.803 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.818 6.621 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[2] SLICE_X88Y423 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.235 6.856 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/O net (fo=5, routed) 0.195 7.051 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X86Y423 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 7.198 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__12/O net (fo=5, routed) 0.343 7.541 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 SLICE_X86Y422 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.222 10.937 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK SLICE_X86Y422 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.223 11.160 clock uncertainty -0.035 11.125 SLICE_X86Y422 FDRE (Setup_BFF2_SLICEL_C_CE) -0.055 11.070 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 11.070 arrival time -7.541 ------------------------------------------------------------------- slack 3.529 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.034ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[12].rx_data_ngccm_reg[12][45]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.175ns (logic 0.048ns (27.429%) route 0.127ns (72.571%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.344ns Source Clock Delay (SCD): 1.108ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.990ns (routing 0.303ns, distribution 0.687ns) Clock Net Delay (Destination): 1.179ns (routing 0.344ns, distribution 0.835ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.990 1.108 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X76Y422 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X76Y422 FDRE (Prop_CFF2_SLICEM_C_Q) 0.048 1.156 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/Q net (fo=1, routed) 0.127 1.283 rx_data[12][45] SLICE_X77Y422 FDCE r SFP_GEN[12].rx_data_ngccm_reg[12][45]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.179 1.344 g_gbt_bank[1].gbtbank_n_0 SLICE_X77Y422 FDCE r SFP_GEN[12].rx_data_ngccm_reg[12][45]/C clock pessimism -0.151 1.193 SLICE_X77Y422 FDCE (Hold_AFF_SLICEM_C_D) 0.056 1.249 SFP_GEN[12].rx_data_ngccm_reg[12][45] ------------------------------------------------------------------- required time -1.249 arrival time 1.283 ------------------------------------------------------------------- slack 0.034 Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[12].rx_data_ngccm_reg[12][76]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.172ns (logic 0.048ns (27.907%) route 0.124ns (72.093%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.332ns Source Clock Delay (SCD): 1.101ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.983ns (routing 0.303ns, distribution 0.680ns) Clock Net Delay (Destination): 1.167ns (routing 0.344ns, distribution 0.823ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.983 1.101 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X75Y425 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X75Y425 FDRE (Prop_HFF_SLICEL_C_Q) 0.048 1.149 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/Q net (fo=1, routed) 0.124 1.273 rx_data[12][76] SLICE_X76Y425 FDCE r SFP_GEN[12].rx_data_ngccm_reg[12][76]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.167 1.332 g_gbt_bank[1].gbtbank_n_0 SLICE_X76Y425 FDCE r SFP_GEN[12].rx_data_ngccm_reg[12][76]/C clock pessimism -0.151 1.181 SLICE_X76Y425 FDCE (Hold_FFF_SLICEM_C_D) 0.056 1.237 SFP_GEN[12].rx_data_ngccm_reg[12][76] ------------------------------------------------------------------- required time -1.237 arrival time 1.273 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.036ns (arrival time - required time) Source: SFP_GEN[12].rx_data_ngccm_reg[12][4]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[4]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.166ns (logic 0.078ns (46.988%) route 0.088ns (53.012%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.322ns Source Clock Delay (SCD): 1.097ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.979ns (routing 0.303ns, distribution 0.676ns) Clock Net Delay (Destination): 1.157ns (routing 0.344ns, distribution 0.813ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.979 1.097 g_gbt_bank[1].gbtbank_n_0 SLICE_X84Y422 FDCE r SFP_GEN[12].rx_data_ngccm_reg[12][4]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y422 FDCE (Prop_GFF_SLICEL_C_Q) 0.048 1.145 r SFP_GEN[12].rx_data_ngccm_reg[12][4]/Q net (fo=1, routed) 0.074 1.219 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[83]_0[4] SLICE_X85Y422 LUT3 (Prop_G6LUT_SLICEM_I1_O) 0.030 1.249 r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[4]_i_1/O net (fo=1, routed) 0.014 1.263 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[4]_i_1_n_0 SLICE_X85Y422 FDCE r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.157 1.322 SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y422 FDCE r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[4]/C clock pessimism -0.151 1.171 SLICE_X85Y422 FDCE (Hold_GFF_SLICEM_C_D) 0.056 1.227 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[4] ------------------------------------------------------------------- required time -1.227 arrival time 1.263 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.038ns (arrival time - required time) Source: SFP_GEN[12].rx_data_ngccm_reg[12][47]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[46]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.179ns (logic 0.089ns (49.721%) route 0.090ns (50.279%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.344ns Source Clock Delay (SCD): 1.108ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.990ns (routing 0.303ns, distribution 0.687ns) Clock Net Delay (Destination): 1.179ns (routing 0.344ns, distribution 0.835ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.990 1.108 g_gbt_bank[1].gbtbank_n_0 SLICE_X76Y421 FDCE r SFP_GEN[12].rx_data_ngccm_reg[12][47]/C ------------------------------------------------------------------- ------------------- SLICE_X76Y421 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.157 r SFP_GEN[12].rx_data_ngccm_reg[12][47]/Q net (fo=1, routed) 0.078 1.235 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[83]_0[39] SLICE_X77Y421 LUT3 (Prop_D5LUT_SLICEM_I0_O) 0.040 1.275 r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[46]_i_1/O net (fo=1, routed) 0.012 1.287 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[46]_i_1_n_0 SLICE_X77Y421 FDCE r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[46]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.179 1.344 SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y421 FDCE r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[46]/C clock pessimism -0.151 1.193 SLICE_X77Y421 FDCE (Hold_DFF2_SLICEM_C_D) 0.056 1.249 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[46] ------------------------------------------------------------------- required time -1.249 arrival time 1.287 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.174ns (logic 0.080ns (45.977%) route 0.094ns (54.023%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.334ns Source Clock Delay (SCD): 1.104ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.986ns (routing 0.303ns, distribution 0.683ns) Clock Net Delay (Destination): 1.169ns (routing 0.344ns, distribution 0.825ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.986 1.104 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X75Y422 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X75Y422 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.153 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Q net (fo=2, routed) 0.078 1.231 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_25_in SLICE_X76Y422 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.031 1.262 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__11/O net (fo=1, routed) 0.016 1.278 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[11] SLICE_X76Y422 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.169 1.334 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X76Y422 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C clock pessimism -0.151 1.183 SLICE_X76Y422 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.239 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11] ------------------------------------------------------------------- required time -1.239 arrival time 1.278 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.172ns (logic 0.079ns (45.930%) route 0.093ns (54.070%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.329ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.989ns (routing 0.303ns, distribution 0.686ns) Clock Net Delay (Destination): 1.164ns (routing 0.344ns, distribution 0.820ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X76Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X76Y425 FDCE (Prop_AFF2_SLICEM_C_Q) 0.049 1.156 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Q net (fo=2, routed) 0.077 1.233 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_25_in SLICE_X75Y425 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.030 1.263 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__11/O net (fo=1, routed) 0.016 1.279 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[11] SLICE_X75Y425 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.164 1.329 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X75Y425 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C clock pessimism -0.151 1.178 SLICE_X75Y425 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.234 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11] ------------------------------------------------------------------- required time -1.234 arrival time 1.279 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: SFP_GEN[12].rx_data_ngccm_reg[12][45]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[44]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.103ns (66.883%) route 0.051ns (33.117%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.344ns Source Clock Delay (SCD): 1.111ns Clock Pessimism Removal (CPR): 0.180ns Clock Net Delay (Source): 0.993ns (routing 0.303ns, distribution 0.690ns) Clock Net Delay (Destination): 1.179ns (routing 0.344ns, distribution 0.835ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.993 1.111 g_gbt_bank[1].gbtbank_n_0 SLICE_X77Y422 FDCE r SFP_GEN[12].rx_data_ngccm_reg[12][45]/C ------------------------------------------------------------------- ------------------- SLICE_X77Y422 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.160 r SFP_GEN[12].rx_data_ngccm_reg[12][45]/Q net (fo=1, routed) 0.035 1.195 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[83]_0[37] SLICE_X77Y421 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.054 1.249 r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[44]_i_1/O net (fo=1, routed) 0.016 1.265 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[44]_i_1_n_0 SLICE_X77Y421 FDCE r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[44]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.179 1.344 SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y421 FDCE r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[44]/C clock pessimism -0.180 1.164 SLICE_X77Y421 FDCE (Hold_DFF_SLICEM_C_D) 0.056 1.220 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[44] ------------------------------------------------------------------- required time -1.220 arrival time 1.265 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: SFP_GEN[12].rx_data_ngccm_reg[12][32]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[32]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.103ns (66.883%) route 0.051ns (33.117%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.332ns Source Clock Delay (SCD): 1.100ns Clock Pessimism Removal (CPR): 0.179ns Clock Net Delay (Source): 0.982ns (routing 0.303ns, distribution 0.679ns) Clock Net Delay (Destination): 1.167ns (routing 0.344ns, distribution 0.823ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.982 1.100 g_gbt_bank[1].gbtbank_n_0 SLICE_X83Y423 FDCE r SFP_GEN[12].rx_data_ngccm_reg[12][32]/C ------------------------------------------------------------------- ------------------- SLICE_X83Y423 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.149 r SFP_GEN[12].rx_data_ngccm_reg[12][32]/Q net (fo=1, routed) 0.035 1.184 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[83]_0[24] SLICE_X83Y422 LUT3 (Prop_D6LUT_SLICEM_I1_O) 0.054 1.238 r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[32]_i_1/O net (fo=1, routed) 0.016 1.254 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[32]_i_1_n_0 SLICE_X83Y422 FDCE r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[32]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.167 1.332 SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X83Y422 FDCE r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[32]/C clock pessimism -0.179 1.153 SLICE_X83Y422 FDCE (Hold_DFF_SLICEM_C_D) 0.056 1.209 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[32] ------------------------------------------------------------------- required time -1.209 arrival time 1.254 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.174ns (logic 0.086ns (49.425%) route 0.088ns (50.575%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.329ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.989ns (routing 0.303ns, distribution 0.686ns) Clock Net Delay (Destination): 1.164ns (routing 0.344ns, distribution 0.820ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X76Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X76Y425 FDCE (Prop_BFF2_SLICEM_C_Q) 0.048 1.155 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Q net (fo=2, routed) 0.077 1.232 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_31_in SLICE_X75Y425 LUT3 (Prop_C5LUT_SLICEL_I2_O) 0.038 1.270 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__11/O net (fo=1, routed) 0.011 1.281 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[14] SLICE_X75Y425 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.164 1.329 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X75Y425 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C clock pessimism -0.151 1.178 SLICE_X75Y425 FDRE (Hold_CFF2_SLICEL_C_D) 0.056 1.234 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14] ------------------------------------------------------------------- required time -1.234 arrival time 1.281 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[37]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.160ns (logic 0.065ns (40.625%) route 0.095ns (59.375%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.057ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.342ns Source Clock Delay (SCD): 1.105ns Clock Pessimism Removal (CPR): 0.180ns Clock Net Delay (Source): 0.987ns (routing 0.303ns, distribution 0.684ns) Clock Net Delay (Destination): 1.177ns (routing 0.344ns, distribution 0.833ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.987 1.105 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X79Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y425 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.154 f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/Q net (fo=28, routed) 0.080 1.234 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] SLICE_X79Y426 LUT5 (Prop_B6LUT_SLICEM_I0_O) 0.016 1.250 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0[37]_i_1__13/O net (fo=1, routed) 0.015 1.265 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg00[37] SLICE_X79Y426 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[37]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.177 1.342 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X79Y426 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[37]/C clock pessimism -0.180 1.162 SLICE_X79Y426 FDCE (Hold_BFF_SLICEM_C_D) 0.056 1.218 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[37] ------------------------------------------------------------------- required time -1.218 arrival time 1.265 ------------------------------------------------------------------- slack 0.048 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_12 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y185 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X90Y421 g_clock_rate_din[12].ngccm_status_cnt_reg[12][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X90Y421 g_clock_rate_din[12].ngccm_status_cnt_reg[12][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X90Y421 g_clock_rate_din[12].ngccm_status_cnt_reg[12][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X90Y421 g_clock_rate_din[12].ngccm_status_cnt_reg[12][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X90Y421 g_clock_rate_din[12].ngccm_status_cnt_reg[12][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X90Y421 g_clock_rate_din[12].ngccm_status_cnt_reg[12][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X91Y420 g_clock_rate_din[12].ngccm_status_cnt_reg[12][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X90Y421 g_clock_rate_din[12].ngccm_status_cnt_reg[12][0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X90Y421 g_clock_rate_din[12].ngccm_status_cnt_reg[12][0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X90Y421 g_clock_rate_din[12].ngccm_status_cnt_reg[12][1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X90Y421 g_clock_rate_din[12].ngccm_status_cnt_reg[12][1]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X90Y421 g_clock_rate_din[12].ngccm_status_cnt_reg[12][2]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X90Y421 g_clock_rate_din[12].ngccm_status_cnt_reg[12][2]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X90Y421 g_clock_rate_din[12].ngccm_status_cnt_reg[12][0]/C High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X90Y421 g_clock_rate_din[12].ngccm_status_cnt_reg[12][1]/C High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X90Y421 g_clock_rate_din[12].ngccm_status_cnt_reg[12][2]/C High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X90Y421 g_clock_rate_din[12].ngccm_status_cnt_reg[12][3]/C High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X90Y421 g_clock_rate_din[12].ngccm_status_cnt_reg[12][4]/C High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X90Y421 g_clock_rate_din[12].ngccm_status_cnt_reg[12][5]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.037 0.493 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.037 1.291 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_13 To Clock: gtwiz_userclk_rx_srcclk_out[0]_13 Setup : 0 Failing Endpoints, Worst Slack 4.061ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.031ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.061ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 4.063ns (logic 1.651ns (40.635%) route 2.412ns (59.365%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.102ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.306ns = ( 10.623 - 8.317 ) Source Clock Delay (SCD): 2.632ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.157ns (routing 0.623ns, distribution 1.534ns) Clock Net Delay (Destination): 1.908ns (routing 0.566ns, distribution 1.342ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.157 2.632 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.718 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.719 5.437 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X119Y582 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.149 5.586 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/O net (fo=5, routed) 0.266 5.852 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X119Y582 LUT4 (Prop_B6LUT_SLICEM_I2_O) 0.243 6.095 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__21/O net (fo=1, routed) 0.169 6.264 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__21_n_0 SLICE_X119Y583 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.173 6.437 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__21/O net (fo=2, routed) 0.258 6.695 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__21_n_0 SLICE_X119Y583 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.908 10.623 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK SLICE_X119Y583 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.223 10.847 clock uncertainty -0.035 10.811 SLICE_X119Y583 FDCE (Setup_GFF_SLICEM_C_CE) -0.055 10.756 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.756 arrival time -6.695 ------------------------------------------------------------------- slack 4.061 Slack (MET) : 4.061ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 4.063ns (logic 1.651ns (40.635%) route 2.412ns (59.365%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.102ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.306ns = ( 10.623 - 8.317 ) Source Clock Delay (SCD): 2.632ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.157ns (routing 0.623ns, distribution 1.534ns) Clock Net Delay (Destination): 1.908ns (routing 0.566ns, distribution 1.342ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.157 2.632 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.718 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.719 5.437 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X119Y582 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.149 5.586 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/O net (fo=5, routed) 0.266 5.852 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X119Y582 LUT4 (Prop_B6LUT_SLICEM_I2_O) 0.243 6.095 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__21/O net (fo=1, routed) 0.169 6.264 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__21_n_0 SLICE_X119Y583 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.173 6.437 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__21/O net (fo=2, routed) 0.258 6.695 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__21_n_0 SLICE_X119Y583 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.908 10.623 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK SLICE_X119Y583 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.223 10.847 clock uncertainty -0.035 10.811 SLICE_X119Y583 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 10.756 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.756 arrival time -6.695 ------------------------------------------------------------------- slack 4.061 Slack (MET) : 4.219ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[22].ngccm_status_reg_reg[22][23]/CE (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 4.130ns (logic 0.287ns (6.949%) route 3.843ns (93.051%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.121ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.587ns = ( 10.904 - 8.317 ) Source Clock Delay (SCD): 2.680ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.205ns (routing 0.623ns, distribution 1.582ns) Clock Net Delay (Destination): 2.189ns (routing 0.566ns, distribution 1.623ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.205 2.680 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X121Y570 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C ------------------------------------------------------------------- ------------------- SLICE_X121Y570 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.820 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/Q net (fo=137, routed) 3.063 5.883 SFP_GEN[22].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X80Y543 LUT2 (Prop_H6LUT_SLICEL_I1_O) 0.147 6.030 r SFP_GEN[22].ngCCM_gbt/SFP_GEN[22].ngccm_status_reg[22][24]_i_1/O net (fo=18, routed) 0.780 6.810 rx_test_comm_cnt259_out SLICE_X82Y541 FDPE r SFP_GEN[22].ngccm_status_reg_reg[22][23]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.189 10.904 g_gbt_bank[1].gbtbank_n_124 SLICE_X82Y541 FDPE r SFP_GEN[22].ngccm_status_reg_reg[22][23]/C clock pessimism 0.214 11.119 clock uncertainty -0.035 11.083 SLICE_X82Y541 FDPE (Setup_DFF_SLICEM_C_CE) -0.054 11.029 SFP_GEN[22].ngccm_status_reg_reg[22][23] ------------------------------------------------------------------- required time 11.029 arrival time -6.810 ------------------------------------------------------------------- slack 4.219 Slack (MET) : 4.316ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[22].ngccm_status_reg_reg[22][1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 4.044ns (logic 0.287ns (7.097%) route 3.757ns (92.903%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.602ns = ( 10.919 - 8.317 ) Source Clock Delay (SCD): 2.680ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.205ns (routing 0.623ns, distribution 1.582ns) Clock Net Delay (Destination): 2.204ns (routing 0.566ns, distribution 1.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.205 2.680 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X121Y570 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C ------------------------------------------------------------------- ------------------- SLICE_X121Y570 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.820 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/Q net (fo=137, routed) 3.063 5.883 SFP_GEN[22].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X80Y543 LUT2 (Prop_H6LUT_SLICEL_I1_O) 0.147 6.030 r SFP_GEN[22].ngCCM_gbt/SFP_GEN[22].ngccm_status_reg[22][24]_i_1/O net (fo=18, routed) 0.694 6.724 rx_test_comm_cnt259_out SLICE_X80Y540 FDCE r SFP_GEN[22].ngccm_status_reg_reg[22][1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.204 10.919 g_gbt_bank[1].gbtbank_n_124 SLICE_X80Y540 FDCE r SFP_GEN[22].ngccm_status_reg_reg[22][1]/C clock pessimism 0.214 11.134 clock uncertainty -0.035 11.098 SLICE_X80Y540 FDCE (Setup_EFF2_SLICEL_C_CE) -0.058 11.040 SFP_GEN[22].ngccm_status_reg_reg[22][1] ------------------------------------------------------------------- required time 11.040 arrival time -6.724 ------------------------------------------------------------------- slack 4.316 Slack (MET) : 4.316ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[22].ngccm_status_reg_reg[22][4]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 4.044ns (logic 0.287ns (7.097%) route 3.757ns (92.903%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.602ns = ( 10.919 - 8.317 ) Source Clock Delay (SCD): 2.680ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.205ns (routing 0.623ns, distribution 1.582ns) Clock Net Delay (Destination): 2.204ns (routing 0.566ns, distribution 1.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.205 2.680 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X121Y570 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C ------------------------------------------------------------------- ------------------- SLICE_X121Y570 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.820 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/Q net (fo=137, routed) 3.063 5.883 SFP_GEN[22].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X80Y543 LUT2 (Prop_H6LUT_SLICEL_I1_O) 0.147 6.030 r SFP_GEN[22].ngCCM_gbt/SFP_GEN[22].ngccm_status_reg[22][24]_i_1/O net (fo=18, routed) 0.694 6.724 rx_test_comm_cnt259_out SLICE_X80Y540 FDCE r SFP_GEN[22].ngccm_status_reg_reg[22][4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.204 10.919 g_gbt_bank[1].gbtbank_n_124 SLICE_X80Y540 FDCE r SFP_GEN[22].ngccm_status_reg_reg[22][4]/C clock pessimism 0.214 11.134 clock uncertainty -0.035 11.098 SLICE_X80Y540 FDCE (Setup_FFF2_SLICEL_C_CE) -0.058 11.040 SFP_GEN[22].ngccm_status_reg_reg[22][4] ------------------------------------------------------------------- required time 11.040 arrival time -6.724 ------------------------------------------------------------------- slack 4.316 Slack (MET) : 4.316ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[22].ngccm_status_reg_reg[22][6]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 4.044ns (logic 0.287ns (7.097%) route 3.757ns (92.903%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.602ns = ( 10.919 - 8.317 ) Source Clock Delay (SCD): 2.680ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.205ns (routing 0.623ns, distribution 1.582ns) Clock Net Delay (Destination): 2.204ns (routing 0.566ns, distribution 1.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.205 2.680 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X121Y570 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C ------------------------------------------------------------------- ------------------- SLICE_X121Y570 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.820 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/Q net (fo=137, routed) 3.063 5.883 SFP_GEN[22].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X80Y543 LUT2 (Prop_H6LUT_SLICEL_I1_O) 0.147 6.030 r SFP_GEN[22].ngCCM_gbt/SFP_GEN[22].ngccm_status_reg[22][24]_i_1/O net (fo=18, routed) 0.694 6.724 rx_test_comm_cnt259_out SLICE_X80Y540 FDCE r SFP_GEN[22].ngccm_status_reg_reg[22][6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.204 10.919 g_gbt_bank[1].gbtbank_n_124 SLICE_X80Y540 FDCE r SFP_GEN[22].ngccm_status_reg_reg[22][6]/C clock pessimism 0.214 11.134 clock uncertainty -0.035 11.098 SLICE_X80Y540 FDCE (Setup_GFF2_SLICEL_C_CE) -0.058 11.040 SFP_GEN[22].ngccm_status_reg_reg[22][6] ------------------------------------------------------------------- required time 11.040 arrival time -6.724 ------------------------------------------------------------------- slack 4.316 Slack (MET) : 4.323ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[22].ngccm_status_reg_reg[22][0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 4.040ns (logic 0.287ns (7.104%) route 3.753ns (92.896%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.602ns = ( 10.919 - 8.317 ) Source Clock Delay (SCD): 2.680ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.205ns (routing 0.623ns, distribution 1.582ns) Clock Net Delay (Destination): 2.204ns (routing 0.566ns, distribution 1.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.205 2.680 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X121Y570 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C ------------------------------------------------------------------- ------------------- SLICE_X121Y570 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.820 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/Q net (fo=137, routed) 3.063 5.883 SFP_GEN[22].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X80Y543 LUT2 (Prop_H6LUT_SLICEL_I1_O) 0.147 6.030 r SFP_GEN[22].ngCCM_gbt/SFP_GEN[22].ngccm_status_reg[22][24]_i_1/O net (fo=18, routed) 0.690 6.720 rx_test_comm_cnt259_out SLICE_X80Y540 FDCE r SFP_GEN[22].ngccm_status_reg_reg[22][0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.204 10.919 g_gbt_bank[1].gbtbank_n_124 SLICE_X80Y540 FDCE r SFP_GEN[22].ngccm_status_reg_reg[22][0]/C clock pessimism 0.214 11.134 clock uncertainty -0.035 11.098 SLICE_X80Y540 FDCE (Setup_EFF_SLICEL_C_CE) -0.055 11.043 SFP_GEN[22].ngccm_status_reg_reg[22][0] ------------------------------------------------------------------- required time 11.043 arrival time -6.720 ------------------------------------------------------------------- slack 4.323 Slack (MET) : 4.323ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[22].ngccm_status_reg_reg[22][3]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 4.040ns (logic 0.287ns (7.104%) route 3.753ns (92.896%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.602ns = ( 10.919 - 8.317 ) Source Clock Delay (SCD): 2.680ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.205ns (routing 0.623ns, distribution 1.582ns) Clock Net Delay (Destination): 2.204ns (routing 0.566ns, distribution 1.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.205 2.680 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X121Y570 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C ------------------------------------------------------------------- ------------------- SLICE_X121Y570 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.820 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/Q net (fo=137, routed) 3.063 5.883 SFP_GEN[22].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X80Y543 LUT2 (Prop_H6LUT_SLICEL_I1_O) 0.147 6.030 r SFP_GEN[22].ngCCM_gbt/SFP_GEN[22].ngccm_status_reg[22][24]_i_1/O net (fo=18, routed) 0.690 6.720 rx_test_comm_cnt259_out SLICE_X80Y540 FDCE r SFP_GEN[22].ngccm_status_reg_reg[22][3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.204 10.919 g_gbt_bank[1].gbtbank_n_124 SLICE_X80Y540 FDCE r SFP_GEN[22].ngccm_status_reg_reg[22][3]/C clock pessimism 0.214 11.134 clock uncertainty -0.035 11.098 SLICE_X80Y540 FDCE (Setup_FFF_SLICEL_C_CE) -0.055 11.043 SFP_GEN[22].ngccm_status_reg_reg[22][3] ------------------------------------------------------------------- required time 11.043 arrival time -6.720 ------------------------------------------------------------------- slack 4.323 Slack (MET) : 4.323ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[22].ngccm_status_reg_reg[22][5]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 4.040ns (logic 0.287ns (7.104%) route 3.753ns (92.896%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.602ns = ( 10.919 - 8.317 ) Source Clock Delay (SCD): 2.680ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.205ns (routing 0.623ns, distribution 1.582ns) Clock Net Delay (Destination): 2.204ns (routing 0.566ns, distribution 1.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.205 2.680 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X121Y570 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C ------------------------------------------------------------------- ------------------- SLICE_X121Y570 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.820 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/Q net (fo=137, routed) 3.063 5.883 SFP_GEN[22].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X80Y543 LUT2 (Prop_H6LUT_SLICEL_I1_O) 0.147 6.030 r SFP_GEN[22].ngCCM_gbt/SFP_GEN[22].ngccm_status_reg[22][24]_i_1/O net (fo=18, routed) 0.690 6.720 rx_test_comm_cnt259_out SLICE_X80Y540 FDCE r SFP_GEN[22].ngccm_status_reg_reg[22][5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.204 10.919 g_gbt_bank[1].gbtbank_n_124 SLICE_X80Y540 FDCE r SFP_GEN[22].ngccm_status_reg_reg[22][5]/C clock pessimism 0.214 11.134 clock uncertainty -0.035 11.098 SLICE_X80Y540 FDCE (Setup_GFF_SLICEL_C_CE) -0.055 11.043 SFP_GEN[22].ngccm_status_reg_reg[22][5] ------------------------------------------------------------------- required time 11.043 arrival time -6.720 ------------------------------------------------------------------- slack 4.323 Slack (MET) : 4.323ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[22].ngccm_status_reg_reg[22][8]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 4.040ns (logic 0.287ns (7.104%) route 3.753ns (92.896%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.602ns = ( 10.919 - 8.317 ) Source Clock Delay (SCD): 2.680ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.205ns (routing 0.623ns, distribution 1.582ns) Clock Net Delay (Destination): 2.204ns (routing 0.566ns, distribution 1.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.205 2.680 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X121Y570 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C ------------------------------------------------------------------- ------------------- SLICE_X121Y570 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.820 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/Q net (fo=137, routed) 3.063 5.883 SFP_GEN[22].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X80Y543 LUT2 (Prop_H6LUT_SLICEL_I1_O) 0.147 6.030 r SFP_GEN[22].ngCCM_gbt/SFP_GEN[22].ngccm_status_reg[22][24]_i_1/O net (fo=18, routed) 0.690 6.720 rx_test_comm_cnt259_out SLICE_X80Y540 FDCE r SFP_GEN[22].ngccm_status_reg_reg[22][8]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.204 10.919 g_gbt_bank[1].gbtbank_n_124 SLICE_X80Y540 FDCE r SFP_GEN[22].ngccm_status_reg_reg[22][8]/C clock pessimism 0.214 11.134 clock uncertainty -0.035 11.098 SLICE_X80Y540 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 11.043 SFP_GEN[22].ngccm_status_reg_reg[22][8] ------------------------------------------------------------------- required time 11.043 arrival time -6.720 ------------------------------------------------------------------- slack 4.323 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.031ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[22].rx_data_ngccm_reg[22][64]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.294ns (logic 0.122ns (41.497%) route 0.172ns (58.503%)) Logic Levels: 0 Clock Path Skew: 0.136ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.666ns Source Clock Delay (SCD): 2.306ns Clock Pessimism Removal (CPR): 0.224ns Clock Net Delay (Source): 1.908ns (routing 0.566ns, distribution 1.342ns) Clock Net Delay (Destination): 2.191ns (routing 0.623ns, distribution 1.568ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 0.052 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 0.398 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.908 2.306 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X124Y571 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X124Y571 FDRE (Prop_CFF_SLICEL_C_Q) 0.122 2.428 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/Q net (fo=1, routed) 0.172 2.600 rx_data[22][64] SLICE_X122Y571 FDCE r SFP_GEN[22].rx_data_ngccm_reg[22][64]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.191 2.666 g_gbt_bank[1].gbtbank_n_124 SLICE_X122Y571 FDCE r SFP_GEN[22].rx_data_ngccm_reg[22][64]/C clock pessimism -0.224 2.442 SLICE_X122Y571 FDCE (Hold_EFF2_SLICEL_C_D) 0.127 2.569 SFP_GEN[22].rx_data_ngccm_reg[22][64] ------------------------------------------------------------------- required time -2.569 arrival time 2.600 ------------------------------------------------------------------- slack 0.031 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[22].rx_data_ngccm_reg[22][57]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.049ns (34.028%) route 0.095ns (65.972%)) Logic Levels: 0 Clock Path Skew: 0.047ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.139ns Source Clock Delay (SCD): 0.929ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 0.811ns (routing 0.271ns, distribution 0.540ns) Clock Net Delay (Destination): 0.974ns (routing 0.311ns, distribution 0.663ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.811 0.929 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X124Y575 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X124Y575 FDRE (Prop_AFF2_SLICEL_C_Q) 0.049 0.978 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/Q net (fo=1, routed) 0.095 1.073 rx_data[22][57] SLICE_X124Y573 FDCE r SFP_GEN[22].rx_data_ngccm_reg[22][57]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.139 g_gbt_bank[1].gbtbank_n_124 SLICE_X124Y573 FDCE r SFP_GEN[22].rx_data_ngccm_reg[22][57]/C clock pessimism -0.163 0.976 SLICE_X124Y573 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 1.032 SFP_GEN[22].rx_data_ngccm_reg[22][57] ------------------------------------------------------------------- required time -1.032 arrival time 1.073 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.136ns Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.173ns Clock Net Delay (Source): 0.803ns (routing 0.271ns, distribution 0.532ns) Clock Net Delay (Destination): 0.971ns (routing 0.311ns, distribution 0.660ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.803 0.921 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X124Y571 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X124Y571 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 0.970 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Q net (fo=1, routed) 0.034 1.004 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] SLICE_X124Y571 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.045 1.049 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__21/O net (fo=1, routed) 0.016 1.065 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[1] SLICE_X124Y571 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.971 1.136 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X124Y571 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.173 0.963 SLICE_X124Y571 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.019 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.019 arrival time 1.065 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.159ns (logic 0.078ns (49.057%) route 0.081ns (50.943%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.133ns Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.162ns Clock Net Delay (Source): 0.797ns (routing 0.271ns, distribution 0.526ns) Clock Net Delay (Destination): 0.968ns (routing 0.311ns, distribution 0.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.797 0.915 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X119Y571 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X119Y571 FDCE (Prop_BFF2_SLICEM_C_Q) 0.048 0.963 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Q net (fo=2, routed) 0.069 1.032 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_7_in SLICE_X119Y572 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.030 1.062 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__21/O net (fo=1, routed) 0.012 1.074 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[4] SLICE_X119Y572 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.968 1.133 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X119Y572 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.162 0.971 SLICE_X119Y572 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.027 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.027 arrival time 1.074 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.094ns (66.197%) route 0.048ns (33.803%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.132ns Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.172ns Clock Net Delay (Source): 0.804ns (routing 0.271ns, distribution 0.533ns) Clock Net Delay (Destination): 0.967ns (routing 0.311ns, distribution 0.656ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.804 0.922 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X119Y573 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X119Y573 FDCE (Prop_DFF_SLICEM_C_Q) 0.049 0.971 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Q net (fo=2, routed) 0.036 1.007 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_13_in SLICE_X119Y573 LUT3 (Prop_E6LUT_SLICEM_I2_O) 0.045 1.052 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__21/O net (fo=1, routed) 0.012 1.064 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[5] SLICE_X119Y573 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.967 1.132 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X119Y573 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism -0.172 0.960 SLICE_X119Y573 FDRE (Hold_EFF_SLICEM_C_D) 0.056 1.016 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time -1.016 arrival time 1.064 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.094ns (64.828%) route 0.051ns (35.172%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.136ns Source Clock Delay (SCD): 0.923ns Clock Pessimism Removal (CPR): 0.172ns Clock Net Delay (Source): 0.805ns (routing 0.271ns, distribution 0.534ns) Clock Net Delay (Destination): 0.971ns (routing 0.311ns, distribution 0.660ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.805 0.923 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X119Y574 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X119Y574 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 0.972 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Q net (fo=1, routed) 0.035 1.007 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] SLICE_X119Y574 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.045 1.052 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__21/O net (fo=1, routed) 0.016 1.068 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[1] SLICE_X119Y574 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.971 1.136 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X119Y574 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.172 0.964 SLICE_X119Y574 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.020 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.020 arrival time 1.068 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.094ns (64.384%) route 0.052ns (35.616%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.143ns Source Clock Delay (SCD): 0.927ns Clock Pessimism Removal (CPR): 0.174ns Clock Net Delay (Source): 0.809ns (routing 0.271ns, distribution 0.538ns) Clock Net Delay (Destination): 0.978ns (routing 0.311ns, distribution 0.667ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.809 0.927 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X124Y575 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X124Y575 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 0.976 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Q net (fo=2, routed) 0.036 1.012 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_23_in SLICE_X124Y575 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.045 1.057 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__21/O net (fo=1, routed) 0.016 1.073 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[10] SLICE_X124Y575 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.978 1.143 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X124Y575 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C clock pessimism -0.174 0.969 SLICE_X124Y575 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.025 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10] ------------------------------------------------------------------- required time -1.025 arrival time 1.073 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.094ns (64.384%) route 0.052ns (35.616%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.141ns Source Clock Delay (SCD): 0.926ns Clock Pessimism Removal (CPR): 0.173ns Clock Net Delay (Source): 0.808ns (routing 0.271ns, distribution 0.537ns) Clock Net Delay (Destination): 0.976ns (routing 0.311ns, distribution 0.665ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.808 0.926 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X124Y574 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X124Y574 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 0.975 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/Q net (fo=2, routed) 0.036 1.011 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_9_in SLICE_X124Y574 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.045 1.056 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__21/O net (fo=1, routed) 0.016 1.072 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[5] SLICE_X124Y574 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.976 1.141 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X124Y574 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism -0.173 0.968 SLICE_X124Y574 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.024 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time -1.024 arrival time 1.072 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[22].rx_data_ngccm_reg[22][34]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.048ns (33.103%) route 0.097ns (66.897%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.132ns Source Clock Delay (SCD): 0.920ns Clock Pessimism Removal (CPR): 0.172ns Clock Net Delay (Source): 0.802ns (routing 0.271ns, distribution 0.531ns) Clock Net Delay (Destination): 0.967ns (routing 0.311ns, distribution 0.656ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.802 0.920 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X119Y572 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X119Y572 FDRE (Prop_HFF_SLICEM_C_Q) 0.048 0.968 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/Q net (fo=1, routed) 0.097 1.065 rx_data[22][34] SLICE_X120Y572 FDCE r SFP_GEN[22].rx_data_ngccm_reg[22][34]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.967 1.132 g_gbt_bank[1].gbtbank_n_124 SLICE_X120Y572 FDCE r SFP_GEN[22].rx_data_ngccm_reg[22][34]/C clock pessimism -0.172 0.960 SLICE_X120Y572 FDCE (Hold_BFF2_SLICEL_C_D) 0.056 1.016 SFP_GEN[22].rx_data_ngccm_reg[22][34] ------------------------------------------------------------------- required time -1.016 arrival time 1.065 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.132ns Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.172ns Clock Net Delay (Source): 0.804ns (routing 0.271ns, distribution 0.533ns) Clock Net Delay (Destination): 0.967ns (routing 0.311ns, distribution 0.656ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.804 0.922 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X119Y573 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X119Y573 FDCE (Prop_AFF2_SLICEM_C_Q) 0.049 0.971 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.036 1.007 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_35_in SLICE_X119Y573 LUT3 (Prop_G6LUT_SLICEM_I2_O) 0.045 1.052 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__21/O net (fo=1, routed) 0.014 1.066 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[16] SLICE_X119Y573 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.967 1.132 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X119Y573 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.172 0.960 SLICE_X119Y573 FDRE (Hold_GFF_SLICEM_C_D) 0.056 1.016 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.016 arrival time 1.066 ------------------------------------------------------------------- slack 0.050 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_13 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y237 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y541 g_clock_rate_din[22].ngccm_status_cnt_reg[22][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y541 g_clock_rate_din[22].ngccm_status_cnt_reg[22][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y543 g_clock_rate_din[22].ngccm_status_cnt_reg[22][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y543 g_clock_rate_din[22].ngccm_status_cnt_reg[22][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y543 g_clock_rate_din[22].ngccm_status_cnt_reg[22][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y543 g_clock_rate_din[22].ngccm_status_cnt_reg[22][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X93Y540 g_clock_rate_din[22].ngccm_status_cnt_reg[22][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y541 g_clock_rate_din[22].ngccm_status_cnt_reg[22][0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y541 g_clock_rate_din[22].ngccm_status_cnt_reg[22][0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y541 g_clock_rate_din[22].ngccm_status_cnt_reg[22][1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y541 g_clock_rate_din[22].ngccm_status_cnt_reg[22][1]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y543 g_clock_rate_din[22].ngccm_status_cnt_reg[22][2]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y543 g_clock_rate_din[22].ngccm_status_cnt_reg[22][3]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X118Y540 SFP_GEN[22].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X118Y540 SFP_GEN[22].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X106Y560 SFP_GEN[22].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X106Y560 SFP_GEN[22].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X106Y560 SFP_GEN[22].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X112Y548 SFP_GEN[22].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_14 To Clock: gtwiz_userclk_rx_srcclk_out[0]_14 Setup : 0 Failing Endpoints, Worst Slack 3.090ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.035ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.493ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.090ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 4.923ns (logic 1.549ns (31.465%) route 3.374ns (68.535%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.214ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.215ns = ( 10.532 - 8.317 ) Source Clock Delay (SCD): 2.636ns Clock Pessimism Removal (CPR): 0.207ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.161ns (routing 0.620ns, distribution 1.541ns) Clock Net Delay (Destination): 1.817ns (routing 0.564ns, distribution 1.253ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.161 2.636 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.797 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.268 6.065 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X108Y557 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.303 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/O net (fo=5, routed) 0.533 6.836 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y556 LUT6 (Prop_F6LUT_SLICEM_I0_O) 0.150 6.986 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__23/O net (fo=5, routed) 0.573 7.559 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 SLICE_X109Y556 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.817 10.532 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y556 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.207 10.739 clock uncertainty -0.035 10.704 SLICE_X109Y556 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 10.649 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 10.649 arrival time -7.559 ------------------------------------------------------------------- slack 3.090 Slack (MET) : 3.090ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 4.923ns (logic 1.549ns (31.465%) route 3.374ns (68.535%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.214ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.215ns = ( 10.532 - 8.317 ) Source Clock Delay (SCD): 2.636ns Clock Pessimism Removal (CPR): 0.207ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.161ns (routing 0.620ns, distribution 1.541ns) Clock Net Delay (Destination): 1.817ns (routing 0.564ns, distribution 1.253ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.161 2.636 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.797 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.268 6.065 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X108Y557 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.303 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/O net (fo=5, routed) 0.533 6.836 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y556 LUT6 (Prop_F6LUT_SLICEM_I0_O) 0.150 6.986 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__23/O net (fo=5, routed) 0.573 7.559 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 SLICE_X109Y556 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.817 10.532 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y556 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.207 10.739 clock uncertainty -0.035 10.704 SLICE_X109Y556 FDRE (Setup_BFF2_SLICEM_C_CE) -0.055 10.649 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 10.649 arrival time -7.559 ------------------------------------------------------------------- slack 3.090 Slack (MET) : 3.094ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 4.920ns (logic 1.549ns (31.484%) route 3.371ns (68.516%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.214ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.215ns = ( 10.532 - 8.317 ) Source Clock Delay (SCD): 2.636ns Clock Pessimism Removal (CPR): 0.207ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.161ns (routing 0.620ns, distribution 1.541ns) Clock Net Delay (Destination): 1.817ns (routing 0.564ns, distribution 1.253ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.161 2.636 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.797 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.268 6.065 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X108Y557 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.303 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/O net (fo=5, routed) 0.533 6.836 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y556 LUT6 (Prop_F6LUT_SLICEM_I0_O) 0.150 6.986 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__23/O net (fo=5, routed) 0.570 7.556 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 SLICE_X109Y556 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.817 10.532 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y556 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C clock pessimism 0.207 10.739 clock uncertainty -0.035 10.704 SLICE_X109Y556 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 10.650 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0] ------------------------------------------------------------------- required time 10.650 arrival time -7.556 ------------------------------------------------------------------- slack 3.094 Slack (MET) : 3.094ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 4.920ns (logic 1.549ns (31.484%) route 3.371ns (68.516%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.214ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.215ns = ( 10.532 - 8.317 ) Source Clock Delay (SCD): 2.636ns Clock Pessimism Removal (CPR): 0.207ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.161ns (routing 0.620ns, distribution 1.541ns) Clock Net Delay (Destination): 1.817ns (routing 0.564ns, distribution 1.253ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.161 2.636 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.797 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.268 6.065 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X108Y557 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.303 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/O net (fo=5, routed) 0.533 6.836 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y556 LUT6 (Prop_F6LUT_SLICEM_I0_O) 0.150 6.986 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__23/O net (fo=5, routed) 0.570 7.556 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 SLICE_X109Y556 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.817 10.532 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y556 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C clock pessimism 0.207 10.739 clock uncertainty -0.035 10.704 SLICE_X109Y556 FDRE (Setup_BFF_SLICEM_C_CE) -0.054 10.650 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2] ------------------------------------------------------------------- required time 10.650 arrival time -7.556 ------------------------------------------------------------------- slack 3.094 Slack (MET) : 3.211ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 4.793ns (logic 1.712ns (35.719%) route 3.081ns (64.281%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.205ns = ( 10.522 - 8.317 ) Source Clock Delay (SCD): 2.636ns Clock Pessimism Removal (CPR): 0.207ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.161ns (routing 0.620ns, distribution 1.541ns) Clock Net Delay (Destination): 1.807ns (routing 0.564ns, distribution 1.243ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.161 2.636 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.797 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.268 6.065 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X108Y557 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.303 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/O net (fo=5, routed) 0.315 6.618 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X111Y557 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.147 6.765 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__22/O net (fo=1, routed) 0.079 6.844 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__22_n_0 SLICE_X111Y557 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.166 7.010 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__22/O net (fo=2, routed) 0.419 7.429 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__22_n_0 SLICE_X109Y558 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.807 10.522 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y558 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.207 10.729 clock uncertainty -0.035 10.694 SLICE_X109Y558 FDCE (Setup_BFF_SLICEM_C_CE) -0.054 10.640 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.640 arrival time -7.429 ------------------------------------------------------------------- slack 3.211 Slack (MET) : 3.211ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 4.793ns (logic 1.712ns (35.719%) route 3.081ns (64.281%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.205ns = ( 10.522 - 8.317 ) Source Clock Delay (SCD): 2.636ns Clock Pessimism Removal (CPR): 0.207ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.161ns (routing 0.620ns, distribution 1.541ns) Clock Net Delay (Destination): 1.807ns (routing 0.564ns, distribution 1.243ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.161 2.636 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.797 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.268 6.065 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X108Y557 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.303 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/O net (fo=5, routed) 0.315 6.618 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X111Y557 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.147 6.765 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__22/O net (fo=1, routed) 0.079 6.844 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__22_n_0 SLICE_X111Y557 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.166 7.010 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__22/O net (fo=2, routed) 0.419 7.429 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__22_n_0 SLICE_X109Y558 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.807 10.522 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y558 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.207 10.729 clock uncertainty -0.035 10.694 SLICE_X109Y558 FDCE (Setup_CFF_SLICEM_C_CE) -0.054 10.640 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.640 arrival time -7.429 ------------------------------------------------------------------- slack 3.211 Slack (MET) : 3.255ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 4.756ns (logic 1.549ns (32.569%) route 3.207ns (67.431%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.213ns = ( 10.530 - 8.317 ) Source Clock Delay (SCD): 2.636ns Clock Pessimism Removal (CPR): 0.207ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.161ns (routing 0.620ns, distribution 1.541ns) Clock Net Delay (Destination): 1.815ns (routing 0.564ns, distribution 1.251ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.161 2.636 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.797 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.268 6.065 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X108Y557 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.303 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/O net (fo=5, routed) 0.533 6.836 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y556 LUT6 (Prop_F6LUT_SLICEM_I0_O) 0.150 6.986 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__23/O net (fo=5, routed) 0.406 7.392 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 SLICE_X109Y557 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.815 10.530 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y557 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism 0.207 10.737 clock uncertainty -0.035 10.702 SLICE_X109Y557 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 10.647 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time 10.647 arrival time -7.392 ------------------------------------------------------------------- slack 3.255 Slack (MET) : 3.510ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 4.504ns (logic 1.450ns (32.194%) route 3.054ns (67.806%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.213ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.216ns = ( 10.533 - 8.317 ) Source Clock Delay (SCD): 2.636ns Clock Pessimism Removal (CPR): 0.207ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.161ns (routing 0.620ns, distribution 1.541ns) Clock Net Delay (Destination): 1.818ns (routing 0.564ns, distribution 1.254ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.161 2.636 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.797 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.268 6.065 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X108Y557 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.303 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/O net (fo=5, routed) 0.316 6.619 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X111Y557 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.051 6.670 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__23/O net (fo=7, routed) 0.470 7.140 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 SLICE_X109Y555 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.818 10.533 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y555 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.207 10.740 clock uncertainty -0.035 10.705 SLICE_X109Y555 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 10.650 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 10.650 arrival time -7.140 ------------------------------------------------------------------- slack 3.510 Slack (MET) : 3.514ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 4.501ns (logic 1.450ns (32.215%) route 3.051ns (67.785%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.213ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.216ns = ( 10.533 - 8.317 ) Source Clock Delay (SCD): 2.636ns Clock Pessimism Removal (CPR): 0.207ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.161ns (routing 0.620ns, distribution 1.541ns) Clock Net Delay (Destination): 1.818ns (routing 0.564ns, distribution 1.254ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.161 2.636 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.797 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.268 6.065 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X108Y557 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.303 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/O net (fo=5, routed) 0.316 6.619 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X111Y557 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.051 6.670 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__23/O net (fo=7, routed) 0.467 7.137 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 SLICE_X109Y555 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.818 10.533 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y555 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.207 10.740 clock uncertainty -0.035 10.705 SLICE_X109Y555 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 10.651 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 10.651 arrival time -7.137 ------------------------------------------------------------------- slack 3.514 Slack (MET) : 3.523ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 4.487ns (logic 1.454ns (32.405%) route 3.033ns (67.595%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.214ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.215ns = ( 10.532 - 8.317 ) Source Clock Delay (SCD): 2.636ns Clock Pessimism Removal (CPR): 0.207ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.161ns (routing 0.620ns, distribution 1.541ns) Clock Net Delay (Destination): 1.817ns (routing 0.564ns, distribution 1.253ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.161 2.636 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.797 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.268 6.065 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X108Y557 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.303 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/O net (fo=5, routed) 0.421 6.724 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y555 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.055 6.779 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__23/O net (fo=3, routed) 0.344 7.123 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 SLICE_X109Y555 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.817 10.532 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y555 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.207 10.739 clock uncertainty -0.035 10.704 SLICE_X109Y555 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 10.646 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 10.646 arrival time -7.123 ------------------------------------------------------------------- slack 3.523 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.035ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[23].rx_data_ngccm_reg[23][7]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.048ns (32.215%) route 0.101ns (67.785%)) Logic Levels: 0 Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.086ns Source Clock Delay (SCD): 0.900ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.782ns (routing 0.270ns, distribution 0.512ns) Clock Net Delay (Destination): 0.921ns (routing 0.308ns, distribution 0.613ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.782 0.900 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X102Y563 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X102Y563 FDRE (Prop_CFF2_SLICEL_C_Q) 0.048 0.948 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/Q net (fo=1, routed) 0.101 1.049 rx_data[23][7] SLICE_X104Y563 FDCE r SFP_GEN[23].rx_data_ngccm_reg[23][7]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.921 1.086 g_gbt_bank[1].gbtbank_n_134 SLICE_X104Y563 FDCE r SFP_GEN[23].rx_data_ngccm_reg[23][7]/C clock pessimism -0.128 0.958 SLICE_X104Y563 FDCE (Hold_HFF2_SLICEL_C_D) 0.056 1.014 SFP_GEN[23].rx_data_ngccm_reg[23][7] ------------------------------------------------------------------- required time -1.014 arrival time 1.049 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.035ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.063ns (44.056%) route 0.080ns (55.944%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.118ns Source Clock Delay (SCD): 0.908ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 0.790ns (routing 0.270ns, distribution 0.520ns) Clock Net Delay (Destination): 0.953ns (routing 0.308ns, distribution 0.645ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.790 0.908 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X101Y553 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X101Y553 FDCE (Prop_EFF2_SLICEM_C_Q) 0.048 0.956 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.068 1.024 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/O84[1] SLICE_X102Y554 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.015 1.039 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__22/O net (fo=1, routed) 0.012 1.051 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[1] SLICE_X102Y554 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.953 1.118 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X102Y554 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C clock pessimism -0.158 0.960 SLICE_X102Y554 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.016 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20] ------------------------------------------------------------------- required time -1.016 arrival time 1.051 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.043ns (arrival time - required time) Source: SFP_GEN[23].rx_data_ngccm_reg[23][63]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[62]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.190ns (logic 0.103ns (54.211%) route 0.087ns (45.789%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.116ns Source Clock Delay (SCD): 0.897ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.779ns (routing 0.270ns, distribution 0.509ns) Clock Net Delay (Destination): 0.951ns (routing 0.308ns, distribution 0.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.779 0.897 g_gbt_bank[1].gbtbank_n_134 SLICE_X104Y553 FDCE r SFP_GEN[23].rx_data_ngccm_reg[23][63]/C ------------------------------------------------------------------- ------------------- SLICE_X104Y553 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 0.945 r SFP_GEN[23].rx_data_ngccm_reg[23][63]/Q net (fo=1, routed) 0.075 1.020 SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[83]_0[55] SLICE_X102Y553 LUT3 (Prop_H5LUT_SLICEL_I0_O) 0.055 1.075 r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40[62]_i_1/O net (fo=1, routed) 0.012 1.087 SFP_GEN[23].ngCCM_gbt/RX_Word_rx40[62]_i_1_n_0 SLICE_X102Y553 FDCE r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[62]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.951 1.116 SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X102Y553 FDCE r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[62]/C clock pessimism -0.128 0.988 SLICE_X102Y553 FDCE (Hold_HFF2_SLICEL_C_D) 0.056 1.044 SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[62] ------------------------------------------------------------------- required time -1.044 arrival time 1.087 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.109ns Source Clock Delay (SCD): 0.897ns Clock Pessimism Removal (CPR): 0.170ns Clock Net Delay (Source): 0.779ns (routing 0.270ns, distribution 0.509ns) Clock Net Delay (Destination): 0.944ns (routing 0.308ns, distribution 0.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.779 0.897 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X102Y564 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X102Y564 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 0.946 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Q net (fo=1, routed) 0.034 0.980 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] SLICE_X102Y564 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.045 1.025 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__22/O net (fo=1, routed) 0.016 1.041 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[1] SLICE_X102Y564 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.944 1.109 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X102Y564 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.170 0.939 SLICE_X102Y564 FDRE (Hold_CFF_SLICEL_C_D) 0.056 0.995 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -0.995 arrival time 1.041 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.163ns (logic 0.079ns (48.466%) route 0.084ns (51.534%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.118ns Source Clock Delay (SCD): 0.899ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.781ns (routing 0.270ns, distribution 0.511ns) Clock Net Delay (Destination): 0.953ns (routing 0.308ns, distribution 0.645ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.781 0.899 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X102Y555 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X102Y555 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 0.948 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Q net (fo=2, routed) 0.068 1.016 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_27_in SLICE_X102Y554 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.030 1.046 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__22/O net (fo=1, routed) 0.016 1.062 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[12] SLICE_X102Y554 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.953 1.118 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X102Y554 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C clock pessimism -0.159 0.959 SLICE_X102Y554 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.015 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12] ------------------------------------------------------------------- required time -1.015 arrival time 1.062 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.094ns (64.384%) route 0.052ns (35.616%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.111ns Source Clock Delay (SCD): 0.899ns Clock Pessimism Removal (CPR): 0.170ns Clock Net Delay (Source): 0.781ns (routing 0.270ns, distribution 0.511ns) Clock Net Delay (Destination): 0.946ns (routing 0.308ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.781 0.899 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X102Y562 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X102Y562 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 0.948 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.036 0.984 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/O83[0] SLICE_X102Y562 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.045 1.029 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__22/O net (fo=1, routed) 0.016 1.045 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[17] SLICE_X102Y562 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.946 1.111 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X102Y562 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.170 0.941 SLICE_X102Y562 FDRE (Hold_DFF_SLICEL_C_D) 0.056 0.997 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -0.997 arrival time 1.045 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.166ns (logic 0.087ns (52.410%) route 0.079ns (47.590%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.118ns Source Clock Delay (SCD): 0.899ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.781ns (routing 0.270ns, distribution 0.511ns) Clock Net Delay (Destination): 0.953ns (routing 0.308ns, distribution 0.645ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.781 0.899 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X102Y555 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X102Y555 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 0.948 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Q net (fo=2, routed) 0.068 1.016 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_27_in SLICE_X102Y554 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.038 1.054 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__22/O net (fo=1, routed) 0.011 1.065 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[14] SLICE_X102Y554 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.953 1.118 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X102Y554 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C clock pessimism -0.159 0.959 SLICE_X102Y554 FDRE (Hold_DFF2_SLICEL_C_D) 0.056 1.015 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14] ------------------------------------------------------------------- required time -1.015 arrival time 1.065 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: SFP_GEN[23].ngccm_status_reg_reg[23][24]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[23].ngccm_status_reg_reg[23][24]/D (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.111ns (logic 0.064ns (57.658%) route 0.047ns (42.342%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.289ns Source Clock Delay (SCD): 1.068ns Clock Pessimism Removal (CPR): 0.216ns Clock Net Delay (Source): 0.950ns (routing 0.270ns, distribution 0.680ns) Clock Net Delay (Destination): 1.124ns (routing 0.308ns, distribution 0.816ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.950 1.068 g_gbt_bank[1].gbtbank_n_134 SLICE_X81Y542 FDPE r SFP_GEN[23].ngccm_status_reg_reg[23][24]/C ------------------------------------------------------------------- ------------------- SLICE_X81Y542 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.117 r SFP_GEN[23].ngccm_status_reg_reg[23][24]/Q net (fo=2, routed) 0.035 1.152 SFP_GEN[23].ngCCM_gbt/SFP_GEN[23].ngccm_status_reg_reg[23][24]_0[8] SLICE_X81Y542 LUT2 (Prop_A6LUT_SLICEL_I0_O) 0.015 1.167 r SFP_GEN[23].ngCCM_gbt/SFP_GEN[23].ngccm_status_reg[23][24]_i_2/O net (fo=1, routed) 0.012 1.179 SFP_GEN[23].ngCCM_gbt_n_393 SLICE_X81Y542 FDPE r SFP_GEN[23].ngccm_status_reg_reg[23][24]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.124 1.289 g_gbt_bank[1].gbtbank_n_134 SLICE_X81Y542 FDPE r SFP_GEN[23].ngccm_status_reg_reg[23][24]/C clock pessimism -0.216 1.073 SLICE_X81Y542 FDPE (Hold_AFF_SLICEL_C_D) 0.056 1.129 SFP_GEN[23].ngccm_status_reg_reg[23][24] ------------------------------------------------------------------- required time -1.129 arrival time 1.179 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[23].rx_data_ngccm_reg[23][56]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.160ns (logic 0.049ns (30.625%) route 0.111ns (69.375%)) Logic Levels: 0 Clock Path Skew: 0.054ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.120ns Source Clock Delay (SCD): 0.908ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 0.790ns (routing 0.270ns, distribution 0.520ns) Clock Net Delay (Destination): 0.955ns (routing 0.308ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.790 0.908 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X102Y554 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X102Y554 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 0.957 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/Q net (fo=1, routed) 0.111 1.068 rx_data[23][56] SLICE_X101Y553 FDCE r SFP_GEN[23].rx_data_ngccm_reg[23][56]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.955 1.120 g_gbt_bank[1].gbtbank_n_134 SLICE_X101Y553 FDCE r SFP_GEN[23].rx_data_ngccm_reg[23][56]/C clock pessimism -0.158 0.962 SLICE_X101Y553 FDCE (Hold_BFF2_SLICEM_C_D) 0.056 1.018 SFP_GEN[23].rx_data_ngccm_reg[23][56] ------------------------------------------------------------------- required time -1.018 arrival time 1.068 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.168ns (logic 0.086ns (51.190%) route 0.082ns (48.810%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.118ns Source Clock Delay (SCD): 0.899ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.781ns (routing 0.270ns, distribution 0.511ns) Clock Net Delay (Destination): 0.953ns (routing 0.308ns, distribution 0.645ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.781 0.899 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X102Y555 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X102Y555 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 0.947 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.071 1.018 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in SLICE_X102Y554 LUT3 (Prop_C5LUT_SLICEL_I2_O) 0.038 1.056 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__22/O net (fo=1, routed) 0.011 1.067 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[15] SLICE_X102Y554 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.953 1.118 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X102Y554 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C clock pessimism -0.159 0.959 SLICE_X102Y554 FDRE (Hold_CFF2_SLICEL_C_D) 0.056 1.015 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15] ------------------------------------------------------------------- required time -1.015 arrival time 1.067 ------------------------------------------------------------------- slack 0.052 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_14 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y233 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X81Y540 g_clock_rate_din[23].ngccm_status_cnt_reg[23][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X81Y540 g_clock_rate_din[23].ngccm_status_cnt_reg[23][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X81Y540 g_clock_rate_din[23].ngccm_status_cnt_reg[23][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X81Y540 g_clock_rate_din[23].ngccm_status_cnt_reg[23][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X81Y542 g_clock_rate_din[23].ngccm_status_cnt_reg[23][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X81Y542 g_clock_rate_din[23].ngccm_status_cnt_reg[23][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X93Y541 g_clock_rate_din[23].ngccm_status_cnt_reg[23][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X81Y540 g_clock_rate_din[23].ngccm_status_cnt_reg[23][0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X81Y540 g_clock_rate_din[23].ngccm_status_cnt_reg[23][1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X81Y540 g_clock_rate_din[23].ngccm_status_cnt_reg[23][2]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X81Y540 g_clock_rate_din[23].ngccm_status_cnt_reg[23][3]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X81Y542 g_clock_rate_din[23].ngccm_status_cnt_reg[23][4]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X81Y542 g_clock_rate_din[23].ngccm_status_cnt_reg[23][5]/C High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X106Y540 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X106Y540 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X106Y540 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X106Y541 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X106Y542 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X106Y542 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.037 0.493 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.037 1.292 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_15 To Clock: gtwiz_userclk_rx_srcclk_out[0]_15 Setup : 0 Failing Endpoints, Worst Slack 3.165ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.043ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.493ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.165ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 5.204ns (logic 1.637ns (31.457%) route 3.567ns (68.543%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.142ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.621ns = ( 10.938 - 8.317 ) Source Clock Delay (SCD): 2.699ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.224ns (routing 0.665ns, distribution 1.559ns) Clock Net Delay (Destination): 2.223ns (routing 0.604ns, distribution 1.619ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.224 2.699 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.803 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.999 6.802 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X86Y444 LUT4 (Prop_C6LUT_SLICEL_I1_O) 0.219 7.021 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/O net (fo=5, routed) 0.211 7.232 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X88Y444 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.147 7.379 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__12/O net (fo=1, routed) 0.079 7.458 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__12_n_0 SLICE_X88Y444 LUT6 (Prop_H6LUT_SLICEL_I5_O) 0.167 7.625 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__12/O net (fo=2, routed) 0.278 7.903 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__12_n_0 SLICE_X89Y444 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.223 10.938 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y444 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.220 11.159 clock uncertainty -0.035 11.123 SLICE_X89Y444 FDCE (Setup_GFF_SLICEM_C_CE) -0.055 11.068 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.068 arrival time -7.903 ------------------------------------------------------------------- slack 3.165 Slack (MET) : 3.165ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 5.204ns (logic 1.637ns (31.457%) route 3.567ns (68.543%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.142ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.621ns = ( 10.938 - 8.317 ) Source Clock Delay (SCD): 2.699ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.224ns (routing 0.665ns, distribution 1.559ns) Clock Net Delay (Destination): 2.223ns (routing 0.604ns, distribution 1.619ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.224 2.699 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.803 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.999 6.802 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X86Y444 LUT4 (Prop_C6LUT_SLICEL_I1_O) 0.219 7.021 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/O net (fo=5, routed) 0.211 7.232 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X88Y444 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.147 7.379 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__12/O net (fo=1, routed) 0.079 7.458 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__12_n_0 SLICE_X88Y444 LUT6 (Prop_H6LUT_SLICEL_I5_O) 0.167 7.625 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__12/O net (fo=2, routed) 0.278 7.903 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__12_n_0 SLICE_X89Y444 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.223 10.938 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y444 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.220 11.159 clock uncertainty -0.035 11.123 SLICE_X89Y444 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 11.068 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.068 arrival time -7.903 ------------------------------------------------------------------- slack 3.165 Slack (MET) : 3.333ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 5.057ns (logic 1.469ns (29.049%) route 3.588ns (70.951%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.166ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.645ns = ( 10.962 - 8.317 ) Source Clock Delay (SCD): 2.699ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.224ns (routing 0.665ns, distribution 1.559ns) Clock Net Delay (Destination): 2.247ns (routing 0.604ns, distribution 1.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.224 2.699 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.803 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.999 6.802 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X86Y444 LUT4 (Prop_C6LUT_SLICEL_I1_O) 0.219 7.021 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/O net (fo=5, routed) 0.078 7.099 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X86Y444 LUT6 (Prop_E6LUT_SLICEL_I5_O) 0.146 7.245 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__13/O net (fo=3, routed) 0.511 7.756 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecFalseHeaders0 SLICE_X85Y444 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.247 10.962 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y444 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.220 11.183 clock uncertainty -0.035 11.147 SLICE_X85Y444 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 11.089 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 11.089 arrival time -7.756 ------------------------------------------------------------------- slack 3.333 Slack (MET) : 3.335ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 5.036ns (logic 1.470ns (29.190%) route 3.566ns (70.810%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.623ns = ( 10.940 - 8.317 ) Source Clock Delay (SCD): 2.699ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.224ns (routing 0.665ns, distribution 1.559ns) Clock Net Delay (Destination): 2.225ns (routing 0.604ns, distribution 1.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.224 2.699 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.803 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.999 6.802 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X86Y444 LUT4 (Prop_C6LUT_SLICEL_I1_O) 0.219 7.021 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/O net (fo=5, routed) 0.210 7.231 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X88Y444 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 7.378 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__13/O net (fo=5, routed) 0.357 7.735 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecCorrectHeaders0 SLICE_X89Y444 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.225 10.940 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y444 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.220 11.161 clock uncertainty -0.035 11.125 SLICE_X89Y444 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 11.070 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.070 arrival time -7.735 ------------------------------------------------------------------- slack 3.335 Slack (MET) : 3.335ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 5.036ns (logic 1.470ns (29.190%) route 3.566ns (70.810%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.623ns = ( 10.940 - 8.317 ) Source Clock Delay (SCD): 2.699ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.224ns (routing 0.665ns, distribution 1.559ns) Clock Net Delay (Destination): 2.225ns (routing 0.604ns, distribution 1.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.224 2.699 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.803 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.999 6.802 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X86Y444 LUT4 (Prop_C6LUT_SLICEL_I1_O) 0.219 7.021 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/O net (fo=5, routed) 0.210 7.231 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X88Y444 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 7.378 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__13/O net (fo=5, routed) 0.357 7.735 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecCorrectHeaders0 SLICE_X89Y444 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.225 10.940 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y444 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.220 11.161 clock uncertainty -0.035 11.125 SLICE_X89Y444 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 11.070 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 11.070 arrival time -7.735 ------------------------------------------------------------------- slack 3.335 Slack (MET) : 3.339ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 5.033ns (logic 1.470ns (29.207%) route 3.563ns (70.793%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.623ns = ( 10.940 - 8.317 ) Source Clock Delay (SCD): 2.699ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.224ns (routing 0.665ns, distribution 1.559ns) Clock Net Delay (Destination): 2.225ns (routing 0.604ns, distribution 1.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.224 2.699 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.803 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.999 6.802 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X86Y444 LUT4 (Prop_C6LUT_SLICEL_I1_O) 0.219 7.021 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/O net (fo=5, routed) 0.210 7.231 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X88Y444 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 7.378 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__13/O net (fo=5, routed) 0.354 7.732 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecCorrectHeaders0 SLICE_X89Y444 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.225 10.940 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y444 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C clock pessimism 0.220 11.161 clock uncertainty -0.035 11.125 SLICE_X89Y444 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 11.071 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0] ------------------------------------------------------------------- required time 11.071 arrival time -7.732 ------------------------------------------------------------------- slack 3.339 Slack (MET) : 3.339ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 5.033ns (logic 1.470ns (29.207%) route 3.563ns (70.793%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.623ns = ( 10.940 - 8.317 ) Source Clock Delay (SCD): 2.699ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.224ns (routing 0.665ns, distribution 1.559ns) Clock Net Delay (Destination): 2.225ns (routing 0.604ns, distribution 1.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.224 2.699 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.803 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.999 6.802 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X86Y444 LUT4 (Prop_C6LUT_SLICEL_I1_O) 0.219 7.021 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/O net (fo=5, routed) 0.210 7.231 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X88Y444 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 7.378 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__13/O net (fo=5, routed) 0.354 7.732 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecCorrectHeaders0 SLICE_X89Y444 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.225 10.940 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y444 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C clock pessimism 0.220 11.161 clock uncertainty -0.035 11.125 SLICE_X89Y444 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 11.071 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2] ------------------------------------------------------------------- required time 11.071 arrival time -7.732 ------------------------------------------------------------------- slack 3.339 Slack (MET) : 3.339ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 5.033ns (logic 1.470ns (29.207%) route 3.563ns (70.793%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.623ns = ( 10.940 - 8.317 ) Source Clock Delay (SCD): 2.699ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.224ns (routing 0.665ns, distribution 1.559ns) Clock Net Delay (Destination): 2.225ns (routing 0.604ns, distribution 1.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.224 2.699 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.803 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.999 6.802 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X86Y444 LUT4 (Prop_C6LUT_SLICEL_I1_O) 0.219 7.021 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/O net (fo=5, routed) 0.210 7.231 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X88Y444 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 7.378 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__13/O net (fo=5, routed) 0.354 7.732 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecCorrectHeaders0 SLICE_X89Y444 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.225 10.940 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y444 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism 0.220 11.161 clock uncertainty -0.035 11.125 SLICE_X89Y444 FDRE (Setup_BFF_SLICEM_C_CE) -0.054 11.071 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time 11.071 arrival time -7.732 ------------------------------------------------------------------- slack 3.339 Slack (MET) : 3.339ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 5.054ns (logic 1.469ns (29.066%) route 3.585ns (70.934%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.166ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.645ns = ( 10.962 - 8.317 ) Source Clock Delay (SCD): 2.699ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.224ns (routing 0.665ns, distribution 1.559ns) Clock Net Delay (Destination): 2.247ns (routing 0.604ns, distribution 1.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.224 2.699 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.803 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.999 6.802 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X86Y444 LUT4 (Prop_C6LUT_SLICEL_I1_O) 0.219 7.021 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/O net (fo=5, routed) 0.078 7.099 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X86Y444 LUT6 (Prop_E6LUT_SLICEL_I5_O) 0.146 7.245 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__13/O net (fo=3, routed) 0.508 7.753 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecFalseHeaders0 SLICE_X85Y444 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.247 10.962 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y444 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.220 11.183 clock uncertainty -0.035 11.147 SLICE_X85Y444 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 11.092 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 11.092 arrival time -7.753 ------------------------------------------------------------------- slack 3.339 Slack (MET) : 3.352ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 5.015ns (logic 1.415ns (28.215%) route 3.600ns (71.785%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.619ns = ( 10.936 - 8.317 ) Source Clock Delay (SCD): 2.699ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.224ns (routing 0.665ns, distribution 1.559ns) Clock Net Delay (Destination): 2.221ns (routing 0.604ns, distribution 1.617ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.224 2.699 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.803 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.999 6.802 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X86Y444 LUT4 (Prop_C6LUT_SLICEL_I1_O) 0.219 7.021 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/O net (fo=5, routed) 0.184 7.205 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X87Y444 LUT5 (Prop_B6LUT_SLICEM_I3_O) 0.092 7.297 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__13/O net (fo=7, routed) 0.417 7.714 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X88Y444 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.221 10.936 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y444 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.220 11.157 clock uncertainty -0.035 11.121 SLICE_X88Y444 FDRE (Setup_EFF_SLICEL_C_CE) -0.055 11.066 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 11.066 arrival time -7.714 ------------------------------------------------------------------- slack 3.352 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[13].rx_data_ngccm_reg[13][38]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.148ns (logic 0.049ns (33.108%) route 0.099ns (66.892%)) Logic Levels: 0 Clock Path Skew: 0.049ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.358ns Source Clock Delay (SCD): 1.122ns Clock Pessimism Removal (CPR): 0.187ns Clock Net Delay (Source): 1.004ns (routing 0.300ns, distribution 0.704ns) Clock Net Delay (Destination): 1.193ns (routing 0.344ns, distribution 0.849ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.004 1.122 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X77Y437 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X77Y437 FDRE (Prop_FFF_SLICEM_C_Q) 0.049 1.171 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/Q net (fo=1, routed) 0.099 1.270 rx_data[13][38] SLICE_X77Y438 FDCE r SFP_GEN[13].rx_data_ngccm_reg[13][38]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.193 1.358 g_gbt_bank[1].gbtbank_n_34 SLICE_X77Y438 FDCE r SFP_GEN[13].rx_data_ngccm_reg[13][38]/C clock pessimism -0.187 1.171 SLICE_X77Y438 FDCE (Hold_GFF_SLICEM_C_D) 0.056 1.227 SFP_GEN[13].rx_data_ngccm_reg[13][38] ------------------------------------------------------------------- required time -1.227 arrival time 1.270 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.152ns (logic 0.101ns (66.447%) route 0.051ns (33.553%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.356ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.187ns Clock Net Delay (Source): 0.999ns (routing 0.300ns, distribution 0.699ns) Clock Net Delay (Destination): 1.191ns (routing 0.344ns, distribution 0.847ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.117 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X79Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y442 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.166 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Q net (fo=2, routed) 0.035 1.201 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_25_in SLICE_X79Y441 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.052 1.253 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__12/O net (fo=1, routed) 0.016 1.269 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[13] SLICE_X79Y441 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.191 1.356 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X79Y441 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C clock pessimism -0.187 1.169 SLICE_X79Y441 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.225 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13] ------------------------------------------------------------------- required time -1.225 arrival time 1.269 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.046ns (arrival time - required time) Source: SFP_GEN[13].rx_data_ngccm_reg[13][56]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[13].ngCCM_gbt/RX_Word_rx40_reg[56]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.355ns Source Clock Delay (SCD): 1.115ns Clock Pessimism Removal (CPR): 0.198ns Clock Net Delay (Source): 0.997ns (routing 0.300ns, distribution 0.697ns) Clock Net Delay (Destination): 1.190ns (routing 0.344ns, distribution 0.846ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.115 g_gbt_bank[1].gbtbank_n_34 SLICE_X80Y441 FDCE r SFP_GEN[13].rx_data_ngccm_reg[13][56]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y441 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.164 r SFP_GEN[13].rx_data_ngccm_reg[13][56]/Q net (fo=1, routed) 0.034 1.198 g_gbt_bank[1].gbtbank/RX_Word_rx40_reg[78][32] SLICE_X80Y441 LUT3 (Prop_D6LUT_SLICEL_I1_O) 0.045 1.243 r g_gbt_bank[1].gbtbank/RX_Word_rx40[56]_i_1/O net (fo=1, routed) 0.016 1.259 SFP_GEN[13].ngCCM_gbt/RX_Word_rx40_reg[83]_0[32] SLICE_X80Y441 FDCE r SFP_GEN[13].ngCCM_gbt/RX_Word_rx40_reg[56]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.190 1.355 SFP_GEN[13].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y441 FDCE r SFP_GEN[13].ngCCM_gbt/RX_Word_rx40_reg[56]/C clock pessimism -0.198 1.157 SLICE_X80Y441 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.213 SFP_GEN[13].ngCCM_gbt/RX_Word_rx40_reg[56] ------------------------------------------------------------------- required time -1.213 arrival time 1.259 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.360ns Source Clock Delay (SCD): 1.120ns Clock Pessimism Removal (CPR): 0.198ns Clock Net Delay (Source): 1.002ns (routing 0.300ns, distribution 0.702ns) Clock Net Delay (Destination): 1.195ns (routing 0.344ns, distribution 0.851ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.002 1.120 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X78Y437 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y437 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.169 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Q net (fo=2, routed) 0.034 1.203 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_11_in SLICE_X78Y437 LUT3 (Prop_C6LUT_SLICEL_I2_O) 0.045 1.248 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__12/O net (fo=1, routed) 0.016 1.264 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[4] SLICE_X78Y437 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.195 1.360 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X78Y437 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.198 1.162 SLICE_X78Y437 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.218 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.218 arrival time 1.264 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[13].rx_data_ngccm_reg[13][26]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.152ns (logic 0.049ns (32.237%) route 0.103ns (67.763%)) Logic Levels: 0 Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.360ns Source Clock Delay (SCD): 1.123ns Clock Pessimism Removal (CPR): 0.187ns Clock Net Delay (Source): 1.005ns (routing 0.300ns, distribution 0.705ns) Clock Net Delay (Destination): 1.195ns (routing 0.344ns, distribution 0.851ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.005 1.123 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X77Y437 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X77Y437 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 1.172 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/Q net (fo=1, routed) 0.103 1.275 rx_data[13][26] SLICE_X77Y436 FDCE r SFP_GEN[13].rx_data_ngccm_reg[13][26]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.195 1.360 g_gbt_bank[1].gbtbank_n_34 SLICE_X77Y436 FDCE r SFP_GEN[13].rx_data_ngccm_reg[13][26]/C clock pessimism -0.187 1.173 SLICE_X77Y436 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.228 SFP_GEN[13].rx_data_ngccm_reg[13][26] ------------------------------------------------------------------- required time -1.228 arrival time 1.275 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.156ns (logic 0.103ns (66.026%) route 0.053ns (33.974%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.356ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.187ns Clock Net Delay (Source): 0.999ns (routing 0.300ns, distribution 0.699ns) Clock Net Delay (Destination): 1.191ns (routing 0.344ns, distribution 0.847ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.117 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X79Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y442 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.166 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Q net (fo=2, routed) 0.037 1.203 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_25_in SLICE_X79Y441 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.054 1.257 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__12/O net (fo=1, routed) 0.016 1.273 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[11] SLICE_X79Y441 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.191 1.356 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X79Y441 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C clock pessimism -0.187 1.169 SLICE_X79Y441 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.225 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11] ------------------------------------------------------------------- required time -1.225 arrival time 1.273 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[13].rx_data_ngccm_reg[13][35]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.194ns (logic 0.048ns (24.742%) route 0.146ns (75.258%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.358ns Source Clock Delay (SCD): 1.116ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.998ns (routing 0.300ns, distribution 0.698ns) Clock Net Delay (Destination): 1.193ns (routing 0.344ns, distribution 0.849ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.116 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X76Y438 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X76Y438 FDRE (Prop_BFF2_SLICEM_C_Q) 0.048 1.164 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/Q net (fo=1, routed) 0.146 1.310 rx_data[13][35] SLICE_X77Y438 FDCE r SFP_GEN[13].rx_data_ngccm_reg[13][35]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.193 1.358 g_gbt_bank[1].gbtbank_n_34 SLICE_X77Y438 FDCE r SFP_GEN[13].rx_data_ngccm_reg[13][35]/C clock pessimism -0.154 1.204 SLICE_X77Y438 FDCE (Hold_FFF2_SLICEM_C_D) 0.055 1.259 SFP_GEN[13].rx_data_ngccm_reg[13][35] ------------------------------------------------------------------- required time -1.259 arrival time 1.310 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.353ns Source Clock Delay (SCD): 1.118ns Clock Pessimism Removal (CPR): 0.198ns Clock Net Delay (Source): 1.000ns (routing 0.300ns, distribution 0.700ns) Clock Net Delay (Destination): 1.188ns (routing 0.344ns, distribution 0.844ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.000 1.118 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X78Y441 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y441 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 1.167 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.036 1.203 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/O85[1] SLICE_X78Y441 LUT3 (Prop_G6LUT_SLICEL_I0_O) 0.045 1.248 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__12/O net (fo=1, routed) 0.014 1.262 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/I9[1] SLICE_X78Y441 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.188 1.353 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X78Y441 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C clock pessimism -0.198 1.155 SLICE_X78Y441 FDRE (Hold_GFF_SLICEL_C_D) 0.056 1.211 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20] ------------------------------------------------------------------- required time -1.211 arrival time 1.262 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.104ns (69.799%) route 0.045ns (30.201%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.360ns Source Clock Delay (SCD): 1.120ns Clock Pessimism Removal (CPR): 0.198ns Clock Net Delay (Source): 1.002ns (routing 0.300ns, distribution 0.702ns) Clock Net Delay (Destination): 1.195ns (routing 0.344ns, distribution 0.851ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.002 1.120 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X78Y437 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y437 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.169 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Q net (fo=2, routed) 0.034 1.203 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_11_in SLICE_X78Y437 LUT3 (Prop_C5LUT_SLICEL_I0_O) 0.055 1.258 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__12/O net (fo=1, routed) 0.011 1.269 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[6] SLICE_X78Y437 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.195 1.360 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X78Y437 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C clock pessimism -0.198 1.162 SLICE_X78Y437 FDRE (Hold_CFF2_SLICEL_C_D) 0.056 1.218 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6] ------------------------------------------------------------------- required time -1.218 arrival time 1.269 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.159ns (logic 0.078ns (49.057%) route 0.081ns (50.943%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.051ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.354ns Source Clock Delay (SCD): 1.116ns Clock Pessimism Removal (CPR): 0.187ns Clock Net Delay (Source): 0.998ns (routing 0.300ns, distribution 0.698ns) Clock Net Delay (Destination): 1.189ns (routing 0.344ns, distribution 0.845ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.116 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X79Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y442 FDCE (Prop_FFF2_SLICEM_C_Q) 0.048 1.164 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.067 1.231 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_35_in SLICE_X79Y441 LUT3 (Prop_G6LUT_SLICEM_I2_O) 0.030 1.261 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__12/O net (fo=1, routed) 0.014 1.275 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] SLICE_X79Y441 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.189 1.354 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X79Y441 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.187 1.167 SLICE_X79Y441 FDRE (Hold_GFF_SLICEM_C_D) 0.056 1.223 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.223 arrival time 1.275 ------------------------------------------------------------------- slack 0.052 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_15 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y189 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y420 g_clock_rate_din[13].ngccm_status_cnt_reg[13][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y420 g_clock_rate_din[13].ngccm_status_cnt_reg[13][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y420 g_clock_rate_din[13].ngccm_status_cnt_reg[13][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y420 g_clock_rate_din[13].ngccm_status_cnt_reg[13][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y420 g_clock_rate_din[13].ngccm_status_cnt_reg[13][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y420 g_clock_rate_din[13].ngccm_status_cnt_reg[13][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y420 g_clock_rate_din[13].ngccm_status_cnt_reg[13][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y420 g_clock_rate_din[13].ngccm_status_cnt_reg[13][0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y420 g_clock_rate_din[13].ngccm_status_cnt_reg[13][1]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y420 g_clock_rate_din[13].ngccm_status_cnt_reg[13][2]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y420 g_clock_rate_din[13].ngccm_status_cnt_reg[13][3]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y420 g_clock_rate_din[13].ngccm_status_cnt_reg[13][3]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y420 g_clock_rate_din[13].ngccm_status_cnt_reg[13][4]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y420 g_clock_rate_din[13].ngccm_status_cnt_reg[13][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y420 g_clock_rate_din[13].ngccm_status_cnt_reg[13][1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y420 g_clock_rate_din[13].ngccm_status_cnt_reg[13][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y420 g_clock_rate_din[13].ngccm_status_cnt_reg[13][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y420 g_clock_rate_din[13].ngccm_status_cnt_reg[13][5]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y420 g_clock_rate_din[13].ngccm_status_cnt_reg[13][6]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.037 0.493 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.037 1.291 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_16 To Clock: gtwiz_userclk_rx_srcclk_out[0]_16 Setup : 0 Failing Endpoints, Worst Slack 2.973ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.030ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.493ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.973ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 5.386ns (logic 1.650ns (30.635%) route 3.736ns (69.365%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.131ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.649ns = ( 10.966 - 8.317 ) Source Clock Delay (SCD): 2.741ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.266ns (routing 0.683ns, distribution 1.583ns) Clock Net Delay (Destination): 2.251ns (routing 0.619ns, distribution 1.632ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.266 2.741 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.825 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.049 6.874 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X93Y437 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.235 7.109 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/O net (fo=5, routed) 0.286 7.395 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X93Y436 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.165 7.560 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__13/O net (fo=1, routed) 0.078 7.638 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__13_n_0 SLICE_X93Y436 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.166 7.804 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__13/O net (fo=2, routed) 0.323 8.127 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__13_n_0 SLICE_X93Y435 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.251 10.966 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y435 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.223 11.189 clock uncertainty -0.035 11.154 SLICE_X93Y435 FDCE (Setup_BFF_SLICEL_C_CE) -0.054 11.100 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.100 arrival time -8.127 ------------------------------------------------------------------- slack 2.973 Slack (MET) : 2.973ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 5.386ns (logic 1.650ns (30.635%) route 3.736ns (69.365%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.131ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.649ns = ( 10.966 - 8.317 ) Source Clock Delay (SCD): 2.741ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.266ns (routing 0.683ns, distribution 1.583ns) Clock Net Delay (Destination): 2.251ns (routing 0.619ns, distribution 1.632ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.266 2.741 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.825 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.049 6.874 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X93Y437 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.235 7.109 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/O net (fo=5, routed) 0.286 7.395 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X93Y436 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.165 7.560 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__13/O net (fo=1, routed) 0.078 7.638 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__13_n_0 SLICE_X93Y436 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.166 7.804 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__13/O net (fo=2, routed) 0.323 8.127 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__13_n_0 SLICE_X93Y435 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.251 10.966 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y435 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.223 11.189 clock uncertainty -0.035 11.154 SLICE_X93Y435 FDCE (Setup_DFF_SLICEL_C_CE) -0.054 11.100 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.100 arrival time -8.127 ------------------------------------------------------------------- slack 2.973 Slack (MET) : 3.089ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 5.274ns (logic 1.466ns (27.797%) route 3.808ns (72.203%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.654ns = ( 10.971 - 8.317 ) Source Clock Delay (SCD): 2.741ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.266ns (routing 0.683ns, distribution 1.583ns) Clock Net Delay (Destination): 2.256ns (routing 0.619ns, distribution 1.637ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.266 2.741 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.825 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.049 6.874 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X93Y437 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.235 7.109 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/O net (fo=5, routed) 0.186 7.295 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X93Y435 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 7.442 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__14/O net (fo=5, routed) 0.573 8.015 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecCorrectHeaders0 SLICE_X93Y436 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.256 10.971 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y436 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism 0.223 11.194 clock uncertainty -0.035 11.159 SLICE_X93Y436 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 11.104 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time 11.104 arrival time -8.015 ------------------------------------------------------------------- slack 3.089 Slack (MET) : 3.090ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 5.275ns (logic 1.466ns (27.791%) route 3.809ns (72.209%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.659ns = ( 10.976 - 8.317 ) Source Clock Delay (SCD): 2.741ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.266ns (routing 0.683ns, distribution 1.583ns) Clock Net Delay (Destination): 2.261ns (routing 0.619ns, distribution 1.642ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.266 2.741 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.825 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.049 6.874 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X93Y437 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.235 7.109 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/O net (fo=5, routed) 0.186 7.295 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X93Y435 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 7.442 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__14/O net (fo=5, routed) 0.574 8.016 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecCorrectHeaders0 SLICE_X92Y436 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.261 10.976 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X92Y436 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.223 11.199 clock uncertainty -0.035 11.164 SLICE_X92Y436 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 11.106 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.106 arrival time -8.016 ------------------------------------------------------------------- slack 3.090 Slack (MET) : 3.090ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 5.275ns (logic 1.466ns (27.791%) route 3.809ns (72.209%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.659ns = ( 10.976 - 8.317 ) Source Clock Delay (SCD): 2.741ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.266ns (routing 0.683ns, distribution 1.583ns) Clock Net Delay (Destination): 2.261ns (routing 0.619ns, distribution 1.642ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.266 2.741 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.825 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.049 6.874 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X93Y437 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.235 7.109 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/O net (fo=5, routed) 0.186 7.295 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X93Y435 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 7.442 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__14/O net (fo=5, routed) 0.574 8.016 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecCorrectHeaders0 SLICE_X92Y436 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.261 10.976 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X92Y436 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.223 11.199 clock uncertainty -0.035 11.164 SLICE_X92Y436 FDRE (Setup_GFF2_SLICEM_C_CE) -0.058 11.106 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 11.106 arrival time -8.016 ------------------------------------------------------------------- slack 3.090 Slack (MET) : 3.096ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 5.272ns (logic 1.466ns (27.807%) route 3.806ns (72.193%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.659ns = ( 10.976 - 8.317 ) Source Clock Delay (SCD): 2.741ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.266ns (routing 0.683ns, distribution 1.583ns) Clock Net Delay (Destination): 2.261ns (routing 0.619ns, distribution 1.642ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.266 2.741 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.825 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.049 6.874 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X93Y437 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.235 7.109 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/O net (fo=5, routed) 0.186 7.295 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X93Y435 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 7.442 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__14/O net (fo=5, routed) 0.571 8.013 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecCorrectHeaders0 SLICE_X92Y436 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.261 10.976 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X92Y436 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C clock pessimism 0.223 11.199 clock uncertainty -0.035 11.164 SLICE_X92Y436 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 11.109 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0] ------------------------------------------------------------------- required time 11.109 arrival time -8.013 ------------------------------------------------------------------- slack 3.096 Slack (MET) : 3.096ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 5.272ns (logic 1.466ns (27.807%) route 3.806ns (72.193%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.659ns = ( 10.976 - 8.317 ) Source Clock Delay (SCD): 2.741ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.266ns (routing 0.683ns, distribution 1.583ns) Clock Net Delay (Destination): 2.261ns (routing 0.619ns, distribution 1.642ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.266 2.741 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.825 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.049 6.874 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X93Y437 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.235 7.109 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/O net (fo=5, routed) 0.186 7.295 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X93Y435 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 7.442 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__14/O net (fo=5, routed) 0.571 8.013 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecCorrectHeaders0 SLICE_X92Y436 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.261 10.976 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X92Y436 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C clock pessimism 0.223 11.199 clock uncertainty -0.035 11.164 SLICE_X92Y436 FDRE (Setup_GFF_SLICEM_C_CE) -0.055 11.109 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2] ------------------------------------------------------------------- required time 11.109 arrival time -8.013 ------------------------------------------------------------------- slack 3.096 Slack (MET) : 3.177ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 5.163ns (logic 1.555ns (30.118%) route 3.608ns (69.882%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.631ns = ( 10.948 - 8.317 ) Source Clock Delay (SCD): 2.741ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.266ns (routing 0.683ns, distribution 1.583ns) Clock Net Delay (Destination): 2.233ns (routing 0.619ns, distribution 1.614ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.266 2.741 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.825 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.049 6.874 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X93Y437 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.235 7.109 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/O net (fo=5, routed) 0.196 7.305 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X93Y436 LUT5 (Prop_A6LUT_SLICEL_I3_O) 0.236 7.541 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/O net (fo=7, routed) 0.363 7.904 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X93Y438 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.233 10.948 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y438 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.223 11.171 clock uncertainty -0.035 11.136 SLICE_X93Y438 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 11.081 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.081 arrival time -7.904 ------------------------------------------------------------------- slack 3.177 Slack (MET) : 3.182ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 5.159ns (logic 1.555ns (30.142%) route 3.604ns (69.859%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.631ns = ( 10.948 - 8.317 ) Source Clock Delay (SCD): 2.741ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.266ns (routing 0.683ns, distribution 1.583ns) Clock Net Delay (Destination): 2.233ns (routing 0.619ns, distribution 1.614ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.266 2.741 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.825 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.049 6.874 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X93Y437 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.235 7.109 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/O net (fo=5, routed) 0.196 7.305 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X93Y436 LUT5 (Prop_A6LUT_SLICEL_I3_O) 0.236 7.541 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/O net (fo=7, routed) 0.359 7.900 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X93Y438 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.233 10.948 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y438 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.223 11.171 clock uncertainty -0.035 11.136 SLICE_X93Y438 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 11.082 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 11.082 arrival time -7.900 ------------------------------------------------------------------- slack 3.182 Slack (MET) : 3.182ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 5.159ns (logic 1.555ns (30.142%) route 3.604ns (69.859%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.631ns = ( 10.948 - 8.317 ) Source Clock Delay (SCD): 2.741ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.266ns (routing 0.683ns, distribution 1.583ns) Clock Net Delay (Destination): 2.233ns (routing 0.619ns, distribution 1.614ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.266 2.741 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.825 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.049 6.874 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X93Y437 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.235 7.109 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/O net (fo=5, routed) 0.196 7.305 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X93Y436 LUT5 (Prop_A6LUT_SLICEL_I3_O) 0.236 7.541 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/O net (fo=7, routed) 0.359 7.900 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X93Y438 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.233 10.948 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y438 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.223 11.171 clock uncertainty -0.035 11.136 SLICE_X93Y438 FDRE (Setup_BFF_SLICEL_C_CE) -0.054 11.082 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 11.082 arrival time -7.900 ------------------------------------------------------------------- slack 3.182 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[14].rx_data_ngccm_reg[14][28]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[14].ngCCM_gbt/RX_Word_rx40_reg[28]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.141ns (logic 0.048ns (34.043%) route 0.093ns (65.957%)) Logic Levels: 0 Clock Path Skew: 0.055ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.379ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.188ns Clock Net Delay (Source): 1.018ns (routing 0.306ns, distribution 0.712ns) Clock Net Delay (Destination): 1.214ns (routing 0.352ns, distribution 0.862ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.018 1.136 g_gbt_bank[1].gbtbank_n_44 SLICE_X86Y428 FDCE r SFP_GEN[14].rx_data_ngccm_reg[14][28]/C ------------------------------------------------------------------- ------------------- SLICE_X86Y428 FDCE (Prop_FFF2_SLICEL_C_Q) 0.048 1.184 r SFP_GEN[14].rx_data_ngccm_reg[14][28]/Q net (fo=1, routed) 0.093 1.277 SFP_GEN[14].ngCCM_gbt/RX_Word_rx40_reg[83]_0[16] SLICE_X86Y427 FDCE r SFP_GEN[14].ngCCM_gbt/RX_Word_rx40_reg[28]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.214 1.379 SFP_GEN[14].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y427 FDCE r SFP_GEN[14].ngCCM_gbt/RX_Word_rx40_reg[28]/C clock pessimism -0.188 1.191 SLICE_X86Y427 FDCE (Hold_BFF2_SLICEL_C_D) 0.056 1.247 SFP_GEN[14].ngCCM_gbt/RX_Word_rx40_reg[28] ------------------------------------------------------------------- required time -1.247 arrival time 1.277 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.033ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.183ns (logic 0.094ns (51.366%) route 0.089ns (48.634%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.379ns Source Clock Delay (SCD): 1.130ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 1.012ns (routing 0.306ns, distribution 0.706ns) Clock Net Delay (Destination): 1.214ns (routing 0.352ns, distribution 0.862ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.012 1.130 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X87Y428 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X87Y428 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.179 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Q net (fo=1, routed) 0.073 1.252 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] SLICE_X86Y428 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.045 1.297 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__13/O net (fo=1, routed) 0.016 1.313 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[0] SLICE_X86Y428 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.214 1.379 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X86Y428 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.155 1.224 SLICE_X86Y428 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.280 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -1.280 arrival time 1.313 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.034ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.191ns (logic 0.095ns (49.738%) route 0.096ns (50.262%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.101ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.102ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 0.984ns (routing 0.306ns, distribution 0.678ns) Clock Net Delay (Destination): 1.194ns (routing 0.352ns, distribution 0.842ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.984 1.102 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X92Y430 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y430 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.151 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Q net (fo=2, routed) 0.080 1.231 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_23_in SLICE_X90Y430 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.046 1.277 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__13/O net (fo=1, routed) 0.016 1.293 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[12] SLICE_X90Y430 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.194 1.359 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X90Y430 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C clock pessimism -0.156 1.203 SLICE_X90Y430 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.259 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12] ------------------------------------------------------------------- required time -1.259 arrival time 1.293 ------------------------------------------------------------------- slack 0.034 Slack (MET) : 0.035ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[14].rx_data_ngccm_reg[14][73]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.150ns (logic 0.049ns (32.667%) route 0.101ns (67.333%)) Logic Levels: 0 Clock Path Skew: 0.059ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.358ns Source Clock Delay (SCD): 1.112ns Clock Pessimism Removal (CPR): 0.187ns Clock Net Delay (Source): 0.994ns (routing 0.306ns, distribution 0.688ns) Clock Net Delay (Destination): 1.193ns (routing 0.352ns, distribution 0.841ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.994 1.112 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X90Y431 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X90Y431 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 1.161 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/Q net (fo=1, routed) 0.101 1.262 rx_data[14][73] SLICE_X90Y429 FDCE r SFP_GEN[14].rx_data_ngccm_reg[14][73]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.193 1.358 g_gbt_bank[1].gbtbank_n_44 SLICE_X90Y429 FDCE r SFP_GEN[14].rx_data_ngccm_reg[14][73]/C clock pessimism -0.187 1.171 SLICE_X90Y429 FDCE (Hold_GFF_SLICEM_C_D) 0.056 1.227 SFP_GEN[14].rx_data_ngccm_reg[14][73] ------------------------------------------------------------------- required time -1.227 arrival time 1.262 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.038ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[14].rx_data_ngccm_reg[14][43]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.168ns (logic 0.049ns (29.167%) route 0.119ns (70.833%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.367ns Source Clock Delay (SCD): 1.138ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 1.020ns (routing 0.306ns, distribution 0.714ns) Clock Net Delay (Destination): 1.202ns (routing 0.352ns, distribution 0.850ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.138 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X86Y428 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X86Y428 FDRE (Prop_BFF_SLICEL_C_Q) 0.049 1.187 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/Q net (fo=1, routed) 0.119 1.306 rx_data[14][43] SLICE_X87Y428 FDCE r SFP_GEN[14].rx_data_ngccm_reg[14][43]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.202 1.367 g_gbt_bank[1].gbtbank_n_44 SLICE_X87Y428 FDCE r SFP_GEN[14].rx_data_ngccm_reg[14][43]/C clock pessimism -0.155 1.212 SLICE_X87Y428 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.268 SFP_GEN[14].rx_data_ngccm_reg[14][43] ------------------------------------------------------------------- required time -1.268 arrival time 1.306 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.191ns (logic 0.101ns (52.880%) route 0.090ns (47.120%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.379ns Source Clock Delay (SCD): 1.130ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 1.012ns (routing 0.306ns, distribution 0.706ns) Clock Net Delay (Destination): 1.214ns (routing 0.352ns, distribution 0.862ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.012 1.130 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X87Y428 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X87Y428 FDCE (Prop_GFF2_SLICEM_C_Q) 0.048 1.178 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Q net (fo=2, routed) 0.075 1.253 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_5_in SLICE_X86Y428 LUT3 (Prop_B6LUT_SLICEL_I2_O) 0.053 1.306 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__13/O net (fo=1, routed) 0.015 1.321 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[1] SLICE_X86Y428 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.214 1.379 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X86Y428 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.155 1.224 SLICE_X86Y428 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.280 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.280 arrival time 1.321 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[14].rx_data_ngccm_reg[14][45]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.175ns (logic 0.048ns (27.429%) route 0.127ns (72.571%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.368ns Source Clock Delay (SCD): 1.138ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 1.020ns (routing 0.306ns, distribution 0.714ns) Clock Net Delay (Destination): 1.203ns (routing 0.352ns, distribution 0.851ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.138 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X86Y428 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X86Y428 FDRE (Prop_BFF2_SLICEL_C_Q) 0.048 1.186 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/Q net (fo=1, routed) 0.127 1.313 rx_data[14][45] SLICE_X88Y428 FDCE r SFP_GEN[14].rx_data_ngccm_reg[14][45]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.203 1.368 g_gbt_bank[1].gbtbank_n_44 SLICE_X88Y428 FDCE r SFP_GEN[14].rx_data_ngccm_reg[14][45]/C clock pessimism -0.155 1.213 SLICE_X88Y428 FDCE (Hold_AFF2_SLICEL_C_D) 0.056 1.269 SFP_GEN[14].rx_data_ngccm_reg[14][45] ------------------------------------------------------------------- required time -1.269 arrival time 1.313 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.103ns (66.883%) route 0.051ns (33.117%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.360ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.186ns Clock Net Delay (Source): 1.003ns (routing 0.306ns, distribution 0.697ns) Clock Net Delay (Destination): 1.195ns (routing 0.352ns, distribution 0.843ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.003 1.121 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X90Y429 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X90Y429 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.170 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Q net (fo=2, routed) 0.035 1.205 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_21_in SLICE_X90Y428 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.054 1.259 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__13/O net (fo=1, routed) 0.016 1.275 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[11] SLICE_X90Y428 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.195 1.360 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X90Y428 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C clock pessimism -0.186 1.174 SLICE_X90Y428 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.230 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11] ------------------------------------------------------------------- required time -1.230 arrival time 1.275 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: SFP_GEN[14].rx_data_ngccm_reg[14][56]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[14].ngCCM_gbt/RX_Word_rx40_reg[56]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.102ns (66.234%) route 0.052ns (33.766%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.120ns Clock Pessimism Removal (CPR): 0.186ns Clock Net Delay (Source): 1.002ns (routing 0.306ns, distribution 0.696ns) Clock Net Delay (Destination): 1.194ns (routing 0.352ns, distribution 0.842ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.002 1.120 g_gbt_bank[1].gbtbank_n_44 SLICE_X91Y429 FDCE r SFP_GEN[14].rx_data_ngccm_reg[14][56]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y429 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.169 r SFP_GEN[14].rx_data_ngccm_reg[14][56]/Q net (fo=1, routed) 0.036 1.205 g_gbt_bank[1].gbtbank/RX_Word_rx40_reg[78]_0[32] SLICE_X91Y428 LUT3 (Prop_D6LUT_SLICEL_I1_O) 0.053 1.258 r g_gbt_bank[1].gbtbank/RX_Word_rx40[56]_i_1__0/O net (fo=1, routed) 0.016 1.274 SFP_GEN[14].ngCCM_gbt/RX_Word_rx40_reg[83]_0[32] SLICE_X91Y428 FDCE r SFP_GEN[14].ngCCM_gbt/RX_Word_rx40_reg[56]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.194 1.359 SFP_GEN[14].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y428 FDCE r SFP_GEN[14].ngCCM_gbt/RX_Word_rx40_reg[56]/C clock pessimism -0.186 1.173 SLICE_X91Y428 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.229 SFP_GEN[14].ngCCM_gbt/RX_Word_rx40_reg[56] ------------------------------------------------------------------- required time -1.229 arrival time 1.274 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.094ns (64.384%) route 0.052ns (35.616%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.378ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.198ns Clock Net Delay (Source): 1.018ns (routing 0.306ns, distribution 0.712ns) Clock Net Delay (Destination): 1.213ns (routing 0.352ns, distribution 0.861ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.018 1.136 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X86Y429 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X86Y429 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.185 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/Q net (fo=2, routed) 0.036 1.221 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_9_in SLICE_X86Y429 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.045 1.266 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__13/O net (fo=1, routed) 0.016 1.282 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[5] SLICE_X86Y429 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.213 1.378 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X86Y429 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism -0.198 1.180 SLICE_X86Y429 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.236 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time -1.236 arrival time 1.282 ------------------------------------------------------------------- slack 0.046 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_16 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y187 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X88Y420 g_clock_rate_din[14].ngccm_status_cnt_reg[14][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X88Y420 g_clock_rate_din[14].ngccm_status_cnt_reg[14][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X88Y420 g_clock_rate_din[14].ngccm_status_cnt_reg[14][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X88Y420 g_clock_rate_din[14].ngccm_status_cnt_reg[14][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X88Y420 g_clock_rate_din[14].ngccm_status_cnt_reg[14][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X88Y420 g_clock_rate_din[14].ngccm_status_cnt_reg[14][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X88Y422 g_clock_rate_din[14].ngccm_status_cnt_reg[14][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X88Y420 g_clock_rate_din[14].ngccm_status_cnt_reg[14][0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X88Y420 g_clock_rate_din[14].ngccm_status_cnt_reg[14][0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X88Y420 g_clock_rate_din[14].ngccm_status_cnt_reg[14][1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X88Y420 g_clock_rate_din[14].ngccm_status_cnt_reg[14][1]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X88Y420 g_clock_rate_din[14].ngccm_status_cnt_reg[14][2]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X88Y420 g_clock_rate_din[14].ngccm_status_cnt_reg[14][2]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X94Y433 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X94Y433 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X94Y434 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X94Y434 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X94Y434 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X94Y434 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.037 0.493 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.037 1.291 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_17 To Clock: gtwiz_userclk_rx_srcclk_out[0]_17 Setup : 0 Failing Endpoints, Worst Slack 3.244ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.035ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.244ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[86]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 4.947ns (logic 0.955ns (19.305%) route 3.992ns (80.695%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.154ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.275ns = ( 10.592 - 8.317 ) Source Clock Delay (SCD): 2.645ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.170ns (routing 0.664ns, distribution 1.506ns) Clock Net Delay (Destination): 1.877ns (routing 0.602ns, distribution 1.275ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.170 2.645 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y432 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[86]/C ------------------------------------------------------------------- ------------------- SLICE_X105Y432 FDCE (Prop_BFF2_SLICEL_C_Q) 0.138 2.783 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[86]/Q net (fo=9, routed) 0.443 3.226 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/Q[35] SLICE_X104Y433 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.239 3.465 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/syndromes/i___105_i_34__14/O net (fo=1, routed) 0.436 3.901 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/syndromes/i___105_i_34__14_n_0 SLICE_X106Y432 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 4.145 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/syndromes/i___105_i_19__14/O net (fo=29, routed) 2.075 6.220 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/s3_from_syndromes[3] SLICE_X95Y422 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.090 6.310 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_i_2__30/O net (fo=1, routed) 1.003 7.313 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_i_2__30_n_0 SLICE_X100Y422 LUT6 (Prop_D6LUT_SLICEM_I0_O) 0.244 7.557 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__30/O net (fo=1, routed) 0.035 7.592 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg_3 SLICE_X100Y422 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.877 10.592 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/CLK SLICE_X100Y422 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C clock pessimism 0.216 10.809 clock uncertainty -0.035 10.773 SLICE_X100Y422 FDRE (Setup_DFF_SLICEM_C_D) 0.063 10.836 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg ------------------------------------------------------------------- required time 10.836 arrival time -7.592 ------------------------------------------------------------------- slack 3.244 Slack (MET) : 3.558ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 4.426ns (logic 1.569ns (35.450%) route 2.857ns (64.550%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.243ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.264ns = ( 10.581 - 8.317 ) Source Clock Delay (SCD): 2.722ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.247ns (routing 0.664ns, distribution 1.583ns) Clock Net Delay (Destination): 1.866ns (routing 0.602ns, distribution 1.264ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.247 2.722 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.808 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.275 6.083 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X109Y441 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.327 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/O net (fo=5, routed) 0.175 6.502 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y440 LUT4 (Prop_G6LUT_SLICEM_I2_O) 0.146 6.648 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__14/O net (fo=1, routed) 0.074 6.722 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__14_n_0 SLICE_X109Y440 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.093 6.815 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__14/O net (fo=2, routed) 0.333 7.148 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__14_n_0 SLICE_X109Y439 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.866 10.581 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y439 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.215 10.796 clock uncertainty -0.035 10.761 SLICE_X109Y439 FDCE (Setup_GFF_SLICEM_C_CE) -0.055 10.706 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.706 arrival time -7.148 ------------------------------------------------------------------- slack 3.558 Slack (MET) : 3.558ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 4.426ns (logic 1.569ns (35.450%) route 2.857ns (64.550%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.243ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.264ns = ( 10.581 - 8.317 ) Source Clock Delay (SCD): 2.722ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.247ns (routing 0.664ns, distribution 1.583ns) Clock Net Delay (Destination): 1.866ns (routing 0.602ns, distribution 1.264ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.247 2.722 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.808 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.275 6.083 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X109Y441 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.327 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/O net (fo=5, routed) 0.175 6.502 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y440 LUT4 (Prop_G6LUT_SLICEM_I2_O) 0.146 6.648 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__14/O net (fo=1, routed) 0.074 6.722 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__14_n_0 SLICE_X109Y440 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.093 6.815 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__14/O net (fo=2, routed) 0.333 7.148 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__14_n_0 SLICE_X109Y439 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.866 10.581 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y439 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.215 10.796 clock uncertainty -0.035 10.761 SLICE_X109Y439 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 10.706 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.706 arrival time -7.148 ------------------------------------------------------------------- slack 3.558 Slack (MET) : 3.642ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 4.328ns (logic 1.419ns (32.787%) route 2.909ns (67.214%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.254ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.253ns = ( 10.570 - 8.317 ) Source Clock Delay (SCD): 2.722ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.247ns (routing 0.664ns, distribution 1.583ns) Clock Net Delay (Destination): 1.855ns (routing 0.602ns, distribution 1.253ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.247 2.722 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.808 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.275 6.083 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X109Y441 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.327 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/O net (fo=5, routed) 0.182 6.509 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y440 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.089 6.598 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__15/O net (fo=7, routed) 0.452 7.050 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 SLICE_X109Y442 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.855 10.570 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y442 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.215 10.785 clock uncertainty -0.035 10.750 SLICE_X109Y442 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 10.692 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 10.692 arrival time -7.050 ------------------------------------------------------------------- slack 3.642 Slack (MET) : 3.648ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 4.325ns (logic 1.419ns (32.809%) route 2.906ns (67.191%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.254ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.253ns = ( 10.570 - 8.317 ) Source Clock Delay (SCD): 2.722ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.247ns (routing 0.664ns, distribution 1.583ns) Clock Net Delay (Destination): 1.855ns (routing 0.602ns, distribution 1.253ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.247 2.722 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.808 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.275 6.083 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X109Y441 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.327 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/O net (fo=5, routed) 0.182 6.509 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y440 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.089 6.598 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__15/O net (fo=7, routed) 0.449 7.047 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 SLICE_X109Y442 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.855 10.570 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y442 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.215 10.785 clock uncertainty -0.035 10.750 SLICE_X109Y442 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 10.695 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 10.695 arrival time -7.047 ------------------------------------------------------------------- slack 3.648 Slack (MET) : 3.658ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 4.321ns (logic 1.419ns (32.840%) route 2.902ns (67.160%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.245ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.262ns = ( 10.579 - 8.317 ) Source Clock Delay (SCD): 2.722ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.247ns (routing 0.664ns, distribution 1.583ns) Clock Net Delay (Destination): 1.864ns (routing 0.602ns, distribution 1.262ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.247 2.722 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.808 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.275 6.083 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X109Y441 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.327 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/O net (fo=5, routed) 0.182 6.509 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y440 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.089 6.598 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__15/O net (fo=7, routed) 0.445 7.043 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 SLICE_X109Y441 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.864 10.579 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y441 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.215 10.794 clock uncertainty -0.035 10.759 SLICE_X109Y441 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 10.701 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 10.701 arrival time -7.043 ------------------------------------------------------------------- slack 3.658 Slack (MET) : 3.664ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 4.318ns (logic 1.419ns (32.862%) route 2.899ns (67.138%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.245ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.262ns = ( 10.579 - 8.317 ) Source Clock Delay (SCD): 2.722ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.247ns (routing 0.664ns, distribution 1.583ns) Clock Net Delay (Destination): 1.864ns (routing 0.602ns, distribution 1.262ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.247 2.722 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.808 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.275 6.083 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X109Y441 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.327 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/O net (fo=5, routed) 0.182 6.509 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y440 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.089 6.598 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__15/O net (fo=7, routed) 0.442 7.040 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 SLICE_X109Y441 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.864 10.579 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y441 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.215 10.794 clock uncertainty -0.035 10.759 SLICE_X109Y441 FDRE (Setup_EFF_SLICEM_C_CE) -0.055 10.704 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 10.704 arrival time -7.040 ------------------------------------------------------------------- slack 3.664 Slack (MET) : 3.664ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 4.318ns (logic 1.419ns (32.862%) route 2.899ns (67.138%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.245ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.262ns = ( 10.579 - 8.317 ) Source Clock Delay (SCD): 2.722ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.247ns (routing 0.664ns, distribution 1.583ns) Clock Net Delay (Destination): 1.864ns (routing 0.602ns, distribution 1.262ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.247 2.722 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.808 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.275 6.083 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X109Y441 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.327 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/O net (fo=5, routed) 0.182 6.509 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y440 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.089 6.598 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__15/O net (fo=7, routed) 0.442 7.040 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 SLICE_X109Y441 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.864 10.579 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y441 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.215 10.794 clock uncertainty -0.035 10.759 SLICE_X109Y441 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 10.704 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 10.704 arrival time -7.040 ------------------------------------------------------------------- slack 3.664 Slack (MET) : 3.678ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 4.299ns (logic 1.419ns (33.008%) route 2.880ns (66.992%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.250ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.257ns = ( 10.574 - 8.317 ) Source Clock Delay (SCD): 2.722ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.247ns (routing 0.664ns, distribution 1.583ns) Clock Net Delay (Destination): 1.859ns (routing 0.602ns, distribution 1.257ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.247 2.722 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.808 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.275 6.083 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X109Y441 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.327 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/O net (fo=5, routed) 0.182 6.509 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y440 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.089 6.598 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__15/O net (fo=7, routed) 0.423 7.021 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 SLICE_X109Y438 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.859 10.574 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y438 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.215 10.789 clock uncertainty -0.035 10.754 SLICE_X109Y438 FDRE (Setup_EFF_SLICEM_C_CE) -0.055 10.699 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 10.699 arrival time -7.021 ------------------------------------------------------------------- slack 3.678 Slack (MET) : 3.686ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 4.299ns (logic 1.419ns (33.008%) route 2.880ns (66.992%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.243ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.264ns = ( 10.581 - 8.317 ) Source Clock Delay (SCD): 2.722ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.247ns (routing 0.664ns, distribution 1.583ns) Clock Net Delay (Destination): 1.866ns (routing 0.602ns, distribution 1.264ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.247 2.722 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.808 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.275 6.083 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X109Y441 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.327 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/O net (fo=5, routed) 0.182 6.509 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y440 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.089 6.598 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__15/O net (fo=7, routed) 0.423 7.021 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 SLICE_X109Y441 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.866 10.581 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y441 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.215 10.796 clock uncertainty -0.035 10.761 SLICE_X109Y441 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 10.707 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 10.707 arrival time -7.021 ------------------------------------------------------------------- slack 3.686 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.035ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[15].rx_data_ngccm_reg[15][72]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.169ns (logic 0.048ns (28.402%) route 0.121ns (71.598%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.138ns Source Clock Delay (SCD): 0.928ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.810ns (routing 0.301ns, distribution 0.509ns) Clock Net Delay (Destination): 0.973ns (routing 0.342ns, distribution 0.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.810 0.928 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X112Y423 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y423 FDRE (Prop_BFF2_SLICEM_C_Q) 0.048 0.976 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/Q net (fo=1, routed) 0.121 1.097 rx_data[15][72] SLICE_X113Y423 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][72]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.973 1.138 g_gbt_bank[1].gbtbank_n_54 SLICE_X113Y423 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][72]/C clock pessimism -0.132 1.006 SLICE_X113Y423 FDCE (Hold_CFF2_SLICEM_C_D) 0.056 1.062 SFP_GEN[15].rx_data_ngccm_reg[15][72] ------------------------------------------------------------------- required time -1.062 arrival time 1.097 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.037ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.166ns (logic 0.078ns (46.988%) route 0.088ns (53.012%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.133ns Source Clock Delay (SCD): 0.928ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.810ns (routing 0.301ns, distribution 0.509ns) Clock Net Delay (Destination): 0.968ns (routing 0.342ns, distribution 0.626ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.810 0.928 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X106Y427 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y427 FDCE (Prop_BFF2_SLICEM_C_Q) 0.048 0.976 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Q net (fo=2, routed) 0.072 1.048 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_11_in SLICE_X105Y427 LUT3 (Prop_C6LUT_SLICEL_I2_O) 0.030 1.078 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__14/O net (fo=1, routed) 0.016 1.094 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[4] SLICE_X105Y427 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.968 1.133 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X105Y427 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.132 1.001 SLICE_X105Y427 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.057 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.057 arrival time 1.094 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.038ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[15].rx_data_ngccm_reg[15][31]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.141ns (logic 0.048ns (34.043%) route 0.093ns (65.957%)) Logic Levels: 0 Clock Path Skew: 0.047ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.138ns Source Clock Delay (SCD): 0.927ns Clock Pessimism Removal (CPR): 0.164ns Clock Net Delay (Source): 0.809ns (routing 0.301ns, distribution 0.508ns) Clock Net Delay (Destination): 0.973ns (routing 0.342ns, distribution 0.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.809 0.927 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X105Y425 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X105Y425 FDRE (Prop_HFF_SLICEL_C_Q) 0.048 0.975 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/Q net (fo=1, routed) 0.093 1.068 rx_data[15][31] SLICE_X105Y424 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][31]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.973 1.138 g_gbt_bank[1].gbtbank_n_54 SLICE_X105Y424 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][31]/C clock pessimism -0.164 0.974 SLICE_X105Y424 FDCE (Hold_HFF2_SLICEL_C_D) 0.056 1.030 SFP_GEN[15].rx_data_ngccm_reg[15][31] ------------------------------------------------------------------- required time -1.030 arrival time 1.068 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[15].rx_data_ngccm_reg[15][27]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.048ns (33.803%) route 0.094ns (66.197%)) Logic Levels: 0 Clock Path Skew: 0.047ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.138ns Source Clock Delay (SCD): 0.927ns Clock Pessimism Removal (CPR): 0.164ns Clock Net Delay (Source): 0.809ns (routing 0.301ns, distribution 0.508ns) Clock Net Delay (Destination): 0.973ns (routing 0.342ns, distribution 0.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.809 0.927 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X105Y425 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X105Y425 FDRE (Prop_GFF2_SLICEL_C_Q) 0.048 0.975 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/Q net (fo=1, routed) 0.094 1.069 rx_data[15][27] SLICE_X105Y424 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][27]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.973 1.138 g_gbt_bank[1].gbtbank_n_54 SLICE_X105Y424 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][27]/C clock pessimism -0.164 0.974 SLICE_X105Y424 FDCE (Hold_GFF_SLICEL_C_D) 0.056 1.030 SFP_GEN[15].rx_data_ngccm_reg[15][27] ------------------------------------------------------------------- required time -1.030 arrival time 1.069 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.169ns (logic 0.086ns (50.888%) route 0.083ns (49.112%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.133ns Source Clock Delay (SCD): 0.928ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.810ns (routing 0.301ns, distribution 0.509ns) Clock Net Delay (Destination): 0.968ns (routing 0.342ns, distribution 0.626ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.810 0.928 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X106Y427 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y427 FDCE (Prop_BFF2_SLICEM_C_Q) 0.048 0.976 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Q net (fo=2, routed) 0.072 1.048 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_11_in SLICE_X105Y427 LUT3 (Prop_C5LUT_SLICEL_I0_O) 0.038 1.086 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__14/O net (fo=1, routed) 0.011 1.097 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[6] SLICE_X105Y427 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.968 1.133 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X105Y427 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C clock pessimism -0.132 1.001 SLICE_X105Y427 FDRE (Hold_CFF2_SLICEL_C_D) 0.056 1.057 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6] ------------------------------------------------------------------- required time -1.057 arrival time 1.097 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[39]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[39]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.164ns (logic 0.049ns (29.878%) route 0.115ns (70.122%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.137ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.822ns (routing 0.301ns, distribution 0.521ns) Clock Net Delay (Destination): 0.972ns (routing 0.342ns, distribution 0.630ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.822 0.940 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y430 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[39]/C ------------------------------------------------------------------- ------------------- SLICE_X107Y430 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 0.989 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[39]/Q net (fo=1, routed) 0.115 1.104 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[39] SLICE_X106Y430 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[39]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.137 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y430 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[39]/C clock pessimism -0.132 1.005 SLICE_X106Y430 FDCE (Hold_GFF2_SLICEM_C_D) 0.056 1.061 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[39] ------------------------------------------------------------------- required time -1.061 arrival time 1.104 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[25]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[25]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.049ns (31.613%) route 0.106ns (68.387%)) Logic Levels: 0 Clock Path Skew: 0.055ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.126ns Source Clock Delay (SCD): 0.939ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.821ns (routing 0.301ns, distribution 0.520ns) Clock Net Delay (Destination): 0.961ns (routing 0.342ns, distribution 0.619ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.821 0.939 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y430 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[25]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y430 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 0.988 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[25]/Q net (fo=1, routed) 0.106 1.094 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[25] SLICE_X109Y430 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.961 1.126 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y430 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[25]/C clock pessimism -0.132 0.994 SLICE_X109Y430 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.049 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[25] ------------------------------------------------------------------- required time -1.049 arrival time 1.094 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.103ns (66.883%) route 0.051ns (33.117%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.146ns Source Clock Delay (SCD): 0.931ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 0.813ns (routing 0.301ns, distribution 0.512ns) Clock Net Delay (Destination): 0.981ns (routing 0.342ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.813 0.931 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X113Y426 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y426 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 0.980 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[10]/Q net (fo=2, routed) 0.035 1.015 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_19_in SLICE_X113Y425 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.054 1.069 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__14/O net (fo=1, routed) 0.016 1.085 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[10] SLICE_X113Y425 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.981 1.146 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X113Y425 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C clock pessimism -0.163 0.983 SLICE_X113Y425 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.039 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10] ------------------------------------------------------------------- required time -1.039 arrival time 1.085 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[15].rx_data_ngccm_reg[15][51]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.192ns (logic 0.049ns (25.521%) route 0.143ns (74.479%)) Logic Levels: 0 Clock Path Skew: 0.090ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.150ns Source Clock Delay (SCD): 0.928ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.810ns (routing 0.301ns, distribution 0.509ns) Clock Net Delay (Destination): 0.985ns (routing 0.342ns, distribution 0.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.810 0.928 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X112Y424 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y424 FDRE (Prop_DFF2_SLICEM_C_Q) 0.049 0.977 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/Q net (fo=1, routed) 0.143 1.120 rx_data[15][51] SLICE_X111Y423 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][51]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.985 1.150 g_gbt_bank[1].gbtbank_n_54 SLICE_X111Y423 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][51]/C clock pessimism -0.132 1.018 SLICE_X111Y423 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.074 SFP_GEN[15].rx_data_ngccm_reg[15][51] ------------------------------------------------------------------- required time -1.074 arrival time 1.120 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: SFP_GEN[15].ngCCM_gbt/RX_Word_rx40_reg[30]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[15].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.183ns (logic 0.049ns (26.776%) route 0.134ns (73.224%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.142ns Source Clock Delay (SCD): 0.930ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.812ns (routing 0.301ns, distribution 0.511ns) Clock Net Delay (Destination): 0.977ns (routing 0.342ns, distribution 0.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.812 0.930 SFP_GEN[15].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X104Y422 FDCE r SFP_GEN[15].ngCCM_gbt/RX_Word_rx40_reg[30]/C ------------------------------------------------------------------- ------------------- SLICE_X104Y422 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 0.979 r SFP_GEN[15].ngCCM_gbt/RX_Word_rx40_reg[30]/Q net (fo=2, routed) 0.134 1.113 SFP_GEN[15].ngCCM_gbt/gbt_rx_checker/Q[14] SLICE_X105Y422 FDRE r SFP_GEN[15].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.977 1.142 SFP_GEN[15].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y422 FDRE r SFP_GEN[15].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/C clock pessimism -0.132 1.010 SLICE_X105Y422 FDRE (Hold_AFF2_SLICEL_C_D) 0.056 1.066 SFP_GEN[15].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14] ------------------------------------------------------------------- required time -1.066 arrival time 1.113 ------------------------------------------------------------------- slack 0.047 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_17 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y184 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X94Y421 g_clock_rate_din[15].ngccm_status_cnt_reg[15][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X94Y421 g_clock_rate_din[15].ngccm_status_cnt_reg[15][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X93Y421 g_clock_rate_din[15].ngccm_status_cnt_reg[15][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X93Y421 g_clock_rate_din[15].ngccm_status_cnt_reg[15][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X93Y421 g_clock_rate_din[15].ngccm_status_cnt_reg[15][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X93Y421 g_clock_rate_din[15].ngccm_status_cnt_reg[15][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X94Y421 g_clock_rate_din[15].ngccm_status_cnt_reg[15][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X91Y421 g_clock_rate_din[15].rx_wordclk_div2_reg[15]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X107Y433 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X107Y433 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X107Y433 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X107Y433 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X107Y433 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X108Y433 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X108Y432 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X108Y432 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X101Y433 g_gbt_bank[1].gbtbank/i_gbt_bank/g_rx_data_good[3].rx_data_good_cntr_reg[3][0]/C High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X101Y433 g_gbt_bank[1].gbtbank/i_gbt_bank/g_rx_data_good[3].rx_data_good_cntr_reg[3][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X101Y433 g_gbt_bank[1].gbtbank/i_gbt_bank/g_rx_data_good[3].rx_data_good_cntr_reg[3][1]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_18 To Clock: gtwiz_userclk_rx_srcclk_out[0]_18 Setup : 0 Failing Endpoints, Worst Slack 3.176ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.030ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.493ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.176ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 5.208ns (logic 1.716ns (32.949%) route 3.492ns (67.051%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.157ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.584ns = ( 10.901 - 8.317 ) Source Clock Delay (SCD): 2.647ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.172ns (routing 0.633ns, distribution 1.539ns) Clock Net Delay (Destination): 2.186ns (routing 0.572ns, distribution 1.614ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.172 2.647 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.751 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.562 6.313 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X94Y489 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.223 6.536 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/O net (fo=5, routed) 0.276 6.812 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X95Y491 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.146 6.958 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__15/O net (fo=1, routed) 0.179 7.137 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__15_n_0 SLICE_X95Y490 LUT6 (Prop_B6LUT_SLICEM_I5_O) 0.243 7.380 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__15/O net (fo=2, routed) 0.475 7.855 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__15_n_0 SLICE_X95Y489 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.186 10.901 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X95Y489 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.220 11.122 clock uncertainty -0.035 11.086 SLICE_X95Y489 FDCE (Setup_GFF_SLICEM_C_CE) -0.055 11.031 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.031 arrival time -7.855 ------------------------------------------------------------------- slack 3.176 Slack (MET) : 3.176ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 5.208ns (logic 1.716ns (32.949%) route 3.492ns (67.051%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.157ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.584ns = ( 10.901 - 8.317 ) Source Clock Delay (SCD): 2.647ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.172ns (routing 0.633ns, distribution 1.539ns) Clock Net Delay (Destination): 2.186ns (routing 0.572ns, distribution 1.614ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.172 2.647 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.751 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.562 6.313 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X94Y489 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.223 6.536 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/O net (fo=5, routed) 0.276 6.812 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X95Y491 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.146 6.958 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__15/O net (fo=1, routed) 0.179 7.137 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__15_n_0 SLICE_X95Y490 LUT6 (Prop_B6LUT_SLICEM_I5_O) 0.243 7.380 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__15/O net (fo=2, routed) 0.475 7.855 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__15_n_0 SLICE_X95Y489 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.186 10.901 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X95Y489 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.220 11.122 clock uncertainty -0.035 11.086 SLICE_X95Y489 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 11.031 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.031 arrival time -7.855 ------------------------------------------------------------------- slack 3.176 Slack (MET) : 3.451ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 4.927ns (logic 1.473ns (29.896%) route 3.454ns (70.104%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.151ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.578ns = ( 10.895 - 8.317 ) Source Clock Delay (SCD): 2.647ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.172ns (routing 0.633ns, distribution 1.539ns) Clock Net Delay (Destination): 2.180ns (routing 0.572ns, distribution 1.608ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.172 2.647 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.751 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.562 6.313 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X94Y489 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.223 6.536 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/O net (fo=5, routed) 0.363 6.899 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X95Y490 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.146 7.045 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__16/O net (fo=7, routed) 0.529 7.574 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X95Y490 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.180 10.895 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X95Y490 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.220 11.116 clock uncertainty -0.035 11.080 SLICE_X95Y490 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 11.025 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.025 arrival time -7.574 ------------------------------------------------------------------- slack 3.451 Slack (MET) : 3.455ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 4.924ns (logic 1.473ns (29.915%) route 3.451ns (70.085%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.151ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.578ns = ( 10.895 - 8.317 ) Source Clock Delay (SCD): 2.647ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.172ns (routing 0.633ns, distribution 1.539ns) Clock Net Delay (Destination): 2.180ns (routing 0.572ns, distribution 1.608ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.172 2.647 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.751 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.562 6.313 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X94Y489 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.223 6.536 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/O net (fo=5, routed) 0.363 6.899 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X95Y490 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.146 7.045 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__16/O net (fo=7, routed) 0.526 7.571 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X95Y490 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.180 10.895 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X95Y490 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.220 11.116 clock uncertainty -0.035 11.080 SLICE_X95Y490 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 11.026 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 11.026 arrival time -7.571 ------------------------------------------------------------------- slack 3.455 Slack (MET) : 3.455ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 4.924ns (logic 1.473ns (29.915%) route 3.451ns (70.085%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.151ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.578ns = ( 10.895 - 8.317 ) Source Clock Delay (SCD): 2.647ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.172ns (routing 0.633ns, distribution 1.539ns) Clock Net Delay (Destination): 2.180ns (routing 0.572ns, distribution 1.608ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.172 2.647 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.751 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.562 6.313 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X94Y489 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.223 6.536 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/O net (fo=5, routed) 0.363 6.899 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X95Y490 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.146 7.045 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__16/O net (fo=7, routed) 0.526 7.571 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X95Y490 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.180 10.895 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X95Y490 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.220 11.116 clock uncertainty -0.035 11.080 SLICE_X95Y490 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 11.026 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 11.026 arrival time -7.571 ------------------------------------------------------------------- slack 3.455 Slack (MET) : 3.623ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 4.757ns (logic 1.473ns (30.965%) route 3.284ns (69.035%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.156ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.583ns = ( 10.900 - 8.317 ) Source Clock Delay (SCD): 2.647ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.172ns (routing 0.633ns, distribution 1.539ns) Clock Net Delay (Destination): 2.185ns (routing 0.572ns, distribution 1.613ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.172 2.647 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.751 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.562 6.313 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X94Y489 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.223 6.536 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/O net (fo=5, routed) 0.363 6.899 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X95Y490 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.146 7.045 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__16/O net (fo=7, routed) 0.359 7.404 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X95Y491 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.185 10.900 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X95Y491 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.220 11.121 clock uncertainty -0.035 11.085 SLICE_X95Y491 FDRE (Setup_EFF2_SLICEM_C_CE) -0.058 11.027 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 11.027 arrival time -7.404 ------------------------------------------------------------------- slack 3.623 Slack (MET) : 3.623ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 4.757ns (logic 1.473ns (30.965%) route 3.284ns (69.035%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.156ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.583ns = ( 10.900 - 8.317 ) Source Clock Delay (SCD): 2.647ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.172ns (routing 0.633ns, distribution 1.539ns) Clock Net Delay (Destination): 2.185ns (routing 0.572ns, distribution 1.613ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.172 2.647 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.751 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.562 6.313 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X94Y489 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.223 6.536 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/O net (fo=5, routed) 0.363 6.899 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X95Y490 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.146 7.045 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__16/O net (fo=7, routed) 0.359 7.404 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X95Y491 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.185 10.900 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X95Y491 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.220 11.121 clock uncertainty -0.035 11.085 SLICE_X95Y491 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 11.027 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.027 arrival time -7.404 ------------------------------------------------------------------- slack 3.623 Slack (MET) : 3.629ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 4.754ns (logic 1.473ns (30.984%) route 3.281ns (69.016%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.156ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.583ns = ( 10.900 - 8.317 ) Source Clock Delay (SCD): 2.647ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.172ns (routing 0.633ns, distribution 1.539ns) Clock Net Delay (Destination): 2.185ns (routing 0.572ns, distribution 1.613ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.172 2.647 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.751 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.562 6.313 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X94Y489 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.223 6.536 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/O net (fo=5, routed) 0.363 6.899 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X95Y490 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.146 7.045 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__16/O net (fo=7, routed) 0.356 7.401 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X95Y491 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.185 10.900 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X95Y491 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.220 11.121 clock uncertainty -0.035 11.085 SLICE_X95Y491 FDRE (Setup_EFF_SLICEM_C_CE) -0.055 11.030 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 11.030 arrival time -7.401 ------------------------------------------------------------------- slack 3.629 Slack (MET) : 3.629ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 4.754ns (logic 1.473ns (30.984%) route 3.281ns (69.016%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.156ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.583ns = ( 10.900 - 8.317 ) Source Clock Delay (SCD): 2.647ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.172ns (routing 0.633ns, distribution 1.539ns) Clock Net Delay (Destination): 2.185ns (routing 0.572ns, distribution 1.613ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.172 2.647 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.751 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.562 6.313 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X94Y489 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.223 6.536 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/O net (fo=5, routed) 0.363 6.899 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X95Y490 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.146 7.045 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__16/O net (fo=7, routed) 0.356 7.401 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X95Y491 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.185 10.900 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X95Y491 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.220 11.121 clock uncertainty -0.035 11.085 SLICE_X95Y491 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 11.030 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.030 arrival time -7.401 ------------------------------------------------------------------- slack 3.629 Slack (MET) : 3.765ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 4.614ns (logic 1.473ns (31.925%) route 3.141ns (68.075%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.155ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.582ns = ( 10.899 - 8.317 ) Source Clock Delay (SCD): 2.647ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.172ns (routing 0.633ns, distribution 1.539ns) Clock Net Delay (Destination): 2.184ns (routing 0.572ns, distribution 1.612ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.172 2.647 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.751 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.562 6.313 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X94Y489 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.223 6.536 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/O net (fo=5, routed) 0.277 6.813 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X95Y491 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.146 6.959 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__16/O net (fo=5, routed) 0.302 7.261 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 SLICE_X94Y491 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.184 10.899 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y491 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.220 11.120 clock uncertainty -0.035 11.084 SLICE_X94Y491 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 11.026 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.026 arrival time -7.261 ------------------------------------------------------------------- slack 3.765 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.030ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.151ns (logic 0.064ns (42.384%) route 0.087ns (57.616%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.313ns Source Clock Delay (SCD): 1.099ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 0.981ns (routing 0.275ns, distribution 0.706ns) Clock Net Delay (Destination): 1.148ns (routing 0.314ns, distribution 0.834ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.981 1.099 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X88Y482 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y482 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.148 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.075 1.223 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/O84[1] SLICE_X89Y482 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.015 1.238 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__15/O net (fo=1, routed) 0.012 1.250 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[1] SLICE_X89Y482 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.148 1.313 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X89Y482 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C clock pessimism -0.149 1.164 SLICE_X89Y482 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.220 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20] ------------------------------------------------------------------- required time -1.220 arrival time 1.250 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.033ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[16].rx_data_ngccm_reg[16][78]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.175ns (logic 0.048ns (27.429%) route 0.127ns (72.571%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.334ns Source Clock Delay (SCD): 1.099ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 0.981ns (routing 0.275ns, distribution 0.706ns) Clock Net Delay (Destination): 1.169ns (routing 0.314ns, distribution 0.855ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.981 1.099 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X87Y482 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X87Y482 FDRE (Prop_GFF2_SLICEM_C_Q) 0.048 1.147 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/Q net (fo=1, routed) 0.127 1.274 rx_data[16][78] SLICE_X86Y482 FDCE r SFP_GEN[16].rx_data_ngccm_reg[16][78]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.169 1.334 g_gbt_bank[1].gbtbank_n_64 SLICE_X86Y482 FDCE r SFP_GEN[16].rx_data_ngccm_reg[16][78]/C clock pessimism -0.148 1.186 SLICE_X86Y482 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 1.242 SFP_GEN[16].rx_data_ngccm_reg[16][78] ------------------------------------------------------------------- required time -1.242 arrival time 1.274 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.038ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[16].rx_data_ngccm_reg[16][39]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.162ns (logic 0.048ns (29.630%) route 0.114ns (70.370%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.318ns Source Clock Delay (SCD): 1.101ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 0.983ns (routing 0.275ns, distribution 0.708ns) Clock Net Delay (Destination): 1.153ns (routing 0.314ns, distribution 0.839ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.983 1.101 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X84Y486 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y486 FDRE (Prop_GFF2_SLICEL_C_Q) 0.048 1.149 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/Q net (fo=1, routed) 0.114 1.263 rx_data[16][39] SLICE_X85Y486 FDCE r SFP_GEN[16].rx_data_ngccm_reg[16][39]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.153 1.318 g_gbt_bank[1].gbtbank_n_64 SLICE_X85Y486 FDCE r SFP_GEN[16].rx_data_ngccm_reg[16][39]/C clock pessimism -0.149 1.169 SLICE_X85Y486 FDCE (Hold_BFF2_SLICEM_C_D) 0.056 1.225 SFP_GEN[16].rx_data_ngccm_reg[16][39] ------------------------------------------------------------------- required time -1.225 arrival time 1.263 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.038ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[32]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.163ns (logic 0.063ns (38.650%) route 0.100ns (61.350%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.312ns Source Clock Delay (SCD): 1.094ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 0.976ns (routing 0.275ns, distribution 0.701ns) Clock Net Delay (Destination): 1.147ns (routing 0.314ns, distribution 0.833ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.976 1.094 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y487 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y487 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.142 f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Q net (fo=27, routed) 0.084 1.226 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] SLICE_X89Y487 LUT5 (Prop_C6LUT_SLICEM_I1_O) 0.015 1.241 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[32]_i_1__21/O net (fo=1, routed) 0.016 1.257 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg00[32] SLICE_X89Y487 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[32]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.147 1.312 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y487 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[32]/C clock pessimism -0.149 1.163 SLICE_X89Y487 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.219 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[32] ------------------------------------------------------------------- required time -1.219 arrival time 1.257 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[16].rx_data_ngccm_reg[16][37]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.164ns (logic 0.048ns (29.268%) route 0.116ns (70.732%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.318ns Source Clock Delay (SCD): 1.101ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 0.983ns (routing 0.275ns, distribution 0.708ns) Clock Net Delay (Destination): 1.153ns (routing 0.314ns, distribution 0.839ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.983 1.101 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X84Y486 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y486 FDRE (Prop_GFF_SLICEL_C_Q) 0.048 1.149 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/Q net (fo=1, routed) 0.116 1.265 rx_data[16][37] SLICE_X85Y486 FDCE r SFP_GEN[16].rx_data_ngccm_reg[16][37]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.153 1.318 g_gbt_bank[1].gbtbank_n_64 SLICE_X85Y486 FDCE r SFP_GEN[16].rx_data_ngccm_reg[16][37]/C clock pessimism -0.149 1.169 SLICE_X85Y486 FDCE (Hold_AFF2_SLICEM_C_D) 0.056 1.225 SFP_GEN[16].rx_data_ngccm_reg[16][37] ------------------------------------------------------------------- required time -1.225 arrival time 1.265 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.158ns (logic 0.112ns (70.886%) route 0.046ns (29.114%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.062ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.324ns Source Clock Delay (SCD): 1.083ns Clock Pessimism Removal (CPR): 0.179ns Clock Net Delay (Source): 0.965ns (routing 0.275ns, distribution 0.690ns) Clock Net Delay (Destination): 1.159ns (routing 0.314ns, distribution 0.845ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.965 1.083 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X90Y483 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X90Y483 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.132 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.035 1.167 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in SLICE_X90Y482 LUT3 (Prop_C5LUT_SLICEM_I2_O) 0.063 1.230 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__15/O net (fo=1, routed) 0.011 1.241 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[15] SLICE_X90Y482 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.159 1.324 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X90Y482 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C clock pessimism -0.179 1.145 SLICE_X90Y482 FDRE (Hold_CFF2_SLICEM_C_D) 0.056 1.201 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15] ------------------------------------------------------------------- required time -1.201 arrival time 1.241 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.181ns (logic 0.094ns (51.934%) route 0.087ns (48.066%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.332ns Source Clock Delay (SCD): 1.099ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 0.981ns (routing 0.275ns, distribution 0.706ns) Clock Net Delay (Destination): 1.167ns (routing 0.314ns, distribution 0.853ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.981 1.099 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X86Y482 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X86Y482 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.148 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.071 1.219 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_35_in SLICE_X87Y482 LUT3 (Prop_C6LUT_SLICEM_I2_O) 0.045 1.264 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__15/O net (fo=1, routed) 0.016 1.280 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] SLICE_X87Y482 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.167 1.332 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X87Y482 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.149 1.183 SLICE_X87Y482 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.239 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.239 arrival time 1.280 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[16].rx_data_ngccm_reg[16][64]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.049ns (33.562%) route 0.097ns (66.438%)) Logic Levels: 0 Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.328ns Source Clock Delay (SCD): 1.100ns Clock Pessimism Removal (CPR): 0.178ns Clock Net Delay (Source): 0.982ns (routing 0.275ns, distribution 0.707ns) Clock Net Delay (Destination): 1.163ns (routing 0.314ns, distribution 0.849ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.982 1.100 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X88Y480 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y480 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.149 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/Q net (fo=1, routed) 0.097 1.246 rx_data[16][64] SLICE_X88Y482 FDCE r SFP_GEN[16].rx_data_ngccm_reg[16][64]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.163 1.328 g_gbt_bank[1].gbtbank_n_64 SLICE_X88Y482 FDCE r SFP_GEN[16].rx_data_ngccm_reg[16][64]/C clock pessimism -0.178 1.150 SLICE_X88Y482 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.205 SFP_GEN[16].rx_data_ngccm_reg[16][64] ------------------------------------------------------------------- required time -1.205 arrival time 1.246 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[27]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.167ns (logic 0.064ns (38.323%) route 0.103ns (61.677%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.312ns Source Clock Delay (SCD): 1.094ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 0.976ns (routing 0.275ns, distribution 0.701ns) Clock Net Delay (Destination): 1.147ns (routing 0.314ns, distribution 0.833ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.976 1.094 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y487 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y487 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.142 f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Q net (fo=27, routed) 0.087 1.229 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] SLICE_X89Y487 LUT5 (Prop_D6LUT_SLICEM_I1_O) 0.016 1.245 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[27]_i_1__21/O net (fo=1, routed) 0.016 1.261 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg00[27] SLICE_X89Y487 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[27]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.147 1.312 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y487 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[27]/C clock pessimism -0.149 1.163 SLICE_X89Y487 FDCE (Hold_DFF_SLICEM_C_D) 0.056 1.219 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[27] ------------------------------------------------------------------- required time -1.219 arrival time 1.261 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[16].rx_data_ngccm_reg[16][35]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.165ns (logic 0.048ns (29.091%) route 0.117ns (70.909%)) Logic Levels: 0 Clock Path Skew: 0.066ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.316ns Source Clock Delay (SCD): 1.101ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 0.983ns (routing 0.275ns, distribution 0.708ns) Clock Net Delay (Destination): 1.151ns (routing 0.314ns, distribution 0.837ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.983 1.101 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X84Y486 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y486 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 1.149 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/Q net (fo=1, routed) 0.117 1.266 rx_data[16][35] SLICE_X85Y486 FDCE r SFP_GEN[16].rx_data_ngccm_reg[16][35]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.151 1.316 g_gbt_bank[1].gbtbank_n_64 SLICE_X85Y486 FDCE r SFP_GEN[16].rx_data_ngccm_reg[16][35]/C clock pessimism -0.149 1.167 SLICE_X85Y486 FDCE (Hold_FFF2_SLICEM_C_D) 0.055 1.222 SFP_GEN[16].rx_data_ngccm_reg[16][35] ------------------------------------------------------------------- required time -1.222 arrival time 1.266 ------------------------------------------------------------------- slack 0.044 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_18 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y211 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X79Y482 g_clock_rate_din[16].ngccm_status_cnt_reg[16][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X79Y482 g_clock_rate_din[16].ngccm_status_cnt_reg[16][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y481 g_clock_rate_din[16].ngccm_status_cnt_reg[16][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y481 g_clock_rate_din[16].ngccm_status_cnt_reg[16][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y481 g_clock_rate_din[16].ngccm_status_cnt_reg[16][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y481 g_clock_rate_din[16].ngccm_status_cnt_reg[16][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X84Y480 g_clock_rate_din[16].ngccm_status_cnt_reg[16][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X79Y482 g_clock_rate_din[16].ngccm_status_cnt_reg[16][0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X79Y482 g_clock_rate_din[16].ngccm_status_cnt_reg[16][1]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X87Y480 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X87Y480 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X87Y481 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X87Y480 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y481 g_clock_rate_din[16].ngccm_status_cnt_reg[16][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y481 g_clock_rate_din[16].ngccm_status_cnt_reg[16][3]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y481 g_clock_rate_din[16].ngccm_status_cnt_reg[16][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y481 g_clock_rate_din[16].ngccm_status_cnt_reg[16][5]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y481 g_clock_rate_din[16].ngccm_status_cnt_reg[16][7]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X88Y484 g_clock_rate_din[16].rx_frameclk_div2_reg[16]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.037 0.493 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.037 1.292 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_19 To Clock: gtwiz_userclk_rx_srcclk_out[0]_19 Setup : 0 Failing Endpoints, Worst Slack 3.185ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.039ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.185ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 4.862ns (logic 1.698ns (34.924%) route 3.164ns (65.076%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.181ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.242ns = ( 10.559 - 8.317 ) Source Clock Delay (SCD): 2.635ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.160ns (routing 0.630ns, distribution 1.530ns) Clock Net Delay (Destination): 1.844ns (routing 0.571ns, distribution 1.273ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.160 2.635 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.719 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.254 5.973 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X109Y491 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.224 6.197 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/O net (fo=5, routed) 0.222 6.419 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X107Y491 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.244 6.663 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__16/O net (fo=1, routed) 0.178 6.841 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__16_n_0 SLICE_X109Y491 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 6.987 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__16/O net (fo=2, routed) 0.510 7.497 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__16_n_0 SLICE_X109Y491 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.844 10.559 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y491 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.212 10.772 clock uncertainty -0.035 10.736 SLICE_X109Y491 FDCE (Setup_DFF_SLICEM_C_CE) -0.054 10.682 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.682 arrival time -7.497 ------------------------------------------------------------------- slack 3.185 Slack (MET) : 3.428ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 4.617ns (logic 1.698ns (36.777%) route 2.919ns (63.223%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.182ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.241ns = ( 10.558 - 8.317 ) Source Clock Delay (SCD): 2.635ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.160ns (routing 0.630ns, distribution 1.530ns) Clock Net Delay (Destination): 1.843ns (routing 0.571ns, distribution 1.272ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.160 2.635 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.719 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.254 5.973 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X109Y491 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.224 6.197 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/O net (fo=5, routed) 0.222 6.419 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X107Y491 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.244 6.663 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__16/O net (fo=1, routed) 0.178 6.841 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__16_n_0 SLICE_X109Y491 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 6.987 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__16/O net (fo=2, routed) 0.265 7.252 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__16_n_0 SLICE_X109Y491 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.843 10.558 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y491 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.212 10.771 clock uncertainty -0.035 10.735 SLICE_X109Y491 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 10.680 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.680 arrival time -7.252 ------------------------------------------------------------------- slack 3.428 Slack (MET) : 3.738ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 4.313ns (logic 1.454ns (33.712%) route 2.859ns (66.288%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.176ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.247ns = ( 10.564 - 8.317 ) Source Clock Delay (SCD): 2.635ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.160ns (routing 0.630ns, distribution 1.530ns) Clock Net Delay (Destination): 1.849ns (routing 0.571ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.160 2.635 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.719 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.254 5.973 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X109Y491 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.224 6.197 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/O net (fo=5, routed) 0.197 6.394 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X108Y491 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.146 6.540 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__17/O net (fo=3, routed) 0.408 6.948 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 SLICE_X108Y490 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.849 10.564 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y490 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.212 10.777 clock uncertainty -0.035 10.741 SLICE_X108Y490 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 10.686 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 10.686 arrival time -6.948 ------------------------------------------------------------------- slack 3.738 Slack (MET) : 3.738ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 4.313ns (logic 1.454ns (33.712%) route 2.859ns (66.288%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.176ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.247ns = ( 10.564 - 8.317 ) Source Clock Delay (SCD): 2.635ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.160ns (routing 0.630ns, distribution 1.530ns) Clock Net Delay (Destination): 1.849ns (routing 0.571ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.160 2.635 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.719 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.254 5.973 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X109Y491 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.224 6.197 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/O net (fo=5, routed) 0.197 6.394 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X108Y491 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.146 6.540 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__17/O net (fo=3, routed) 0.408 6.948 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 SLICE_X108Y490 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.849 10.564 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y490 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C clock pessimism 0.212 10.777 clock uncertainty -0.035 10.741 SLICE_X108Y490 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 10.686 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2] ------------------------------------------------------------------- required time 10.686 arrival time -6.948 ------------------------------------------------------------------- slack 3.738 Slack (MET) : 3.743ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 4.309ns (logic 1.454ns (33.743%) route 2.855ns (66.257%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.176ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.247ns = ( 10.564 - 8.317 ) Source Clock Delay (SCD): 2.635ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.160ns (routing 0.630ns, distribution 1.530ns) Clock Net Delay (Destination): 1.849ns (routing 0.571ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.160 2.635 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.719 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.254 5.973 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X109Y491 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.224 6.197 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/O net (fo=5, routed) 0.197 6.394 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X108Y491 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.146 6.540 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__17/O net (fo=3, routed) 0.404 6.944 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 SLICE_X108Y490 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.849 10.564 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y490 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.212 10.777 clock uncertainty -0.035 10.741 SLICE_X108Y490 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 10.687 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 10.687 arrival time -6.944 ------------------------------------------------------------------- slack 3.743 Slack (MET) : 3.805ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 4.250ns (logic 1.458ns (34.306%) route 2.792ns (65.694%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.172ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.251ns = ( 10.568 - 8.317 ) Source Clock Delay (SCD): 2.635ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.160ns (routing 0.630ns, distribution 1.530ns) Clock Net Delay (Destination): 1.853ns (routing 0.571ns, distribution 1.282ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.160 2.635 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.719 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.254 5.973 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X109Y491 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.224 6.197 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/O net (fo=5, routed) 0.091 6.288 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y491 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.150 6.438 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__17/O net (fo=7, routed) 0.447 6.885 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 SLICE_X107Y490 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.853 10.568 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y490 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.212 10.781 clock uncertainty -0.035 10.745 SLICE_X107Y490 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 10.690 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 10.690 arrival time -6.885 ------------------------------------------------------------------- slack 3.805 Slack (MET) : 3.805ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 4.250ns (logic 1.458ns (34.306%) route 2.792ns (65.694%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.172ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.251ns = ( 10.568 - 8.317 ) Source Clock Delay (SCD): 2.635ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.160ns (routing 0.630ns, distribution 1.530ns) Clock Net Delay (Destination): 1.853ns (routing 0.571ns, distribution 1.282ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.160 2.635 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.719 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.254 5.973 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X109Y491 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.224 6.197 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/O net (fo=5, routed) 0.091 6.288 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y491 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.150 6.438 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__17/O net (fo=7, routed) 0.447 6.885 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 SLICE_X107Y490 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.853 10.568 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y490 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.212 10.781 clock uncertainty -0.035 10.745 SLICE_X107Y490 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 10.690 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 10.690 arrival time -6.885 ------------------------------------------------------------------- slack 3.805 Slack (MET) : 3.809ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 4.247ns (logic 1.458ns (34.330%) route 2.789ns (65.670%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.172ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.251ns = ( 10.568 - 8.317 ) Source Clock Delay (SCD): 2.635ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.160ns (routing 0.630ns, distribution 1.530ns) Clock Net Delay (Destination): 1.853ns (routing 0.571ns, distribution 1.282ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.160 2.635 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.719 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.254 5.973 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X109Y491 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.224 6.197 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/O net (fo=5, routed) 0.091 6.288 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y491 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.150 6.438 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__17/O net (fo=7, routed) 0.444 6.882 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 SLICE_X107Y490 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.853 10.568 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y490 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.212 10.781 clock uncertainty -0.035 10.745 SLICE_X107Y490 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 10.691 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 10.691 arrival time -6.882 ------------------------------------------------------------------- slack 3.809 Slack (MET) : 3.809ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 4.247ns (logic 1.458ns (34.330%) route 2.789ns (65.670%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.172ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.251ns = ( 10.568 - 8.317 ) Source Clock Delay (SCD): 2.635ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.160ns (routing 0.630ns, distribution 1.530ns) Clock Net Delay (Destination): 1.853ns (routing 0.571ns, distribution 1.282ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.160 2.635 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.719 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.254 5.973 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X109Y491 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.224 6.197 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/O net (fo=5, routed) 0.091 6.288 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y491 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.150 6.438 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__17/O net (fo=7, routed) 0.444 6.882 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 SLICE_X107Y490 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.853 10.568 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y490 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.212 10.781 clock uncertainty -0.035 10.745 SLICE_X107Y490 FDRE (Setup_BFF_SLICEM_C_CE) -0.054 10.691 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 10.691 arrival time -6.882 ------------------------------------------------------------------- slack 3.809 Slack (MET) : 3.809ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 4.247ns (logic 1.458ns (34.330%) route 2.789ns (65.670%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.172ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.251ns = ( 10.568 - 8.317 ) Source Clock Delay (SCD): 2.635ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.160ns (routing 0.630ns, distribution 1.530ns) Clock Net Delay (Destination): 1.853ns (routing 0.571ns, distribution 1.282ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.160 2.635 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.719 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.254 5.973 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X109Y491 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.224 6.197 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/O net (fo=5, routed) 0.091 6.288 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y491 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.150 6.438 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__17/O net (fo=7, routed) 0.444 6.882 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 SLICE_X107Y490 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.853 10.568 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y490 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.212 10.781 clock uncertainty -0.035 10.745 SLICE_X107Y490 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 10.691 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 10.691 arrival time -6.882 ------------------------------------------------------------------- slack 3.809 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.152ns (logic 0.064ns (42.105%) route 0.088ns (57.895%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.057ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.125ns Source Clock Delay (SCD): 0.909ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.791ns (routing 0.275ns, distribution 0.516ns) Clock Net Delay (Destination): 0.960ns (routing 0.312ns, distribution 0.648ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.791 0.909 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X113Y487 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y487 FDCE (Prop_EFF2_SLICEM_C_Q) 0.048 0.957 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.073 1.030 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/O84[1] SLICE_X113Y486 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.016 1.046 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__16/O net (fo=1, routed) 0.015 1.061 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[1] SLICE_X113Y486 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.960 1.125 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X113Y486 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C clock pessimism -0.159 0.966 SLICE_X113Y486 FDRE (Hold_BFF_SLICEM_C_D) 0.056 1.022 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20] ------------------------------------------------------------------- required time -1.022 arrival time 1.061 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.102ns (66.234%) route 0.052ns (33.766%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.059ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.121ns Source Clock Delay (SCD): 0.903ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.785ns (routing 0.275ns, distribution 0.510ns) Clock Net Delay (Destination): 0.956ns (routing 0.312ns, distribution 0.644ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.785 0.903 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X114Y493 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X114Y493 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 0.952 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Q net (fo=2, routed) 0.036 0.988 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_3_in SLICE_X114Y492 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.053 1.041 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__16/O net (fo=1, routed) 0.016 1.057 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[0] SLICE_X114Y492 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.956 1.121 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X114Y492 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.159 0.962 SLICE_X114Y492 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.018 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -1.018 arrival time 1.057 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.141ns (logic 0.094ns (66.667%) route 0.047ns (33.333%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.124ns Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 0.793ns (routing 0.275ns, distribution 0.518ns) Clock Net Delay (Destination): 0.959ns (routing 0.312ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.793 0.911 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y491 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y491 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 0.960 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0]/Q net (fo=5, routed) 0.035 0.995 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg_n_0_[0] SLICE_X108Y491 LUT3 (Prop_A6LUT_SLICEL_I1_O) 0.045 1.040 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_i_1__16/O net (fo=1, routed) 0.012 1.052 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_i_1__16_n_0 SLICE_X108Y491 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.959 1.124 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y491 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_reg/C clock pessimism -0.169 0.955 SLICE_X108Y491 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.011 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_reg ------------------------------------------------------------------- required time -1.011 arrival time 1.052 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.159ns (logic 0.112ns (70.440%) route 0.047ns (29.560%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.059ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.121ns Source Clock Delay (SCD): 0.903ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.785ns (routing 0.275ns, distribution 0.510ns) Clock Net Delay (Destination): 0.956ns (routing 0.312ns, distribution 0.644ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.785 0.903 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X114Y493 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X114Y493 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 0.952 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Q net (fo=2, routed) 0.036 0.988 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_3_in SLICE_X114Y492 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.063 1.051 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__16/O net (fo=1, routed) 0.011 1.062 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[2] SLICE_X114Y492 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.956 1.121 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X114Y492 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C clock pessimism -0.159 0.962 SLICE_X114Y492 FDRE (Hold_DFF2_SLICEL_C_D) 0.056 1.018 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2] ------------------------------------------------------------------- required time -1.018 arrival time 1.062 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.193ns (logic 0.101ns (52.332%) route 0.092ns (47.668%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.092ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.121ns Source Clock Delay (SCD): 0.901ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.783ns (routing 0.275ns, distribution 0.508ns) Clock Net Delay (Destination): 0.956ns (routing 0.312ns, distribution 0.644ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.783 0.901 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X112Y483 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y483 FDCE (Prop_FFF2_SLICEM_C_Q) 0.048 0.949 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Q net (fo=2, routed) 0.076 1.025 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_25_in SLICE_X111Y483 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.053 1.078 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__16/O net (fo=1, routed) 0.016 1.094 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[11] SLICE_X111Y483 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.956 1.121 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X111Y483 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C clock pessimism -0.128 0.993 SLICE_X111Y483 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.049 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11] ------------------------------------------------------------------- required time -1.049 arrival time 1.094 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.103ns (66.883%) route 0.051ns (33.117%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.120ns Source Clock Delay (SCD): 0.910ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 0.792ns (routing 0.275ns, distribution 0.517ns) Clock Net Delay (Destination): 0.955ns (routing 0.312ns, distribution 0.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.792 0.910 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X110Y486 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y486 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 0.959 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Q net (fo=1, routed) 0.035 0.994 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] SLICE_X110Y485 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.054 1.048 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__16/O net (fo=1, routed) 0.016 1.064 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[1] SLICE_X110Y485 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.955 1.120 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X110Y485 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.158 0.962 SLICE_X110Y485 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.018 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.018 arrival time 1.064 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: SFP_GEN[17].rx_data_ngccm_reg[17][59]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[58]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.159ns (logic 0.112ns (70.440%) route 0.047ns (29.560%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.124ns Source Clock Delay (SCD): 0.909ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.791ns (routing 0.275ns, distribution 0.516ns) Clock Net Delay (Destination): 0.959ns (routing 0.312ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.791 0.909 g_gbt_bank[1].gbtbank_n_74 SLICE_X114Y487 FDCE r SFP_GEN[17].rx_data_ngccm_reg[17][59]/C ------------------------------------------------------------------- ------------------- SLICE_X114Y487 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 0.958 r SFP_GEN[17].rx_data_ngccm_reg[17][59]/Q net (fo=1, routed) 0.036 0.994 SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[83]_0[51] SLICE_X114Y486 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.063 1.057 r SFP_GEN[17].ngCCM_gbt/RX_Word_rx40[58]_i_1/O net (fo=1, routed) 0.011 1.068 SFP_GEN[17].ngCCM_gbt/RX_Word_rx40[58]_i_1_n_0 SLICE_X114Y486 FDCE r SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[58]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.959 1.124 SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X114Y486 FDCE r SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[58]/C clock pessimism -0.159 0.965 SLICE_X114Y486 FDCE (Hold_DFF2_SLICEL_C_D) 0.056 1.021 SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[58] ------------------------------------------------------------------- required time -1.021 arrival time 1.068 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[17].rx_data_ngccm_reg[17][7]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.049ns (28.324%) route 0.124ns (71.676%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.105ns Source Clock Delay (SCD): 0.907ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.789ns (routing 0.275ns, distribution 0.514ns) Clock Net Delay (Destination): 0.940ns (routing 0.312ns, distribution 0.628ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.789 0.907 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X113Y483 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y483 FDRE (Prop_AFF2_SLICEM_C_Q) 0.049 0.956 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/Q net (fo=1, routed) 0.124 1.080 rx_data[17][7] SLICE_X112Y483 FDCE r SFP_GEN[17].rx_data_ngccm_reg[17][7]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.940 1.105 g_gbt_bank[1].gbtbank_n_74 SLICE_X112Y483 FDCE r SFP_GEN[17].rx_data_ngccm_reg[17][7]/C clock pessimism -0.128 0.977 SLICE_X112Y483 FDCE (Hold_CFF2_SLICEM_C_D) 0.056 1.033 SFP_GEN[17].rx_data_ngccm_reg[17][7] ------------------------------------------------------------------- required time -1.033 arrival time 1.080 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.094ns (64.384%) route 0.052ns (35.616%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.121ns Source Clock Delay (SCD): 0.909ns Clock Pessimism Removal (CPR): 0.170ns Clock Net Delay (Source): 0.791ns (routing 0.275ns, distribution 0.516ns) Clock Net Delay (Destination): 0.956ns (routing 0.312ns, distribution 0.644ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.791 0.909 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X114Y492 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X114Y492 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 0.958 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Q net (fo=2, routed) 0.036 0.994 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_23_in SLICE_X114Y492 LUT3 (Prop_C6LUT_SLICEL_I2_O) 0.045 1.039 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__16/O net (fo=1, routed) 0.016 1.055 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[10] SLICE_X114Y492 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.956 1.121 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X114Y492 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C clock pessimism -0.170 0.951 SLICE_X114Y492 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.007 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10] ------------------------------------------------------------------- required time -1.007 arrival time 1.055 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.109ns (logic 0.064ns (58.716%) route 0.045ns (41.284%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.123ns Source Clock Delay (SCD): 0.914ns Clock Pessimism Removal (CPR): 0.204ns Clock Net Delay (Source): 0.796ns (routing 0.275ns, distribution 0.521ns) Clock Net Delay (Destination): 0.958ns (routing 0.312ns, distribution 0.646ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.796 0.914 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y491 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X107Y491 FDRE (Prop_AFF_SLICEM_C_Q) 0.049 0.963 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/Q net (fo=2, routed) 0.033 0.996 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg_n_0_[4] SLICE_X107Y491 LUT6 (Prop_A6LUT_SLICEM_I5_O) 0.015 1.011 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__17/O net (fo=1, routed) 0.012 1.023 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__17_n_0 SLICE_X107Y491 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.958 1.123 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y491 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism -0.204 0.919 SLICE_X107Y491 FDRE (Hold_AFF_SLICEM_C_D) 0.056 0.975 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time -0.975 arrival time 1.023 ------------------------------------------------------------------- slack 0.048 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_19 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y208 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y482 g_clock_rate_din[17].ngccm_status_cnt_reg[17][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y482 g_clock_rate_din[17].ngccm_status_cnt_reg[17][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y481 g_clock_rate_din[17].ngccm_status_cnt_reg[17][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y481 g_clock_rate_din[17].ngccm_status_cnt_reg[17][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y481 g_clock_rate_din[17].ngccm_status_cnt_reg[17][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y481 g_clock_rate_din[17].ngccm_status_cnt_reg[17][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X92Y480 g_clock_rate_din[17].ngccm_status_cnt_reg[17][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y482 g_clock_rate_din[17].ngccm_status_cnt_reg[17][0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y482 g_clock_rate_din[17].ngccm_status_cnt_reg[17][0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y482 g_clock_rate_din[17].ngccm_status_cnt_reg[17][1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y482 g_clock_rate_din[17].ngccm_status_cnt_reg[17][1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X92Y480 g_clock_rate_din[17].ngccm_status_cnt_reg[17][6]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X104Y481 g_clock_rate_din[17].rx_frameclk_div2_reg[17]/C High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y481 g_clock_rate_din[17].ngccm_status_cnt_reg[17][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y481 g_clock_rate_din[17].ngccm_status_cnt_reg[17][3]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y481 g_clock_rate_din[17].ngccm_status_cnt_reg[17][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y481 g_clock_rate_din[17].ngccm_status_cnt_reg[17][5]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y481 g_clock_rate_din[17].ngccm_status_cnt_reg[17][7]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X104Y481 g_clock_rate_din[17].rx_frameclk_div2_reg[17]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_20 To Clock: gtwiz_userclk_rx_srcclk_out[0]_20 Setup : 0 Failing Endpoints, Worst Slack 3.275ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.045ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.493ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.275ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].ngccm_status_reg_reg[18][21]/CE (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 5.139ns (logic 0.382ns (7.433%) route 4.757ns (92.567%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.187ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.595ns = ( 10.912 - 8.317 ) Source Clock Delay (SCD): 2.628ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.153ns (routing 0.632ns, distribution 1.521ns) Clock Net Delay (Destination): 2.197ns (routing 0.573ns, distribution 1.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.153 2.628 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X108Y507 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y507 FDCE (Prop_HFF_SLICEL_C_Q) 0.138 2.766 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 4.318 7.084 SFP_GEN[18].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X82Y480 LUT2 (Prop_C6LUT_SLICEM_I1_O) 0.244 7.328 r SFP_GEN[18].ngCCM_gbt/SFP_GEN[18].ngccm_status_reg[18][24]_i_1/O net (fo=18, routed) 0.439 7.767 rx_test_comm_cnt271_out SLICE_X80Y480 FDPE r SFP_GEN[18].ngccm_status_reg_reg[18][21]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.197 10.912 g_gbt_bank[1].gbtbank_n_84 SLICE_X80Y480 FDPE r SFP_GEN[18].ngccm_status_reg_reg[18][21]/C clock pessimism 0.220 11.133 clock uncertainty -0.035 11.097 SLICE_X80Y480 FDPE (Setup_DFF2_SLICEL_C_CE) -0.055 11.042 SFP_GEN[18].ngccm_status_reg_reg[18][21] ------------------------------------------------------------------- required time 11.042 arrival time -7.767 ------------------------------------------------------------------- slack 3.275 Slack (MET) : 3.275ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].ngccm_status_reg_reg[18][7]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 5.139ns (logic 0.382ns (7.433%) route 4.757ns (92.567%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.187ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.595ns = ( 10.912 - 8.317 ) Source Clock Delay (SCD): 2.628ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.153ns (routing 0.632ns, distribution 1.521ns) Clock Net Delay (Destination): 2.197ns (routing 0.573ns, distribution 1.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.153 2.628 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X108Y507 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y507 FDCE (Prop_HFF_SLICEL_C_Q) 0.138 2.766 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 4.318 7.084 SFP_GEN[18].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X82Y480 LUT2 (Prop_C6LUT_SLICEM_I1_O) 0.244 7.328 r SFP_GEN[18].ngCCM_gbt/SFP_GEN[18].ngccm_status_reg[18][24]_i_1/O net (fo=18, routed) 0.439 7.767 rx_test_comm_cnt271_out SLICE_X80Y480 FDCE r SFP_GEN[18].ngccm_status_reg_reg[18][7]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.197 10.912 g_gbt_bank[1].gbtbank_n_84 SLICE_X80Y480 FDCE r SFP_GEN[18].ngccm_status_reg_reg[18][7]/C clock pessimism 0.220 11.133 clock uncertainty -0.035 11.097 SLICE_X80Y480 FDCE (Setup_AFF2_SLICEL_C_CE) -0.055 11.042 SFP_GEN[18].ngccm_status_reg_reg[18][7] ------------------------------------------------------------------- required time 11.042 arrival time -7.767 ------------------------------------------------------------------- slack 3.275 Slack (MET) : 3.280ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].ngccm_status_reg_reg[18][23]/CE (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 5.135ns (logic 0.382ns (7.439%) route 4.753ns (92.561%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.187ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.595ns = ( 10.912 - 8.317 ) Source Clock Delay (SCD): 2.628ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.153ns (routing 0.632ns, distribution 1.521ns) Clock Net Delay (Destination): 2.197ns (routing 0.573ns, distribution 1.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.153 2.628 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X108Y507 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y507 FDCE (Prop_HFF_SLICEL_C_Q) 0.138 2.766 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 4.318 7.084 SFP_GEN[18].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X82Y480 LUT2 (Prop_C6LUT_SLICEM_I1_O) 0.244 7.328 r SFP_GEN[18].ngCCM_gbt/SFP_GEN[18].ngccm_status_reg[18][24]_i_1/O net (fo=18, routed) 0.435 7.763 rx_test_comm_cnt271_out SLICE_X80Y480 FDPE r SFP_GEN[18].ngccm_status_reg_reg[18][23]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.197 10.912 g_gbt_bank[1].gbtbank_n_84 SLICE_X80Y480 FDPE r SFP_GEN[18].ngccm_status_reg_reg[18][23]/C clock pessimism 0.220 11.133 clock uncertainty -0.035 11.097 SLICE_X80Y480 FDPE (Setup_DFF_SLICEL_C_CE) -0.054 11.043 SFP_GEN[18].ngccm_status_reg_reg[18][23] ------------------------------------------------------------------- required time 11.043 arrival time -7.763 ------------------------------------------------------------------- slack 3.280 Slack (MET) : 3.280ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].ngccm_status_reg_reg[18][24]/CE (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 5.135ns (logic 0.382ns (7.439%) route 4.753ns (92.561%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.187ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.595ns = ( 10.912 - 8.317 ) Source Clock Delay (SCD): 2.628ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.153ns (routing 0.632ns, distribution 1.521ns) Clock Net Delay (Destination): 2.197ns (routing 0.573ns, distribution 1.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.153 2.628 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X108Y507 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y507 FDCE (Prop_HFF_SLICEL_C_Q) 0.138 2.766 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 4.318 7.084 SFP_GEN[18].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X82Y480 LUT2 (Prop_C6LUT_SLICEM_I1_O) 0.244 7.328 r SFP_GEN[18].ngCCM_gbt/SFP_GEN[18].ngccm_status_reg[18][24]_i_1/O net (fo=18, routed) 0.435 7.763 rx_test_comm_cnt271_out SLICE_X80Y480 FDPE r SFP_GEN[18].ngccm_status_reg_reg[18][24]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.197 10.912 g_gbt_bank[1].gbtbank_n_84 SLICE_X80Y480 FDPE r SFP_GEN[18].ngccm_status_reg_reg[18][24]/C clock pessimism 0.220 11.133 clock uncertainty -0.035 11.097 SLICE_X80Y480 FDPE (Setup_CFF_SLICEL_C_CE) -0.054 11.043 SFP_GEN[18].ngccm_status_reg_reg[18][24] ------------------------------------------------------------------- required time 11.043 arrival time -7.763 ------------------------------------------------------------------- slack 3.280 Slack (MET) : 3.280ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].ngccm_status_reg_reg[18][5]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 5.135ns (logic 0.382ns (7.439%) route 4.753ns (92.561%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.187ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.595ns = ( 10.912 - 8.317 ) Source Clock Delay (SCD): 2.628ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.153ns (routing 0.632ns, distribution 1.521ns) Clock Net Delay (Destination): 2.197ns (routing 0.573ns, distribution 1.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.153 2.628 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X108Y507 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y507 FDCE (Prop_HFF_SLICEL_C_Q) 0.138 2.766 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 4.318 7.084 SFP_GEN[18].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X82Y480 LUT2 (Prop_C6LUT_SLICEM_I1_O) 0.244 7.328 r SFP_GEN[18].ngCCM_gbt/SFP_GEN[18].ngccm_status_reg[18][24]_i_1/O net (fo=18, routed) 0.435 7.763 rx_test_comm_cnt271_out SLICE_X80Y480 FDCE r SFP_GEN[18].ngccm_status_reg_reg[18][5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.197 10.912 g_gbt_bank[1].gbtbank_n_84 SLICE_X80Y480 FDCE r SFP_GEN[18].ngccm_status_reg_reg[18][5]/C clock pessimism 0.220 11.133 clock uncertainty -0.035 11.097 SLICE_X80Y480 FDCE (Setup_AFF_SLICEL_C_CE) -0.054 11.043 SFP_GEN[18].ngccm_status_reg_reg[18][5] ------------------------------------------------------------------- required time 11.043 arrival time -7.763 ------------------------------------------------------------------- slack 3.280 Slack (MET) : 3.280ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].ngccm_status_reg_reg[18][8]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 5.135ns (logic 0.382ns (7.439%) route 4.753ns (92.561%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.187ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.595ns = ( 10.912 - 8.317 ) Source Clock Delay (SCD): 2.628ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.153ns (routing 0.632ns, distribution 1.521ns) Clock Net Delay (Destination): 2.197ns (routing 0.573ns, distribution 1.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.153 2.628 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X108Y507 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y507 FDCE (Prop_HFF_SLICEL_C_Q) 0.138 2.766 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 4.318 7.084 SFP_GEN[18].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X82Y480 LUT2 (Prop_C6LUT_SLICEM_I1_O) 0.244 7.328 r SFP_GEN[18].ngCCM_gbt/SFP_GEN[18].ngccm_status_reg[18][24]_i_1/O net (fo=18, routed) 0.435 7.763 rx_test_comm_cnt271_out SLICE_X80Y480 FDCE r SFP_GEN[18].ngccm_status_reg_reg[18][8]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.197 10.912 g_gbt_bank[1].gbtbank_n_84 SLICE_X80Y480 FDCE r SFP_GEN[18].ngccm_status_reg_reg[18][8]/C clock pessimism 0.220 11.133 clock uncertainty -0.035 11.097 SLICE_X80Y480 FDCE (Setup_BFF_SLICEL_C_CE) -0.054 11.043 SFP_GEN[18].ngccm_status_reg_reg[18][8] ------------------------------------------------------------------- required time 11.043 arrival time -7.763 ------------------------------------------------------------------- slack 3.280 Slack (MET) : 3.293ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_clock_rate_din[18].ngccm_status_cnt_reg[18][7]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 5.226ns (logic 0.406ns (7.769%) route 4.820ns (92.231%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.174ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.582ns = ( 10.899 - 8.317 ) Source Clock Delay (SCD): 2.628ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.153ns (routing 0.632ns, distribution 1.521ns) Clock Net Delay (Destination): 2.184ns (routing 0.573ns, distribution 1.611ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.153 2.628 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X108Y507 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y507 FDCE (Prop_HFF_SLICEL_C_Q) 0.138 2.766 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 4.318 7.084 SFP_GEN[18].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X82Y480 LUT4 (Prop_C5LUT_SLICEM_I2_O) 0.268 7.352 r SFP_GEN[18].ngCCM_gbt/g_clock_rate_din[18].ngccm_status_cnt[18][7]_i_1/O net (fo=1, routed) 0.502 7.854 SFP_GEN[18].ngCCM_gbt_n_392 SLICE_X82Y480 FDRE r g_clock_rate_din[18].ngccm_status_cnt_reg[18][7]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.184 10.899 g_gbt_bank[1].gbtbank_n_84 SLICE_X82Y480 FDRE r g_clock_rate_din[18].ngccm_status_cnt_reg[18][7]/C clock pessimism 0.220 11.120 clock uncertainty -0.035 11.084 SLICE_X82Y480 FDRE (Setup_HFF_SLICEM_C_D) 0.063 11.147 g_clock_rate_din[18].ngccm_status_cnt_reg[18][7] ------------------------------------------------------------------- required time 11.147 arrival time -7.854 ------------------------------------------------------------------- slack 3.293 Slack (MET) : 3.358ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_clock_rate_din[18].ngccm_status_cnt_reg[18][2]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 5.161ns (logic 0.327ns (6.336%) route 4.834ns (93.664%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.174ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.582ns = ( 10.899 - 8.317 ) Source Clock Delay (SCD): 2.628ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.153ns (routing 0.632ns, distribution 1.521ns) Clock Net Delay (Destination): 2.184ns (routing 0.573ns, distribution 1.611ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.153 2.628 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X108Y507 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y507 FDCE (Prop_HFF_SLICEL_C_Q) 0.138 2.766 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 4.337 7.103 SFP_GEN[18].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X81Y480 LUT4 (Prop_H5LUT_SLICEL_I2_O) 0.189 7.292 r SFP_GEN[18].ngCCM_gbt/g_clock_rate_din[18].ngccm_status_cnt[18][2]_i_1/O net (fo=1, routed) 0.497 7.789 SFP_GEN[18].ngCCM_gbt_n_417 SLICE_X82Y480 FDRE r g_clock_rate_din[18].ngccm_status_cnt_reg[18][2]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.184 10.899 g_gbt_bank[1].gbtbank_n_84 SLICE_X82Y480 FDRE r g_clock_rate_din[18].ngccm_status_cnt_reg[18][2]/C clock pessimism 0.220 11.120 clock uncertainty -0.035 11.084 SLICE_X82Y480 FDRE (Setup_FFF_SLICEM_C_D) 0.063 11.147 g_clock_rate_din[18].ngccm_status_cnt_reg[18][2] ------------------------------------------------------------------- required time 11.147 arrival time -7.789 ------------------------------------------------------------------- slack 3.358 Slack (MET) : 3.377ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_clock_rate_din[18].ngccm_status_cnt_reg[18][5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 5.144ns (logic 0.403ns (7.834%) route 4.741ns (92.166%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.174ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.582ns = ( 10.899 - 8.317 ) Source Clock Delay (SCD): 2.628ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.153ns (routing 0.632ns, distribution 1.521ns) Clock Net Delay (Destination): 2.184ns (routing 0.573ns, distribution 1.611ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.153 2.628 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X108Y507 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y507 FDCE (Prop_HFF_SLICEL_C_Q) 0.138 2.766 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 4.324 7.090 SFP_GEN[18].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X82Y480 LUT4 (Prop_D5LUT_SLICEM_I2_O) 0.265 7.355 r SFP_GEN[18].ngCCM_gbt/g_clock_rate_din[18].ngccm_status_cnt[18][5]_i_1/O net (fo=1, routed) 0.417 7.772 SFP_GEN[18].ngCCM_gbt_n_412 SLICE_X82Y480 FDRE r g_clock_rate_din[18].ngccm_status_cnt_reg[18][5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.184 10.899 g_gbt_bank[1].gbtbank_n_84 SLICE_X82Y480 FDRE r g_clock_rate_din[18].ngccm_status_cnt_reg[18][5]/C clock pessimism 0.220 11.120 clock uncertainty -0.035 11.084 SLICE_X82Y480 FDRE (Setup_GFF2_SLICEM_C_D) 0.065 11.149 g_clock_rate_din[18].ngccm_status_cnt_reg[18][5] ------------------------------------------------------------------- required time 11.149 arrival time -7.772 ------------------------------------------------------------------- slack 3.377 Slack (MET) : 3.407ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].ngccm_status_reg_reg[18][19]/CE (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 5.003ns (logic 0.382ns (7.635%) route 4.621ns (92.365%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.186ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.594ns = ( 10.911 - 8.317 ) Source Clock Delay (SCD): 2.628ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.153ns (routing 0.632ns, distribution 1.521ns) Clock Net Delay (Destination): 2.196ns (routing 0.573ns, distribution 1.623ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.153 2.628 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X108Y507 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y507 FDCE (Prop_HFF_SLICEL_C_Q) 0.138 2.766 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 4.318 7.084 SFP_GEN[18].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X82Y480 LUT2 (Prop_C6LUT_SLICEM_I1_O) 0.244 7.328 r SFP_GEN[18].ngCCM_gbt/SFP_GEN[18].ngccm_status_reg[18][24]_i_1/O net (fo=18, routed) 0.303 7.631 rx_test_comm_cnt271_out SLICE_X81Y480 FDPE r SFP_GEN[18].ngccm_status_reg_reg[18][19]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.196 10.911 g_gbt_bank[1].gbtbank_n_84 SLICE_X81Y480 FDPE r SFP_GEN[18].ngccm_status_reg_reg[18][19]/C clock pessimism 0.220 11.132 clock uncertainty -0.035 11.096 SLICE_X81Y480 FDPE (Setup_EFF2_SLICEL_C_CE) -0.058 11.038 SFP_GEN[18].ngccm_status_reg_reg[18][19] ------------------------------------------------------------------- required time 11.038 arrival time -7.631 ------------------------------------------------------------------- slack 3.407 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[32]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[32]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.141ns (logic 0.048ns (34.043%) route 0.093ns (65.957%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.097ns Source Clock Delay (SCD): 0.896ns Clock Pessimism Removal (CPR): 0.161ns Clock Net Delay (Source): 0.778ns (routing 0.275ns, distribution 0.503ns) Clock Net Delay (Destination): 0.932ns (routing 0.312ns, distribution 0.620ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.778 0.896 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X108Y514 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[32]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y514 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 0.944 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[32]/Q net (fo=1, routed) 0.093 1.037 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[32] SLICE_X108Y515 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.932 1.097 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X108Y515 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[32]/C clock pessimism -0.161 0.936 SLICE_X108Y515 FDCE (Hold_GFF2_SLICEL_C_D) 0.056 0.992 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[32] ------------------------------------------------------------------- required time -0.992 arrival time 1.037 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: SFP_GEN[18].rx_data_ngccm_reg[18][52]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[52]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.176ns (logic 0.078ns (44.318%) route 0.098ns (55.682%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.093ns Source Clock Delay (SCD): 0.890ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.772ns (routing 0.275ns, distribution 0.497ns) Clock Net Delay (Destination): 0.928ns (routing 0.312ns, distribution 0.616ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.772 0.890 g_gbt_bank[1].gbtbank_n_84 SLICE_X105Y510 FDCE r SFP_GEN[18].rx_data_ngccm_reg[18][52]/C ------------------------------------------------------------------- ------------------- SLICE_X105Y510 FDCE (Prop_EFF2_SLICEL_C_Q) 0.048 0.938 r SFP_GEN[18].rx_data_ngccm_reg[18][52]/Q net (fo=1, routed) 0.082 1.020 SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[83]_0[44] SLICE_X105Y509 LUT3 (Prop_D6LUT_SLICEL_I1_O) 0.030 1.050 r SFP_GEN[18].ngCCM_gbt/RX_Word_rx40[52]_i_1/O net (fo=1, routed) 0.016 1.066 SFP_GEN[18].ngCCM_gbt/RX_Word_rx40[52]_i_1_n_0 SLICE_X105Y509 FDCE r SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[52]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.928 1.093 SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y509 FDCE r SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[52]/C clock pessimism -0.128 0.965 SLICE_X105Y509 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.021 SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[52] ------------------------------------------------------------------- required time -1.021 arrival time 1.066 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.048ns (arrival time - required time) Source: SFP_GEN[18].rx_data_ngccm_reg[18][41]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[40]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.141ns (logic 0.094ns (66.667%) route 0.047ns (33.333%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.115ns Source Clock Delay (SCD): 0.909ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 0.791ns (routing 0.275ns, distribution 0.516ns) Clock Net Delay (Destination): 0.950ns (routing 0.312ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.791 0.909 g_gbt_bank[1].gbtbank_n_84 SLICE_X104Y514 FDCE r SFP_GEN[18].rx_data_ngccm_reg[18][41]/C ------------------------------------------------------------------- ------------------- SLICE_X104Y514 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 0.958 r SFP_GEN[18].rx_data_ngccm_reg[18][41]/Q net (fo=1, routed) 0.035 0.993 SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[83]_0[33] SLICE_X104Y514 LUT3 (Prop_F6LUT_SLICEL_I0_O) 0.045 1.038 r SFP_GEN[18].ngCCM_gbt/RX_Word_rx40[40]_i_1/O net (fo=1, routed) 0.012 1.050 SFP_GEN[18].ngCCM_gbt/RX_Word_rx40[40]_i_1_n_0 SLICE_X104Y514 FDCE r SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[40]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.950 1.115 SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X104Y514 FDCE r SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[40]/C clock pessimism -0.169 0.946 SLICE_X104Y514 FDCE (Hold_FFF_SLICEL_C_D) 0.056 1.002 SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[40] ------------------------------------------------------------------- required time -1.002 arrival time 1.050 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].rx_data_ngccm_reg[18][72]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.161ns (logic 0.049ns (30.435%) route 0.112ns (69.565%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.109ns Source Clock Delay (SCD): 0.892ns Clock Pessimism Removal (CPR): 0.161ns Clock Net Delay (Source): 0.774ns (routing 0.275ns, distribution 0.499ns) Clock Net Delay (Destination): 0.944ns (routing 0.312ns, distribution 0.632ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.774 0.892 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X108Y509 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y509 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 0.941 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/Q net (fo=1, routed) 0.112 1.053 rx_data[18][72] SLICE_X107Y508 FDCE r SFP_GEN[18].rx_data_ngccm_reg[18][72]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.944 1.109 g_gbt_bank[1].gbtbank_n_84 SLICE_X107Y508 FDCE r SFP_GEN[18].rx_data_ngccm_reg[18][72]/C clock pessimism -0.161 0.948 SLICE_X107Y508 FDCE (Hold_AFF2_SLICEM_C_D) 0.056 1.004 SFP_GEN[18].rx_data_ngccm_reg[18][72] ------------------------------------------------------------------- required time -1.004 arrival time 1.053 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].rx_data_ngccm_reg[18][52]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.141ns (logic 0.049ns (34.752%) route 0.092ns (65.248%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.091ns Source Clock Delay (SCD): 0.894ns Clock Pessimism Removal (CPR): 0.161ns Clock Net Delay (Source): 0.776ns (routing 0.275ns, distribution 0.501ns) Clock Net Delay (Destination): 0.926ns (routing 0.312ns, distribution 0.614ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.776 0.894 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X105Y511 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X105Y511 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 0.943 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/Q net (fo=1, routed) 0.092 1.035 rx_data[18][52] SLICE_X105Y510 FDCE r SFP_GEN[18].rx_data_ngccm_reg[18][52]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.926 1.091 g_gbt_bank[1].gbtbank_n_84 SLICE_X105Y510 FDCE r SFP_GEN[18].rx_data_ngccm_reg[18][52]/C clock pessimism -0.161 0.930 SLICE_X105Y510 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 0.985 SFP_GEN[18].rx_data_ngccm_reg[18][52] ------------------------------------------------------------------- required time -0.985 arrival time 1.035 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].rx_data_ngccm_reg[18][73]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.177ns (logic 0.049ns (27.684%) route 0.128ns (72.316%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.099ns Source Clock Delay (SCD): 0.900ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.782ns (routing 0.275ns, distribution 0.507ns) Clock Net Delay (Destination): 0.934ns (routing 0.312ns, distribution 0.622ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.782 0.900 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X107Y511 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X107Y511 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 0.949 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/Q net (fo=1, routed) 0.128 1.077 rx_data[18][73] SLICE_X107Y509 FDCE r SFP_GEN[18].rx_data_ngccm_reg[18][73]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.934 1.099 g_gbt_bank[1].gbtbank_n_84 SLICE_X107Y509 FDCE r SFP_GEN[18].rx_data_ngccm_reg[18][73]/C clock pessimism -0.128 0.971 SLICE_X107Y509 FDCE (Hold_DFF2_SLICEM_C_D) 0.056 1.027 SFP_GEN[18].rx_data_ngccm_reg[18][73] ------------------------------------------------------------------- required time -1.027 arrival time 1.077 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.150ns (logic 0.064ns (42.667%) route 0.086ns (57.333%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.105ns Source Clock Delay (SCD): 0.901ns Clock Pessimism Removal (CPR): 0.161ns Clock Net Delay (Source): 0.783ns (routing 0.275ns, distribution 0.508ns) Clock Net Delay (Destination): 0.940ns (routing 0.312ns, distribution 0.628ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.783 0.901 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X105Y516 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X105Y516 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 0.950 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.071 1.021 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_33_in SLICE_X105Y517 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.015 1.036 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__17/O net (fo=1, routed) 0.015 1.051 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[17] SLICE_X105Y517 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.940 1.105 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X105Y517 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.161 0.944 SLICE_X105Y517 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.000 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.000 arrival time 1.051 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].rx_data_ngccm_reg[18][65]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.180ns (logic 0.048ns (26.667%) route 0.132ns (73.333%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.099ns Source Clock Delay (SCD): 0.899ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.781ns (routing 0.275ns, distribution 0.506ns) Clock Net Delay (Destination): 0.934ns (routing 0.312ns, distribution 0.622ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.781 0.899 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X107Y511 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X107Y511 FDRE (Prop_HFF2_SLICEM_C_Q) 0.048 0.947 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/Q net (fo=1, routed) 0.132 1.079 rx_data[18][65] SLICE_X107Y509 FDCE r SFP_GEN[18].rx_data_ngccm_reg[18][65]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.934 1.099 g_gbt_bank[1].gbtbank_n_84 SLICE_X107Y509 FDCE r SFP_GEN[18].rx_data_ngccm_reg[18][65]/C clock pessimism -0.128 0.971 SLICE_X107Y509 FDCE (Hold_AFF2_SLICEM_C_D) 0.056 1.027 SFP_GEN[18].rx_data_ngccm_reg[18][65] ------------------------------------------------------------------- required time -1.027 arrival time 1.079 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.053ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[24]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.151ns (logic 0.094ns (62.252%) route 0.057ns (37.748%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.119ns Source Clock Delay (SCD): 0.906ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.788ns (routing 0.275ns, distribution 0.513ns) Clock Net Delay (Destination): 0.954ns (routing 0.312ns, distribution 0.642ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.788 0.906 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X108Y518 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y518 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 0.955 f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Q net (fo=27, routed) 0.041 0.996 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] SLICE_X108Y518 LUT5 (Prop_C6LUT_SLICEL_I1_O) 0.045 1.041 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[24]_i_1__19/O net (fo=1, routed) 0.016 1.057 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg00[24] SLICE_X108Y518 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[24]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.954 1.119 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X108Y518 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[24]/C clock pessimism -0.171 0.948 SLICE_X108Y518 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.004 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[24] ------------------------------------------------------------------- required time -1.004 arrival time 1.057 ------------------------------------------------------------------- slack 0.053 Slack (MET) : 0.053ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].rx_data_ngccm_reg[18][51]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.179ns (logic 0.049ns (27.374%) route 0.130ns (72.626%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.095ns Source Clock Delay (SCD): 0.897ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.779ns (routing 0.275ns, distribution 0.504ns) Clock Net Delay (Destination): 0.930ns (routing 0.312ns, distribution 0.618ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.779 0.897 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X105Y513 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X105Y513 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 0.946 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/Q net (fo=1, routed) 0.130 1.076 rx_data[18][51] SLICE_X106Y512 FDCE r SFP_GEN[18].rx_data_ngccm_reg[18][51]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.930 1.095 g_gbt_bank[1].gbtbank_n_84 SLICE_X106Y512 FDCE r SFP_GEN[18].rx_data_ngccm_reg[18][51]/C clock pessimism -0.128 0.967 SLICE_X106Y512 FDCE (Hold_FFF_SLICEM_C_D) 0.056 1.023 SFP_GEN[18].rx_data_ngccm_reg[18][51] ------------------------------------------------------------------- required time -1.023 arrival time 1.076 ------------------------------------------------------------------- slack 0.053 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_20 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y209 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X82Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X82Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X82Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X82Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X82Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X82Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X92Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X82Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X82Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X82Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X82Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][1]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X82Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][2]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X82Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][2]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X92Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][6]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X104Y511 g_clock_rate_din[18].rx_frameclk_div2_reg[18]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X92Y480 g_clock_rate_din[18].rx_test_comm_cnt_reg[18]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X92Y480 g_clock_rate_din[18].rx_wordclk_div2_reg[18]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X108Y508 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X107Y507 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.037 0.493 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.037 1.292 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_21 To Clock: gtwiz_userclk_rx_srcclk_out[0]_21 Setup : 0 Failing Endpoints, Worst Slack 3.032ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.038ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.032ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 5.106ns (logic 1.666ns (32.628%) route 3.440ns (67.372%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.089ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.323ns = ( 10.640 - 8.317 ) Source Clock Delay (SCD): 2.633ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.158ns (routing 0.632ns, distribution 1.526ns) Clock Net Delay (Destination): 1.925ns (routing 0.572ns, distribution 1.353ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.158 2.633 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.719 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.331 6.050 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X126Y498 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.168 6.218 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/O net (fo=5, routed) 0.380 6.598 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X126Y498 LUT4 (Prop_H5LUT_SLICEM_I2_O) 0.265 6.863 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__18/O net (fo=1, routed) 0.236 7.099 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__18_n_0 SLICE_X125Y498 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 7.246 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__18/O net (fo=2, routed) 0.493 7.739 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__18_n_0 SLICE_X125Y498 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.925 10.640 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X125Y498 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.221 10.862 clock uncertainty -0.035 10.826 SLICE_X125Y498 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 10.771 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.771 arrival time -7.739 ------------------------------------------------------------------- slack 3.032 Slack (MET) : 3.200ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 4.942ns (logic 1.666ns (33.711%) route 3.276ns (66.289%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.326ns = ( 10.643 - 8.317 ) Source Clock Delay (SCD): 2.633ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.158ns (routing 0.632ns, distribution 1.526ns) Clock Net Delay (Destination): 1.928ns (routing 0.572ns, distribution 1.356ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.158 2.633 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.719 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.331 6.050 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X126Y498 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.168 6.218 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/O net (fo=5, routed) 0.380 6.598 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X126Y498 LUT4 (Prop_H5LUT_SLICEM_I2_O) 0.265 6.863 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__18/O net (fo=1, routed) 0.236 7.099 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__18_n_0 SLICE_X125Y498 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 7.246 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__18/O net (fo=2, routed) 0.329 7.575 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__18_n_0 SLICE_X125Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.928 10.643 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X125Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.221 10.865 clock uncertainty -0.035 10.829 SLICE_X125Y497 FDCE (Setup_DFF_SLICEL_C_CE) -0.054 10.775 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.775 arrival time -7.575 ------------------------------------------------------------------- slack 3.200 Slack (MET) : 3.504ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 4.632ns (logic 1.489ns (32.146%) route 3.143ns (67.854%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.088ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.324ns = ( 10.641 - 8.317 ) Source Clock Delay (SCD): 2.633ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.158ns (routing 0.632ns, distribution 1.526ns) Clock Net Delay (Destination): 1.926ns (routing 0.572ns, distribution 1.354ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.158 2.633 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.719 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.331 6.050 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X126Y498 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.168 6.218 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/O net (fo=5, routed) 0.313 6.531 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X125Y498 LUT6 (Prop_E6LUT_SLICEL_I5_O) 0.235 6.766 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__19/O net (fo=3, routed) 0.499 7.265 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/consecFalseHeaders0 SLICE_X125Y497 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.926 10.641 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X125Y497 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.221 10.863 clock uncertainty -0.035 10.827 SLICE_X125Y497 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 10.769 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 10.769 arrival time -7.265 ------------------------------------------------------------------- slack 3.504 Slack (MET) : 3.511ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 4.628ns (logic 1.489ns (32.174%) route 3.139ns (67.826%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.088ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.324ns = ( 10.641 - 8.317 ) Source Clock Delay (SCD): 2.633ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.158ns (routing 0.632ns, distribution 1.526ns) Clock Net Delay (Destination): 1.926ns (routing 0.572ns, distribution 1.354ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.158 2.633 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.719 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.331 6.050 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X126Y498 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.168 6.218 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/O net (fo=5, routed) 0.313 6.531 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X125Y498 LUT6 (Prop_E6LUT_SLICEL_I5_O) 0.235 6.766 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__19/O net (fo=3, routed) 0.495 7.261 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/consecFalseHeaders0 SLICE_X125Y497 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.926 10.641 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X125Y497 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.221 10.863 clock uncertainty -0.035 10.827 SLICE_X125Y497 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 10.772 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 10.772 arrival time -7.261 ------------------------------------------------------------------- slack 3.511 Slack (MET) : 3.511ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 4.628ns (logic 1.489ns (32.174%) route 3.139ns (67.826%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.088ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.324ns = ( 10.641 - 8.317 ) Source Clock Delay (SCD): 2.633ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.158ns (routing 0.632ns, distribution 1.526ns) Clock Net Delay (Destination): 1.926ns (routing 0.572ns, distribution 1.354ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.158 2.633 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.719 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.331 6.050 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X126Y498 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.168 6.218 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/O net (fo=5, routed) 0.313 6.531 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X125Y498 LUT6 (Prop_E6LUT_SLICEL_I5_O) 0.235 6.766 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__19/O net (fo=3, routed) 0.495 7.261 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/consecFalseHeaders0 SLICE_X125Y497 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.926 10.641 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X125Y497 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C clock pessimism 0.221 10.863 clock uncertainty -0.035 10.827 SLICE_X125Y497 FDRE (Setup_EFF_SLICEL_C_CE) -0.055 10.772 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2] ------------------------------------------------------------------- required time 10.772 arrival time -7.261 ------------------------------------------------------------------- slack 3.511 Slack (MET) : 3.632ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 4.498ns (logic 1.491ns (33.148%) route 3.007ns (66.852%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.094ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.318ns = ( 10.635 - 8.317 ) Source Clock Delay (SCD): 2.633ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.158ns (routing 0.632ns, distribution 1.526ns) Clock Net Delay (Destination): 1.920ns (routing 0.572ns, distribution 1.348ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.158 2.633 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.719 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.331 6.050 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X126Y498 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.168 6.218 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/O net (fo=5, routed) 0.314 6.532 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X125Y498 LUT5 (Prop_B6LUT_SLICEL_I3_O) 0.237 6.769 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__19/O net (fo=7, routed) 0.362 7.131 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X126Y497 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.920 10.635 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X126Y497 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.221 10.857 clock uncertainty -0.035 10.821 SLICE_X126Y497 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 10.763 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 10.763 arrival time -7.131 ------------------------------------------------------------------- slack 3.632 Slack (MET) : 3.637ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 4.494ns (logic 1.491ns (33.178%) route 3.003ns (66.822%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.316ns = ( 10.633 - 8.317 ) Source Clock Delay (SCD): 2.633ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.158ns (routing 0.632ns, distribution 1.526ns) Clock Net Delay (Destination): 1.918ns (routing 0.572ns, distribution 1.346ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.158 2.633 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.719 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.331 6.050 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X126Y498 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.168 6.218 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/O net (fo=5, routed) 0.314 6.532 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X125Y498 LUT5 (Prop_B6LUT_SLICEL_I3_O) 0.237 6.769 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__19/O net (fo=7, routed) 0.358 7.127 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X125Y499 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.918 10.633 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X125Y499 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.221 10.855 clock uncertainty -0.035 10.819 SLICE_X125Y499 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 10.764 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 10.764 arrival time -7.127 ------------------------------------------------------------------- slack 3.637 Slack (MET) : 3.637ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 4.494ns (logic 1.491ns (33.178%) route 3.003ns (66.822%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.316ns = ( 10.633 - 8.317 ) Source Clock Delay (SCD): 2.633ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.158ns (routing 0.632ns, distribution 1.526ns) Clock Net Delay (Destination): 1.918ns (routing 0.572ns, distribution 1.346ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.158 2.633 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.719 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.331 6.050 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X126Y498 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.168 6.218 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/O net (fo=5, routed) 0.314 6.532 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X125Y498 LUT5 (Prop_B6LUT_SLICEL_I3_O) 0.237 6.769 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__19/O net (fo=7, routed) 0.358 7.127 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X125Y499 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.918 10.633 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X125Y499 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.221 10.855 clock uncertainty -0.035 10.819 SLICE_X125Y499 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 10.764 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 10.764 arrival time -7.127 ------------------------------------------------------------------- slack 3.637 Slack (MET) : 3.642ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 4.490ns (logic 1.491ns (33.207%) route 2.999ns (66.793%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.316ns = ( 10.633 - 8.317 ) Source Clock Delay (SCD): 2.633ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.158ns (routing 0.632ns, distribution 1.526ns) Clock Net Delay (Destination): 1.918ns (routing 0.572ns, distribution 1.346ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.158 2.633 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.719 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.331 6.050 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X126Y498 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.168 6.218 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/O net (fo=5, routed) 0.314 6.532 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X125Y498 LUT5 (Prop_B6LUT_SLICEL_I3_O) 0.237 6.769 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__19/O net (fo=7, routed) 0.354 7.123 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X125Y499 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.918 10.633 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X125Y499 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.221 10.855 clock uncertainty -0.035 10.819 SLICE_X125Y499 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 10.765 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 10.765 arrival time -7.123 ------------------------------------------------------------------- slack 3.642 Slack (MET) : 3.642ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 4.490ns (logic 1.491ns (33.207%) route 2.999ns (66.793%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.316ns = ( 10.633 - 8.317 ) Source Clock Delay (SCD): 2.633ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.158ns (routing 0.632ns, distribution 1.526ns) Clock Net Delay (Destination): 1.918ns (routing 0.572ns, distribution 1.346ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.158 2.633 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.719 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.331 6.050 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X126Y498 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.168 6.218 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/O net (fo=5, routed) 0.314 6.532 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X125Y498 LUT5 (Prop_B6LUT_SLICEL_I3_O) 0.237 6.769 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__19/O net (fo=7, routed) 0.354 7.123 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X125Y499 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.918 10.633 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X125Y499 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.221 10.855 clock uncertainty -0.035 10.819 SLICE_X125Y499 FDRE (Setup_BFF_SLICEL_C_CE) -0.054 10.765 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 10.765 arrival time -7.123 ------------------------------------------------------------------- slack 3.642 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.038ns (arrival time - required time) Source: SFP_GEN[19].rx_data_ngccm_reg[19][76]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[76]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.167ns (logic 0.079ns (47.305%) route 0.088ns (52.695%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.155ns Source Clock Delay (SCD): 0.949ns Clock Pessimism Removal (CPR): 0.133ns Clock Net Delay (Source): 0.831ns (routing 0.274ns, distribution 0.557ns) Clock Net Delay (Destination): 0.990ns (routing 0.313ns, distribution 0.677ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.831 0.949 g_gbt_bank[1].gbtbank_n_94 SLICE_X131Y485 FDCE r SFP_GEN[19].rx_data_ngccm_reg[19][76]/C ------------------------------------------------------------------- ------------------- SLICE_X131Y485 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 0.998 r SFP_GEN[19].rx_data_ngccm_reg[19][76]/Q net (fo=1, routed) 0.072 1.070 g_gbt_bank[1].gbtbank/RX_Word_rx40_reg[78]_3[52] SLICE_X130Y485 LUT3 (Prop_D6LUT_SLICEL_I1_O) 0.030 1.100 r g_gbt_bank[1].gbtbank/RX_Word_rx40[76]_i_1__3/O net (fo=1, routed) 0.016 1.116 SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[83]_0[42] SLICE_X130Y485 FDCE r SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[76]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.990 1.155 SFP_GEN[19].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X130Y485 FDCE r SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[76]/C clock pessimism -0.133 1.022 SLICE_X130Y485 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.078 SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[76] ------------------------------------------------------------------- required time -1.078 arrival time 1.116 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[35]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[35]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.141ns (logic 0.049ns (34.752%) route 0.092ns (65.248%)) Logic Levels: 0 Clock Path Skew: 0.046ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.150ns Source Clock Delay (SCD): 0.939ns Clock Pessimism Removal (CPR): 0.165ns Clock Net Delay (Source): 0.821ns (routing 0.274ns, distribution 0.547ns) Clock Net Delay (Destination): 0.985ns (routing 0.313ns, distribution 0.672ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.821 0.939 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X128Y491 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[35]/C ------------------------------------------------------------------- ------------------- SLICE_X128Y491 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 0.988 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[35]/Q net (fo=1, routed) 0.092 1.080 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0[35] SLICE_X128Y490 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[35]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.985 1.150 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X128Y490 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[35]/C clock pessimism -0.165 0.985 SLICE_X128Y490 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 1.041 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[35] ------------------------------------------------------------------- required time -1.041 arrival time 1.080 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.042ns (arrival time - required time) Source: SFP_GEN[19].rx_data_ngccm_reg[19][74]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[74]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.172ns (logic 0.087ns (50.581%) route 0.085ns (49.419%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.152ns Source Clock Delay (SCD): 0.944ns Clock Pessimism Removal (CPR): 0.133ns Clock Net Delay (Source): 0.826ns (routing 0.274ns, distribution 0.552ns) Clock Net Delay (Destination): 0.987ns (routing 0.313ns, distribution 0.674ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.826 0.944 g_gbt_bank[1].gbtbank_n_94 SLICE_X131Y483 FDCE r SFP_GEN[19].rx_data_ngccm_reg[19][74]/C ------------------------------------------------------------------- ------------------- SLICE_X131Y483 FDCE (Prop_EFF2_SLICEL_C_Q) 0.048 0.992 r SFP_GEN[19].rx_data_ngccm_reg[19][74]/Q net (fo=1, routed) 0.071 1.063 g_gbt_bank[1].gbtbank/RX_Word_rx40_reg[78]_3[50] SLICE_X130Y483 LUT3 (Prop_F5LUT_SLICEL_I1_O) 0.039 1.102 r g_gbt_bank[1].gbtbank/RX_Word_rx40[74]_i_1__3/O net (fo=1, routed) 0.014 1.116 SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[83]_0[41] SLICE_X130Y483 FDCE r SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[74]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.987 1.152 SFP_GEN[19].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X130Y483 FDCE r SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[74]/C clock pessimism -0.133 1.019 SLICE_X130Y483 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.074 SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[74] ------------------------------------------------------------------- required time -1.074 arrival time 1.116 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[19].rx_data_ngccm_reg[19][38]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.176ns (logic 0.049ns (27.841%) route 0.127ns (72.159%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.157ns Source Clock Delay (SCD): 0.947ns Clock Pessimism Removal (CPR): 0.133ns Clock Net Delay (Source): 0.829ns (routing 0.274ns, distribution 0.555ns) Clock Net Delay (Destination): 0.992ns (routing 0.313ns, distribution 0.679ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.829 0.947 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X123Y485 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X123Y485 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 0.996 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/Q net (fo=1, routed) 0.127 1.123 rx_data[19][38] SLICE_X121Y485 FDCE r SFP_GEN[19].rx_data_ngccm_reg[19][38]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.992 1.157 g_gbt_bank[1].gbtbank_n_94 SLICE_X121Y485 FDCE r SFP_GEN[19].rx_data_ngccm_reg[19][38]/C clock pessimism -0.133 1.024 SLICE_X121Y485 FDCE (Hold_HFF2_SLICEL_C_D) 0.056 1.080 SFP_GEN[19].rx_data_ngccm_reg[19][38] ------------------------------------------------------------------- required time -1.080 arrival time 1.123 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.183ns (logic 0.094ns (51.366%) route 0.089ns (48.634%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.162ns Source Clock Delay (SCD): 0.946ns Clock Pessimism Removal (CPR): 0.133ns Clock Net Delay (Source): 0.828ns (routing 0.274ns, distribution 0.554ns) Clock Net Delay (Destination): 0.997ns (routing 0.313ns, distribution 0.684ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.828 0.946 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X123Y486 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X123Y486 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 0.995 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.074 1.069 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/O83[0] SLICE_X122Y486 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.045 1.114 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__18/O net (fo=1, routed) 0.015 1.129 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/I7[0] SLICE_X122Y486 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.162 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X122Y486 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C clock pessimism -0.133 1.029 SLICE_X122Y486 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.085 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[19] ------------------------------------------------------------------- required time -1.085 arrival time 1.129 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[19].rx_data_ngccm_reg[19][56]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.048ns (33.333%) route 0.096ns (66.667%)) Logic Levels: 0 Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.150ns Source Clock Delay (SCD): 0.942ns Clock Pessimism Removal (CPR): 0.164ns Clock Net Delay (Source): 0.824ns (routing 0.274ns, distribution 0.550ns) Clock Net Delay (Destination): 0.985ns (routing 0.313ns, distribution 0.672ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.824 0.942 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X129Y487 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y487 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 0.990 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/Q net (fo=1, routed) 0.096 1.086 rx_data[19][56] SLICE_X129Y485 FDCE r SFP_GEN[19].rx_data_ngccm_reg[19][56]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.985 1.150 g_gbt_bank[1].gbtbank_n_94 SLICE_X129Y485 FDCE r SFP_GEN[19].rx_data_ngccm_reg[19][56]/C clock pessimism -0.164 0.986 SLICE_X129Y485 FDCE (Hold_AFF2_SLICEL_C_D) 0.056 1.042 SFP_GEN[19].rx_data_ngccm_reg[19][56] ------------------------------------------------------------------- required time -1.042 arrival time 1.086 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.178ns (logic 0.079ns (44.382%) route 0.099ns (55.618%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.145ns Source Clock Delay (SCD): 0.934ns Clock Pessimism Removal (CPR): 0.133ns Clock Net Delay (Source): 0.816ns (routing 0.274ns, distribution 0.542ns) Clock Net Delay (Destination): 0.980ns (routing 0.313ns, distribution 0.667ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.816 0.934 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X125Y498 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X125Y498 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.983 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[2]/Q net (fo=8, routed) 0.083 1.066 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress[2] SLICE_X126Y498 LUT6 (Prop_C6LUT_SLICEM_I3_O) 0.030 1.096 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_i_1__18/O net (fo=1, routed) 0.016 1.112 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd SLICE_X126Y498 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.980 1.145 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X126Y498 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_reg/C clock pessimism -0.133 1.012 SLICE_X126Y498 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.068 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_reg ------------------------------------------------------------------- required time -1.068 arrival time 1.112 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[19].rx_data_ngccm_reg[19][1]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.048ns (30.968%) route 0.107ns (69.032%)) Logic Levels: 0 Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.158ns Source Clock Delay (SCD): 0.943ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 0.825ns (routing 0.274ns, distribution 0.551ns) Clock Net Delay (Destination): 0.993ns (routing 0.313ns, distribution 0.680ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.825 0.943 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X121Y489 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X121Y489 FDRE (Prop_HFF_SLICEL_C_Q) 0.048 0.991 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/Q net (fo=1, routed) 0.107 1.098 rx_data[19][1] SLICE_X121Y488 FDCE r SFP_GEN[19].rx_data_ngccm_reg[19][1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.993 1.158 g_gbt_bank[1].gbtbank_n_94 SLICE_X121Y488 FDCE r SFP_GEN[19].rx_data_ngccm_reg[19][1]/C clock pessimism -0.163 0.995 SLICE_X121Y488 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.051 SFP_GEN[19].rx_data_ngccm_reg[19][1] ------------------------------------------------------------------- required time -1.051 arrival time 1.098 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.109ns (logic 0.064ns (58.716%) route 0.045ns (41.284%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.145ns Source Clock Delay (SCD): 0.937ns Clock Pessimism Removal (CPR): 0.203ns Clock Net Delay (Source): 0.819ns (routing 0.274ns, distribution 0.545ns) Clock Net Delay (Destination): 0.980ns (routing 0.313ns, distribution 0.667ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.819 0.937 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X126Y498 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X126Y498 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 0.986 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg/Q net (fo=2, routed) 0.033 1.019 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/ready_from_bitSlipCtrller_7 SLICE_X126Y498 LUT3 (Prop_A6LUT_SLICEM_I2_O) 0.015 1.034 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_i_1__18/O net (fo=1, routed) 0.012 1.046 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_i_1__18_n_0 SLICE_X126Y498 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.980 1.145 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X126Y498 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg/C clock pessimism -0.203 0.942 SLICE_X126Y498 FDCE (Hold_AFF_SLICEM_C_D) 0.056 0.998 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg ------------------------------------------------------------------- required time -0.998 arrival time 1.046 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.183ns (logic 0.094ns (51.366%) route 0.089ns (48.634%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.155ns Source Clock Delay (SCD): 0.944ns Clock Pessimism Removal (CPR): 0.133ns Clock Net Delay (Source): 0.826ns (routing 0.274ns, distribution 0.552ns) Clock Net Delay (Destination): 0.990ns (routing 0.313ns, distribution 0.677ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.826 0.944 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X130Y486 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X130Y486 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 0.993 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Q net (fo=2, routed) 0.073 1.066 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_29_in SLICE_X131Y486 LUT3 (Prop_C6LUT_SLICEL_I2_O) 0.045 1.111 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__18/O net (fo=1, routed) 0.016 1.127 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[13] SLICE_X131Y486 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.990 1.155 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X131Y486 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C clock pessimism -0.133 1.022 SLICE_X131Y486 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.078 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13] ------------------------------------------------------------------- required time -1.078 arrival time 1.127 ------------------------------------------------------------------- slack 0.049 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_21 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y213 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X79Y480 g_clock_rate_din[19].ngccm_status_cnt_reg[19][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X79Y480 g_clock_rate_din[19].ngccm_status_cnt_reg[19][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X79Y480 g_clock_rate_din[19].ngccm_status_cnt_reg[19][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X79Y480 g_clock_rate_din[19].ngccm_status_cnt_reg[19][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X79Y480 g_clock_rate_din[19].ngccm_status_cnt_reg[19][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X79Y480 g_clock_rate_din[19].ngccm_status_cnt_reg[19][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X92Y481 g_clock_rate_din[19].ngccm_status_cnt_reg[19][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X92Y481 g_clock_rate_din[19].ngccm_status_cnt_reg[19][6]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X92Y481 g_clock_rate_din[19].ngccm_status_cnt_reg[19][6]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X121Y487 g_clock_rate_din[19].rx_frameclk_div2_reg[19]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X92Y481 g_clock_rate_din[19].rx_test_comm_cnt_reg[19]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X92Y481 g_clock_rate_din[19].rx_test_comm_cnt_reg[19]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X93Y480 g_clock_rate_din[19].rx_wordclk_div2_reg[19]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X92Y481 g_clock_rate_din[19].ngccm_status_cnt_reg[19][6]/C High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X92Y481 g_clock_rate_din[19].rx_test_comm_cnt_reg[19]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X127Y483 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X127Y483 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X127Y483 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X127Y483 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_22 To Clock: gtwiz_userclk_rx_srcclk_out[0]_22 Setup : 0 Failing Endpoints, Worst Slack 3.325ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.041ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.325ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 4.786ns (logic 1.853ns (38.717%) route 2.933ns (61.283%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.319ns = ( 10.636 - 8.317 ) Source Clock Delay (SCD): 2.662ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.187ns (routing 0.628ns, distribution 1.559ns) Clock Net Delay (Destination): 1.921ns (routing 0.568ns, distribution 1.353ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.187 2.662 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.823 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.679 5.502 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X121Y544 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 5.740 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/O net (fo=5, routed) 0.302 6.042 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X122Y543 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.235 6.277 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__19/O net (fo=1, routed) 0.327 6.604 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__19_n_0 SLICE_X122Y544 LUT6 (Prop_B6LUT_SLICEL_I5_O) 0.219 6.823 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__19/O net (fo=2, routed) 0.625 7.448 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__19_n_0 SLICE_X120Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.921 10.636 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X120Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.227 10.864 clock uncertainty -0.035 10.828 SLICE_X120Y545 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 10.773 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.773 arrival time -7.448 ------------------------------------------------------------------- slack 3.325 Slack (MET) : 3.614ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 4.510ns (logic 1.853ns (41.086%) route 2.657ns (58.914%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.103ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.332ns = ( 10.649 - 8.317 ) Source Clock Delay (SCD): 2.662ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.187ns (routing 0.628ns, distribution 1.559ns) Clock Net Delay (Destination): 1.934ns (routing 0.568ns, distribution 1.366ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.187 2.662 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.823 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.679 5.502 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X121Y544 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 5.740 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/O net (fo=5, routed) 0.302 6.042 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X122Y543 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.235 6.277 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__19/O net (fo=1, routed) 0.327 6.604 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__19_n_0 SLICE_X122Y544 LUT6 (Prop_B6LUT_SLICEL_I5_O) 0.219 6.823 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__19/O net (fo=2, routed) 0.349 7.172 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__19_n_0 SLICE_X119Y544 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.934 10.649 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X119Y544 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.227 10.876 clock uncertainty -0.035 10.841 SLICE_X119Y544 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 10.786 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.786 arrival time -7.172 ------------------------------------------------------------------- slack 3.614 Slack (MET) : 4.075ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 4.057ns (logic 1.565ns (38.575%) route 2.492ns (61.425%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.092ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.343ns = ( 10.660 - 8.317 ) Source Clock Delay (SCD): 2.662ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.187ns (routing 0.628ns, distribution 1.559ns) Clock Net Delay (Destination): 1.945ns (routing 0.568ns, distribution 1.377ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.187 2.662 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.823 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.679 5.502 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X121Y544 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 5.740 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/O net (fo=5, routed) 0.191 5.931 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X122Y544 LUT5 (Prop_G6LUT_SLICEL_I3_O) 0.166 6.097 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__20/O net (fo=7, routed) 0.622 6.719 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X121Y545 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.945 10.660 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X121Y545 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.227 10.887 clock uncertainty -0.035 10.852 SLICE_X121Y545 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 10.794 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 10.794 arrival time -6.719 ------------------------------------------------------------------- slack 4.075 Slack (MET) : 4.076ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 4.061ns (logic 1.565ns (38.537%) route 2.496ns (61.463%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.090ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.345ns = ( 10.662 - 8.317 ) Source Clock Delay (SCD): 2.662ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.187ns (routing 0.628ns, distribution 1.559ns) Clock Net Delay (Destination): 1.947ns (routing 0.568ns, distribution 1.379ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.187 2.662 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.823 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.679 5.502 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X121Y544 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 5.740 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/O net (fo=5, routed) 0.191 5.931 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X122Y544 LUT5 (Prop_G6LUT_SLICEL_I3_O) 0.166 6.097 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__20/O net (fo=7, routed) 0.626 6.723 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X122Y545 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.947 10.662 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X122Y545 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.227 10.889 clock uncertainty -0.035 10.854 SLICE_X122Y545 FDRE (Setup_BFF2_SLICEL_C_CE) -0.055 10.799 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 10.799 arrival time -6.723 ------------------------------------------------------------------- slack 4.076 Slack (MET) : 4.081ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 4.057ns (logic 1.565ns (38.575%) route 2.492ns (61.425%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.090ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.345ns = ( 10.662 - 8.317 ) Source Clock Delay (SCD): 2.662ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.187ns (routing 0.628ns, distribution 1.559ns) Clock Net Delay (Destination): 1.947ns (routing 0.568ns, distribution 1.379ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.187 2.662 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.823 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.679 5.502 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X121Y544 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 5.740 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/O net (fo=5, routed) 0.191 5.931 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X122Y544 LUT5 (Prop_G6LUT_SLICEL_I3_O) 0.166 6.097 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__20/O net (fo=7, routed) 0.622 6.719 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X122Y545 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.947 10.662 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X122Y545 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.227 10.889 clock uncertainty -0.035 10.854 SLICE_X122Y545 FDRE (Setup_BFF_SLICEL_C_CE) -0.054 10.800 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 10.800 arrival time -6.719 ------------------------------------------------------------------- slack 4.081 Slack (MET) : 4.110ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 4.001ns (logic 1.546ns (38.640%) route 2.455ns (61.360%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.319ns = ( 10.636 - 8.317 ) Source Clock Delay (SCD): 2.662ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.187ns (routing 0.628ns, distribution 1.559ns) Clock Net Delay (Destination): 1.921ns (routing 0.568ns, distribution 1.353ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.187 2.662 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.823 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.679 5.502 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X121Y544 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 5.740 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/O net (fo=5, routed) 0.261 6.001 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X120Y543 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 6.148 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__20/O net (fo=5, routed) 0.515 6.663 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecCorrectHeaders0 SLICE_X120Y543 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.921 10.636 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X120Y543 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism 0.227 10.864 clock uncertainty -0.035 10.828 SLICE_X120Y543 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 10.773 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time 10.773 arrival time -6.663 ------------------------------------------------------------------- slack 4.110 Slack (MET) : 4.154ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 3.978ns (logic 1.565ns (39.341%) route 2.413ns (60.659%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.092ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.343ns = ( 10.660 - 8.317 ) Source Clock Delay (SCD): 2.662ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.187ns (routing 0.628ns, distribution 1.559ns) Clock Net Delay (Destination): 1.945ns (routing 0.568ns, distribution 1.377ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.187 2.662 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.823 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.679 5.502 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X121Y544 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 5.740 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/O net (fo=5, routed) 0.191 5.931 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X122Y544 LUT5 (Prop_G6LUT_SLICEL_I3_O) 0.166 6.097 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__20/O net (fo=7, routed) 0.543 6.640 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X122Y543 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.945 10.660 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X122Y543 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.227 10.887 clock uncertainty -0.035 10.852 SLICE_X122Y543 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 10.794 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 10.794 arrival time -6.640 ------------------------------------------------------------------- slack 4.154 Slack (MET) : 4.195ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 3.942ns (logic 1.450ns (36.783%) route 2.492ns (63.217%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.090ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.345ns = ( 10.662 - 8.317 ) Source Clock Delay (SCD): 2.662ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.187ns (routing 0.628ns, distribution 1.559ns) Clock Net Delay (Destination): 1.947ns (routing 0.568ns, distribution 1.379ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.187 2.662 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.823 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.679 5.502 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X121Y544 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 5.740 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/O net (fo=5, routed) 0.291 6.031 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X121Y543 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.051 6.082 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__20/O net (fo=3, routed) 0.522 6.604 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecFalseHeaders0 SLICE_X122Y543 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.947 10.662 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X122Y543 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.227 10.889 clock uncertainty -0.035 10.854 SLICE_X122Y543 FDRE (Setup_BFF2_SLICEL_C_CE) -0.055 10.799 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 10.799 arrival time -6.604 ------------------------------------------------------------------- slack 4.195 Slack (MET) : 4.200ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 3.938ns (logic 1.450ns (36.821%) route 2.488ns (63.179%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.090ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.345ns = ( 10.662 - 8.317 ) Source Clock Delay (SCD): 2.662ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.187ns (routing 0.628ns, distribution 1.559ns) Clock Net Delay (Destination): 1.947ns (routing 0.568ns, distribution 1.379ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.187 2.662 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.823 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.679 5.502 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X121Y544 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 5.740 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/O net (fo=5, routed) 0.291 6.031 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X121Y543 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.051 6.082 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__20/O net (fo=3, routed) 0.518 6.600 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecFalseHeaders0 SLICE_X122Y543 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.947 10.662 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X122Y543 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.227 10.889 clock uncertainty -0.035 10.854 SLICE_X122Y543 FDRE (Setup_BFF_SLICEL_C_CE) -0.054 10.800 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 10.800 arrival time -6.600 ------------------------------------------------------------------- slack 4.200 Slack (MET) : 4.267ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 3.846ns (logic 1.546ns (40.198%) route 2.300ns (59.802%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.321ns = ( 10.638 - 8.317 ) Source Clock Delay (SCD): 2.662ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.187ns (routing 0.628ns, distribution 1.559ns) Clock Net Delay (Destination): 1.923ns (routing 0.568ns, distribution 1.355ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.187 2.662 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.823 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.679 5.502 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X121Y544 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 5.740 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/O net (fo=5, routed) 0.261 6.001 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X120Y543 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 6.148 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__20/O net (fo=5, routed) 0.360 6.508 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecCorrectHeaders0 SLICE_X120Y545 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.923 10.638 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X120Y545 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.227 10.866 clock uncertainty -0.035 10.830 SLICE_X120Y545 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 10.775 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 10.775 arrival time -6.508 ------------------------------------------------------------------- slack 4.267 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].rx_data_ngccm_reg[20][47]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.141ns (logic 0.048ns (34.043%) route 0.093ns (65.957%)) Logic Levels: 0 Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.176ns Source Clock Delay (SCD): 0.956ns Clock Pessimism Removal (CPR): 0.176ns Clock Net Delay (Source): 0.838ns (routing 0.273ns, distribution 0.565ns) Clock Net Delay (Destination): 1.011ns (routing 0.314ns, distribution 0.697ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.838 0.956 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X121Y546 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X121Y546 FDRE (Prop_GFF_SLICEL_C_Q) 0.048 1.004 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/Q net (fo=1, routed) 0.093 1.097 rx_data[20][47] SLICE_X122Y546 FDCE r SFP_GEN[20].rx_data_ngccm_reg[20][47]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.011 1.176 g_gbt_bank[1].gbtbank_n_104 SLICE_X122Y546 FDCE r SFP_GEN[20].rx_data_ngccm_reg[20][47]/C clock pessimism -0.176 1.000 SLICE_X122Y546 FDCE (Hold_BFF2_SLICEL_C_D) 0.056 1.056 SFP_GEN[20].rx_data_ngccm_reg[20][47] ------------------------------------------------------------------- required time -1.056 arrival time 1.097 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.044ns (arrival time - required time) Source: SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[26]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.161ns (logic 0.048ns (29.814%) route 0.113ns (70.186%)) Logic Levels: 0 Clock Path Skew: 0.061ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.130ns Source Clock Delay (SCD): 0.907ns Clock Pessimism Removal (CPR): 0.162ns Clock Net Delay (Source): 0.789ns (routing 0.273ns, distribution 0.516ns) Clock Net Delay (Destination): 0.965ns (routing 0.314ns, distribution 0.651ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.789 0.907 SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y547 FDCE r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[26]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y547 FDCE (Prop_CFF2_SLICEL_C_Q) 0.048 0.955 r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[26]/Q net (fo=2, routed) 0.113 1.068 SFP_GEN[20].ngCCM_gbt/gbt_rx_checker/Q[10] SLICE_X111Y545 FDRE r SFP_GEN[20].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.965 1.130 SFP_GEN[20].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y545 FDRE r SFP_GEN[20].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]/C clock pessimism -0.162 0.968 SLICE_X111Y545 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.024 SFP_GEN[20].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10] ------------------------------------------------------------------- required time -1.024 arrival time 1.068 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].rx_data_ngccm_reg[20][70]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.140ns (logic 0.048ns (34.286%) route 0.092ns (65.714%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.174ns Source Clock Delay (SCD): 0.959ns Clock Pessimism Removal (CPR): 0.175ns Clock Net Delay (Source): 0.841ns (routing 0.273ns, distribution 0.568ns) Clock Net Delay (Destination): 1.009ns (routing 0.314ns, distribution 0.695ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.841 0.959 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X123Y547 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X123Y547 FDRE (Prop_BFF2_SLICEL_C_Q) 0.048 1.007 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/Q net (fo=1, routed) 0.092 1.099 rx_data[20][70] SLICE_X124Y547 FDCE r SFP_GEN[20].rx_data_ngccm_reg[20][70]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.009 1.174 g_gbt_bank[1].gbtbank_n_104 SLICE_X124Y547 FDCE r SFP_GEN[20].rx_data_ngccm_reg[20][70]/C clock pessimism -0.175 0.999 SLICE_X124Y547 FDCE (Hold_GFF2_SLICEL_C_D) 0.056 1.055 SFP_GEN[20].rx_data_ngccm_reg[20][70] ------------------------------------------------------------------- required time -1.055 arrival time 1.099 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.044ns (arrival time - required time) Source: SFP_GEN[20].rx_data_ngccm_reg[20][30]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[30]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.183ns (logic 0.049ns (26.776%) route 0.134ns (73.224%)) Logic Levels: 0 Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.113ns Source Clock Delay (SCD): 0.900ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.782ns (routing 0.273ns, distribution 0.509ns) Clock Net Delay (Destination): 0.948ns (routing 0.314ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.782 0.900 g_gbt_bank[1].gbtbank_n_104 SLICE_X112Y548 FDCE r SFP_GEN[20].rx_data_ngccm_reg[20][30]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y548 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 0.949 r SFP_GEN[20].rx_data_ngccm_reg[20][30]/Q net (fo=1, routed) 0.134 1.083 SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[83]_0[22] SLICE_X111Y546 FDCE r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[30]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.948 1.113 SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y546 FDCE r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[30]/C clock pessimism -0.130 0.983 SLICE_X111Y546 FDCE (Hold_BFF2_SLICEL_C_D) 0.056 1.039 SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[30] ------------------------------------------------------------------- required time -1.039 arrival time 1.083 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.183ns (logic 0.094ns (51.366%) route 0.089ns (48.634%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.169ns Source Clock Delay (SCD): 0.947ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 0.829ns (routing 0.273ns, distribution 0.556ns) Clock Net Delay (Destination): 1.004ns (routing 0.314ns, distribution 0.690ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.829 0.947 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X120Y546 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X120Y546 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 0.996 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Q net (fo=1, routed) 0.073 1.069 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] SLICE_X121Y546 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.045 1.114 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__19/O net (fo=1, routed) 0.016 1.130 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[0] SLICE_X121Y546 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.004 1.169 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X121Y546 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.141 1.028 SLICE_X121Y546 FDRE (Hold_HFF_SLICEL_C_D) 0.056 1.084 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -1.084 arrival time 1.130 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: SFP_GEN[20].rx_data_ngccm_reg[20][27]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[27]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.185ns (logic 0.049ns (26.486%) route 0.136ns (73.514%)) Logic Levels: 0 Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.113ns Source Clock Delay (SCD): 0.900ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.782ns (routing 0.273ns, distribution 0.509ns) Clock Net Delay (Destination): 0.948ns (routing 0.314ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.782 0.900 g_gbt_bank[1].gbtbank_n_104 SLICE_X112Y548 FDCE r SFP_GEN[20].rx_data_ngccm_reg[20][27]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y548 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.949 r SFP_GEN[20].rx_data_ngccm_reg[20][27]/Q net (fo=1, routed) 0.136 1.085 SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[83]_0[19] SLICE_X111Y546 FDCE r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[27]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.948 1.113 SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y546 FDCE r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[27]/C clock pessimism -0.130 0.983 SLICE_X111Y546 FDCE (Hold_AFF2_SLICEL_C_D) 0.056 1.039 SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[27] ------------------------------------------------------------------- required time -1.039 arrival time 1.085 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.094ns (63.946%) route 0.053ns (36.054%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.116ns Source Clock Delay (SCD): 0.900ns Clock Pessimism Removal (CPR): 0.172ns Clock Net Delay (Source): 0.782ns (routing 0.273ns, distribution 0.509ns) Clock Net Delay (Destination): 0.951ns (routing 0.314ns, distribution 0.637ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.782 0.900 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X114Y549 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X114Y549 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 0.949 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Q net (fo=2, routed) 0.037 0.986 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_31_in SLICE_X114Y549 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.045 1.031 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__19/O net (fo=1, routed) 0.016 1.047 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[16] SLICE_X114Y549 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.951 1.116 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X114Y549 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.172 0.944 SLICE_X114Y549 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.000 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.000 arrival time 1.047 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.094ns (64.828%) route 0.051ns (35.172%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.115ns Source Clock Delay (SCD): 0.902ns Clock Pessimism Removal (CPR): 0.172ns Clock Net Delay (Source): 0.784ns (routing 0.273ns, distribution 0.511ns) Clock Net Delay (Destination): 0.950ns (routing 0.314ns, distribution 0.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.784 0.902 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X113Y549 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y549 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 0.951 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/Q net (fo=2, routed) 0.035 0.986 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_19_in SLICE_X113Y549 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.045 1.031 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__19/O net (fo=1, routed) 0.016 1.047 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[10] SLICE_X113Y549 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.950 1.115 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X113Y549 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C clock pessimism -0.172 0.943 SLICE_X113Y549 FDRE (Hold_CFF_SLICEM_C_D) 0.056 0.999 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10] ------------------------------------------------------------------- required time -0.999 arrival time 1.047 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.094ns (64.828%) route 0.051ns (35.172%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.115ns Source Clock Delay (SCD): 0.903ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.785ns (routing 0.273ns, distribution 0.512ns) Clock Net Delay (Destination): 0.950ns (routing 0.314ns, distribution 0.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.785 0.903 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X113Y548 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y548 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 0.952 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Q net (fo=1, routed) 0.035 0.987 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] SLICE_X113Y548 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.045 1.032 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__19/O net (fo=1, routed) 0.016 1.048 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[1] SLICE_X113Y548 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.950 1.115 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X113Y548 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.171 0.944 SLICE_X113Y548 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.000 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.000 arrival time 1.048 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.050ns (arrival time - required time) Source: SFP_GEN[20].rx_data_ngccm_reg[20][67]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[66]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.159ns (logic 0.112ns (70.440%) route 0.047ns (29.560%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.176ns Source Clock Delay (SCD): 0.957ns Clock Pessimism Removal (CPR): 0.166ns Clock Net Delay (Source): 0.839ns (routing 0.273ns, distribution 0.566ns) Clock Net Delay (Destination): 1.011ns (routing 0.314ns, distribution 0.697ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.839 0.957 g_gbt_bank[1].gbtbank_n_104 SLICE_X122Y548 FDCE r SFP_GEN[20].rx_data_ngccm_reg[20][67]/C ------------------------------------------------------------------- ------------------- SLICE_X122Y548 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.006 r SFP_GEN[20].rx_data_ngccm_reg[20][67]/Q net (fo=1, routed) 0.036 1.042 SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[83]_0[59] SLICE_X122Y547 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.063 1.105 r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40[66]_i_1/O net (fo=1, routed) 0.011 1.116 SFP_GEN[20].ngCCM_gbt/RX_Word_rx40[66]_i_1_n_0 SLICE_X122Y547 FDCE r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[66]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.011 1.176 SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X122Y547 FDCE r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[66]/C clock pessimism -0.166 1.010 SLICE_X122Y547 FDCE (Hold_DFF2_SLICEL_C_D) 0.056 1.066 SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[66] ------------------------------------------------------------------- required time -1.066 arrival time 1.116 ------------------------------------------------------------------- slack 0.050 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_22 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y235 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X120Y540 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X121Y540 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X104Y543 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X104Y543 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X104Y543 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X111Y545 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X118Y544 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X120Y540 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X111Y545 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X118Y544 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X121Y545 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[48]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X121Y545 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[48]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X122Y544 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[52]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X104Y543 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X104Y543 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X104Y543 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X104Y543 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X104Y543 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X104Y543 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_23 To Clock: gtwiz_userclk_rx_srcclk_out[0]_23 Setup : 0 Failing Endpoints, Worst Slack 2.775ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.036ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.775ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[112]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 5.262ns (logic 1.114ns (21.171%) route 4.148ns (78.829%)) Logic Levels: 0 Clock Path Skew: -0.309ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.299ns = ( 11.616 - 8.317 ) Source Clock Delay (SCD): 3.924ns Clock Pessimism Removal (CPR): 0.316ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.449ns (routing 1.356ns, distribution 2.093ns) Clock Net Delay (Destination): 2.901ns (routing 1.239ns, distribution 1.662ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.449 3.924 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[10]) 1.114 5.038 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[10] net (fo=6, routed) 4.148 9.186 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/D[12] SLICE_X98Y554 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[112]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.901 11.616 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X98Y554 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[112]/C clock pessimism 0.316 11.933 clock uncertainty -0.035 11.897 SLICE_X98Y554 FDCE (Setup_EFF_SLICEL_C_D) 0.064 11.961 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[112] ------------------------------------------------------------------- required time 11.961 arrival time -9.186 ------------------------------------------------------------------- slack 2.775 Slack (MET) : 2.853ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[74]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 5.196ns (logic 1.056ns (20.323%) route 4.140ns (79.677%)) Logic Levels: 0 Clock Path Skew: -0.299ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.309ns = ( 11.626 - 8.317 ) Source Clock Delay (SCD): 3.924ns Clock Pessimism Removal (CPR): 0.316ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.449ns (routing 1.356ns, distribution 2.093ns) Clock Net Delay (Destination): 2.911ns (routing 1.239ns, distribution 1.672ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.449 3.924 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[12]) 1.056 4.980 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[12] net (fo=6, routed) 4.140 9.120 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/D[14] SLICE_X97Y551 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[74]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.911 11.626 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X97Y551 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[74]/C clock pessimism 0.316 11.943 clock uncertainty -0.035 11.907 SLICE_X97Y551 FDCE (Setup_CFF2_SLICEM_C_D) 0.066 11.973 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[74] ------------------------------------------------------------------- required time 11.973 arrival time -9.120 ------------------------------------------------------------------- slack 2.853 Slack (MET) : 2.888ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[82]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 5.173ns (logic 1.084ns (20.955%) route 4.089ns (79.045%)) Logic Levels: 0 Clock Path Skew: -0.284ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.324ns = ( 11.641 - 8.317 ) Source Clock Delay (SCD): 3.924ns Clock Pessimism Removal (CPR): 0.316ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.449ns (routing 1.356ns, distribution 2.093ns) Clock Net Delay (Destination): 2.926ns (routing 1.239ns, distribution 1.687ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.449 3.924 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 5.008 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 4.089 9.097 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/D[2] SLICE_X98Y552 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[82]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.926 11.641 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X98Y552 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[82]/C clock pessimism 0.316 11.957 clock uncertainty -0.035 11.922 SLICE_X98Y552 FDCE (Setup_HFF_SLICEL_C_D) 0.063 11.985 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[82] ------------------------------------------------------------------- required time 11.985 arrival time -9.097 ------------------------------------------------------------------- slack 2.888 Slack (MET) : 2.898ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[21].rx_data_ngccm_reg[21][45]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 4.972ns (logic 0.375ns (7.542%) route 4.597ns (92.458%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.354ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.317ns = ( 11.634 - 8.317 ) Source Clock Delay (SCD): 3.987ns Clock Pessimism Removal (CPR): 0.316ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.512ns (routing 1.356ns, distribution 2.156ns) Clock Net Delay (Destination): 2.919ns (routing 1.239ns, distribution 1.680ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.512 3.987 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y563 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y563 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.127 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.744 6.871 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X94Y534 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.235 7.106 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[21].rx_data_ngccm[21][83]_i_1/O net (fo=76, routed) 1.853 8.959 rx_data_ngccm[21] SLICE_X97Y543 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][45]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.919 11.634 g_gbt_bank[1].gbtbank_n_114 SLICE_X97Y543 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][45]/C clock pessimism 0.316 11.951 clock uncertainty -0.035 11.915 SLICE_X97Y543 FDCE (Setup_EFF2_SLICEM_C_CE) -0.058 11.857 SFP_GEN[21].rx_data_ngccm_reg[21][45] ------------------------------------------------------------------- required time 11.857 arrival time -8.959 ------------------------------------------------------------------- slack 2.898 Slack (MET) : 2.900ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[21].rx_data_ngccm_reg[21][53]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 4.967ns (logic 0.375ns (7.550%) route 4.592ns (92.450%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.357ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.314ns = ( 11.631 - 8.317 ) Source Clock Delay (SCD): 3.987ns Clock Pessimism Removal (CPR): 0.316ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.512ns (routing 1.356ns, distribution 2.156ns) Clock Net Delay (Destination): 2.916ns (routing 1.239ns, distribution 1.677ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.512 3.987 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y563 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y563 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.127 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.744 6.871 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X94Y534 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.235 7.106 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[21].rx_data_ngccm[21][83]_i_1/O net (fo=76, routed) 1.848 8.954 rx_data_ngccm[21] SLICE_X99Y545 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][53]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.916 11.631 g_gbt_bank[1].gbtbank_n_114 SLICE_X99Y545 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][53]/C clock pessimism 0.316 11.948 clock uncertainty -0.035 11.912 SLICE_X99Y545 FDCE (Setup_EFF2_SLICEL_C_CE) -0.058 11.854 SFP_GEN[21].rx_data_ngccm_reg[21][53] ------------------------------------------------------------------- required time 11.854 arrival time -8.954 ------------------------------------------------------------------- slack 2.900 Slack (MET) : 2.900ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[21].rx_data_ngccm_reg[21][55]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 4.967ns (logic 0.375ns (7.550%) route 4.592ns (92.450%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.357ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.314ns = ( 11.631 - 8.317 ) Source Clock Delay (SCD): 3.987ns Clock Pessimism Removal (CPR): 0.316ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.512ns (routing 1.356ns, distribution 2.156ns) Clock Net Delay (Destination): 2.916ns (routing 1.239ns, distribution 1.677ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.512 3.987 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y563 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y563 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.127 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.744 6.871 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X94Y534 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.235 7.106 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[21].rx_data_ngccm[21][83]_i_1/O net (fo=76, routed) 1.848 8.954 rx_data_ngccm[21] SLICE_X99Y545 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][55]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.916 11.631 g_gbt_bank[1].gbtbank_n_114 SLICE_X99Y545 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][55]/C clock pessimism 0.316 11.948 clock uncertainty -0.035 11.912 SLICE_X99Y545 FDCE (Setup_FFF2_SLICEL_C_CE) -0.058 11.854 SFP_GEN[21].rx_data_ngccm_reg[21][55] ------------------------------------------------------------------- required time 11.854 arrival time -8.954 ------------------------------------------------------------------- slack 2.900 Slack (MET) : 2.900ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[21].rx_data_ngccm_reg[21][59]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 4.967ns (logic 0.375ns (7.550%) route 4.592ns (92.450%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.357ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.314ns = ( 11.631 - 8.317 ) Source Clock Delay (SCD): 3.987ns Clock Pessimism Removal (CPR): 0.316ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.512ns (routing 1.356ns, distribution 2.156ns) Clock Net Delay (Destination): 2.916ns (routing 1.239ns, distribution 1.677ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.512 3.987 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y563 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y563 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.127 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.744 6.871 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X94Y534 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.235 7.106 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[21].rx_data_ngccm[21][83]_i_1/O net (fo=76, routed) 1.848 8.954 rx_data_ngccm[21] SLICE_X99Y545 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][59]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.916 11.631 g_gbt_bank[1].gbtbank_n_114 SLICE_X99Y545 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][59]/C clock pessimism 0.316 11.948 clock uncertainty -0.035 11.912 SLICE_X99Y545 FDCE (Setup_GFF2_SLICEL_C_CE) -0.058 11.854 SFP_GEN[21].rx_data_ngccm_reg[21][59] ------------------------------------------------------------------- required time 11.854 arrival time -8.954 ------------------------------------------------------------------- slack 2.900 Slack (MET) : 2.904ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[21].rx_data_ngccm_reg[21][44]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 4.969ns (logic 0.375ns (7.547%) route 4.594ns (92.453%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.354ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.317ns = ( 11.634 - 8.317 ) Source Clock Delay (SCD): 3.987ns Clock Pessimism Removal (CPR): 0.316ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.512ns (routing 1.356ns, distribution 2.156ns) Clock Net Delay (Destination): 2.919ns (routing 1.239ns, distribution 1.680ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.512 3.987 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y563 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y563 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.127 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.744 6.871 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X94Y534 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.235 7.106 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[21].rx_data_ngccm[21][83]_i_1/O net (fo=76, routed) 1.850 8.956 rx_data_ngccm[21] SLICE_X97Y543 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][44]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.919 11.634 g_gbt_bank[1].gbtbank_n_114 SLICE_X97Y543 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][44]/C clock pessimism 0.316 11.951 clock uncertainty -0.035 11.915 SLICE_X97Y543 FDCE (Setup_EFF_SLICEM_C_CE) -0.055 11.860 SFP_GEN[21].rx_data_ngccm_reg[21][44] ------------------------------------------------------------------- required time 11.860 arrival time -8.956 ------------------------------------------------------------------- slack 2.904 Slack (MET) : 2.904ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[21].rx_data_ngccm_reg[21][46]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 4.969ns (logic 0.375ns (7.547%) route 4.594ns (92.453%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.354ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.317ns = ( 11.634 - 8.317 ) Source Clock Delay (SCD): 3.987ns Clock Pessimism Removal (CPR): 0.316ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.512ns (routing 1.356ns, distribution 2.156ns) Clock Net Delay (Destination): 2.919ns (routing 1.239ns, distribution 1.680ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.512 3.987 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y563 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y563 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.127 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.744 6.871 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X94Y534 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.235 7.106 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[21].rx_data_ngccm[21][83]_i_1/O net (fo=76, routed) 1.850 8.956 rx_data_ngccm[21] SLICE_X97Y543 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][46]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.919 11.634 g_gbt_bank[1].gbtbank_n_114 SLICE_X97Y543 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][46]/C clock pessimism 0.316 11.951 clock uncertainty -0.035 11.915 SLICE_X97Y543 FDCE (Setup_FFF_SLICEM_C_CE) -0.055 11.860 SFP_GEN[21].rx_data_ngccm_reg[21][46] ------------------------------------------------------------------- required time 11.860 arrival time -8.956 ------------------------------------------------------------------- slack 2.904 Slack (MET) : 2.907ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[21].rx_data_ngccm_reg[21][52]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 4.963ns (logic 0.375ns (7.556%) route 4.588ns (92.444%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.357ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.314ns = ( 11.631 - 8.317 ) Source Clock Delay (SCD): 3.987ns Clock Pessimism Removal (CPR): 0.316ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.512ns (routing 1.356ns, distribution 2.156ns) Clock Net Delay (Destination): 2.916ns (routing 1.239ns, distribution 1.677ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.512 3.987 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y563 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y563 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.127 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.744 6.871 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X94Y534 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.235 7.106 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[21].rx_data_ngccm[21][83]_i_1/O net (fo=76, routed) 1.844 8.950 rx_data_ngccm[21] SLICE_X99Y545 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][52]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.916 11.631 g_gbt_bank[1].gbtbank_n_114 SLICE_X99Y545 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][52]/C clock pessimism 0.316 11.948 clock uncertainty -0.035 11.912 SLICE_X99Y545 FDCE (Setup_EFF_SLICEL_C_CE) -0.055 11.857 SFP_GEN[21].rx_data_ngccm_reg[21][52] ------------------------------------------------------------------- required time 11.857 arrival time -8.950 ------------------------------------------------------------------- slack 2.907 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[21].rx_data_ngccm_reg[21][61]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.195ns (logic 0.048ns (24.615%) route 0.147ns (75.385%)) Logic Levels: 0 Clock Path Skew: 0.103ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.644ns Source Clock Delay (SCD): 1.362ns Clock Pessimism Removal (CPR): 0.179ns Clock Net Delay (Source): 1.244ns (routing 0.571ns, distribution 0.673ns) Clock Net Delay (Destination): 1.479ns (routing 0.638ns, distribution 0.841ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.244 1.362 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X96Y545 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y545 FDRE (Prop_GFF_SLICEL_C_Q) 0.048 1.410 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/Q net (fo=1, routed) 0.147 1.557 rx_data[21][61] SLICE_X97Y545 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][61]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.479 1.644 g_gbt_bank[1].gbtbank_n_114 SLICE_X97Y545 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][61]/C clock pessimism -0.179 1.465 SLICE_X97Y545 FDCE (Hold_AFF2_SLICEM_C_D) 0.056 1.521 SFP_GEN[21].rx_data_ngccm_reg[21][61] ------------------------------------------------------------------- required time -1.521 arrival time 1.557 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.198ns (logic 0.101ns (51.010%) route 0.097ns (48.990%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.103ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.644ns Source Clock Delay (SCD): 1.362ns Clock Pessimism Removal (CPR): 0.179ns Clock Net Delay (Source): 1.244ns (routing 0.571ns, distribution 0.673ns) Clock Net Delay (Destination): 1.479ns (routing 0.638ns, distribution 0.841ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.244 1.362 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X96Y546 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y546 FDCE (Prop_GFF_SLICEL_C_Q) 0.048 1.410 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.082 1.492 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_33_in SLICE_X97Y546 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.053 1.545 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__20/O net (fo=1, routed) 0.015 1.560 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[17] SLICE_X97Y546 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.479 1.644 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X97Y546 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.179 1.465 SLICE_X97Y546 FDRE (Hold_BFF_SLICEM_C_D) 0.056 1.521 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.521 arrival time 1.560 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.064ns (42.953%) route 0.085ns (57.047%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.054ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.643ns Source Clock Delay (SCD): 1.380ns Clock Pessimism Removal (CPR): 0.209ns Clock Net Delay (Source): 1.262ns (routing 0.571ns, distribution 0.691ns) Clock Net Delay (Destination): 1.478ns (routing 0.638ns, distribution 0.840ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.262 1.380 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X98Y547 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X98Y547 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 1.429 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.069 1.498 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in SLICE_X98Y546 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.015 1.513 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__20/O net (fo=1, routed) 0.016 1.529 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] SLICE_X98Y546 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.478 1.643 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X98Y546 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.209 1.434 SLICE_X98Y546 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.490 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.490 arrival time 1.529 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[21].rx_data_ngccm_reg[21][45]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.190ns (logic 0.048ns (25.263%) route 0.142ns (74.737%)) Logic Levels: 0 Clock Path Skew: 0.093ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.634ns Source Clock Delay (SCD): 1.362ns Clock Pessimism Removal (CPR): 0.179ns Clock Net Delay (Source): 1.244ns (routing 0.571ns, distribution 0.673ns) Clock Net Delay (Destination): 1.469ns (routing 0.638ns, distribution 0.831ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.244 1.362 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X96Y545 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y545 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 1.410 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/Q net (fo=1, routed) 0.142 1.552 rx_data[21][45] SLICE_X97Y543 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][45]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.469 1.634 g_gbt_bank[1].gbtbank_n_114 SLICE_X97Y543 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][45]/C clock pessimism -0.179 1.455 SLICE_X97Y543 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.510 SFP_GEN[21].rx_data_ngccm_reg[21][45] ------------------------------------------------------------------- required time -1.510 arrival time 1.552 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.201ns (logic 0.101ns (50.249%) route 0.100ns (49.751%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.102ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.643ns Source Clock Delay (SCD): 1.362ns Clock Pessimism Removal (CPR): 0.179ns Clock Net Delay (Source): 1.244ns (routing 0.571ns, distribution 0.673ns) Clock Net Delay (Destination): 1.478ns (routing 0.638ns, distribution 0.840ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.244 1.362 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X96Y546 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y546 FDCE (Prop_EFF2_SLICEL_C_Q) 0.048 1.410 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Q net (fo=2, routed) 0.084 1.494 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_29_in SLICE_X98Y546 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.053 1.547 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__20/O net (fo=1, routed) 0.016 1.563 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[13] SLICE_X98Y546 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.478 1.643 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X98Y546 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C clock pessimism -0.179 1.464 SLICE_X98Y546 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.520 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13] ------------------------------------------------------------------- required time -1.520 arrival time 1.563 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[21].rx_data_ngccm_reg[21][4]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.150ns (logic 0.048ns (32.000%) route 0.102ns (68.000%)) Logic Levels: 0 Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.768ns Source Clock Delay (SCD): 1.517ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.399ns (routing 0.571ns, distribution 0.828ns) Clock Net Delay (Destination): 1.603ns (routing 0.638ns, distribution 0.965ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.399 1.517 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X91Y547 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y547 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 1.565 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/Q net (fo=1, routed) 0.102 1.667 rx_data[21][4] SLICE_X93Y547 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.603 1.768 g_gbt_bank[1].gbtbank_n_114 SLICE_X93Y547 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][4]/C clock pessimism -0.201 1.567 SLICE_X93Y547 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.622 SFP_GEN[21].rx_data_ngccm_reg[21][4] ------------------------------------------------------------------- required time -1.622 arrival time 1.667 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: SFP_GEN[21].rx_data_ngccm_reg[21][75]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[74]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.178ns (logic 0.088ns (49.438%) route 0.090ns (50.562%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.632ns Source Clock Delay (SCD): 1.376ns Clock Pessimism Removal (CPR): 0.179ns Clock Net Delay (Source): 1.258ns (routing 0.571ns, distribution 0.687ns) Clock Net Delay (Destination): 1.467ns (routing 0.638ns, distribution 0.829ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.258 1.376 g_gbt_bank[1].gbtbank_n_114 SLICE_X99Y545 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][75]/C ------------------------------------------------------------------- ------------------- SLICE_X99Y545 FDCE (Prop_CFF2_SLICEL_C_Q) 0.048 1.424 r SFP_GEN[21].rx_data_ngccm_reg[21][75]/Q net (fo=1, routed) 0.078 1.502 SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[83]_0[67] SLICE_X100Y545 LUT3 (Prop_D5LUT_SLICEM_I0_O) 0.040 1.542 r SFP_GEN[21].ngCCM_gbt/RX_Word_rx40[74]_i_1/O net (fo=1, routed) 0.012 1.554 SFP_GEN[21].ngCCM_gbt/RX_Word_rx40[74]_i_1_n_0 SLICE_X100Y545 FDCE r SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[74]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.467 1.632 SFP_GEN[21].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X100Y545 FDCE r SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[74]/C clock pessimism -0.179 1.453 SLICE_X100Y545 FDCE (Hold_DFF2_SLICEM_C_D) 0.056 1.509 SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[74] ------------------------------------------------------------------- required time -1.509 arrival time 1.554 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[21].rx_data_ngccm_reg[21][71]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.048ns (33.803%) route 0.094ns (66.197%)) Logic Levels: 0 Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.626ns Source Clock Delay (SCD): 1.374ns Clock Pessimism Removal (CPR): 0.210ns Clock Net Delay (Source): 1.256ns (routing 0.571ns, distribution 0.685ns) Clock Net Delay (Destination): 1.461ns (routing 0.638ns, distribution 0.823ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.256 1.374 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X99Y548 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X99Y548 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 1.422 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/Q net (fo=1, routed) 0.094 1.516 rx_data[21][71] SLICE_X99Y547 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][71]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.461 1.626 g_gbt_bank[1].gbtbank_n_114 SLICE_X99Y547 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][71]/C clock pessimism -0.210 1.416 SLICE_X99Y547 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.471 SFP_GEN[21].rx_data_ngccm_reg[21][71] ------------------------------------------------------------------- required time -1.471 arrival time 1.516 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.094ns (64.828%) route 0.051ns (35.172%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.797ns Source Clock Delay (SCD): 1.517ns Clock Pessimism Removal (CPR): 0.239ns Clock Net Delay (Source): 1.399ns (routing 0.571ns, distribution 0.828ns) Clock Net Delay (Destination): 1.632ns (routing 0.638ns, distribution 0.994ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.399 1.517 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X90Y547 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X90Y547 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.566 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.035 1.601 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/feedbackRegister[0] SLICE_X90Y547 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.045 1.646 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__20/O net (fo=1, routed) 0.016 1.662 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[0] SLICE_X90Y547 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.632 1.797 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X90Y547 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C clock pessimism -0.239 1.558 SLICE_X90Y547 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.614 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19] ------------------------------------------------------------------- required time -1.614 arrival time 1.662 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.206ns (logic 0.111ns (53.883%) route 0.095ns (46.116%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.102ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.643ns Source Clock Delay (SCD): 1.362ns Clock Pessimism Removal (CPR): 0.179ns Clock Net Delay (Source): 1.244ns (routing 0.571ns, distribution 0.673ns) Clock Net Delay (Destination): 1.478ns (routing 0.638ns, distribution 0.840ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.244 1.362 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X96Y546 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y546 FDCE (Prop_EFF2_SLICEL_C_Q) 0.048 1.410 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Q net (fo=2, routed) 0.084 1.494 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_29_in SLICE_X98Y546 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.063 1.557 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__20/O net (fo=1, routed) 0.011 1.568 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[15] SLICE_X98Y546 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.478 1.643 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X98Y546 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C clock pessimism -0.179 1.464 SLICE_X98Y546 FDRE (Hold_DFF2_SLICEL_C_D) 0.056 1.520 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15] ------------------------------------------------------------------- required time -1.520 arrival time 1.568 ------------------------------------------------------------------- slack 0.048 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_23 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y216 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X98Y511 SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X98Y511 SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X91Y540 SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X91Y540 SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X91Y540 SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X91Y540 SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X98Y536 SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X81Y527 g_clock_rate_din[21].ngccm_status_cnt_reg[21][0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X81Y527 g_clock_rate_din[21].ngccm_status_cnt_reg[21][1]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X81Y527 g_clock_rate_din[21].ngccm_status_cnt_reg[21][2]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X81Y527 g_clock_rate_din[21].ngccm_status_cnt_reg[21][3]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X93Y526 g_clock_rate_din[21].ngccm_status_cnt_reg[21][6]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X93Y526 g_clock_rate_din[21].rx_test_comm_cnt_reg[21]/C High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X91Y540 SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X91Y540 SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X91Y540 SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X91Y540 SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X95Y531 SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[44]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X98Y513 SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[48]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_24 To Clock: gtwiz_userclk_rx_srcclk_out[0]_24 Setup : 0 Failing Endpoints, Worst Slack 2.549ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.035ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.549ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 5.770ns (logic 1.626ns (28.180%) route 4.144ns (71.820%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.092ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.635ns = ( 10.952 - 8.317 ) Source Clock Delay (SCD): 2.755ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.330ns (routing 0.794ns, distribution 1.536ns) Clock Net Delay (Destination): 2.259ns (routing 0.710ns, distribution 1.549ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.330 2.755 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.841 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.493 7.334 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] SLICE_X53Y152 LUT4 (Prop_H6LUT_SLICEM_I0_O) 0.244 7.578 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/O net (fo=5, routed) 0.250 7.828 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y154 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.146 7.974 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__23/O net (fo=1, routed) 0.076 8.050 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__23_n_0 SLICE_X53Y154 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.150 8.200 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__23/O net (fo=2, routed) 0.325 8.525 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__23_n_0 SLICE_X53Y154 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.259 10.952 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK SLICE_X53Y154 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.212 11.165 clock uncertainty -0.035 11.129 SLICE_X53Y154 FDCE (Setup_GFF_SLICEM_C_CE) -0.055 11.074 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.074 arrival time -8.525 ------------------------------------------------------------------- slack 2.549 Slack (MET) : 2.549ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 5.770ns (logic 1.626ns (28.180%) route 4.144ns (71.820%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.092ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.635ns = ( 10.952 - 8.317 ) Source Clock Delay (SCD): 2.755ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.330ns (routing 0.794ns, distribution 1.536ns) Clock Net Delay (Destination): 2.259ns (routing 0.710ns, distribution 1.549ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.330 2.755 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.841 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.493 7.334 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] SLICE_X53Y152 LUT4 (Prop_H6LUT_SLICEM_I0_O) 0.244 7.578 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/O net (fo=5, routed) 0.250 7.828 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y154 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.146 7.974 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__23/O net (fo=1, routed) 0.076 8.050 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__23_n_0 SLICE_X53Y154 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.150 8.200 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__23/O net (fo=2, routed) 0.325 8.525 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__23_n_0 SLICE_X53Y154 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.259 10.952 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK SLICE_X53Y154 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.212 11.165 clock uncertainty -0.035 11.129 SLICE_X53Y154 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 11.074 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.074 arrival time -8.525 ------------------------------------------------------------------- slack 2.549 Slack (MET) : 2.694ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 5.621ns (logic 1.420ns (25.262%) route 4.201ns (74.738%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.087ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.630ns = ( 10.947 - 8.317 ) Source Clock Delay (SCD): 2.755ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.330ns (routing 0.794ns, distribution 1.536ns) Clock Net Delay (Destination): 2.254ns (routing 0.710ns, distribution 1.544ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.330 2.755 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.841 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.493 7.334 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] SLICE_X53Y152 LUT4 (Prop_H6LUT_SLICEM_I0_O) 0.244 7.578 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/O net (fo=5, routed) 0.258 7.836 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y154 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.090 7.926 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__24/O net (fo=7, routed) 0.450 8.376 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 SLICE_X52Y152 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.254 10.947 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK SLICE_X52Y152 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.212 11.160 clock uncertainty -0.035 11.124 SLICE_X52Y152 FDRE (Setup_AFF_SLICEM_C_CE) -0.054 11.070 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 11.070 arrival time -8.376 ------------------------------------------------------------------- slack 2.694 Slack (MET) : 2.694ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 5.621ns (logic 1.420ns (25.262%) route 4.201ns (74.738%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.087ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.630ns = ( 10.947 - 8.317 ) Source Clock Delay (SCD): 2.755ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.330ns (routing 0.794ns, distribution 1.536ns) Clock Net Delay (Destination): 2.254ns (routing 0.710ns, distribution 1.544ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.330 2.755 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.841 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.493 7.334 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] SLICE_X53Y152 LUT4 (Prop_H6LUT_SLICEM_I0_O) 0.244 7.578 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/O net (fo=5, routed) 0.258 7.836 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y154 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.090 7.926 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__24/O net (fo=7, routed) 0.450 8.376 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 SLICE_X52Y152 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.254 10.947 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK SLICE_X52Y152 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.212 11.160 clock uncertainty -0.035 11.124 SLICE_X52Y152 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 11.070 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 11.070 arrival time -8.376 ------------------------------------------------------------------- slack 2.694 Slack (MET) : 2.725ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 5.567ns (logic 1.420ns (25.507%) route 4.147ns (74.493%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.608ns = ( 10.925 - 8.317 ) Source Clock Delay (SCD): 2.755ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.330ns (routing 0.794ns, distribution 1.536ns) Clock Net Delay (Destination): 2.232ns (routing 0.710ns, distribution 1.522ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.330 2.755 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.841 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.493 7.334 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] SLICE_X53Y152 LUT4 (Prop_H6LUT_SLICEM_I0_O) 0.244 7.578 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/O net (fo=5, routed) 0.258 7.836 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y154 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.090 7.926 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__24/O net (fo=7, routed) 0.396 8.322 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 SLICE_X51Y154 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.232 10.925 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK SLICE_X51Y154 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.212 11.138 clock uncertainty -0.035 11.102 SLICE_X51Y154 FDRE (Setup_EFF_SLICEL_C_CE) -0.055 11.047 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 11.047 arrival time -8.322 ------------------------------------------------------------------- slack 2.725 Slack (MET) : 2.738ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 5.572ns (logic 1.420ns (25.485%) route 4.152ns (74.515%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.629ns = ( 10.946 - 8.317 ) Source Clock Delay (SCD): 2.755ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.330ns (routing 0.794ns, distribution 1.536ns) Clock Net Delay (Destination): 2.253ns (routing 0.710ns, distribution 1.543ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.330 2.755 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.841 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.493 7.334 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] SLICE_X53Y152 LUT4 (Prop_H6LUT_SLICEM_I0_O) 0.244 7.578 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/O net (fo=5, routed) 0.258 7.836 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y154 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.090 7.926 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__24/O net (fo=7, routed) 0.401 8.327 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 SLICE_X52Y152 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.253 10.946 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK SLICE_X52Y152 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.212 11.159 clock uncertainty -0.035 11.123 SLICE_X52Y152 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 11.065 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.065 arrival time -8.327 ------------------------------------------------------------------- slack 2.738 Slack (MET) : 2.738ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 5.572ns (logic 1.420ns (25.485%) route 4.152ns (74.515%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.629ns = ( 10.946 - 8.317 ) Source Clock Delay (SCD): 2.755ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.330ns (routing 0.794ns, distribution 1.536ns) Clock Net Delay (Destination): 2.253ns (routing 0.710ns, distribution 1.543ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.330 2.755 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.841 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.493 7.334 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] SLICE_X53Y152 LUT4 (Prop_H6LUT_SLICEM_I0_O) 0.244 7.578 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/O net (fo=5, routed) 0.258 7.836 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y154 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.090 7.926 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__24/O net (fo=7, routed) 0.401 8.327 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 SLICE_X52Y152 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.253 10.946 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK SLICE_X52Y152 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.212 11.159 clock uncertainty -0.035 11.123 SLICE_X52Y152 FDRE (Setup_GFF2_SLICEM_C_CE) -0.058 11.065 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.065 arrival time -8.327 ------------------------------------------------------------------- slack 2.738 Slack (MET) : 2.744ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 5.569ns (logic 1.420ns (25.498%) route 4.149ns (74.502%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.629ns = ( 10.946 - 8.317 ) Source Clock Delay (SCD): 2.755ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.330ns (routing 0.794ns, distribution 1.536ns) Clock Net Delay (Destination): 2.253ns (routing 0.710ns, distribution 1.543ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.330 2.755 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.841 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.493 7.334 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] SLICE_X53Y152 LUT4 (Prop_H6LUT_SLICEM_I0_O) 0.244 7.578 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/O net (fo=5, routed) 0.258 7.836 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y154 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.090 7.926 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__24/O net (fo=7, routed) 0.398 8.324 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 SLICE_X52Y152 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.253 10.946 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK SLICE_X52Y152 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.212 11.159 clock uncertainty -0.035 11.123 SLICE_X52Y152 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 11.068 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 11.068 arrival time -8.324 ------------------------------------------------------------------- slack 2.744 Slack (MET) : 2.744ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 5.569ns (logic 1.420ns (25.498%) route 4.149ns (74.502%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.629ns = ( 10.946 - 8.317 ) Source Clock Delay (SCD): 2.755ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.330ns (routing 0.794ns, distribution 1.536ns) Clock Net Delay (Destination): 2.253ns (routing 0.710ns, distribution 1.543ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.330 2.755 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.841 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.493 7.334 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] SLICE_X53Y152 LUT4 (Prop_H6LUT_SLICEM_I0_O) 0.244 7.578 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/O net (fo=5, routed) 0.258 7.836 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y154 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.090 7.926 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__24/O net (fo=7, routed) 0.398 8.324 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 SLICE_X52Y152 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.253 10.946 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK SLICE_X52Y152 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.212 11.159 clock uncertainty -0.035 11.123 SLICE_X52Y152 FDRE (Setup_GFF_SLICEM_C_CE) -0.055 11.068 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.068 arrival time -8.324 ------------------------------------------------------------------- slack 2.744 Slack (MET) : 2.949ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 5.357ns (logic 1.420ns (26.507%) route 3.937ns (73.493%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.082ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.625ns = ( 10.942 - 8.317 ) Source Clock Delay (SCD): 2.755ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.330ns (routing 0.794ns, distribution 1.536ns) Clock Net Delay (Destination): 2.249ns (routing 0.710ns, distribution 1.539ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.330 2.755 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.841 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.493 7.334 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] SLICE_X53Y152 LUT4 (Prop_H6LUT_SLICEM_I0_O) 0.244 7.578 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/O net (fo=5, routed) 0.168 7.746 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y153 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.090 7.836 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__24/O net (fo=5, routed) 0.276 8.112 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 SLICE_X53Y153 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.249 10.942 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK SLICE_X53Y153 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.212 11.155 clock uncertainty -0.035 11.119 SLICE_X53Y153 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 11.061 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.061 arrival time -8.112 ------------------------------------------------------------------- slack 2.949 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.035ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[24].rx_data_ngccm_reg[24][43]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.167ns (logic 0.049ns (29.341%) route 0.118ns (70.659%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.123ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.007ns (routing 0.377ns, distribution 0.630ns) Clock Net Delay (Destination): 1.207ns (routing 0.443ns, distribution 0.764ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.123 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X57Y164 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y164 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.172 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/Q net (fo=1, routed) 0.118 1.290 rx_data[24][43] SLICE_X58Y164 FDCE r SFP_GEN[24].rx_data_ngccm_reg[24][43]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.207 1.359 g_gbt_bank[2].gbtbank_n_0 SLICE_X58Y164 FDCE r SFP_GEN[24].rx_data_ngccm_reg[24][43]/C clock pessimism -0.160 1.199 SLICE_X58Y164 FDCE (Hold_AFF_SLICEM_C_D) 0.056 1.255 SFP_GEN[24].rx_data_ngccm_reg[24][43] ------------------------------------------------------------------- required time -1.255 arrival time 1.290 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.035ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.169ns (logic 0.079ns (46.746%) route 0.090ns (53.254%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.356ns Source Clock Delay (SCD): 1.118ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.002ns (routing 0.377ns, distribution 0.625ns) Clock Net Delay (Destination): 1.204ns (routing 0.443ns, distribution 0.761ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.002 1.118 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X60Y150 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y150 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.167 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Q net (fo=2, routed) 0.076 1.243 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_23_in SLICE_X61Y150 LUT3 (Prop_G6LUT_SLICEM_I2_O) 0.030 1.273 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__23/O net (fo=1, routed) 0.014 1.287 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[10] SLICE_X61Y150 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.204 1.356 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X61Y150 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C clock pessimism -0.160 1.196 SLICE_X61Y150 FDRE (Hold_GFF_SLICEM_C_D) 0.056 1.252 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10] ------------------------------------------------------------------- required time -1.252 arrival time 1.287 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.171ns (logic 0.079ns (46.199%) route 0.092ns (53.801%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.360ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.005ns (routing 0.377ns, distribution 0.628ns) Clock Net Delay (Destination): 1.208ns (routing 0.443ns, distribution 0.765ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.005 1.121 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X60Y149 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y149 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 1.169 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Q net (fo=2, routed) 0.077 1.246 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_7_in SLICE_X61Y149 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.031 1.277 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__23/O net (fo=1, routed) 0.015 1.292 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[4] SLICE_X61Y149 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.208 1.360 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X61Y149 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.160 1.200 SLICE_X61Y149 FDRE (Hold_BFF_SLICEM_C_D) 0.056 1.256 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.256 arrival time 1.292 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.156ns (logic 0.103ns (66.026%) route 0.053ns (33.974%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.054ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.378ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.191ns Clock Net Delay (Source): 1.017ns (routing 0.377ns, distribution 0.640ns) Clock Net Delay (Destination): 1.226ns (routing 0.443ns, distribution 0.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.133 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X59Y164 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y164 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.182 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Q net (fo=2, routed) 0.037 1.219 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_25_in SLICE_X59Y163 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.054 1.273 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__23/O net (fo=1, routed) 0.016 1.289 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[13] SLICE_X59Y163 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.226 1.378 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X59Y163 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C clock pessimism -0.191 1.187 SLICE_X59Y163 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.243 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13] ------------------------------------------------------------------- required time -1.243 arrival time 1.289 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[24].rx_data_ngccm_reg[24][42]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.199ns (logic 0.048ns (24.121%) route 0.151ns (75.879%)) Logic Levels: 0 Clock Path Skew: 0.096ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.372ns Source Clock Delay (SCD): 1.116ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.000ns (routing 0.377ns, distribution 0.623ns) Clock Net Delay (Destination): 1.220ns (routing 0.443ns, distribution 0.777ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.000 1.116 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X54Y161 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y161 FDRE (Prop_HFF_SLICEL_C_Q) 0.048 1.164 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/Q net (fo=1, routed) 0.151 1.315 rx_data[24][42] SLICE_X55Y162 FDCE r SFP_GEN[24].rx_data_ngccm_reg[24][42]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.220 1.372 g_gbt_bank[2].gbtbank_n_0 SLICE_X55Y162 FDCE r SFP_GEN[24].rx_data_ngccm_reg[24][42]/C clock pessimism -0.160 1.212 SLICE_X55Y162 FDCE (Hold_EFF_SLICEM_C_D) 0.056 1.268 SFP_GEN[24].rx_data_ngccm_reg[24][42] ------------------------------------------------------------------- required time -1.268 arrival time 1.315 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.109ns (logic 0.064ns (58.716%) route 0.045ns (41.284%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.353ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.231ns Clock Net Delay (Source): 1.001ns (routing 0.377ns, distribution 0.624ns) Clock Net Delay (Destination): 1.201ns (routing 0.443ns, distribution 0.758ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.001 1.117 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/CLK SLICE_X53Y152 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X53Y152 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.166 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg/Q net (fo=2, routed) 0.033 1.199 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/ready_from_bitSlipCtrller_0 SLICE_X53Y152 LUT3 (Prop_A6LUT_SLICEM_I2_O) 0.015 1.214 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_i_1__23/O net (fo=1, routed) 0.012 1.226 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_i_1__23_n_0 SLICE_X53Y152 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.201 1.353 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/CLK SLICE_X53Y152 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg/C clock pessimism -0.231 1.122 SLICE_X53Y152 FDCE (Hold_AFF_SLICEM_C_D) 0.056 1.178 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg ------------------------------------------------------------------- required time -1.178 arrival time 1.226 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.148ns (logic 0.094ns (63.513%) route 0.054ns (36.486%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.363ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.005ns (routing 0.377ns, distribution 0.628ns) Clock Net Delay (Destination): 1.211ns (routing 0.443ns, distribution 0.768ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.005 1.121 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X59Y149 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y149 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.170 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.038 1.208 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/O83[1] SLICE_X59Y149 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.045 1.253 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__23/O net (fo=1, routed) 0.016 1.269 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/I7[1] SLICE_X59Y149 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.211 1.363 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X59Y149 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C clock pessimism -0.201 1.162 SLICE_X59Y149 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.218 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20] ------------------------------------------------------------------- required time -1.218 arrival time 1.269 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.180ns (logic 0.093ns (51.667%) route 0.087ns (48.333%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.358ns Source Clock Delay (SCD): 1.125ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.009ns (routing 0.377ns, distribution 0.632ns) Clock Net Delay (Destination): 1.206ns (routing 0.443ns, distribution 0.763ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.009 1.125 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X58Y164 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X58Y164 FDCE (Prop_FFF2_SLICEM_C_Q) 0.048 1.173 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Q net (fo=2, routed) 0.071 1.244 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_13_in SLICE_X57Y164 LUT3 (Prop_C6LUT_SLICEL_I2_O) 0.045 1.289 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__23/O net (fo=1, routed) 0.016 1.305 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[5] SLICE_X57Y164 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.206 1.358 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X57Y164 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism -0.160 1.198 SLICE_X57Y164 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.254 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time -1.254 arrival time 1.305 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.163ns (logic 0.079ns (48.466%) route 0.084ns (51.534%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.055ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.379ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.191ns Clock Net Delay (Source): 1.017ns (routing 0.377ns, distribution 0.640ns) Clock Net Delay (Destination): 1.227ns (routing 0.443ns, distribution 0.784ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.133 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X59Y164 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y164 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.182 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Q net (fo=2, routed) 0.068 1.250 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_25_in SLICE_X59Y165 LUT3 (Prop_C6LUT_SLICEM_I2_O) 0.030 1.280 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__23/O net (fo=1, routed) 0.016 1.296 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[11] SLICE_X59Y165 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.227 1.379 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X59Y165 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C clock pessimism -0.191 1.188 SLICE_X59Y165 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.244 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11] ------------------------------------------------------------------- required time -1.244 arrival time 1.296 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.184ns (logic 0.095ns (51.630%) route 0.089ns (48.370%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.356ns Source Clock Delay (SCD): 1.120ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.004ns (routing 0.377ns, distribution 0.627ns) Clock Net Delay (Destination): 1.204ns (routing 0.443ns, distribution 0.761ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.004 1.120 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X60Y150 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y150 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 1.169 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Q net (fo=2, routed) 0.077 1.246 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_27_in SLICE_X61Y150 LUT3 (Prop_F6LUT_SLICEM_I2_O) 0.046 1.292 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__23/O net (fo=1, routed) 0.012 1.304 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[12] SLICE_X61Y150 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.204 1.356 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X61Y150 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C clock pessimism -0.160 1.196 SLICE_X61Y150 FDRE (Hold_FFF_SLICEM_C_D) 0.056 1.252 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12] ------------------------------------------------------------------- required time -1.252 arrival time 1.304 ------------------------------------------------------------------- slack 0.052 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_24 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y67 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X65Y178 g_clock_rate_din[24].ngccm_status_cnt_reg[24][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X65Y178 g_clock_rate_din[24].ngccm_status_cnt_reg[24][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X68Y178 g_clock_rate_din[24].ngccm_status_cnt_reg[24][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X68Y178 g_clock_rate_din[24].ngccm_status_cnt_reg[24][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X68Y178 g_clock_rate_din[24].ngccm_status_cnt_reg[24][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X68Y178 g_clock_rate_din[24].ngccm_status_cnt_reg[24][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X68Y178 g_clock_rate_din[24].ngccm_status_cnt_reg[24][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X60Y163 SFP_GEN[24].ngCCM_gbt/RX_Word_rx40_reg[80]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X60Y163 SFP_GEN[24].ngCCM_gbt/RX_Word_rx40_reg[83]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X57Y165 SFP_GEN[24].rx_data_ngccm_reg[24][49]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X57Y165 SFP_GEN[24].rx_data_ngccm_reg[24][64]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X57Y165 SFP_GEN[24].rx_data_ngccm_reg[24][65]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X57Y165 SFP_GEN[24].rx_data_ngccm_reg[24][66]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X57Y173 SFP_GEN[24].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X57Y173 SFP_GEN[24].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[42]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X57Y173 SFP_GEN[24].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[44]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X57Y173 SFP_GEN[24].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[46]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X57Y173 SFP_GEN[24].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X57Y173 SFP_GEN[24].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[6]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_25 To Clock: gtwiz_userclk_rx_srcclk_out[0]_25 Setup : 0 Failing Endpoints, Worst Slack 3.157ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.035ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.157ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 4.901ns (logic 1.585ns (32.340%) route 3.316ns (67.660%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.169ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.328ns = ( 10.645 - 8.317 ) Source Clock Delay (SCD): 2.701ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.276ns (routing 0.759ns, distribution 1.517ns) Clock Net Delay (Destination): 1.952ns (routing 0.680ns, distribution 1.272ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.276 2.701 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.785 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.163 5.948 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X35Y273 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 6.192 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/O net (fo=5, routed) 0.374 6.566 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X36Y270 LUT4 (Prop_D5LUT_SLICEL_I2_O) 0.168 6.734 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__33/O net (fo=1, routed) 0.321 7.055 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__33_n_0 SLICE_X36Y271 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.089 7.144 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__33/O net (fo=2, routed) 0.458 7.602 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__33_n_0 SLICE_X35Y273 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.952 10.645 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y273 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.204 10.849 clock uncertainty -0.035 10.814 SLICE_X35Y273 FDCE (Setup_GFF_SLICEM_C_CE) -0.055 10.759 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.759 arrival time -7.602 ------------------------------------------------------------------- slack 3.157 Slack (MET) : 3.157ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 4.901ns (logic 1.585ns (32.340%) route 3.316ns (67.660%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.169ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.328ns = ( 10.645 - 8.317 ) Source Clock Delay (SCD): 2.701ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.276ns (routing 0.759ns, distribution 1.517ns) Clock Net Delay (Destination): 1.952ns (routing 0.680ns, distribution 1.272ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.276 2.701 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.785 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.163 5.948 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X35Y273 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 6.192 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/O net (fo=5, routed) 0.374 6.566 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X36Y270 LUT4 (Prop_D5LUT_SLICEL_I2_O) 0.168 6.734 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__33/O net (fo=1, routed) 0.321 7.055 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__33_n_0 SLICE_X36Y271 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.089 7.144 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__33/O net (fo=2, routed) 0.458 7.602 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__33_n_0 SLICE_X35Y273 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.952 10.645 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y273 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.204 10.849 clock uncertainty -0.035 10.814 SLICE_X35Y273 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 10.759 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.759 arrival time -7.602 ------------------------------------------------------------------- slack 3.157 Slack (MET) : 3.333ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 4.723ns (logic 1.563ns (33.093%) route 3.160ns (66.907%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.171ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.326ns = ( 10.643 - 8.317 ) Source Clock Delay (SCD): 2.701ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.276ns (routing 0.759ns, distribution 1.517ns) Clock Net Delay (Destination): 1.950ns (routing 0.680ns, distribution 1.270ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.276 2.701 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.785 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.163 5.948 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X35Y273 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 6.192 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/O net (fo=5, routed) 0.288 6.480 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X36Y271 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.235 6.715 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__34/O net (fo=5, routed) 0.709 7.424 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 SLICE_X36Y271 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.950 10.643 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X36Y271 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism 0.204 10.847 clock uncertainty -0.035 10.812 SLICE_X36Y271 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 10.757 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time 10.757 arrival time -7.424 ------------------------------------------------------------------- slack 3.333 Slack (MET) : 3.697ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 4.360ns (logic 1.563ns (35.849%) route 2.797ns (64.151%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.170ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.327ns = ( 10.644 - 8.317 ) Source Clock Delay (SCD): 2.701ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.276ns (routing 0.759ns, distribution 1.517ns) Clock Net Delay (Destination): 1.951ns (routing 0.680ns, distribution 1.271ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.276 2.701 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.785 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.163 5.948 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X35Y273 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 6.192 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/O net (fo=5, routed) 0.288 6.480 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X36Y271 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.235 6.715 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__34/O net (fo=5, routed) 0.346 7.061 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 SLICE_X35Y271 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.951 10.644 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y271 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.204 10.848 clock uncertainty -0.035 10.813 SLICE_X35Y271 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 10.758 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 10.758 arrival time -7.061 ------------------------------------------------------------------- slack 3.697 Slack (MET) : 3.697ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 4.360ns (logic 1.563ns (35.849%) route 2.797ns (64.151%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.170ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.327ns = ( 10.644 - 8.317 ) Source Clock Delay (SCD): 2.701ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.276ns (routing 0.759ns, distribution 1.517ns) Clock Net Delay (Destination): 1.951ns (routing 0.680ns, distribution 1.271ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.276 2.701 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.785 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.163 5.948 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X35Y273 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 6.192 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/O net (fo=5, routed) 0.288 6.480 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X36Y271 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.235 6.715 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__34/O net (fo=5, routed) 0.346 7.061 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 SLICE_X35Y271 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.951 10.644 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y271 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.204 10.848 clock uncertainty -0.035 10.813 SLICE_X35Y271 FDRE (Setup_BFF2_SLICEM_C_CE) -0.055 10.758 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 10.758 arrival time -7.061 ------------------------------------------------------------------- slack 3.697 Slack (MET) : 3.701ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 4.357ns (logic 1.563ns (35.873%) route 2.794ns (64.127%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.170ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.327ns = ( 10.644 - 8.317 ) Source Clock Delay (SCD): 2.701ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.276ns (routing 0.759ns, distribution 1.517ns) Clock Net Delay (Destination): 1.951ns (routing 0.680ns, distribution 1.271ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.276 2.701 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.785 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.163 5.948 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X35Y273 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 6.192 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/O net (fo=5, routed) 0.288 6.480 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X36Y271 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.235 6.715 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__34/O net (fo=5, routed) 0.343 7.058 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 SLICE_X35Y271 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.951 10.644 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y271 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C clock pessimism 0.204 10.848 clock uncertainty -0.035 10.813 SLICE_X35Y271 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 10.759 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0] ------------------------------------------------------------------- required time 10.759 arrival time -7.058 ------------------------------------------------------------------- slack 3.701 Slack (MET) : 3.701ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 4.357ns (logic 1.563ns (35.873%) route 2.794ns (64.127%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.170ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.327ns = ( 10.644 - 8.317 ) Source Clock Delay (SCD): 2.701ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.276ns (routing 0.759ns, distribution 1.517ns) Clock Net Delay (Destination): 1.951ns (routing 0.680ns, distribution 1.271ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.276 2.701 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.785 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.163 5.948 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X35Y273 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 6.192 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/O net (fo=5, routed) 0.288 6.480 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X36Y271 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.235 6.715 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__34/O net (fo=5, routed) 0.343 7.058 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 SLICE_X35Y271 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.951 10.644 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y271 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C clock pessimism 0.204 10.848 clock uncertainty -0.035 10.813 SLICE_X35Y271 FDRE (Setup_BFF_SLICEM_C_CE) -0.054 10.759 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2] ------------------------------------------------------------------- required time 10.759 arrival time -7.058 ------------------------------------------------------------------- slack 3.701 Slack (MET) : 3.764ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 4.276ns (logic 1.379ns (32.250%) route 2.897ns (67.750%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.187ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.310ns = ( 10.627 - 8.317 ) Source Clock Delay (SCD): 2.701ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.276ns (routing 0.759ns, distribution 1.517ns) Clock Net Delay (Destination): 1.934ns (routing 0.680ns, distribution 1.254ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.276 2.701 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.785 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.163 5.948 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X35Y273 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 6.192 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/O net (fo=5, routed) 0.272 6.464 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X36Y271 LUT5 (Prop_C6LUT_SLICEL_I3_O) 0.051 6.515 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__34/O net (fo=7, routed) 0.462 6.977 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 SLICE_X36Y270 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.934 10.627 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X36Y270 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.204 10.831 clock uncertainty -0.035 10.796 SLICE_X36Y270 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 10.741 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 10.741 arrival time -6.977 ------------------------------------------------------------------- slack 3.764 Slack (MET) : 3.764ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 4.276ns (logic 1.379ns (32.250%) route 2.897ns (67.750%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.187ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.310ns = ( 10.627 - 8.317 ) Source Clock Delay (SCD): 2.701ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.276ns (routing 0.759ns, distribution 1.517ns) Clock Net Delay (Destination): 1.934ns (routing 0.680ns, distribution 1.254ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.276 2.701 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.785 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.163 5.948 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X35Y273 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 6.192 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/O net (fo=5, routed) 0.272 6.464 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X36Y271 LUT5 (Prop_C6LUT_SLICEL_I3_O) 0.051 6.515 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__34/O net (fo=7, routed) 0.462 6.977 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 SLICE_X36Y270 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.934 10.627 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X36Y270 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.204 10.831 clock uncertainty -0.035 10.796 SLICE_X36Y270 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 10.741 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 10.741 arrival time -6.977 ------------------------------------------------------------------- slack 3.764 Slack (MET) : 3.769ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 4.272ns (logic 1.379ns (32.280%) route 2.893ns (67.720%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.187ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.310ns = ( 10.627 - 8.317 ) Source Clock Delay (SCD): 2.701ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.276ns (routing 0.759ns, distribution 1.517ns) Clock Net Delay (Destination): 1.934ns (routing 0.680ns, distribution 1.254ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.276 2.701 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.785 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.163 5.948 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X35Y273 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 6.192 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/O net (fo=5, routed) 0.272 6.464 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X36Y271 LUT5 (Prop_C6LUT_SLICEL_I3_O) 0.051 6.515 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__34/O net (fo=7, routed) 0.458 6.973 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 SLICE_X36Y270 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.934 10.627 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X36Y270 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.204 10.831 clock uncertainty -0.035 10.796 SLICE_X36Y270 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 10.742 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 10.742 arrival time -6.973 ------------------------------------------------------------------- slack 3.769 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.035ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.167ns (logic 0.079ns (47.305%) route 0.088ns (52.695%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.221ns Source Clock Delay (SCD): 1.003ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.887ns (routing 0.364ns, distribution 0.523ns) Clock Net Delay (Destination): 1.069ns (routing 0.427ns, distribution 0.642ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.887 1.003 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X27Y283 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X27Y283 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.052 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Q net (fo=2, routed) 0.074 1.126 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_5_in SLICE_X28Y283 LUT3 (Prop_G6LUT_SLICEM_I2_O) 0.030 1.156 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__33/O net (fo=1, routed) 0.014 1.170 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[1] SLICE_X28Y283 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.069 1.221 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X28Y283 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.142 1.079 SLICE_X28Y283 FDRE (Hold_GFF_SLICEM_C_D) 0.056 1.135 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.135 arrival time 1.170 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.037ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.186ns (logic 0.094ns (50.538%) route 0.092ns (49.462%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.093ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.241ns Source Clock Delay (SCD): 1.006ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.890ns (routing 0.364ns, distribution 0.526ns) Clock Net Delay (Destination): 1.089ns (routing 0.427ns, distribution 0.662ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.890 1.006 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X24Y282 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X24Y282 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.055 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Q net (fo=2, routed) 0.076 1.131 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_7_in SLICE_X25Y282 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.045 1.176 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__33/O net (fo=1, routed) 0.016 1.192 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[4] SLICE_X25Y282 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.089 1.241 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X25Y282 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.142 1.099 SLICE_X25Y282 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.155 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.155 arrival time 1.192 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[44]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[44]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.160ns (logic 0.049ns (30.625%) route 0.111ns (69.375%)) Logic Levels: 0 Clock Path Skew: 0.064ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.200ns Source Clock Delay (SCD): 0.994ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.878ns (routing 0.364ns, distribution 0.514ns) Clock Net Delay (Destination): 1.048ns (routing 0.427ns, distribution 0.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.878 0.994 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X33Y278 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[44]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y278 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 1.043 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[44]/Q net (fo=1, routed) 0.111 1.154 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0[44] SLICE_X34Y278 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[44]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.048 1.200 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X34Y278 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[44]/C clock pessimism -0.142 1.058 SLICE_X34Y278 FDCE (Hold_CFF2_SLICEM_C_D) 0.056 1.114 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[44] ------------------------------------------------------------------- required time -1.114 arrival time 1.154 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.174ns (logic 0.087ns (50.000%) route 0.087ns (50.000%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.221ns Source Clock Delay (SCD): 1.003ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.887ns (routing 0.364ns, distribution 0.523ns) Clock Net Delay (Destination): 1.069ns (routing 0.427ns, distribution 0.642ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.887 1.003 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X27Y283 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X27Y283 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.052 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Q net (fo=2, routed) 0.074 1.126 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_5_in SLICE_X28Y283 LUT3 (Prop_G5LUT_SLICEM_I0_O) 0.038 1.164 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[3]_i_1__33/O net (fo=1, routed) 0.013 1.177 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[3] SLICE_X28Y283 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.069 1.221 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X28Y283 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C clock pessimism -0.142 1.079 SLICE_X28Y283 FDRE (Hold_GFF2_SLICEM_C_D) 0.056 1.135 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3] ------------------------------------------------------------------- required time -1.135 arrival time 1.177 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[34].rx_data_ngccm_reg[34][55]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.152ns (logic 0.049ns (32.237%) route 0.103ns (67.763%)) Logic Levels: 0 Clock Path Skew: 0.051ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.241ns Source Clock Delay (SCD): 1.016ns Clock Pessimism Removal (CPR): 0.174ns Clock Net Delay (Source): 0.900ns (routing 0.364ns, distribution 0.536ns) Clock Net Delay (Destination): 1.089ns (routing 0.427ns, distribution 0.662ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.900 1.016 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X25Y283 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X25Y283 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 1.065 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/Q net (fo=1, routed) 0.103 1.168 rx_data[34][55] SLICE_X25Y285 FDCE r SFP_GEN[34].rx_data_ngccm_reg[34][55]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.089 1.241 g_gbt_bank[2].gbtbank_n_124 SLICE_X25Y285 FDCE r SFP_GEN[34].rx_data_ngccm_reg[34][55]/C clock pessimism -0.174 1.067 SLICE_X25Y285 FDCE (Hold_GFF_SLICEM_C_D) 0.056 1.123 SFP_GEN[34].rx_data_ngccm_reg[34][55] ------------------------------------------------------------------- required time -1.123 arrival time 1.168 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[34].rx_data_ngccm_reg[34][67]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.169ns (logic 0.048ns (28.402%) route 0.121ns (71.598%)) Logic Levels: 0 Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.225ns Source Clock Delay (SCD): 1.016ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.900ns (routing 0.364ns, distribution 0.536ns) Clock Net Delay (Destination): 1.073ns (routing 0.427ns, distribution 0.646ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.900 1.016 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X25Y282 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X25Y282 FDRE (Prop_CFF_SLICEM_C_Q) 0.048 1.064 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/Q net (fo=1, routed) 0.121 1.185 rx_data[34][67] SLICE_X24Y282 FDCE r SFP_GEN[34].rx_data_ngccm_reg[34][67]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.073 1.225 g_gbt_bank[2].gbtbank_n_124 SLICE_X24Y282 FDCE r SFP_GEN[34].rx_data_ngccm_reg[34][67]/C clock pessimism -0.142 1.083 SLICE_X24Y282 FDCE (Hold_BFF_SLICEL_C_D) 0.056 1.139 SFP_GEN[34].rx_data_ngccm_reg[34][67] ------------------------------------------------------------------- required time -1.139 arrival time 1.185 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[34].rx_data_ngccm_reg[34][53]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.156ns (logic 0.049ns (31.410%) route 0.107ns (68.590%)) Logic Levels: 0 Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.242ns Source Clock Delay (SCD): 1.016ns Clock Pessimism Removal (CPR): 0.174ns Clock Net Delay (Source): 0.900ns (routing 0.364ns, distribution 0.536ns) Clock Net Delay (Destination): 1.090ns (routing 0.427ns, distribution 0.663ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.900 1.016 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X26Y284 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X26Y284 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.065 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/Q net (fo=1, routed) 0.107 1.172 rx_data[34][53] SLICE_X26Y285 FDCE r SFP_GEN[34].rx_data_ngccm_reg[34][53]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.090 1.242 g_gbt_bank[2].gbtbank_n_124 SLICE_X26Y285 FDCE r SFP_GEN[34].rx_data_ngccm_reg[34][53]/C clock pessimism -0.174 1.069 SLICE_X26Y285 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.125 SFP_GEN[34].rx_data_ngccm_reg[34][53] ------------------------------------------------------------------- required time -1.124 arrival time 1.172 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[34]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[34]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.148ns (logic 0.049ns (33.108%) route 0.099ns (66.892%)) Logic Levels: 0 Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.215ns Source Clock Delay (SCD): 1.000ns Clock Pessimism Removal (CPR): 0.173ns Clock Net Delay (Source): 0.884ns (routing 0.364ns, distribution 0.520ns) Clock Net Delay (Destination): 1.063ns (routing 0.427ns, distribution 0.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.884 1.000 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X29Y278 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[34]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y278 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.049 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[34]/Q net (fo=1, routed) 0.099 1.148 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0[34] SLICE_X29Y279 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[34]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.063 1.215 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X29Y279 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[34]/C clock pessimism -0.173 1.042 SLICE_X29Y279 FDCE (Hold_GFF_SLICEM_C_D) 0.056 1.098 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[34] ------------------------------------------------------------------- required time -1.098 arrival time 1.148 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.234ns Source Clock Delay (SCD): 1.010ns Clock Pessimism Removal (CPR): 0.186ns Clock Net Delay (Source): 0.894ns (routing 0.364ns, distribution 0.530ns) Clock Net Delay (Destination): 1.082ns (routing 0.427ns, distribution 0.655ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.894 1.010 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X24Y283 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X24Y283 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.059 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Q net (fo=2, routed) 0.034 1.093 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_3_in SLICE_X24Y283 LUT3 (Prop_C6LUT_SLICEL_I2_O) 0.045 1.138 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__33/O net (fo=1, routed) 0.016 1.154 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[0] SLICE_X24Y283 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.082 1.234 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X24Y283 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.186 1.048 SLICE_X24Y283 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.104 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -1.104 arrival time 1.154 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.188ns (logic 0.095ns (50.532%) route 0.093ns (49.468%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.224ns Source Clock Delay (SCD): 1.001ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.885ns (routing 0.364ns, distribution 0.521ns) Clock Net Delay (Destination): 1.072ns (routing 0.427ns, distribution 0.645ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.885 1.001 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X27Y285 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X27Y285 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.050 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Q net (fo=2, routed) 0.077 1.127 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_7_in SLICE_X28Y285 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.046 1.173 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__33/O net (fo=1, routed) 0.016 1.189 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[4] SLICE_X28Y285 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.072 1.224 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X28Y285 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.142 1.082 SLICE_X28Y285 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.138 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.138 arrival time 1.189 ------------------------------------------------------------------- slack 0.051 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_25 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y112 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X62Y272 g_clock_rate_din[34].ngccm_status_cnt_reg[34][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X61Y271 g_clock_rate_din[34].ngccm_status_cnt_reg[34][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X60Y270 g_clock_rate_din[34].ngccm_status_cnt_reg[34][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X60Y270 g_clock_rate_din[34].ngccm_status_cnt_reg[34][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X60Y270 g_clock_rate_din[34].ngccm_status_cnt_reg[34][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X61Y271 g_clock_rate_din[34].ngccm_status_cnt_reg[34][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X64Y269 g_clock_rate_din[34].ngccm_status_cnt_reg[34][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X35Y274 SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[28]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X35Y274 SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[80]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X35Y274 SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[81]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X36Y274 SFP_GEN[34].rx_data_ngccm_reg[34][28]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X27Y283 SFP_GEN[34].rx_data_ngccm_reg[34][42]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X27Y283 SFP_GEN[34].rx_data_ngccm_reg[34][43]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X62Y272 g_clock_rate_din[34].ngccm_status_cnt_reg[34][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X61Y271 g_clock_rate_din[34].ngccm_status_cnt_reg[34][1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X61Y271 g_clock_rate_din[34].ngccm_status_cnt_reg[34][5]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X61Y271 g_clock_rate_din[34].ngccm_status_cnt_reg[34][7]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X27Y284 SFP_GEN[34].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[48]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X27Y284 SFP_GEN[34].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[50]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_26 To Clock: gtwiz_userclk_rx_srcclk_out[0]_26 Setup : 0 Failing Endpoints, Worst Slack 3.276ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.033ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.276ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 5.053ns (logic 1.548ns (30.635%) route 3.505ns (69.365%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.102ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.638ns = ( 10.955 - 8.317 ) Source Clock Delay (SCD): 2.750ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.325ns (routing 0.781ns, distribution 1.544ns) Clock Net Delay (Destination): 2.262ns (routing 0.697ns, distribution 1.565ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.325 2.750 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.911 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.657 6.568 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X48Y295 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.237 6.805 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/O net (fo=5, routed) 0.380 7.185 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X49Y298 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.150 7.335 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__35/O net (fo=3, routed) 0.468 7.803 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 SLICE_X52Y299 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.262 10.955 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X52Y299 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.214 11.170 clock uncertainty -0.035 11.134 SLICE_X52Y299 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 11.079 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 11.079 arrival time -7.803 ------------------------------------------------------------------- slack 3.276 Slack (MET) : 3.280ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 5.050ns (logic 1.548ns (30.653%) route 3.502ns (69.347%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.102ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.638ns = ( 10.955 - 8.317 ) Source Clock Delay (SCD): 2.750ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.325ns (routing 0.781ns, distribution 1.544ns) Clock Net Delay (Destination): 2.262ns (routing 0.697ns, distribution 1.565ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.325 2.750 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.911 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.657 6.568 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X48Y295 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.237 6.805 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/O net (fo=5, routed) 0.380 7.185 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X49Y298 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.150 7.335 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__35/O net (fo=3, routed) 0.465 7.800 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 SLICE_X52Y299 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.262 10.955 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X52Y299 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.214 11.170 clock uncertainty -0.035 11.134 SLICE_X52Y299 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 11.080 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 11.080 arrival time -7.800 ------------------------------------------------------------------- slack 3.280 Slack (MET) : 3.288ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 5.039ns (logic 1.548ns (30.720%) route 3.491ns (69.280%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.100ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.636ns = ( 10.953 - 8.317 ) Source Clock Delay (SCD): 2.750ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.325ns (routing 0.781ns, distribution 1.544ns) Clock Net Delay (Destination): 2.260ns (routing 0.697ns, distribution 1.563ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.325 2.750 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.911 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.657 6.568 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X48Y295 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.237 6.805 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/O net (fo=5, routed) 0.380 7.185 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X49Y298 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.150 7.335 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__35/O net (fo=3, routed) 0.454 7.789 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 SLICE_X52Y299 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.260 10.953 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X52Y299 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C clock pessimism 0.214 11.168 clock uncertainty -0.035 11.132 SLICE_X52Y299 FDRE (Setup_EFF_SLICEM_C_CE) -0.055 11.077 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2] ------------------------------------------------------------------- required time 11.077 arrival time -7.789 ------------------------------------------------------------------- slack 3.288 Slack (MET) : 3.412ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 4.904ns (logic 1.490ns (30.383%) route 3.414ns (69.617%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.089ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.625ns = ( 10.942 - 8.317 ) Source Clock Delay (SCD): 2.750ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.325ns (routing 0.781ns, distribution 1.544ns) Clock Net Delay (Destination): 2.249ns (routing 0.697ns, distribution 1.552ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.325 2.750 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.911 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.657 6.568 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X48Y295 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.237 6.805 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/O net (fo=5, routed) 0.389 7.194 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X49Y297 LUT6 (Prop_B6LUT_SLICEM_I0_O) 0.092 7.286 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__35/O net (fo=5, routed) 0.368 7.654 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 SLICE_X48Y298 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.249 10.942 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y298 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.214 11.157 clock uncertainty -0.035 11.121 SLICE_X48Y298 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 11.066 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.066 arrival time -7.654 ------------------------------------------------------------------- slack 3.412 Slack (MET) : 3.412ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 4.904ns (logic 1.490ns (30.383%) route 3.414ns (69.617%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.089ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.625ns = ( 10.942 - 8.317 ) Source Clock Delay (SCD): 2.750ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.325ns (routing 0.781ns, distribution 1.544ns) Clock Net Delay (Destination): 2.249ns (routing 0.697ns, distribution 1.552ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.325 2.750 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.911 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.657 6.568 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X48Y295 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.237 6.805 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/O net (fo=5, routed) 0.389 7.194 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X49Y297 LUT6 (Prop_B6LUT_SLICEM_I0_O) 0.092 7.286 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__35/O net (fo=5, routed) 0.368 7.654 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 SLICE_X48Y298 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.249 10.942 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y298 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.214 11.157 clock uncertainty -0.035 11.121 SLICE_X48Y298 FDRE (Setup_BFF2_SLICEL_C_CE) -0.055 11.066 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 11.066 arrival time -7.654 ------------------------------------------------------------------- slack 3.412 Slack (MET) : 3.417ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 4.900ns (logic 1.490ns (30.408%) route 3.410ns (69.592%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.089ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.625ns = ( 10.942 - 8.317 ) Source Clock Delay (SCD): 2.750ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.325ns (routing 0.781ns, distribution 1.544ns) Clock Net Delay (Destination): 2.249ns (routing 0.697ns, distribution 1.552ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.325 2.750 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.911 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.657 6.568 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X48Y295 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.237 6.805 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/O net (fo=5, routed) 0.389 7.194 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X49Y297 LUT6 (Prop_B6LUT_SLICEM_I0_O) 0.092 7.286 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__35/O net (fo=5, routed) 0.364 7.650 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 SLICE_X48Y298 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.249 10.942 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y298 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C clock pessimism 0.214 11.157 clock uncertainty -0.035 11.121 SLICE_X48Y298 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 11.067 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0] ------------------------------------------------------------------- required time 11.067 arrival time -7.650 ------------------------------------------------------------------- slack 3.417 Slack (MET) : 3.417ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 4.900ns (logic 1.490ns (30.408%) route 3.410ns (69.592%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.089ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.625ns = ( 10.942 - 8.317 ) Source Clock Delay (SCD): 2.750ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.325ns (routing 0.781ns, distribution 1.544ns) Clock Net Delay (Destination): 2.249ns (routing 0.697ns, distribution 1.552ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.325 2.750 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.911 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.657 6.568 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X48Y295 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.237 6.805 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/O net (fo=5, routed) 0.389 7.194 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X49Y297 LUT6 (Prop_B6LUT_SLICEM_I0_O) 0.092 7.286 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__35/O net (fo=5, routed) 0.364 7.650 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 SLICE_X48Y298 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.249 10.942 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y298 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C clock pessimism 0.214 11.157 clock uncertainty -0.035 11.121 SLICE_X48Y298 FDRE (Setup_BFF_SLICEL_C_CE) -0.054 11.067 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2] ------------------------------------------------------------------- required time 11.067 arrival time -7.650 ------------------------------------------------------------------- slack 3.417 Slack (MET) : 3.435ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 4.879ns (logic 1.490ns (30.539%) route 3.389ns (69.461%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.087ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.623ns = ( 10.940 - 8.317 ) Source Clock Delay (SCD): 2.750ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.325ns (routing 0.781ns, distribution 1.544ns) Clock Net Delay (Destination): 2.247ns (routing 0.697ns, distribution 1.550ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.325 2.750 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.911 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.657 6.568 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X48Y295 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.237 6.805 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/O net (fo=5, routed) 0.389 7.194 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X49Y297 LUT6 (Prop_B6LUT_SLICEM_I0_O) 0.092 7.286 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__35/O net (fo=5, routed) 0.343 7.629 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 SLICE_X48Y297 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.247 10.940 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y297 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism 0.214 11.155 clock uncertainty -0.035 11.119 SLICE_X48Y297 FDRE (Setup_GFF_SLICEL_C_CE) -0.055 11.064 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time 11.064 arrival time -7.629 ------------------------------------------------------------------- slack 3.435 Slack (MET) : 3.469ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 4.848ns (logic 1.598ns (32.962%) route 3.250ns (67.038%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.089ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.625ns = ( 10.942 - 8.317 ) Source Clock Delay (SCD): 2.750ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.325ns (routing 0.781ns, distribution 1.544ns) Clock Net Delay (Destination): 2.249ns (routing 0.697ns, distribution 1.552ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.325 2.750 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.911 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.657 6.568 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X48Y295 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.237 6.805 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/O net (fo=5, routed) 0.181 6.986 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X48Y297 LUT4 (Prop_H6LUT_SLICEL_I2_O) 0.147 7.133 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__34/O net (fo=1, routed) 0.164 7.297 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__34_n_0 SLICE_X48Y295 LUT6 (Prop_H6LUT_SLICEL_I5_O) 0.053 7.350 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__34/O net (fo=2, routed) 0.248 7.598 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__34_n_0 SLICE_X48Y295 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.249 10.942 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y295 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.214 11.157 clock uncertainty -0.035 11.121 SLICE_X48Y295 FDCE (Setup_AFF_SLICEL_C_CE) -0.054 11.067 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.067 arrival time -7.598 ------------------------------------------------------------------- slack 3.469 Slack (MET) : 3.469ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 4.848ns (logic 1.598ns (32.962%) route 3.250ns (67.038%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.089ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.625ns = ( 10.942 - 8.317 ) Source Clock Delay (SCD): 2.750ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.325ns (routing 0.781ns, distribution 1.544ns) Clock Net Delay (Destination): 2.249ns (routing 0.697ns, distribution 1.552ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.325 2.750 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.911 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.657 6.568 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X48Y295 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.237 6.805 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/O net (fo=5, routed) 0.181 6.986 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X48Y297 LUT4 (Prop_H6LUT_SLICEL_I2_O) 0.147 7.133 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__34/O net (fo=1, routed) 0.164 7.297 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__34_n_0 SLICE_X48Y295 LUT6 (Prop_H6LUT_SLICEL_I5_O) 0.053 7.350 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__34/O net (fo=2, routed) 0.248 7.598 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__34_n_0 SLICE_X48Y295 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.249 10.942 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y295 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.214 11.157 clock uncertainty -0.035 11.121 SLICE_X48Y295 FDCE (Setup_CFF_SLICEL_C_CE) -0.054 11.067 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.067 arrival time -7.598 ------------------------------------------------------------------- slack 3.469 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.033ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[35].rx_data_ngccm_reg[35][59]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.178ns (logic 0.048ns (26.966%) route 0.130ns (73.034%)) Logic Levels: 0 Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.392ns Source Clock Delay (SCD): 1.145ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.029ns (routing 0.373ns, distribution 0.656ns) Clock Net Delay (Destination): 1.240ns (routing 0.438ns, distribution 0.802ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.029 1.145 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X61Y290 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y290 FDRE (Prop_CFF_SLICEM_C_Q) 0.048 1.193 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/Q net (fo=1, routed) 0.130 1.323 rx_data[35][59] SLICE_X62Y290 FDCE r SFP_GEN[35].rx_data_ngccm_reg[35][59]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.240 1.392 g_gbt_bank[2].gbtbank_n_134 SLICE_X62Y290 FDCE r SFP_GEN[35].rx_data_ngccm_reg[35][59]/C clock pessimism -0.158 1.234 SLICE_X62Y290 FDCE (Hold_BFF_SLICEM_C_D) 0.056 1.290 SFP_GEN[35].rx_data_ngccm_reg[35][59] ------------------------------------------------------------------- required time -1.290 arrival time 1.323 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.035ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.063ns (43.448%) route 0.082ns (56.552%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.054ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.374ns Source Clock Delay (SCD): 1.130ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 1.014ns (routing 0.373ns, distribution 0.641ns) Clock Net Delay (Destination): 1.222ns (routing 0.438ns, distribution 0.784ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.130 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X54Y287 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y287 FDCE (Prop_EFF2_SLICEL_C_Q) 0.048 1.178 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.068 1.246 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/O83[1] SLICE_X54Y286 LUT3 (Prop_G6LUT_SLICEL_I0_O) 0.015 1.261 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__34/O net (fo=1, routed) 0.014 1.275 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/I7[1] SLICE_X54Y286 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.222 1.374 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X54Y286 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C clock pessimism -0.190 1.184 SLICE_X54Y286 FDRE (Hold_GFF_SLICEL_C_D) 0.056 1.240 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20] ------------------------------------------------------------------- required time -1.240 arrival time 1.275 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.038ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.181ns (logic 0.093ns (51.381%) route 0.088ns (48.619%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.381ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.020ns (routing 0.373ns, distribution 0.647ns) Clock Net Delay (Destination): 1.229ns (routing 0.438ns, distribution 0.791ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.136 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X60Y290 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y290 FDCE (Prop_GFF2_SLICEL_C_Q) 0.048 1.184 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.076 1.260 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/O84[1] SLICE_X61Y290 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.045 1.305 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__34/O net (fo=1, routed) 0.012 1.317 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[1] SLICE_X61Y290 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.229 1.381 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X61Y290 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C clock pessimism -0.158 1.223 SLICE_X61Y290 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.279 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20] ------------------------------------------------------------------- required time -1.279 arrival time 1.317 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.183ns (logic 0.093ns (50.820%) route 0.090ns (49.180%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.379ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.020ns (routing 0.373ns, distribution 0.647ns) Clock Net Delay (Destination): 1.227ns (routing 0.438ns, distribution 0.789ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.136 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X60Y290 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y290 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.184 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Q net (fo=2, routed) 0.076 1.260 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_5_in SLICE_X61Y290 LUT3 (Prop_G6LUT_SLICEM_I2_O) 0.045 1.305 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__34/O net (fo=1, routed) 0.014 1.319 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[1] SLICE_X61Y290 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.227 1.379 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X61Y290 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.158 1.221 SLICE_X61Y290 FDRE (Hold_GFF_SLICEM_C_D) 0.056 1.277 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.277 arrival time 1.319 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[34]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[34]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.160ns (logic 0.049ns (30.625%) route 0.111ns (69.375%)) Logic Levels: 0 Clock Path Skew: 0.059ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.383ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.188ns Clock Net Delay (Source): 1.020ns (routing 0.373ns, distribution 0.647ns) Clock Net Delay (Destination): 1.231ns (routing 0.438ns, distribution 0.793ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.136 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y294 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[34]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y294 FDCE (Prop_BFF_SLICEM_C_Q) 0.049 1.185 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[34]/Q net (fo=1, routed) 0.111 1.296 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[34] SLICE_X59Y295 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[34]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.231 1.383 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y295 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[34]/C clock pessimism -0.188 1.195 SLICE_X59Y295 FDCE (Hold_HFF2_SLICEM_C_D) 0.056 1.251 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[34] ------------------------------------------------------------------- required time -1.251 arrival time 1.296 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.094ns (66.197%) route 0.048ns (33.803%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.376ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.202ns Clock Net Delay (Source): 1.020ns (routing 0.373ns, distribution 0.647ns) Clock Net Delay (Destination): 1.224ns (routing 0.438ns, distribution 0.786ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.136 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X53Y286 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y286 FDCE (Prop_BFF2_SLICEM_C_Q) 0.048 1.184 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Q net (fo=2, routed) 0.036 1.220 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_13_in SLICE_X53Y286 LUT3 (Prop_F6LUT_SLICEM_I2_O) 0.046 1.266 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__34/O net (fo=1, routed) 0.012 1.278 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[5] SLICE_X53Y286 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.224 1.376 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X53Y286 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism -0.202 1.174 SLICE_X53Y286 FDRE (Hold_FFF_SLICEM_C_D) 0.056 1.230 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time -1.230 arrival time 1.278 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.094ns (66.197%) route 0.048ns (33.803%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.376ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.202ns Clock Net Delay (Source): 1.020ns (routing 0.373ns, distribution 0.647ns) Clock Net Delay (Destination): 1.224ns (routing 0.438ns, distribution 0.786ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.136 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X53Y286 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y286 FDCE (Prop_DFF_SLICEM_C_Q) 0.049 1.185 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Q net (fo=2, routed) 0.036 1.221 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_29_in SLICE_X53Y286 LUT3 (Prop_E6LUT_SLICEM_I2_O) 0.045 1.266 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__34/O net (fo=1, routed) 0.012 1.278 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[13] SLICE_X53Y286 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.224 1.376 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X53Y286 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C clock pessimism -0.202 1.174 SLICE_X53Y286 FDRE (Hold_EFF_SLICEM_C_D) 0.056 1.230 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13] ------------------------------------------------------------------- required time -1.230 arrival time 1.278 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[35].rx_data_ngccm_reg[35][68]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.140ns (logic 0.049ns (35.000%) route 0.091ns (65.000%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.397ns Source Clock Delay (SCD): 1.156ns Clock Pessimism Removal (CPR): 0.205ns Clock Net Delay (Source): 1.040ns (routing 0.373ns, distribution 0.667ns) Clock Net Delay (Destination): 1.245ns (routing 0.438ns, distribution 0.807ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.040 1.156 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X62Y292 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y292 FDRE (Prop_AFF_SLICEM_C_Q) 0.049 1.205 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/Q net (fo=1, routed) 0.091 1.296 rx_data[35][68] SLICE_X63Y292 FDCE r SFP_GEN[35].rx_data_ngccm_reg[35][68]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.245 1.397 g_gbt_bank[2].gbtbank_n_134 SLICE_X63Y292 FDCE r SFP_GEN[35].rx_data_ngccm_reg[35][68]/C clock pessimism -0.205 1.192 SLICE_X63Y292 FDCE (Hold_GFF2_SLICEL_C_D) 0.056 1.248 SFP_GEN[35].rx_data_ngccm_reg[35][68] ------------------------------------------------------------------- required time -1.248 arrival time 1.296 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[35].rx_data_ngccm_reg[35][52]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.049ns (32.886%) route 0.100ns (67.114%)) Logic Levels: 0 Clock Path Skew: 0.046ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.379ns Source Clock Delay (SCD): 1.141ns Clock Pessimism Removal (CPR): 0.192ns Clock Net Delay (Source): 1.025ns (routing 0.373ns, distribution 0.652ns) Clock Net Delay (Destination): 1.227ns (routing 0.438ns, distribution 0.789ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.025 1.141 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X61Y292 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y292 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 1.190 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/Q net (fo=1, routed) 0.100 1.290 rx_data[35][52] SLICE_X61Y291 FDCE r SFP_GEN[35].rx_data_ngccm_reg[35][52]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.227 1.379 g_gbt_bank[2].gbtbank_n_134 SLICE_X61Y291 FDCE r SFP_GEN[35].rx_data_ngccm_reg[35][52]/C clock pessimism -0.192 1.187 SLICE_X61Y291 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.242 SFP_GEN[35].rx_data_ngccm_reg[35][52] ------------------------------------------------------------------- required time -1.242 arrival time 1.290 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[35].rx_data_ngccm_reg[35][39]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.196ns (logic 0.048ns (24.490%) route 0.148ns (75.510%)) Logic Levels: 0 Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.375ns Source Clock Delay (SCD): 1.126ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.010ns (routing 0.373ns, distribution 0.637ns) Clock Net Delay (Destination): 1.223ns (routing 0.438ns, distribution 0.785ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.010 1.126 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X56Y285 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y285 FDRE (Prop_GFF2_SLICEL_C_Q) 0.048 1.174 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/Q net (fo=1, routed) 0.148 1.322 rx_data[35][39] SLICE_X53Y285 FDCE r SFP_GEN[35].rx_data_ngccm_reg[35][39]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.223 1.375 g_gbt_bank[2].gbtbank_n_134 SLICE_X53Y285 FDCE r SFP_GEN[35].rx_data_ngccm_reg[35][39]/C clock pessimism -0.158 1.217 SLICE_X53Y285 FDCE (Hold_HFF_SLICEM_C_D) 0.056 1.273 SFP_GEN[35].rx_data_ngccm_reg[35][39] ------------------------------------------------------------------- required time -1.273 arrival time 1.322 ------------------------------------------------------------------- slack 0.049 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_26 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y115 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X61Y276 g_clock_rate_din[35].ngccm_status_cnt_reg[35][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X61Y270 g_clock_rate_din[35].ngccm_status_cnt_reg[35][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X59Y274 g_clock_rate_din[35].ngccm_status_cnt_reg[35][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X59Y274 g_clock_rate_din[35].ngccm_status_cnt_reg[35][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X61Y276 g_clock_rate_din[35].ngccm_status_cnt_reg[35][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X61Y270 g_clock_rate_din[35].ngccm_status_cnt_reg[35][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X61Y270 g_clock_rate_din[35].ngccm_status_cnt_reg[35][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDPE/C n/a 0.275 4.159 3.884 SLICE_X54Y296 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X62Y292 SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[60]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X62Y292 SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[62]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X61Y290 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X61Y290 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X61Y290 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X59Y274 g_clock_rate_din[35].ngccm_status_cnt_reg[35][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X59Y274 g_clock_rate_din[35].ngccm_status_cnt_reg[35][3]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X58Y296 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[11].rx_data_good_cntr_reg[11][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X58Y296 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[11].rx_data_good_cntr_reg[11][1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X58Y296 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[11].rx_data_good_cntr_reg[11][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X58Y296 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[11].rx_data_good_cntr_reg[11][3]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_27 To Clock: gtwiz_userclk_rx_srcclk_out[0]_27 Setup : 0 Failing Endpoints, Worst Slack 2.930ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.031ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.930ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 5.420ns (logic 1.586ns (29.262%) route 3.834ns (70.738%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.123ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.639ns = ( 10.956 - 8.317 ) Source Clock Delay (SCD): 2.727ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.302ns (routing 0.789ns, distribution 1.513ns) Clock Net Delay (Destination): 2.263ns (routing 0.708ns, distribution 1.555ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.302 2.727 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.831 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.897 6.728 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X54Y173 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.238 6.966 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/O net (fo=5, routed) 0.534 7.500 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y173 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.244 7.744 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__25/O net (fo=7, routed) 0.403 8.147 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X53Y172 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.263 10.956 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y172 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.211 11.167 clock uncertainty -0.035 11.132 SLICE_X53Y172 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 11.077 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 11.077 arrival time -8.147 ------------------------------------------------------------------- slack 2.930 Slack (MET) : 2.930ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 5.420ns (logic 1.586ns (29.262%) route 3.834ns (70.738%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.123ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.639ns = ( 10.956 - 8.317 ) Source Clock Delay (SCD): 2.727ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.302ns (routing 0.789ns, distribution 1.513ns) Clock Net Delay (Destination): 2.263ns (routing 0.708ns, distribution 1.555ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.302 2.727 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.831 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.897 6.728 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X54Y173 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.238 6.966 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/O net (fo=5, routed) 0.534 7.500 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y173 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.244 7.744 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__25/O net (fo=7, routed) 0.403 8.147 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X53Y172 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.263 10.956 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y172 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.211 11.167 clock uncertainty -0.035 11.132 SLICE_X53Y172 FDRE (Setup_GFF_SLICEM_C_CE) -0.055 11.077 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 11.077 arrival time -8.147 ------------------------------------------------------------------- slack 2.930 Slack (MET) : 2.979ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 5.373ns (logic 1.586ns (29.518%) route 3.787ns (70.482%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.125ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.641ns = ( 10.958 - 8.317 ) Source Clock Delay (SCD): 2.727ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.302ns (routing 0.789ns, distribution 1.513ns) Clock Net Delay (Destination): 2.265ns (routing 0.708ns, distribution 1.557ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.302 2.727 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.831 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.897 6.728 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X54Y173 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.238 6.966 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/O net (fo=5, routed) 0.534 7.500 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y173 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.244 7.744 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__25/O net (fo=7, routed) 0.356 8.100 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X53Y172 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.265 10.958 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y172 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.211 11.169 clock uncertainty -0.035 11.134 SLICE_X53Y172 FDRE (Setup_BFF2_SLICEM_C_CE) -0.055 11.079 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.079 arrival time -8.100 ------------------------------------------------------------------- slack 2.979 Slack (MET) : 2.983ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 5.370ns (logic 1.586ns (29.534%) route 3.784ns (70.466%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.125ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.641ns = ( 10.958 - 8.317 ) Source Clock Delay (SCD): 2.727ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.302ns (routing 0.789ns, distribution 1.513ns) Clock Net Delay (Destination): 2.265ns (routing 0.708ns, distribution 1.557ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.302 2.727 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.831 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.897 6.728 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X54Y173 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.238 6.966 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/O net (fo=5, routed) 0.534 7.500 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y173 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.244 7.744 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__25/O net (fo=7, routed) 0.353 8.097 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X53Y172 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.265 10.958 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y172 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.211 11.169 clock uncertainty -0.035 11.134 SLICE_X53Y172 FDRE (Setup_BFF_SLICEM_C_CE) -0.054 11.080 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.080 arrival time -8.097 ------------------------------------------------------------------- slack 2.983 Slack (MET) : 3.006ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 5.327ns (logic 1.586ns (29.773%) route 3.741ns (70.227%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.106ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.622ns = ( 10.939 - 8.317 ) Source Clock Delay (SCD): 2.727ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.302ns (routing 0.789ns, distribution 1.513ns) Clock Net Delay (Destination): 2.246ns (routing 0.708ns, distribution 1.538ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.302 2.727 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.831 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.897 6.728 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X54Y173 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.238 6.966 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/O net (fo=5, routed) 0.534 7.500 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y173 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.244 7.744 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__25/O net (fo=7, routed) 0.310 8.054 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X52Y173 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.246 10.939 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X52Y173 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.211 11.150 clock uncertainty -0.035 11.115 SLICE_X52Y173 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 11.060 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.060 arrival time -8.054 ------------------------------------------------------------------- slack 3.006 Slack (MET) : 3.010ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 5.324ns (logic 1.586ns (29.790%) route 3.738ns (70.210%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.106ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.622ns = ( 10.939 - 8.317 ) Source Clock Delay (SCD): 2.727ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.302ns (routing 0.789ns, distribution 1.513ns) Clock Net Delay (Destination): 2.246ns (routing 0.708ns, distribution 1.538ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.302 2.727 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.831 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.897 6.728 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X54Y173 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.238 6.966 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/O net (fo=5, routed) 0.534 7.500 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y173 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.244 7.744 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__25/O net (fo=7, routed) 0.307 8.051 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X52Y173 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.246 10.939 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X52Y173 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.211 11.150 clock uncertainty -0.035 11.115 SLICE_X52Y173 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 11.061 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 11.061 arrival time -8.051 ------------------------------------------------------------------- slack 3.010 Slack (MET) : 3.010ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 5.324ns (logic 1.586ns (29.790%) route 3.738ns (70.210%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.106ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.622ns = ( 10.939 - 8.317 ) Source Clock Delay (SCD): 2.727ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.302ns (routing 0.789ns, distribution 1.513ns) Clock Net Delay (Destination): 2.246ns (routing 0.708ns, distribution 1.538ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.302 2.727 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.831 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.897 6.728 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X54Y173 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.238 6.966 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/O net (fo=5, routed) 0.534 7.500 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y173 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.244 7.744 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__25/O net (fo=7, routed) 0.307 8.051 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X52Y173 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.246 10.939 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X52Y173 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.211 11.150 clock uncertainty -0.035 11.115 SLICE_X52Y173 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 11.061 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 11.061 arrival time -8.051 ------------------------------------------------------------------- slack 3.010 Slack (MET) : 3.153ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 5.192ns (logic 1.605ns (30.913%) route 3.587ns (69.087%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.633ns = ( 10.950 - 8.317 ) Source Clock Delay (SCD): 2.727ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.302ns (routing 0.789ns, distribution 1.513ns) Clock Net Delay (Destination): 2.257ns (routing 0.708ns, distribution 1.549ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.302 2.727 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.831 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.897 6.728 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X54Y173 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.238 6.966 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/O net (fo=5, routed) 0.256 7.222 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y172 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.090 7.312 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__24/O net (fo=1, routed) 0.084 7.396 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__24_n_0 SLICE_X53Y172 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 7.569 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__24/O net (fo=2, routed) 0.350 7.919 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__24_n_0 SLICE_X55Y172 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.257 10.950 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X55Y172 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.211 11.161 clock uncertainty -0.035 11.126 SLICE_X55Y172 FDCE (Setup_BFF_SLICEM_C_CE) -0.054 11.072 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.072 arrival time -7.919 ------------------------------------------------------------------- slack 3.153 Slack (MET) : 3.153ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 5.192ns (logic 1.605ns (30.913%) route 3.587ns (69.087%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.633ns = ( 10.950 - 8.317 ) Source Clock Delay (SCD): 2.727ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.302ns (routing 0.789ns, distribution 1.513ns) Clock Net Delay (Destination): 2.257ns (routing 0.708ns, distribution 1.549ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.302 2.727 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.831 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.897 6.728 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X54Y173 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.238 6.966 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/O net (fo=5, routed) 0.256 7.222 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y172 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.090 7.312 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__24/O net (fo=1, routed) 0.084 7.396 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__24_n_0 SLICE_X53Y172 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 7.569 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__24/O net (fo=2, routed) 0.350 7.919 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__24_n_0 SLICE_X55Y172 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.257 10.950 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X55Y172 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.211 11.161 clock uncertainty -0.035 11.126 SLICE_X55Y172 FDCE (Setup_CFF_SLICEM_C_CE) -0.054 11.072 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.072 arrival time -7.919 ------------------------------------------------------------------- slack 3.153 Slack (MET) : 3.187ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[116]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 5.316ns (logic 1.087ns (20.448%) route 4.229ns (79.552%)) Logic Levels: 0 Clock Path Skew: 0.157ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.673ns = ( 10.990 - 8.317 ) Source Clock Delay (SCD): 2.727ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.302ns (routing 0.789ns, distribution 1.513ns) Clock Net Delay (Destination): 2.297ns (routing 0.708ns, distribution 1.589ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.302 2.727 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[14]) 1.087 3.814 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[14] net (fo=6, routed) 4.229 8.043 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/D[16] SLICE_X63Y178 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[116]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.297 10.990 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y178 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[116]/C clock pessimism 0.211 11.201 clock uncertainty -0.035 11.166 SLICE_X63Y178 FDCE (Setup_EFF_SLICEL_C_D) 0.064 11.230 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[116] ------------------------------------------------------------------- required time 11.230 arrival time -8.043 ------------------------------------------------------------------- slack 3.187 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.031ns (arrival time - required time) Source: SFP_GEN[25].rx_data_ngccm_reg[25][69]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[68]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.179ns (logic 0.094ns (52.514%) route 0.085ns (47.486%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.092ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.371ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.005ns (routing 0.376ns, distribution 0.629ns) Clock Net Delay (Destination): 1.219ns (routing 0.440ns, distribution 0.779ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.005 1.121 g_gbt_bank[2].gbtbank_n_34 SLICE_X54Y175 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][69]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y175 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.169 r SFP_GEN[25].rx_data_ngccm_reg[25][69]/Q net (fo=1, routed) 0.073 1.242 g_gbt_bank[2].gbtbank/RX_Word_rx40_reg[78][45] SLICE_X55Y175 LUT3 (Prop_F6LUT_SLICEM_I0_O) 0.046 1.288 r g_gbt_bank[2].gbtbank/RX_Word_rx40[68]_i_1__4/O net (fo=1, routed) 0.012 1.300 SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[83]_0[38] SLICE_X55Y175 FDCE r SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[68]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.219 1.371 SFP_GEN[25].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X55Y175 FDCE r SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[68]/C clock pessimism -0.158 1.213 SLICE_X55Y175 FDCE (Hold_FFF_SLICEM_C_D) 0.056 1.269 SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[68] ------------------------------------------------------------------- required time -1.269 arrival time 1.300 ------------------------------------------------------------------- slack 0.031 Slack (MET) : 0.032ns (arrival time - required time) Source: SFP_GEN[25].ngCCM_gbt/pwr_good_pre_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[25].ngCCM_gbt/pwr_good_cnt_reg/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.196ns (logic 0.064ns (32.653%) route 0.132ns (67.347%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.108ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.393ns Source Clock Delay (SCD): 1.127ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.011ns (routing 0.376ns, distribution 0.635ns) Clock Net Delay (Destination): 1.241ns (routing 0.440ns, distribution 0.801ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.011 1.127 SFP_GEN[25].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X60Y178 FDCE r SFP_GEN[25].ngCCM_gbt/pwr_good_pre_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y178 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 1.176 r SFP_GEN[25].ngCCM_gbt/pwr_good_pre_reg/Q net (fo=1, routed) 0.116 1.292 SFP_GEN[25].ngCCM_gbt/pwr_good_pre SLICE_X62Y178 LUT4 (Prop_C6LUT_SLICEM_I1_O) 0.015 1.307 r SFP_GEN[25].ngCCM_gbt/pwr_good_cnt_i_1__4/O net (fo=1, routed) 0.016 1.323 SFP_GEN[25].ngCCM_gbt/pwr_good_cnt_i_1__4_n_0 SLICE_X62Y178 FDRE r SFP_GEN[25].ngCCM_gbt/pwr_good_cnt_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.241 1.393 SFP_GEN[25].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X62Y178 FDRE r SFP_GEN[25].ngCCM_gbt/pwr_good_cnt_reg/C clock pessimism -0.158 1.235 SLICE_X62Y178 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.291 SFP_GEN[25].ngCCM_gbt/pwr_good_cnt_reg ------------------------------------------------------------------- required time -1.291 arrival time 1.323 ------------------------------------------------------------------- slack 0.032 Slack (MET) : 0.033ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[93]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.049ns (34.028%) route 0.095ns (65.972%)) Logic Levels: 0 Clock Path Skew: 0.055ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.391ns Source Clock Delay (SCD): 1.145ns Clock Pessimism Removal (CPR): 0.191ns Clock Net Delay (Source): 1.029ns (routing 0.376ns, distribution 0.653ns) Clock Net Delay (Destination): 1.239ns (routing 0.440ns, distribution 0.799ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.029 1.145 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y175 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y175 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.194 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]/Q net (fo=1, routed) 0.095 1.289 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[93] SLICE_X63Y176 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[93]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.239 1.391 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y176 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[93]/C clock pessimism -0.191 1.200 SLICE_X63Y176 FDCE (Hold_AFF2_SLICEL_C_D) 0.056 1.256 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[93] ------------------------------------------------------------------- required time -1.256 arrival time 1.289 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[23]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[23]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.165ns (logic 0.048ns (29.091%) route 0.117ns (70.909%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.376ns Source Clock Delay (SCD): 1.145ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.029ns (routing 0.376ns, distribution 0.653ns) Clock Net Delay (Destination): 1.224ns (routing 0.440ns, distribution 0.784ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.029 1.145 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y174 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[23]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y174 FDCE (Prop_HFF_SLICEL_C_Q) 0.048 1.193 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[23]/Q net (fo=1, routed) 0.117 1.310 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[23] SLICE_X64Y175 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.224 1.376 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X64Y175 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[23]/C clock pessimism -0.158 1.218 SLICE_X64Y175 FDCE (Hold_DFF_SLICEM_C_D) 0.056 1.274 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[23] ------------------------------------------------------------------- required time -1.274 arrival time 1.310 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[4]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr_reg_inv/D (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.153ns (logic 0.064ns (41.830%) route 0.089ns (58.170%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.061ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.373ns Source Clock Delay (SCD): 1.123ns Clock Pessimism Removal (CPR): 0.189ns Clock Net Delay (Source): 1.007ns (routing 0.376ns, distribution 0.631ns) Clock Net Delay (Destination): 1.221ns (routing 0.440ns, distribution 0.781ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.123 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X55Y174 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X55Y174 FDCE (Prop_CFF2_SLICEM_C_Q) 0.048 1.171 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[4]/Q net (fo=4, routed) 0.074 1.245 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/bitSlipCnt[4] SLICE_X55Y173 LUT6 (Prop_B6LUT_SLICEM_I1_O) 0.016 1.261 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr_inv_i_1__25/O net (fo=1, routed) 0.015 1.276 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr3_out SLICE_X55Y173 FDPE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr_reg_inv/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.221 1.373 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X55Y173 FDPE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr_reg_inv/C clock pessimism -0.189 1.184 SLICE_X55Y173 FDPE (Hold_BFF_SLICEM_C_D) 0.056 1.240 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr_reg_inv ------------------------------------------------------------------- required time -1.240 arrival time 1.276 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.037ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[25].rx_data_ngccm_reg[25][77]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.048ns (33.566%) route 0.095ns (66.434%)) Logic Levels: 0 Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.355ns Source Clock Delay (SCD): 1.115ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 0.999ns (routing 0.376ns, distribution 0.623ns) Clock Net Delay (Destination): 1.203ns (routing 0.440ns, distribution 0.763ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.115 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X54Y176 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y176 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 1.163 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/Q net (fo=1, routed) 0.095 1.258 rx_data[25][77] SLICE_X54Y175 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][77]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.203 1.355 g_gbt_bank[2].gbtbank_n_34 SLICE_X54Y175 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][77]/C clock pessimism -0.190 1.165 SLICE_X54Y175 FDCE (Hold_DFF2_SLICEL_C_D) 0.056 1.221 SFP_GEN[25].rx_data_ngccm_reg[25][77] ------------------------------------------------------------------- required time -1.221 arrival time 1.258 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.038ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[25].rx_data_ngccm_reg[25][66]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.156ns (logic 0.048ns (30.769%) route 0.108ns (69.231%)) Logic Levels: 0 Clock Path Skew: 0.062ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.373ns Source Clock Delay (SCD): 1.122ns Clock Pessimism Removal (CPR): 0.189ns Clock Net Delay (Source): 1.006ns (routing 0.376ns, distribution 0.630ns) Clock Net Delay (Destination): 1.221ns (routing 0.440ns, distribution 0.781ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.006 1.122 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X55Y174 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X55Y174 FDRE (Prop_HFF2_SLICEM_C_Q) 0.048 1.170 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/Q net (fo=1, routed) 0.108 1.278 rx_data[25][66] SLICE_X55Y175 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][66]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.221 1.373 g_gbt_bank[2].gbtbank_n_34 SLICE_X55Y175 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][66]/C clock pessimism -0.189 1.184 SLICE_X55Y175 FDCE (Hold_CFF2_SLICEM_C_D) 0.056 1.240 SFP_GEN[25].rx_data_ngccm_reg[25][66] ------------------------------------------------------------------- required time -1.240 arrival time 1.278 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[76]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[76]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.049ns (32.886%) route 0.100ns (67.114%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.389ns Source Clock Delay (SCD): 1.145ns Clock Pessimism Removal (CPR): 0.191ns Clock Net Delay (Source): 1.029ns (routing 0.376ns, distribution 0.653ns) Clock Net Delay (Destination): 1.237ns (routing 0.440ns, distribution 0.797ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.029 1.145 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y176 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[76]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y176 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.194 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[76]/Q net (fo=1, routed) 0.100 1.294 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[76] SLICE_X63Y178 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[76]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.237 1.389 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y178 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[76]/C clock pessimism -0.191 1.198 SLICE_X63Y178 FDCE (Hold_GFF_SLICEL_C_D) 0.056 1.254 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[76] ------------------------------------------------------------------- required time -1.254 arrival time 1.294 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.080ns (46.243%) route 0.093ns (53.757%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.388ns Source Clock Delay (SCD): 1.156ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.040ns (routing 0.376ns, distribution 0.664ns) Clock Net Delay (Destination): 1.236ns (routing 0.440ns, distribution 0.796ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.040 1.156 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X67Y179 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y179 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.205 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Q net (fo=2, routed) 0.077 1.282 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_31_in SLICE_X65Y179 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.031 1.313 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__24/O net (fo=1, routed) 0.016 1.329 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[16] SLICE_X65Y179 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.236 1.388 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X65Y179 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.157 1.231 SLICE_X65Y179 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.287 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.287 arrival time 1.329 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[46]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[46]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.048ns (33.103%) route 0.097ns (66.897%)) Logic Levels: 0 Clock Path Skew: 0.046ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.384ns Source Clock Delay (SCD): 1.147ns Clock Pessimism Removal (CPR): 0.191ns Clock Net Delay (Source): 1.031ns (routing 0.376ns, distribution 0.655ns) Clock Net Delay (Destination): 1.232ns (routing 0.440ns, distribution 0.792ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.031 1.147 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y175 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[46]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y175 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 1.195 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[46]/Q net (fo=1, routed) 0.097 1.292 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[46] SLICE_X63Y177 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[46]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.232 1.384 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y177 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[46]/C clock pessimism -0.191 1.193 SLICE_X63Y177 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 1.249 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[46] ------------------------------------------------------------------- required time -1.249 arrival time 1.292 ------------------------------------------------------------------- slack 0.043 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_27 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y69 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y179 g_clock_rate_din[25].ngccm_status_cnt_reg[25][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y179 g_clock_rate_din[25].ngccm_status_cnt_reg[25][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y179 g_clock_rate_din[25].ngccm_status_cnt_reg[25][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y179 g_clock_rate_din[25].ngccm_status_cnt_reg[25][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y177 g_clock_rate_din[25].ngccm_status_cnt_reg[25][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y179 g_clock_rate_din[25].ngccm_status_cnt_reg[25][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X68Y178 g_clock_rate_din[25].ngccm_status_cnt_reg[25][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X68Y179 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X68Y179 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X68Y179 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X66Y178 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X66Y178 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X66Y178 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X61Y179 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X61Y179 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X61Y179 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X61Y179 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][3]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X61Y179 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X61Y177 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_28 To Clock: gtwiz_userclk_rx_srcclk_out[0]_28 Setup : 0 Failing Endpoints, Worst Slack 4.215ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.039ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.215ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[45]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 3.763ns (logic 0.485ns (12.889%) route 3.278ns (87.111%)) Logic Levels: 2 (LUT3=1 LUT4=1) Clock Path Skew: -0.249ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.364ns = ( 10.681 - 8.317 ) Source Clock Delay (SCD): 2.815ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.390ns (routing 0.772ns, distribution 1.618ns) Clock Net Delay (Destination): 1.988ns (routing 0.693ns, distribution 1.295ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.390 2.815 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X22Y160 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y160 FDCE (Prop_HFF_SLICEM_C_Q) 0.138 2.953 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/Q net (fo=22, routed) 0.430 3.383 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/Q[0] SLICE_X22Y162 LUT3 (Prop_B5LUT_SLICEM_I0_O) 0.258 3.641 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/reg0[99]_i_2__25/O net (fo=40, routed) 0.851 4.492 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/mgt_headerflag_s[0] SLICE_X27Y157 LUT4 (Prop_B6LUT_SLICEL_I1_O) 0.089 4.581 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[59]_i_1__24/O net (fo=20, routed) 1.997 6.578 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[59]_i_1__24_n_0 SLICE_X26Y159 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[45]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.988 10.681 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X26Y159 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[45]/C clock pessimism 0.202 10.883 clock uncertainty -0.035 10.848 SLICE_X26Y159 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 10.793 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[45] ------------------------------------------------------------------- required time 10.793 arrival time -6.578 ------------------------------------------------------------------- slack 4.215 Slack (MET) : 4.215ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[47]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 3.763ns (logic 0.485ns (12.889%) route 3.278ns (87.111%)) Logic Levels: 2 (LUT3=1 LUT4=1) Clock Path Skew: -0.249ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.364ns = ( 10.681 - 8.317 ) Source Clock Delay (SCD): 2.815ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.390ns (routing 0.772ns, distribution 1.618ns) Clock Net Delay (Destination): 1.988ns (routing 0.693ns, distribution 1.295ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.390 2.815 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X22Y160 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y160 FDCE (Prop_HFF_SLICEM_C_Q) 0.138 2.953 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/Q net (fo=22, routed) 0.430 3.383 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/Q[0] SLICE_X22Y162 LUT3 (Prop_B5LUT_SLICEM_I0_O) 0.258 3.641 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/reg0[99]_i_2__25/O net (fo=40, routed) 0.851 4.492 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/mgt_headerflag_s[0] SLICE_X27Y157 LUT4 (Prop_B6LUT_SLICEL_I1_O) 0.089 4.581 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[59]_i_1__24/O net (fo=20, routed) 1.997 6.578 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[59]_i_1__24_n_0 SLICE_X26Y159 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[47]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.988 10.681 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X26Y159 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[47]/C clock pessimism 0.202 10.883 clock uncertainty -0.035 10.848 SLICE_X26Y159 FDCE (Setup_GFF_SLICEL_C_CE) -0.055 10.793 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[47] ------------------------------------------------------------------- required time 10.793 arrival time -6.578 ------------------------------------------------------------------- slack 4.215 Slack (MET) : 4.215ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[52]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 3.763ns (logic 0.485ns (12.889%) route 3.278ns (87.111%)) Logic Levels: 2 (LUT3=1 LUT4=1) Clock Path Skew: -0.249ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.364ns = ( 10.681 - 8.317 ) Source Clock Delay (SCD): 2.815ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.390ns (routing 0.772ns, distribution 1.618ns) Clock Net Delay (Destination): 1.988ns (routing 0.693ns, distribution 1.295ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.390 2.815 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X22Y160 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y160 FDCE (Prop_HFF_SLICEM_C_Q) 0.138 2.953 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/Q net (fo=22, routed) 0.430 3.383 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/Q[0] SLICE_X22Y162 LUT3 (Prop_B5LUT_SLICEM_I0_O) 0.258 3.641 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/reg0[99]_i_2__25/O net (fo=40, routed) 0.851 4.492 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/mgt_headerflag_s[0] SLICE_X27Y157 LUT4 (Prop_B6LUT_SLICEL_I1_O) 0.089 4.581 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[59]_i_1__24/O net (fo=20, routed) 1.997 6.578 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[59]_i_1__24_n_0 SLICE_X26Y159 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[52]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.988 10.681 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X26Y159 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[52]/C clock pessimism 0.202 10.883 clock uncertainty -0.035 10.848 SLICE_X26Y159 FDCE (Setup_FFF_SLICEL_C_CE) -0.055 10.793 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[52] ------------------------------------------------------------------- required time 10.793 arrival time -6.578 ------------------------------------------------------------------- slack 4.215 Slack (MET) : 4.215ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[53]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 3.763ns (logic 0.485ns (12.889%) route 3.278ns (87.111%)) Logic Levels: 2 (LUT3=1 LUT4=1) Clock Path Skew: -0.249ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.364ns = ( 10.681 - 8.317 ) Source Clock Delay (SCD): 2.815ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.390ns (routing 0.772ns, distribution 1.618ns) Clock Net Delay (Destination): 1.988ns (routing 0.693ns, distribution 1.295ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.390 2.815 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X22Y160 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y160 FDCE (Prop_HFF_SLICEM_C_Q) 0.138 2.953 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/Q net (fo=22, routed) 0.430 3.383 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/Q[0] SLICE_X22Y162 LUT3 (Prop_B5LUT_SLICEM_I0_O) 0.258 3.641 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/reg0[99]_i_2__25/O net (fo=40, routed) 0.851 4.492 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/mgt_headerflag_s[0] SLICE_X27Y157 LUT4 (Prop_B6LUT_SLICEL_I1_O) 0.089 4.581 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[59]_i_1__24/O net (fo=20, routed) 1.997 6.578 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[59]_i_1__24_n_0 SLICE_X26Y159 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[53]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.988 10.681 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X26Y159 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[53]/C clock pessimism 0.202 10.883 clock uncertainty -0.035 10.848 SLICE_X26Y159 FDCE (Setup_EFF_SLICEL_C_CE) -0.055 10.793 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[53] ------------------------------------------------------------------- required time 10.793 arrival time -6.578 ------------------------------------------------------------------- slack 4.215 Slack (MET) : 4.365ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 3.700ns (logic 0.563ns (15.216%) route 3.137ns (84.784%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.281ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.332ns = ( 10.649 - 8.317 ) Source Clock Delay (SCD): 2.815ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.390ns (routing 0.772ns, distribution 1.618ns) Clock Net Delay (Destination): 1.956ns (routing 0.693ns, distribution 1.263ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.390 2.815 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X22Y160 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y160 FDCE (Prop_HFF_SLICEM_C_Q) 0.138 2.953 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/Q net (fo=22, routed) 0.430 3.383 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/Q[0] SLICE_X22Y162 LUT3 (Prop_B5LUT_SLICEM_I0_O) 0.258 3.641 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/reg0[99]_i_2__25/O net (fo=40, routed) 1.961 5.602 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]_0 SLICE_X39Y171 LUT2 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.769 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/firstOut_i_1__24/O net (fo=1, routed) 0.746 6.515 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg_0 SLICE_X33Y168 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.956 10.649 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X33Y168 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism 0.202 10.852 clock uncertainty -0.035 10.816 SLICE_X33Y168 FDCE (Setup_EFF_SLICEL_C_D) 0.064 10.880 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time 10.880 arrival time -6.515 ------------------------------------------------------------------- slack 4.365 Slack (MET) : 4.396ns (required time - arrival time) Source: SFP_GEN[26].rx_data_valid_r_reg[26]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[50]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 3.404ns (logic 0.227ns (6.669%) route 3.177ns (93.331%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.427ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.335ns = ( 10.652 - 8.317 ) Source Clock Delay (SCD): 2.974ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.549ns (routing 0.772ns, distribution 1.777ns) Clock Net Delay (Destination): 1.959ns (routing 0.693ns, distribution 1.266ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.549 2.974 g_gbt_bank[2].gbtbank_n_44 SLICE_X51Y158 FDCE r SFP_GEN[26].rx_data_valid_r_reg[26]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y158 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 3.114 r SFP_GEN[26].rx_data_valid_r_reg[26]/Q net (fo=2, routed) 1.548 4.662 SFP_GEN[26].ngCCM_gbt/p_2_in248_in SLICE_X32Y157 LUT2 (Prop_E6LUT_SLICEL_I0_O) 0.087 4.749 r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[83]_i_1__27/O net (fo=48, routed) 1.629 6.378 SFP_GEN[26].ngCCM_gbt/RX_Word_rx400 SLICE_X23Y154 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[50]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.959 10.652 SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X23Y154 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[50]/C clock pessimism 0.212 10.864 clock uncertainty -0.035 10.829 SLICE_X23Y154 FDCE (Setup_DFF2_SLICEM_C_CE) -0.055 10.774 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[50] ------------------------------------------------------------------- required time 10.774 arrival time -6.378 ------------------------------------------------------------------- slack 4.396 Slack (MET) : 4.400ns (required time - arrival time) Source: SFP_GEN[26].rx_data_valid_r_reg[26]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[48]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 3.401ns (logic 0.227ns (6.675%) route 3.174ns (93.325%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.427ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.335ns = ( 10.652 - 8.317 ) Source Clock Delay (SCD): 2.974ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.549ns (routing 0.772ns, distribution 1.777ns) Clock Net Delay (Destination): 1.959ns (routing 0.693ns, distribution 1.266ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.549 2.974 g_gbt_bank[2].gbtbank_n_44 SLICE_X51Y158 FDCE r SFP_GEN[26].rx_data_valid_r_reg[26]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y158 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 3.114 r SFP_GEN[26].rx_data_valid_r_reg[26]/Q net (fo=2, routed) 1.548 4.662 SFP_GEN[26].ngCCM_gbt/p_2_in248_in SLICE_X32Y157 LUT2 (Prop_E6LUT_SLICEL_I0_O) 0.087 4.749 r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[83]_i_1__27/O net (fo=48, routed) 1.626 6.375 SFP_GEN[26].ngCCM_gbt/RX_Word_rx400 SLICE_X23Y154 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[48]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.959 10.652 SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X23Y154 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[48]/C clock pessimism 0.212 10.864 clock uncertainty -0.035 10.829 SLICE_X23Y154 FDCE (Setup_DFF_SLICEM_C_CE) -0.054 10.775 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[48] ------------------------------------------------------------------- required time 10.775 arrival time -6.375 ------------------------------------------------------------------- slack 4.400 Slack (MET) : 4.493ns (required time - arrival time) Source: SFP_GEN[26].rx_data_valid_r_reg[26]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[70]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 3.326ns (logic 0.227ns (6.825%) route 3.099ns (93.175%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.405ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.357ns = ( 10.674 - 8.317 ) Source Clock Delay (SCD): 2.974ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.549ns (routing 0.772ns, distribution 1.777ns) Clock Net Delay (Destination): 1.981ns (routing 0.693ns, distribution 1.288ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.549 2.974 g_gbt_bank[2].gbtbank_n_44 SLICE_X51Y158 FDCE r SFP_GEN[26].rx_data_valid_r_reg[26]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y158 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 3.114 r SFP_GEN[26].rx_data_valid_r_reg[26]/Q net (fo=2, routed) 1.548 4.662 SFP_GEN[26].ngCCM_gbt/p_2_in248_in SLICE_X32Y157 LUT2 (Prop_E6LUT_SLICEL_I0_O) 0.087 4.749 r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[83]_i_1__27/O net (fo=48, routed) 1.551 6.300 SFP_GEN[26].ngCCM_gbt/RX_Word_rx400 SLICE_X25Y154 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[70]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.981 10.674 SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X25Y154 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[70]/C clock pessimism 0.212 10.886 clock uncertainty -0.035 10.851 SLICE_X25Y154 FDCE (Setup_HFF2_SLICEM_C_CE) -0.058 10.793 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[70] ------------------------------------------------------------------- required time 10.793 arrival time -6.300 ------------------------------------------------------------------- slack 4.493 Slack (MET) : 4.499ns (required time - arrival time) Source: SFP_GEN[26].rx_data_valid_r_reg[26]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[68]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 3.323ns (logic 0.227ns (6.831%) route 3.096ns (93.169%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.405ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.357ns = ( 10.674 - 8.317 ) Source Clock Delay (SCD): 2.974ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.549ns (routing 0.772ns, distribution 1.777ns) Clock Net Delay (Destination): 1.981ns (routing 0.693ns, distribution 1.288ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.549 2.974 g_gbt_bank[2].gbtbank_n_44 SLICE_X51Y158 FDCE r SFP_GEN[26].rx_data_valid_r_reg[26]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y158 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 3.114 r SFP_GEN[26].rx_data_valid_r_reg[26]/Q net (fo=2, routed) 1.548 4.662 SFP_GEN[26].ngCCM_gbt/p_2_in248_in SLICE_X32Y157 LUT2 (Prop_E6LUT_SLICEL_I0_O) 0.087 4.749 r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[83]_i_1__27/O net (fo=48, routed) 1.548 6.297 SFP_GEN[26].ngCCM_gbt/RX_Word_rx400 SLICE_X25Y154 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[68]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.981 10.674 SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X25Y154 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[68]/C clock pessimism 0.212 10.886 clock uncertainty -0.035 10.851 SLICE_X25Y154 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 10.796 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[68] ------------------------------------------------------------------- required time 10.796 arrival time -6.297 ------------------------------------------------------------------- slack 4.499 Slack (MET) : 4.499ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 3.566ns (logic 0.872ns (24.453%) route 2.694ns (75.547%)) Logic Levels: 4 (LUT2=1 LUT3=1 LUT6=2) Clock Path Skew: -0.280ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.333ns = ( 10.650 - 8.317 ) Source Clock Delay (SCD): 2.815ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.390ns (routing 0.772ns, distribution 1.618ns) Clock Net Delay (Destination): 1.957ns (routing 0.693ns, distribution 1.264ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.390 2.815 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X22Y160 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y160 FDCE (Prop_HFF_SLICEM_C_Q) 0.138 2.953 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/Q net (fo=22, routed) 0.430 3.383 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/Q[0] SLICE_X22Y162 LUT3 (Prop_B5LUT_SLICEM_I0_O) 0.258 3.641 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/reg0[99]_i_2__25/O net (fo=40, routed) 1.812 5.453 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]_0 SLICE_X43Y172 LUT2 (Prop_B6LUT_SLICEL_I1_O) 0.166 5.619 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i[2]_i_3__1/O net (fo=1, routed) 0.348 5.967 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/cnt[2]1 SLICE_X45Y171 LUT6 (Prop_F6LUT_SLICEL_I3_O) 0.221 6.188 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i[2]_i_2__1/O net (fo=1, routed) 0.069 6.257 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i[2]_i_2__1_n_0 SLICE_X45Y171 LUT6 (Prop_H6LUT_SLICEL_I0_O) 0.089 6.346 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i[2]_i_1__1/O net (fo=1, routed) 0.035 6.381 g_gbt_bank[2].gbtbank/i_gbt_bank_n_147 SLICE_X45Y171 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.957 10.650 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] SLICE_X45Y171 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/C clock pessimism 0.202 10.853 clock uncertainty -0.035 10.817 SLICE_X45Y171 FDCE (Setup_HFF_SLICEL_C_D) 0.063 10.880 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2] ------------------------------------------------------------------- required time 10.880 arrival time -6.381 ------------------------------------------------------------------- slack 4.499 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.039ns (arrival time - required time) Source: SFP_GEN[26].rx_data_ngccm_reg[26][76]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[76]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.181ns (logic 0.094ns (51.934%) route 0.087ns (48.066%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.219ns Source Clock Delay (SCD): 0.989ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.873ns (routing 0.368ns, distribution 0.505ns) Clock Net Delay (Destination): 1.067ns (routing 0.432ns, distribution 0.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.873 0.989 g_gbt_bank[2].gbtbank_n_44 SLICE_X31Y151 FDCE r SFP_GEN[26].rx_data_ngccm_reg[26][76]/C ------------------------------------------------------------------- ------------------- SLICE_X31Y151 FDCE (Prop_AFF2_SLICEM_C_Q) 0.049 1.038 r SFP_GEN[26].rx_data_ngccm_reg[26][76]/Q net (fo=1, routed) 0.073 1.111 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[83]_0[68] SLICE_X30Y151 LUT3 (Prop_G6LUT_SLICEL_I1_O) 0.045 1.156 r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[76]_i_1/O net (fo=1, routed) 0.014 1.170 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[76]_i_1_n_0 SLICE_X30Y151 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[76]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.067 1.219 SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X30Y151 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[76]/C clock pessimism -0.144 1.075 SLICE_X30Y151 FDCE (Hold_GFF_SLICEL_C_D) 0.056 1.131 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[76] ------------------------------------------------------------------- required time -1.131 arrival time 1.170 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.188ns (logic 0.103ns (54.787%) route 0.085ns (45.213%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.090ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.222ns Source Clock Delay (SCD): 0.988ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.872ns (routing 0.368ns, distribution 0.504ns) Clock Net Delay (Destination): 1.070ns (routing 0.432ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.872 0.988 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X31Y151 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X31Y151 FDCE (Prop_FFF2_SLICEM_C_Q) 0.048 1.036 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.074 1.110 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_33_in SLICE_X30Y151 LUT3 (Prop_C5LUT_SLICEL_I2_O) 0.055 1.165 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__25/O net (fo=1, routed) 0.011 1.176 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[15] SLICE_X30Y151 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.070 1.222 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X30Y151 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C clock pessimism -0.144 1.078 SLICE_X30Y151 FDRE (Hold_CFF2_SLICEL_C_D) 0.056 1.134 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15] ------------------------------------------------------------------- required time -1.134 arrival time 1.176 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].rx_data_ngccm_reg[26][22]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.178ns (logic 0.049ns (27.528%) route 0.129ns (72.472%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.231ns Source Clock Delay (SCD): 1.011ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.895ns (routing 0.368ns, distribution 0.527ns) Clock Net Delay (Destination): 1.079ns (routing 0.432ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.895 1.011 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X30Y162 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X30Y162 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.060 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/Q net (fo=1, routed) 0.129 1.189 rx_data[26][22] SLICE_X32Y162 FDCE r SFP_GEN[26].rx_data_ngccm_reg[26][22]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.079 1.231 g_gbt_bank[2].gbtbank_n_44 SLICE_X32Y162 FDCE r SFP_GEN[26].rx_data_ngccm_reg[26][22]/C clock pessimism -0.144 1.087 SLICE_X32Y162 FDCE (Hold_GFF2_SLICEL_C_D) 0.056 1.143 SFP_GEN[26].rx_data_ngccm_reg[26][22] ------------------------------------------------------------------- required time -1.143 arrival time 1.189 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.193ns (logic 0.101ns (52.332%) route 0.092ns (47.668%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.090ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.222ns Source Clock Delay (SCD): 0.988ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.872ns (routing 0.368ns, distribution 0.504ns) Clock Net Delay (Destination): 1.070ns (routing 0.432ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.872 0.988 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X31Y151 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X31Y151 FDCE (Prop_FFF2_SLICEM_C_Q) 0.048 1.036 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.077 1.113 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_33_in SLICE_X30Y151 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.053 1.166 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__25/O net (fo=1, routed) 0.015 1.181 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[17] SLICE_X30Y151 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.070 1.222 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X30Y151 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.144 1.078 SLICE_X30Y151 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.134 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.134 arrival time 1.181 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].rx_data_ngccm_reg[26][29]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.180ns (logic 0.049ns (27.222%) route 0.131ns (72.778%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.230ns Source Clock Delay (SCD): 1.009ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.893ns (routing 0.368ns, distribution 0.525ns) Clock Net Delay (Destination): 1.078ns (routing 0.432ns, distribution 0.646ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.893 1.009 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X30Y160 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X30Y160 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.058 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/Q net (fo=1, routed) 0.131 1.189 rx_data[26][29] SLICE_X32Y160 FDCE r SFP_GEN[26].rx_data_ngccm_reg[26][29]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.078 1.230 g_gbt_bank[2].gbtbank_n_44 SLICE_X32Y160 FDCE r SFP_GEN[26].rx_data_ngccm_reg[26][29]/C clock pessimism -0.144 1.086 SLICE_X32Y160 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.141 SFP_GEN[26].rx_data_ngccm_reg[26][29] ------------------------------------------------------------------- required time -1.141 arrival time 1.189 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/RX_BITSLIPCMD_o_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.109ns (logic 0.064ns (58.716%) route 0.045ns (41.284%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.269ns Source Clock Delay (SCD): 1.045ns Clock Pessimism Removal (CPR): 0.219ns Clock Net Delay (Source): 0.929ns (routing 0.368ns, distribution 0.561ns) Clock Net Delay (Destination): 1.117ns (routing 0.432ns, distribution 0.685ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.929 1.045 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/CLK SLICE_X22Y162 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X22Y162 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.094 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/RX_BITSLIPCMD_o_reg/Q net (fo=2, routed) 0.033 1.127 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/rxslide_in[0] SLICE_X22Y162 LUT3 (Prop_A6LUT_SLICEM_I2_O) 0.015 1.142 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__25/O net (fo=1, routed) 0.012 1.154 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__25_n_0 SLICE_X22Y162 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/RX_BITSLIPCMD_o_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.117 1.269 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/CLK SLICE_X22Y162 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C clock pessimism -0.219 1.050 SLICE_X22Y162 FDCE (Hold_AFF_SLICEM_C_D) 0.056 1.106 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/RX_BITSLIPCMD_o_reg ------------------------------------------------------------------- required time -1.106 arrival time 1.154 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].rx_data_ngccm_reg[26][51]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.153ns (logic 0.048ns (31.373%) route 0.105ns (68.627%)) Logic Levels: 0 Clock Path Skew: 0.049ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.232ns Source Clock Delay (SCD): 1.007ns Clock Pessimism Removal (CPR): 0.176ns Clock Net Delay (Source): 0.891ns (routing 0.368ns, distribution 0.523ns) Clock Net Delay (Destination): 1.080ns (routing 0.432ns, distribution 0.648ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.891 1.007 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X26Y155 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X26Y155 FDRE (Prop_CFF2_SLICEL_C_Q) 0.048 1.055 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/Q net (fo=1, routed) 0.105 1.160 rx_data[26][51] SLICE_X26Y154 FDCE r SFP_GEN[26].rx_data_ngccm_reg[26][51]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.080 1.232 g_gbt_bank[2].gbtbank_n_44 SLICE_X26Y154 FDCE r SFP_GEN[26].rx_data_ngccm_reg[26][51]/C clock pessimism -0.176 1.056 SLICE_X26Y154 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.112 SFP_GEN[26].rx_data_ngccm_reg[26][51] ------------------------------------------------------------------- required time -1.112 arrival time 1.160 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].rx_data_ngccm_reg[26][74]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.167ns (logic 0.049ns (29.341%) route 0.118ns (70.659%)) Logic Levels: 0 Clock Path Skew: 0.063ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.205ns Source Clock Delay (SCD): 0.998ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.882ns (routing 0.368ns, distribution 0.514ns) Clock Net Delay (Destination): 1.053ns (routing 0.432ns, distribution 0.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.882 0.998 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X30Y151 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X30Y151 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.047 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/Q net (fo=1, routed) 0.118 1.165 rx_data[26][74] SLICE_X31Y151 FDCE r SFP_GEN[26].rx_data_ngccm_reg[26][74]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.053 1.205 g_gbt_bank[2].gbtbank_n_44 SLICE_X31Y151 FDCE r SFP_GEN[26].rx_data_ngccm_reg[26][74]/C clock pessimism -0.144 1.061 SLICE_X31Y151 FDCE (Hold_AFF_SLICEM_C_D) 0.056 1.117 SFP_GEN[26].rx_data_ngccm_reg[26][74] ------------------------------------------------------------------- required time -1.117 arrival time 1.165 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].rx_data_ngccm_reg[26][67]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.049ns (33.793%) route 0.096ns (66.207%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.220ns Source Clock Delay (SCD): 0.996ns Clock Pessimism Removal (CPR): 0.184ns Clock Net Delay (Source): 0.880ns (routing 0.368ns, distribution 0.512ns) Clock Net Delay (Destination): 1.068ns (routing 0.432ns, distribution 0.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.880 0.996 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X29Y150 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y150 FDRE (Prop_FFF_SLICEM_C_Q) 0.049 1.045 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/Q net (fo=1, routed) 0.096 1.141 rx_data[26][67] SLICE_X30Y150 FDCE r SFP_GEN[26].rx_data_ngccm_reg[26][67]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.068 1.220 g_gbt_bank[2].gbtbank_n_44 SLICE_X30Y150 FDCE r SFP_GEN[26].rx_data_ngccm_reg[26][67]/C clock pessimism -0.184 1.036 SLICE_X30Y150 FDCE (Hold_AFF2_SLICEL_C_D) 0.056 1.092 SFP_GEN[26].rx_data_ngccm_reg[26][67] ------------------------------------------------------------------- required time -1.092 arrival time 1.141 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].rx_data_ngccm_reg[26][66]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.158ns (logic 0.048ns (30.380%) route 0.110ns (69.620%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.223ns Source Clock Delay (SCD): 0.996ns Clock Pessimism Removal (CPR): 0.174ns Clock Net Delay (Source): 0.880ns (routing 0.368ns, distribution 0.512ns) Clock Net Delay (Destination): 1.071ns (routing 0.432ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.880 0.996 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X29Y150 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y150 FDRE (Prop_GFF2_SLICEM_C_Q) 0.048 1.044 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/Q net (fo=1, routed) 0.110 1.154 rx_data[26][66] SLICE_X29Y151 FDCE r SFP_GEN[26].rx_data_ngccm_reg[26][66]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.071 1.223 g_gbt_bank[2].gbtbank_n_44 SLICE_X29Y151 FDCE r SFP_GEN[26].rx_data_ngccm_reg[26][66]/C clock pessimism -0.174 1.049 SLICE_X29Y151 FDCE (Hold_AFF2_SLICEM_C_D) 0.056 1.105 SFP_GEN[26].rx_data_ngccm_reg[26][66] ------------------------------------------------------------------- required time -1.105 arrival time 1.154 ------------------------------------------------------------------- slack 0.049 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_28 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y64 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y176 g_clock_rate_din[26].ngccm_status_cnt_reg[26][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y176 g_clock_rate_din[26].ngccm_status_cnt_reg[26][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y176 g_clock_rate_din[26].ngccm_status_cnt_reg[26][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y176 g_clock_rate_din[26].ngccm_status_cnt_reg[26][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y176 g_clock_rate_din[26].ngccm_status_cnt_reg[26][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y176 g_clock_rate_din[26].ngccm_status_cnt_reg[26][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y174 g_clock_rate_din[26].ngccm_status_cnt_reg[26][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X32Y168 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[2].rx_data_good_cntr_reg[2][0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X32Y168 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[2].rx_data_good_cntr_reg[2][1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X32Y168 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[2].rx_data_good_cntr_reg[2][2]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X32Y168 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[2].rx_data_good_cntr_reg[2][3]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X32Y168 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[2].rx_data_good_cntr_reg[2][4]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X28Y162 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y176 g_clock_rate_din[26].ngccm_status_cnt_reg[26][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y176 g_clock_rate_din[26].ngccm_status_cnt_reg[26][1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y176 g_clock_rate_din[26].ngccm_status_cnt_reg[26][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y176 g_clock_rate_din[26].ngccm_status_cnt_reg[26][3]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y176 g_clock_rate_din[26].ngccm_status_cnt_reg[26][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y176 g_clock_rate_din[26].ngccm_status_cnt_reg[26][5]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_29 To Clock: gtwiz_userclk_rx_srcclk_out[0]_29 Setup : 0 Failing Endpoints, Worst Slack 2.713ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.036ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.713ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 5.667ns (logic 1.643ns (28.992%) route 4.024ns (71.008%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.153ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.671ns = ( 10.988 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.295ns (routing 0.697ns, distribution 1.598ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.887 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.313 7.200 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X65Y172 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.244 7.444 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/O net (fo=5, routed) 0.295 7.739 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X65Y173 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.092 7.831 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__26/O net (fo=1, routed) 0.075 7.906 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__26_n_0 SLICE_X65Y173 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 8.052 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__26/O net (fo=2, routed) 0.341 8.393 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__26_n_0 SLICE_X65Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.295 10.988 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/CLK SLICE_X65Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.208 11.197 clock uncertainty -0.035 11.161 SLICE_X65Y171 FDCE (Setup_GFF_SLICEM_C_CE) -0.055 11.106 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.106 arrival time -8.393 ------------------------------------------------------------------- slack 2.713 Slack (MET) : 2.713ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 5.667ns (logic 1.643ns (28.992%) route 4.024ns (71.008%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.153ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.671ns = ( 10.988 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.295ns (routing 0.697ns, distribution 1.598ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.887 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.313 7.200 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X65Y172 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.244 7.444 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/O net (fo=5, routed) 0.295 7.739 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X65Y173 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.092 7.831 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__26/O net (fo=1, routed) 0.075 7.906 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__26_n_0 SLICE_X65Y173 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 8.052 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__26/O net (fo=2, routed) 0.341 8.393 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__26_n_0 SLICE_X65Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.295 10.988 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/CLK SLICE_X65Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.208 11.197 clock uncertainty -0.035 11.161 SLICE_X65Y171 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 11.106 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.106 arrival time -8.393 ------------------------------------------------------------------- slack 2.713 Slack (MET) : 2.807ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 5.560ns (logic 1.551ns (27.896%) route 4.009ns (72.104%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.658ns = ( 10.975 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.282ns (routing 0.697ns, distribution 1.585ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.887 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.313 7.200 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X65Y172 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.244 7.444 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/O net (fo=5, routed) 0.187 7.631 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X65Y174 LUT6 (Prop_A6LUT_SLICEM_I0_O) 0.146 7.777 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__27/O net (fo=5, routed) 0.509 8.286 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecCorrectHeaders0 SLICE_X68Y175 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.282 10.975 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/CLK SLICE_X68Y175 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.208 11.184 clock uncertainty -0.035 11.148 SLICE_X68Y175 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 11.093 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.093 arrival time -8.286 ------------------------------------------------------------------- slack 2.807 Slack (MET) : 2.812ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 5.556ns (logic 1.551ns (27.916%) route 4.005ns (72.084%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.658ns = ( 10.975 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.282ns (routing 0.697ns, distribution 1.585ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.887 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.313 7.200 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X65Y172 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.244 7.444 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/O net (fo=5, routed) 0.187 7.631 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X65Y174 LUT6 (Prop_A6LUT_SLICEM_I0_O) 0.146 7.777 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__27/O net (fo=5, routed) 0.505 8.282 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecCorrectHeaders0 SLICE_X68Y175 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.282 10.975 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/CLK SLICE_X68Y175 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C clock pessimism 0.208 11.184 clock uncertainty -0.035 11.148 SLICE_X68Y175 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 11.094 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0] ------------------------------------------------------------------- required time 11.094 arrival time -8.282 ------------------------------------------------------------------- slack 2.812 Slack (MET) : 2.871ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 5.483ns (logic 1.551ns (28.287%) route 3.932ns (71.713%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.130ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.648ns = ( 10.965 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.272ns (routing 0.697ns, distribution 1.575ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.887 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.313 7.200 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X65Y172 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.244 7.444 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/O net (fo=5, routed) 0.187 7.631 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X65Y174 LUT6 (Prop_A6LUT_SLICEM_I0_O) 0.146 7.777 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__27/O net (fo=5, routed) 0.432 8.209 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecCorrectHeaders0 SLICE_X65Y175 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.272 10.965 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/CLK SLICE_X65Y175 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.208 11.174 clock uncertainty -0.035 11.138 SLICE_X65Y175 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 11.080 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 11.080 arrival time -8.209 ------------------------------------------------------------------- slack 2.871 Slack (MET) : 2.877ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 5.480ns (logic 1.551ns (28.303%) route 3.929ns (71.697%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.130ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.648ns = ( 10.965 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.272ns (routing 0.697ns, distribution 1.575ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.887 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.313 7.200 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X65Y172 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.244 7.444 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/O net (fo=5, routed) 0.187 7.631 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X65Y174 LUT6 (Prop_A6LUT_SLICEM_I0_O) 0.146 7.777 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__27/O net (fo=5, routed) 0.429 8.206 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecCorrectHeaders0 SLICE_X65Y175 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.272 10.965 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/CLK SLICE_X65Y175 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C clock pessimism 0.208 11.174 clock uncertainty -0.035 11.138 SLICE_X65Y175 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 11.083 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2] ------------------------------------------------------------------- required time 11.083 arrival time -8.206 ------------------------------------------------------------------- slack 2.877 Slack (MET) : 2.877ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 5.480ns (logic 1.551ns (28.303%) route 3.929ns (71.697%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.130ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.648ns = ( 10.965 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.272ns (routing 0.697ns, distribution 1.575ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.887 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.313 7.200 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X65Y172 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.244 7.444 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/O net (fo=5, routed) 0.187 7.631 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X65Y174 LUT6 (Prop_A6LUT_SLICEM_I0_O) 0.146 7.777 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__27/O net (fo=5, routed) 0.429 8.206 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecCorrectHeaders0 SLICE_X65Y175 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.272 10.965 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/CLK SLICE_X65Y175 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism 0.208 11.174 clock uncertainty -0.035 11.138 SLICE_X65Y175 FDRE (Setup_GFF_SLICEM_C_CE) -0.055 11.083 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time 11.083 arrival time -8.206 ------------------------------------------------------------------- slack 2.877 Slack (MET) : 2.962ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 5.396ns (logic 1.460ns (27.057%) route 3.936ns (72.943%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.131ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.649ns = ( 10.966 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.273ns (routing 0.697ns, distribution 1.576ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.887 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.313 7.200 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X65Y172 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.244 7.444 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/O net (fo=5, routed) 0.191 7.635 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X65Y174 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.055 7.690 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__27/O net (fo=3, routed) 0.432 8.122 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecFalseHeaders0 SLICE_X65Y176 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.273 10.966 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/CLK SLICE_X65Y176 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.208 11.175 clock uncertainty -0.035 11.139 SLICE_X65Y176 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 11.084 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 11.084 arrival time -8.122 ------------------------------------------------------------------- slack 2.962 Slack (MET) : 2.966ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 5.393ns (logic 1.460ns (27.072%) route 3.933ns (72.928%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.131ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.649ns = ( 10.966 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.273ns (routing 0.697ns, distribution 1.576ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.887 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.313 7.200 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X65Y172 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.244 7.444 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/O net (fo=5, routed) 0.191 7.635 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X65Y174 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.055 7.690 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__27/O net (fo=3, routed) 0.429 8.119 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecFalseHeaders0 SLICE_X65Y176 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.273 10.966 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/CLK SLICE_X65Y176 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.208 11.175 clock uncertainty -0.035 11.139 SLICE_X65Y176 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 11.085 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 11.085 arrival time -8.119 ------------------------------------------------------------------- slack 2.966 Slack (MET) : 2.973ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 5.392ns (logic 1.460ns (27.077%) route 3.932ns (72.923%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.656ns = ( 10.973 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.280ns (routing 0.697ns, distribution 1.583ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.887 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.313 7.200 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X65Y172 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.244 7.444 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/O net (fo=5, routed) 0.191 7.635 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X65Y174 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.055 7.690 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__27/O net (fo=3, routed) 0.428 8.118 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecFalseHeaders0 SLICE_X68Y175 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.280 10.973 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/CLK SLICE_X68Y175 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C clock pessimism 0.208 11.182 clock uncertainty -0.035 11.146 SLICE_X68Y175 FDRE (Setup_EFF_SLICEL_C_CE) -0.055 11.091 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2] ------------------------------------------------------------------- required time 11.091 arrival time -8.118 ------------------------------------------------------------------- slack 2.973 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.036ns (arrival time - required time) Source: SFP_GEN[27].rx_data_ngccm_reg[27][61]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[60]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.169ns (logic 0.078ns (46.154%) route 0.091ns (53.846%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.367ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.017ns (routing 0.369ns, distribution 0.648ns) Clock Net Delay (Destination): 1.215ns (routing 0.431ns, distribution 0.784ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.133 g_gbt_bank[2].gbtbank_n_54 SLICE_X69Y156 FDCE r SFP_GEN[27].rx_data_ngccm_reg[27][61]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y156 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 1.181 r SFP_GEN[27].rx_data_ngccm_reg[27][61]/Q net (fo=1, routed) 0.075 1.256 SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[83]_0[53] SLICE_X70Y156 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.030 1.286 r SFP_GEN[27].ngCCM_gbt/RX_Word_rx40[60]_i_1/O net (fo=1, routed) 0.016 1.302 SFP_GEN[27].ngCCM_gbt/RX_Word_rx40[60]_i_1_n_0 SLICE_X70Y156 FDCE r SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[60]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.215 1.367 SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X70Y156 FDCE r SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[60]/C clock pessimism -0.157 1.210 SLICE_X70Y156 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.266 SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[60] ------------------------------------------------------------------- required time -1.266 arrival time 1.302 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.150ns (logic 0.048ns (32.000%) route 0.102ns (68.000%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.382ns Source Clock Delay (SCD): 1.139ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 1.023ns (routing 0.369ns, distribution 0.654ns) Clock Net Delay (Destination): 1.230ns (routing 0.431ns, distribution 0.799ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.023 1.139 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X66Y169 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg/C ------------------------------------------------------------------- ------------------- SLICE_X66Y169 FDCE (Prop_HFF_SLICEL_C_Q) 0.048 1.187 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg/Q net (fo=5, routed) 0.102 1.289 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut SLICE_X66Y168 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.230 1.382 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X66Y168 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C clock pessimism -0.190 1.192 SLICE_X66Y168 FDCE (Hold_HFF2_SLICEL_C_D) 0.056 1.248 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg ------------------------------------------------------------------- required time -1.248 arrival time 1.289 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.043ns (arrival time - required time) Source: SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[40]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[27].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.169ns (logic 0.049ns (28.994%) route 0.120ns (71.006%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.367ns Source Clock Delay (SCD): 1.140ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.024ns (routing 0.369ns, distribution 0.655ns) Clock Net Delay (Destination): 1.215ns (routing 0.431ns, distribution 0.784ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.024 1.140 SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y164 FDCE r SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[40]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y164 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 1.189 r SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[40]/Q net (fo=1, routed) 0.120 1.309 SFP_GEN[27].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]_0[8] SLICE_X70Y164 FDRE r SFP_GEN[27].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.215 1.367 SFP_GEN[27].ngCCM_gbt/CrossClock_DV_cnt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X70Y164 FDRE r SFP_GEN[27].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C clock pessimism -0.157 1.210 SLICE_X70Y164 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.266 SFP_GEN[27].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40] ------------------------------------------------------------------- required time -1.266 arrival time 1.309 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[27].rx_data_ngccm_reg[27][4]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.049ns (34.028%) route 0.095ns (65.972%)) Logic Levels: 0 Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.377ns Source Clock Delay (SCD): 1.142ns Clock Pessimism Removal (CPR): 0.191ns Clock Net Delay (Source): 1.026ns (routing 0.369ns, distribution 0.657ns) Clock Net Delay (Destination): 1.225ns (routing 0.431ns, distribution 0.794ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.026 1.142 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X69Y168 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y168 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.191 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/Q net (fo=1, routed) 0.095 1.286 rx_data[27][4] SLICE_X69Y170 FDCE r SFP_GEN[27].rx_data_ngccm_reg[27][4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.225 1.377 g_gbt_bank[2].gbtbank_n_54 SLICE_X69Y170 FDCE r SFP_GEN[27].rx_data_ngccm_reg[27][4]/C clock pessimism -0.191 1.186 SLICE_X69Y170 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 1.242 SFP_GEN[27].rx_data_ngccm_reg[27][4] ------------------------------------------------------------------- required time -1.242 arrival time 1.286 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[27].rx_data_ngccm_reg[27][80]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.141ns (logic 0.048ns (34.043%) route 0.093ns (65.957%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.371ns Source Clock Delay (SCD): 1.139ns Clock Pessimism Removal (CPR): 0.192ns Clock Net Delay (Source): 1.023ns (routing 0.369ns, distribution 0.654ns) Clock Net Delay (Destination): 1.219ns (routing 0.431ns, distribution 0.788ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.023 1.139 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X69Y163 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y163 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 1.187 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/Q net (fo=1, routed) 0.093 1.280 rx_data[27][80] SLICE_X69Y164 FDCE r SFP_GEN[27].rx_data_ngccm_reg[27][80]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.219 1.371 g_gbt_bank[2].gbtbank_n_54 SLICE_X69Y164 FDCE r SFP_GEN[27].rx_data_ngccm_reg[27][80]/C clock pessimism -0.192 1.179 SLICE_X69Y164 FDCE (Hold_GFF2_SLICEL_C_D) 0.056 1.235 SFP_GEN[27].rx_data_ngccm_reg[27][80] ------------------------------------------------------------------- required time -1.235 arrival time 1.280 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: SFP_GEN[27].rx_data_ngccm_reg[27][2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[2]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.175ns (logic 0.088ns (50.286%) route 0.087ns (49.714%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.366ns Source Clock Delay (SCD): 1.135ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.019ns (routing 0.369ns, distribution 0.650ns) Clock Net Delay (Destination): 1.214ns (routing 0.431ns, distribution 0.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.019 1.135 g_gbt_bank[2].gbtbank_n_54 SLICE_X69Y166 FDCE r SFP_GEN[27].rx_data_ngccm_reg[27][2]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y166 FDCE (Prop_EFF2_SLICEL_C_Q) 0.048 1.183 r SFP_GEN[27].rx_data_ngccm_reg[27][2]/Q net (fo=1, routed) 0.075 1.258 SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[83]_0[2] SLICE_X70Y166 LUT3 (Prop_H5LUT_SLICEM_I1_O) 0.040 1.298 r SFP_GEN[27].ngCCM_gbt/RX_Word_rx40[2]_i_1/O net (fo=1, routed) 0.012 1.310 SFP_GEN[27].ngCCM_gbt/RX_Word_rx40[2]_i_1_n_0 SLICE_X70Y166 FDCE r SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[2]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.214 1.366 SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X70Y166 FDCE r SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[2]/C clock pessimism -0.157 1.209 SLICE_X70Y166 FDCE (Hold_HFF2_SLICEM_C_D) 0.056 1.265 SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[2] ------------------------------------------------------------------- required time -1.265 arrival time 1.310 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[39]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.156ns (logic 0.064ns (41.026%) route 0.092ns (58.974%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.384ns Source Clock Delay (SCD): 1.144ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 1.028ns (routing 0.369ns, distribution 0.659ns) Clock Net Delay (Destination): 1.232ns (routing 0.431ns, distribution 0.801ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.028 1.144 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X66Y168 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y168 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 1.193 f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Q net (fo=27, routed) 0.076 1.269 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] SLICE_X66Y166 LUT5 (Prop_D6LUT_SLICEL_I1_O) 0.015 1.284 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[39]_i_2__34/O net (fo=1, routed) 0.016 1.300 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg00[39] SLICE_X66Y166 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[39]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.232 1.384 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X66Y166 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[39]/C clock pessimism -0.190 1.194 SLICE_X66Y166 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.250 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[39] ------------------------------------------------------------------- required time -1.250 arrival time 1.300 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[36]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[36]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.049ns (34.507%) route 0.093ns (65.493%)) Logic Levels: 0 Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.375ns Source Clock Delay (SCD): 1.142ns Clock Pessimism Removal (CPR): 0.199ns Clock Net Delay (Source): 1.026ns (routing 0.369ns, distribution 0.657ns) Clock Net Delay (Destination): 1.223ns (routing 0.431ns, distribution 0.792ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.026 1.142 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X65Y169 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[36]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y169 FDCE (Prop_BFF_SLICEM_C_Q) 0.049 1.191 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[36]/Q net (fo=1, routed) 0.093 1.284 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[36] SLICE_X66Y169 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[36]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.223 1.375 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X66Y169 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[36]/C clock pessimism -0.199 1.176 SLICE_X66Y169 FDCE (Hold_HFF2_SLICEL_C_D) 0.056 1.232 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[36] ------------------------------------------------------------------- required time -1.232 arrival time 1.284 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.053ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.151ns (logic 0.063ns (41.722%) route 0.088ns (58.278%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.368ns Source Clock Delay (SCD): 1.134ns Clock Pessimism Removal (CPR): 0.192ns Clock Net Delay (Source): 1.018ns (routing 0.369ns, distribution 0.649ns) Clock Net Delay (Destination): 1.216ns (routing 0.431ns, distribution 0.785ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.018 1.134 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X69Y159 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y159 FDCE (Prop_EFF2_SLICEL_C_Q) 0.048 1.182 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.073 1.255 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in SLICE_X69Y158 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.015 1.270 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__26/O net (fo=1, routed) 0.015 1.285 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] SLICE_X69Y158 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.216 1.368 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X69Y158 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.192 1.176 SLICE_X69Y158 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.232 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.232 arrival time 1.285 ------------------------------------------------------------------- slack 0.053 Slack (MET) : 0.053ns (arrival time - required time) Source: SFP_GEN[27].ngccm_status_reg_reg[27][24]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[27].ngccm_status_reg_reg[27][24]/D (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.113ns (logic 0.064ns (56.637%) route 0.049ns (43.363%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.004ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.375ns Source Clock Delay (SCD): 1.142ns Clock Pessimism Removal (CPR): 0.229ns Clock Net Delay (Source): 1.026ns (routing 0.369ns, distribution 0.657ns) Clock Net Delay (Destination): 1.223ns (routing 0.431ns, distribution 0.792ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.026 1.142 g_gbt_bank[2].gbtbank_n_54 SLICE_X69Y175 FDPE r SFP_GEN[27].ngccm_status_reg_reg[27][24]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y175 FDPE (Prop_FFF_SLICEL_C_Q) 0.049 1.191 r SFP_GEN[27].ngccm_status_reg_reg[27][24]/Q net (fo=2, routed) 0.037 1.228 SFP_GEN[27].ngCCM_gbt/SFP_GEN[27].ngccm_status_reg_reg[27][24]_0[8] SLICE_X69Y175 LUT2 (Prop_F6LUT_SLICEL_I0_O) 0.015 1.243 r SFP_GEN[27].ngCCM_gbt/SFP_GEN[27].ngccm_status_reg[27][24]_i_2/O net (fo=1, routed) 0.012 1.255 SFP_GEN[27].ngCCM_gbt_n_393 SLICE_X69Y175 FDPE r SFP_GEN[27].ngccm_status_reg_reg[27][24]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.223 1.375 g_gbt_bank[2].gbtbank_n_54 SLICE_X69Y175 FDPE r SFP_GEN[27].ngccm_status_reg_reg[27][24]/C clock pessimism -0.229 1.146 SLICE_X69Y175 FDPE (Hold_FFF_SLICEL_C_D) 0.056 1.202 SFP_GEN[27].ngccm_status_reg_reg[27][24] ------------------------------------------------------------------- required time -1.202 arrival time 1.255 ------------------------------------------------------------------- slack 0.053 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_29 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y65 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y176 g_clock_rate_din[27].ngccm_status_cnt_reg[27][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y176 g_clock_rate_din[27].ngccm_status_cnt_reg[27][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y176 g_clock_rate_din[27].ngccm_status_cnt_reg[27][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y176 g_clock_rate_din[27].ngccm_status_cnt_reg[27][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y176 g_clock_rate_din[27].ngccm_status_cnt_reg[27][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y176 g_clock_rate_din[27].ngccm_status_cnt_reg[27][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X69Y177 g_clock_rate_din[27].ngccm_status_cnt_reg[27][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X67Y174 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y172 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y172 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X69Y174 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X69Y174 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X69Y175 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X67Y172 g_clock_rate_din[27].rx_frameclk_div2_reg[27]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X66Y178 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X66Y178 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X66Y177 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X66Y177 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X66Y177 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_30 To Clock: gtwiz_userclk_rx_srcclk_out[0]_30 Setup : 0 Failing Endpoints, Worst Slack 2.431ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.034ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.431ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 5.887ns (logic 1.547ns (26.278%) route 4.340ns (73.722%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.091ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.623ns = ( 10.940 - 8.317 ) Source Clock Delay (SCD): 2.742ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.317ns (routing 0.789ns, distribution 1.528ns) Clock Net Delay (Destination): 2.247ns (routing 0.708ns, distribution 1.539ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.317 2.742 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.826 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.195 7.021 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X58Y212 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 7.265 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/O net (fo=5, routed) 0.401 7.666 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X57Y218 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.219 7.885 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__28/O net (fo=7, routed) 0.744 8.629 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X58Y215 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.247 10.940 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y215 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.210 11.151 clock uncertainty -0.035 11.115 SLICE_X58Y215 FDRE (Setup_EFF_SLICEM_C_CE) -0.055 11.060 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 11.060 arrival time -8.629 ------------------------------------------------------------------- slack 2.431 Slack (MET) : 2.596ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 5.710ns (logic 1.651ns (28.914%) route 4.059ns (71.086%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.079ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.611ns = ( 10.928 - 8.317 ) Source Clock Delay (SCD): 2.742ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.317ns (routing 0.789ns, distribution 1.528ns) Clock Net Delay (Destination): 2.235ns (routing 0.708ns, distribution 1.527ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.317 2.742 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.826 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.195 7.021 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X58Y212 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 7.265 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/O net (fo=5, routed) 0.324 7.589 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X58Y218 LUT4 (Prop_B6LUT_SLICEM_I2_O) 0.150 7.739 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__27/O net (fo=1, routed) 0.086 7.825 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__27_n_0 SLICE_X58Y218 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 7.998 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__27/O net (fo=2, routed) 0.454 8.452 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__27_n_0 SLICE_X58Y212 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.235 10.928 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y212 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.210 11.139 clock uncertainty -0.035 11.103 SLICE_X58Y212 FDCE (Setup_GFF_SLICEM_C_CE) -0.055 11.048 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.048 arrival time -8.452 ------------------------------------------------------------------- slack 2.596 Slack (MET) : 2.596ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 5.710ns (logic 1.651ns (28.914%) route 4.059ns (71.086%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.079ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.611ns = ( 10.928 - 8.317 ) Source Clock Delay (SCD): 2.742ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.317ns (routing 0.789ns, distribution 1.528ns) Clock Net Delay (Destination): 2.235ns (routing 0.708ns, distribution 1.527ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.317 2.742 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.826 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.195 7.021 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X58Y212 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 7.265 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/O net (fo=5, routed) 0.324 7.589 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X58Y218 LUT4 (Prop_B6LUT_SLICEM_I2_O) 0.150 7.739 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__27/O net (fo=1, routed) 0.086 7.825 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__27_n_0 SLICE_X58Y218 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 7.998 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__27/O net (fo=2, routed) 0.454 8.452 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__27_n_0 SLICE_X58Y212 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.235 10.928 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y212 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.210 11.139 clock uncertainty -0.035 11.103 SLICE_X58Y212 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 11.048 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.048 arrival time -8.452 ------------------------------------------------------------------- slack 2.596 Slack (MET) : 2.658ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 5.660ns (logic 1.547ns (27.332%) route 4.113ns (72.668%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.094ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.626ns = ( 10.943 - 8.317 ) Source Clock Delay (SCD): 2.742ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.317ns (routing 0.789ns, distribution 1.528ns) Clock Net Delay (Destination): 2.250ns (routing 0.708ns, distribution 1.542ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.317 2.742 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.826 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.195 7.021 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X58Y212 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 7.265 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/O net (fo=5, routed) 0.401 7.666 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X57Y218 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.219 7.885 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__28/O net (fo=7, routed) 0.517 8.402 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X57Y217 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.250 10.943 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X57Y217 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.210 11.154 clock uncertainty -0.035 11.118 SLICE_X57Y217 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 11.060 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.060 arrival time -8.402 ------------------------------------------------------------------- slack 2.658 Slack (MET) : 2.663ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[28].rx_data_ngccm_reg[28][51]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 5.523ns (logic 0.228ns (4.128%) route 5.295ns (95.872%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.041ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.616ns = ( 10.933 - 8.317 ) Source Clock Delay (SCD): 2.867ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.442ns (routing 0.789ns, distribution 1.653ns) Clock Net Delay (Destination): 2.240ns (routing 0.708ns, distribution 1.532ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.442 2.867 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y180 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y180 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.006 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.317 6.323 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X59Y213 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.089 6.412 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/SFP_GEN[28].rx_data_ngccm[28][83]_i_1/O net (fo=76, routed) 1.978 8.390 rx_data_ngccm[28] SLICE_X56Y202 FDCE r SFP_GEN[28].rx_data_ngccm_reg[28][51]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.240 10.933 g_gbt_bank[2].gbtbank_n_64 SLICE_X56Y202 FDCE r SFP_GEN[28].rx_data_ngccm_reg[28][51]/C clock pessimism 0.210 11.143 clock uncertainty -0.035 11.108 SLICE_X56Y202 FDCE (Setup_EFF_SLICEL_C_CE) -0.055 11.053 SFP_GEN[28].rx_data_ngccm_reg[28][51] ------------------------------------------------------------------- required time 11.053 arrival time -8.390 ------------------------------------------------------------------- slack 2.663 Slack (MET) : 2.665ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 5.656ns (logic 1.547ns (27.351%) route 4.109ns (72.649%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.094ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.626ns = ( 10.943 - 8.317 ) Source Clock Delay (SCD): 2.742ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.317ns (routing 0.789ns, distribution 1.528ns) Clock Net Delay (Destination): 2.250ns (routing 0.708ns, distribution 1.542ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.317 2.742 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.826 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.195 7.021 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X58Y212 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 7.265 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/O net (fo=5, routed) 0.401 7.666 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X57Y218 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.219 7.885 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__28/O net (fo=7, routed) 0.513 8.398 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X57Y217 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.250 10.943 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X57Y217 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.210 11.154 clock uncertainty -0.035 11.118 SLICE_X57Y217 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 11.063 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 11.063 arrival time -8.398 ------------------------------------------------------------------- slack 2.665 Slack (MET) : 2.726ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 5.585ns (logic 1.547ns (27.699%) route 4.038ns (72.301%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.084ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.616ns = ( 10.933 - 8.317 ) Source Clock Delay (SCD): 2.742ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.317ns (routing 0.789ns, distribution 1.528ns) Clock Net Delay (Destination): 2.240ns (routing 0.708ns, distribution 1.532ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.317 2.742 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.826 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.195 7.021 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X58Y212 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 7.265 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/O net (fo=5, routed) 0.401 7.666 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X57Y218 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.219 7.885 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__28/O net (fo=7, routed) 0.442 8.327 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X58Y216 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.240 10.933 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y216 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.210 11.144 clock uncertainty -0.035 11.108 SLICE_X58Y216 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 11.053 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 11.053 arrival time -8.327 ------------------------------------------------------------------- slack 2.726 Slack (MET) : 2.816ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 5.508ns (logic 1.474ns (26.761%) route 4.034ns (73.239%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.097ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.629ns = ( 10.946 - 8.317 ) Source Clock Delay (SCD): 2.742ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.317ns (routing 0.789ns, distribution 1.528ns) Clock Net Delay (Destination): 2.253ns (routing 0.708ns, distribution 1.545ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.317 2.742 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.826 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.195 7.021 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X58Y212 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 7.265 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/O net (fo=5, routed) 0.320 7.585 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X58Y218 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 7.731 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__28/O net (fo=3, routed) 0.519 8.250 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecFalseHeaders0 SLICE_X58Y218 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.253 10.946 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y218 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.210 11.157 clock uncertainty -0.035 11.121 SLICE_X58Y218 FDRE (Setup_AFF2_SLICEM_C_CE) -0.055 11.066 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 11.066 arrival time -8.250 ------------------------------------------------------------------- slack 2.816 Slack (MET) : 2.816ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 5.508ns (logic 1.474ns (26.761%) route 4.034ns (73.239%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.097ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.629ns = ( 10.946 - 8.317 ) Source Clock Delay (SCD): 2.742ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.317ns (routing 0.789ns, distribution 1.528ns) Clock Net Delay (Destination): 2.253ns (routing 0.708ns, distribution 1.545ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.317 2.742 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.826 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.195 7.021 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X58Y212 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 7.265 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/O net (fo=5, routed) 0.320 7.585 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X58Y218 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 7.731 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__28/O net (fo=3, routed) 0.519 8.250 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecFalseHeaders0 SLICE_X58Y218 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.253 10.946 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y218 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C clock pessimism 0.210 11.157 clock uncertainty -0.035 11.121 SLICE_X58Y218 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 11.066 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2] ------------------------------------------------------------------- required time 11.066 arrival time -8.250 ------------------------------------------------------------------- slack 2.816 Slack (MET) : 2.818ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 5.504ns (logic 1.547ns (28.107%) route 3.957ns (71.893%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.095ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.627ns = ( 10.944 - 8.317 ) Source Clock Delay (SCD): 2.742ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.317ns (routing 0.789ns, distribution 1.528ns) Clock Net Delay (Destination): 2.251ns (routing 0.708ns, distribution 1.543ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.317 2.742 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.826 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.195 7.021 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X58Y212 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 7.265 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/O net (fo=5, routed) 0.401 7.666 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X57Y218 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.219 7.885 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__28/O net (fo=7, routed) 0.361 8.246 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X58Y218 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.251 10.944 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y218 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.210 11.155 clock uncertainty -0.035 11.119 SLICE_X58Y218 FDRE (Setup_EFF_SLICEM_C_CE) -0.055 11.064 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 11.064 arrival time -8.246 ------------------------------------------------------------------- slack 2.818 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.034ns (arrival time - required time) Source: SFP_GEN[28].rx_data_ngccm_reg[28][21]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[21]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.163ns (logic 0.049ns (30.061%) route 0.114ns (69.939%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.364ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.017ns (routing 0.376ns, distribution 0.641ns) Clock Net Delay (Destination): 1.212ns (routing 0.440ns, distribution 0.772ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.133 g_gbt_bank[2].gbtbank_n_64 SLICE_X66Y212 FDCE r SFP_GEN[28].rx_data_ngccm_reg[28][21]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y212 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.182 r SFP_GEN[28].rx_data_ngccm_reg[28][21]/Q net (fo=1, routed) 0.114 1.296 SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[83]_0[9] SLICE_X67Y212 FDCE r SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[21]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.212 1.364 SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X67Y212 FDCE r SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[21]/C clock pessimism -0.158 1.206 SLICE_X67Y212 FDCE (Hold_AFF2_SLICEM_C_D) 0.056 1.262 SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[21] ------------------------------------------------------------------- required time -1.262 arrival time 1.296 ------------------------------------------------------------------- slack 0.034 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.193ns (logic 0.094ns (48.705%) route 0.099ns (51.295%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.377ns Source Clock Delay (SCD): 1.125ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.009ns (routing 0.376ns, distribution 0.633ns) Clock Net Delay (Destination): 1.225ns (routing 0.440ns, distribution 0.785ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.009 1.125 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X64Y212 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y212 FDCE (Prop_AFF2_SLICEM_C_Q) 0.049 1.174 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.087 1.261 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/feedbackRegister[0] SLICE_X65Y212 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.045 1.306 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__27/O net (fo=1, routed) 0.012 1.318 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[0] SLICE_X65Y212 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.225 1.377 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X65Y212 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C clock pessimism -0.158 1.219 SLICE_X65Y212 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.275 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19] ------------------------------------------------------------------- required time -1.275 arrival time 1.318 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[20]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.202ns (logic 0.095ns (47.030%) route 0.107ns (52.970%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.099ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.369ns Source Clock Delay (SCD): 1.112ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 0.996ns (routing 0.376ns, distribution 0.620ns) Clock Net Delay (Destination): 1.217ns (routing 0.440ns, distribution 0.777ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.996 1.112 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X61Y209 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y209 FDCE (Prop_DFF_SLICEM_C_Q) 0.049 1.161 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/Q net (fo=29, routed) 0.092 1.253 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0] SLICE_X62Y209 LUT5 (Prop_B6LUT_SLICEM_I2_O) 0.046 1.299 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[20]_i_1__33/O net (fo=1, routed) 0.015 1.314 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg00[20] SLICE_X62Y209 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.217 1.369 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X62Y209 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[20]/C clock pessimism -0.158 1.211 SLICE_X62Y209 FDCE (Hold_BFF_SLICEM_C_D) 0.056 1.267 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[20] ------------------------------------------------------------------- required time -1.267 arrival time 1.314 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.141ns (logic 0.094ns (66.667%) route 0.047ns (33.333%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.365ns Source Clock Delay (SCD): 1.126ns Clock Pessimism Removal (CPR): 0.202ns Clock Net Delay (Source): 1.010ns (routing 0.376ns, distribution 0.634ns) Clock Net Delay (Destination): 1.213ns (routing 0.440ns, distribution 0.773ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.010 1.126 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X63Y209 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y209 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 1.175 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Q net (fo=2, routed) 0.035 1.210 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_11_in SLICE_X63Y209 LUT3 (Prop_F6LUT_SLICEL_I2_O) 0.045 1.255 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__27/O net (fo=1, routed) 0.012 1.267 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[4] SLICE_X63Y209 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.213 1.365 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X63Y209 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.202 1.163 SLICE_X63Y209 FDRE (Hold_FFF_SLICEL_C_D) 0.056 1.219 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.219 arrival time 1.267 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: SFP_GEN[28].rx_data_ngccm_reg[28][37]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[36]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.169ns (logic 0.080ns (47.337%) route 0.089ns (52.663%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.351ns Source Clock Delay (SCD): 1.128ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.012ns (routing 0.376ns, distribution 0.636ns) Clock Net Delay (Destination): 1.199ns (routing 0.440ns, distribution 0.759ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.012 1.128 g_gbt_bank[2].gbtbank_n_64 SLICE_X63Y213 FDCE r SFP_GEN[28].rx_data_ngccm_reg[28][37]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y213 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 1.177 r SFP_GEN[28].rx_data_ngccm_reg[28][37]/Q net (fo=1, routed) 0.073 1.250 g_gbt_bank[2].gbtbank/RX_Word_rx40_reg[78]_0[13] SLICE_X64Y213 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.031 1.281 r g_gbt_bank[2].gbtbank/RX_Word_rx40[36]_i_1__5/O net (fo=1, routed) 0.016 1.297 SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[83]_0[22] SLICE_X64Y213 FDCE r SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[36]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.199 1.351 SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X64Y213 FDCE r SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[36]/C clock pessimism -0.158 1.193 SLICE_X64Y213 FDCE (Hold_DFF_SLICEM_C_D) 0.056 1.249 SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[36] ------------------------------------------------------------------- required time -1.249 arrival time 1.297 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.094ns (66.197%) route 0.048ns (33.803%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.365ns Source Clock Delay (SCD): 1.126ns Clock Pessimism Removal (CPR): 0.202ns Clock Net Delay (Source): 1.010ns (routing 0.376ns, distribution 0.634ns) Clock Net Delay (Destination): 1.213ns (routing 0.440ns, distribution 0.773ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.010 1.126 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X63Y209 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y209 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 1.175 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Q net (fo=1, routed) 0.034 1.209 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] SLICE_X63Y209 LUT3 (Prop_G6LUT_SLICEL_I0_O) 0.045 1.254 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__27/O net (fo=1, routed) 0.014 1.268 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[1] SLICE_X63Y209 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.213 1.365 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X63Y209 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.202 1.163 SLICE_X63Y209 FDRE (Hold_GFF_SLICEL_C_D) 0.056 1.219 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.219 arrival time 1.268 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.190ns (logic 0.101ns (53.158%) route 0.089ns (46.842%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.365ns Source Clock Delay (SCD): 1.124ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.008ns (routing 0.376ns, distribution 0.632ns) Clock Net Delay (Destination): 1.213ns (routing 0.440ns, distribution 0.773ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.124 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X64Y212 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y212 FDCE (Prop_FFF2_SLICEM_C_Q) 0.048 1.172 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Q net (fo=2, routed) 0.074 1.246 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_5_in SLICE_X63Y212 LUT3 (Prop_B6LUT_SLICEL_I2_O) 0.053 1.299 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__27/O net (fo=1, routed) 0.015 1.314 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[1] SLICE_X63Y212 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.213 1.365 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X63Y212 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.158 1.207 SLICE_X63Y212 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.263 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.263 arrival time 1.314 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[28].rx_data_ngccm_reg[28][31]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.048ns (33.333%) route 0.096ns (66.667%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.373ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.020ns (routing 0.376ns, distribution 0.644ns) Clock Net Delay (Destination): 1.221ns (routing 0.440ns, distribution 0.781ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.136 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X65Y212 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y212 FDRE (Prop_CFF_SLICEM_C_Q) 0.048 1.184 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/Q net (fo=1, routed) 0.096 1.280 rx_data[28][31] SLICE_X66Y212 FDCE r SFP_GEN[28].rx_data_ngccm_reg[28][31]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.221 1.373 g_gbt_bank[2].gbtbank_n_64 SLICE_X66Y212 FDCE r SFP_GEN[28].rx_data_ngccm_reg[28][31]/C clock pessimism -0.201 1.172 SLICE_X66Y212 FDCE (Hold_HFF2_SLICEL_C_D) 0.056 1.228 SFP_GEN[28].rx_data_ngccm_reg[28][31] ------------------------------------------------------------------- required time -1.228 arrival time 1.280 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.052ns (arrival time - required time) Source: SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[36]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[28].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.193ns (logic 0.049ns (25.389%) route 0.144ns (74.611%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.365ns Source Clock Delay (SCD): 1.122ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.006ns (routing 0.376ns, distribution 0.630ns) Clock Net Delay (Destination): 1.213ns (routing 0.440ns, distribution 0.773ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.006 1.122 SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X64Y213 FDCE r SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[36]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y213 FDCE (Prop_DFF_SLICEM_C_Q) 0.049 1.171 r SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[36]/Q net (fo=1, routed) 0.144 1.315 SFP_GEN[28].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]_0[6] SLICE_X62Y213 FDRE r SFP_GEN[28].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.213 1.365 SFP_GEN[28].ngCCM_gbt/CrossClock_DV_cnt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X62Y213 FDRE r SFP_GEN[28].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C clock pessimism -0.158 1.207 SLICE_X62Y213 FDRE (Hold_GFF2_SLICEM_C_D) 0.056 1.263 SFP_GEN[28].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36] ------------------------------------------------------------------- required time -1.263 arrival time 1.315 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.053ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[28].rx_data_ngccm_reg[28][22]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.196ns (logic 0.049ns (25.000%) route 0.147ns (75.000%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.373ns Source Clock Delay (SCD): 1.127ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.011ns (routing 0.376ns, distribution 0.635ns) Clock Net Delay (Destination): 1.221ns (routing 0.440ns, distribution 0.781ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.011 1.127 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X63Y212 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y212 FDRE (Prop_BFF_SLICEL_C_Q) 0.049 1.176 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/Q net (fo=1, routed) 0.147 1.323 rx_data[28][22] SLICE_X66Y212 FDCE r SFP_GEN[28].rx_data_ngccm_reg[28][22]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.221 1.373 g_gbt_bank[2].gbtbank_n_64 SLICE_X66Y212 FDCE r SFP_GEN[28].rx_data_ngccm_reg[28][22]/C clock pessimism -0.158 1.215 SLICE_X66Y212 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.270 SFP_GEN[28].rx_data_ngccm_reg[28][22] ------------------------------------------------------------------- required time -1.270 arrival time 1.323 ------------------------------------------------------------------- slack 0.053 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_30 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y93 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y215 g_clock_rate_din[28].ngccm_status_cnt_reg[28][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y215 g_clock_rate_din[28].ngccm_status_cnt_reg[28][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y215 g_clock_rate_din[28].ngccm_status_cnt_reg[28][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y215 g_clock_rate_din[28].ngccm_status_cnt_reg[28][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y218 g_clock_rate_din[28].ngccm_status_cnt_reg[28][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y218 g_clock_rate_din[28].ngccm_status_cnt_reg[28][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y215 g_clock_rate_din[28].ngccm_status_cnt_reg[28][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X64Y214 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X55Y213 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/psAddress_reg[1]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X55Y213 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/psAddress_reg[2]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y215 g_clock_rate_din[28].ngccm_status_cnt_reg[28][0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y215 g_clock_rate_din[28].ngccm_status_cnt_reg[28][1]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y215 g_clock_rate_din[28].ngccm_status_cnt_reg[28][2]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X60Y219 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X60Y219 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X60Y219 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X60Y219 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/C High Pulse Width Slow FDPE/C n/a 0.275 4.159 3.884 SLICE_X54Y205 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X65Y212 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_31 To Clock: gtwiz_userclk_rx_srcclk_out[0]_31 Setup : 0 Failing Endpoints, Worst Slack 3.220ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.036ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.220ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 5.133ns (logic 1.486ns (28.950%) route 3.647ns (71.050%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.126ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.653ns = ( 10.970 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.794ns, distribution 1.521ns) Clock Net Delay (Destination): 2.277ns (routing 0.710ns, distribution 1.567ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.844 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.728 6.572 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X51Y198 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.146 6.718 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/O net (fo=5, routed) 0.274 6.992 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X52Y199 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.090 7.082 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__28/O net (fo=1, routed) 0.159 7.241 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__28_n_0 SLICE_X52Y198 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 7.387 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__28/O net (fo=2, routed) 0.486 7.873 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__28_n_0 SLICE_X54Y197 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.277 10.970 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X54Y197 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.213 11.183 clock uncertainty -0.035 11.147 SLICE_X54Y197 FDCE (Setup_CFF_SLICEL_C_CE) -0.054 11.093 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.093 arrival time -7.873 ------------------------------------------------------------------- slack 3.220 Slack (MET) : 3.220ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 5.133ns (logic 1.486ns (28.950%) route 3.647ns (71.050%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.126ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.653ns = ( 10.970 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.794ns, distribution 1.521ns) Clock Net Delay (Destination): 2.277ns (routing 0.710ns, distribution 1.567ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.844 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.728 6.572 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X51Y198 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.146 6.718 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/O net (fo=5, routed) 0.274 6.992 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X52Y199 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.090 7.082 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__28/O net (fo=1, routed) 0.159 7.241 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__28_n_0 SLICE_X52Y198 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 7.387 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__28/O net (fo=2, routed) 0.486 7.873 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__28_n_0 SLICE_X54Y197 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.277 10.970 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X54Y197 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.213 11.183 clock uncertainty -0.035 11.147 SLICE_X54Y197 FDCE (Setup_DFF_SLICEL_C_CE) -0.054 11.093 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.093 arrival time -7.873 ------------------------------------------------------------------- slack 3.220 Slack (MET) : 3.318ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 5.031ns (logic 1.476ns (29.338%) route 3.555ns (70.662%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.123ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.650ns = ( 10.967 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.794ns, distribution 1.521ns) Clock Net Delay (Destination): 2.274ns (routing 0.710ns, distribution 1.564ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.844 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.728 6.572 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X51Y198 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.146 6.718 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/O net (fo=5, routed) 0.220 6.938 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X52Y198 LUT6 (Prop_F6LUT_SLICEM_I0_O) 0.226 7.164 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__29/O net (fo=5, routed) 0.607 7.771 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 SLICE_X53Y195 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.274 10.967 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y195 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.213 11.180 clock uncertainty -0.035 11.144 SLICE_X53Y195 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 11.089 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.089 arrival time -7.771 ------------------------------------------------------------------- slack 3.318 Slack (MET) : 3.318ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 5.031ns (logic 1.476ns (29.338%) route 3.555ns (70.662%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.123ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.650ns = ( 10.967 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.794ns, distribution 1.521ns) Clock Net Delay (Destination): 2.274ns (routing 0.710ns, distribution 1.564ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.844 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.728 6.572 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X51Y198 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.146 6.718 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/O net (fo=5, routed) 0.220 6.938 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X52Y198 LUT6 (Prop_F6LUT_SLICEM_I0_O) 0.226 7.164 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__29/O net (fo=5, routed) 0.607 7.771 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 SLICE_X53Y195 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.274 10.967 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y195 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.213 11.180 clock uncertainty -0.035 11.144 SLICE_X53Y195 FDRE (Setup_BFF2_SLICEM_C_CE) -0.055 11.089 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 11.089 arrival time -7.771 ------------------------------------------------------------------- slack 3.318 Slack (MET) : 3.322ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 5.028ns (logic 1.476ns (29.356%) route 3.552ns (70.644%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.123ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.650ns = ( 10.967 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.794ns, distribution 1.521ns) Clock Net Delay (Destination): 2.274ns (routing 0.710ns, distribution 1.564ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.844 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.728 6.572 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X51Y198 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.146 6.718 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/O net (fo=5, routed) 0.220 6.938 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X52Y198 LUT6 (Prop_F6LUT_SLICEM_I0_O) 0.226 7.164 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__29/O net (fo=5, routed) 0.604 7.768 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 SLICE_X53Y195 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.274 10.967 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y195 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C clock pessimism 0.213 11.180 clock uncertainty -0.035 11.144 SLICE_X53Y195 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 11.090 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0] ------------------------------------------------------------------- required time 11.090 arrival time -7.768 ------------------------------------------------------------------- slack 3.322 Slack (MET) : 3.322ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 5.028ns (logic 1.476ns (29.356%) route 3.552ns (70.644%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.123ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.650ns = ( 10.967 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.794ns, distribution 1.521ns) Clock Net Delay (Destination): 2.274ns (routing 0.710ns, distribution 1.564ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.844 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.728 6.572 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X51Y198 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.146 6.718 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/O net (fo=5, routed) 0.220 6.938 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X52Y198 LUT6 (Prop_F6LUT_SLICEM_I0_O) 0.226 7.164 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__29/O net (fo=5, routed) 0.604 7.768 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 SLICE_X53Y195 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.274 10.967 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y195 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C clock pessimism 0.213 11.180 clock uncertainty -0.035 11.144 SLICE_X53Y195 FDRE (Setup_BFF_SLICEM_C_CE) -0.054 11.090 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2] ------------------------------------------------------------------- required time 11.090 arrival time -7.768 ------------------------------------------------------------------- slack 3.322 Slack (MET) : 3.322ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 5.028ns (logic 1.476ns (29.356%) route 3.552ns (70.644%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.123ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.650ns = ( 10.967 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.794ns, distribution 1.521ns) Clock Net Delay (Destination): 2.274ns (routing 0.710ns, distribution 1.564ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.844 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.728 6.572 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X51Y198 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.146 6.718 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/O net (fo=5, routed) 0.220 6.938 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X52Y198 LUT6 (Prop_F6LUT_SLICEM_I0_O) 0.226 7.164 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__29/O net (fo=5, routed) 0.604 7.768 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 SLICE_X53Y195 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.274 10.967 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y195 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism 0.213 11.180 clock uncertainty -0.035 11.144 SLICE_X53Y195 FDRE (Setup_AFF_SLICEM_C_CE) -0.054 11.090 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time 11.090 arrival time -7.768 ------------------------------------------------------------------- slack 3.322 Slack (MET) : 3.403ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 4.946ns (logic 1.475ns (29.822%) route 3.471ns (70.178%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.123ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.650ns = ( 10.967 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.794ns, distribution 1.521ns) Clock Net Delay (Destination): 2.274ns (routing 0.710ns, distribution 1.564ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.844 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.728 6.572 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X51Y198 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.146 6.718 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/O net (fo=5, routed) 0.215 6.933 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X52Y198 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.225 7.158 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__29/O net (fo=7, routed) 0.528 7.686 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 SLICE_X53Y196 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.274 10.967 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y196 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.213 11.180 clock uncertainty -0.035 11.144 SLICE_X53Y196 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 11.089 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.089 arrival time -7.686 ------------------------------------------------------------------- slack 3.403 Slack (MET) : 3.403ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 4.946ns (logic 1.475ns (29.822%) route 3.471ns (70.178%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.123ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.650ns = ( 10.967 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.794ns, distribution 1.521ns) Clock Net Delay (Destination): 2.274ns (routing 0.710ns, distribution 1.564ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.844 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.728 6.572 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X51Y198 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.146 6.718 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/O net (fo=5, routed) 0.215 6.933 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X52Y198 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.225 7.158 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__29/O net (fo=7, routed) 0.528 7.686 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 SLICE_X53Y196 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.274 10.967 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y196 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.213 11.180 clock uncertainty -0.035 11.144 SLICE_X53Y196 FDRE (Setup_BFF2_SLICEM_C_CE) -0.055 11.089 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.089 arrival time -7.686 ------------------------------------------------------------------- slack 3.403 Slack (MET) : 3.407ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 4.943ns (logic 1.475ns (29.840%) route 3.468ns (70.160%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.123ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.650ns = ( 10.967 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.794ns, distribution 1.521ns) Clock Net Delay (Destination): 2.274ns (routing 0.710ns, distribution 1.564ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.844 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.728 6.572 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X51Y198 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.146 6.718 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/O net (fo=5, routed) 0.215 6.933 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X52Y198 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.225 7.158 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__29/O net (fo=7, routed) 0.525 7.683 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 SLICE_X53Y196 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.274 10.967 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y196 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.213 11.180 clock uncertainty -0.035 11.144 SLICE_X53Y196 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 11.090 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 11.090 arrival time -7.683 ------------------------------------------------------------------- slack 3.407 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.081ns (46.821%) route 0.092ns (53.179%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.377ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.020ns (routing 0.377ns, distribution 0.643ns) Clock Net Delay (Destination): 1.225ns (routing 0.443ns, distribution 0.782ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.136 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X60Y191 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y191 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.185 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Q net (fo=2, routed) 0.076 1.261 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_27_in SLICE_X61Y191 LUT3 (Prop_H6LUT_SLICEM_I2_O) 0.032 1.293 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__28/O net (fo=1, routed) 0.016 1.309 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[12] SLICE_X61Y191 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.225 1.377 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X61Y191 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C clock pessimism -0.160 1.217 SLICE_X61Y191 FDRE (Hold_HFF_SLICEM_C_D) 0.056 1.273 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12] ------------------------------------------------------------------- required time -1.273 arrival time 1.309 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.177ns (logic 0.089ns (50.282%) route 0.088ns (49.718%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.377ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.020ns (routing 0.377ns, distribution 0.643ns) Clock Net Delay (Destination): 1.225ns (routing 0.443ns, distribution 0.782ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.136 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X60Y191 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y191 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.185 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Q net (fo=2, routed) 0.076 1.261 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_27_in SLICE_X61Y191 LUT3 (Prop_H5LUT_SLICEM_I0_O) 0.040 1.301 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__28/O net (fo=1, routed) 0.012 1.313 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[14] SLICE_X61Y191 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.225 1.377 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X61Y191 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C clock pessimism -0.160 1.217 SLICE_X61Y191 FDRE (Hold_HFF2_SLICEM_C_D) 0.056 1.273 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14] ------------------------------------------------------------------- required time -1.273 arrival time 1.313 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.181ns (logic 0.094ns (51.934%) route 0.087ns (48.066%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.375ns Source Clock Delay (SCD): 1.130ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.014ns (routing 0.377ns, distribution 0.637ns) Clock Net Delay (Destination): 1.223ns (routing 0.443ns, distribution 0.780ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.130 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X57Y184 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y184 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.179 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Q net (fo=2, routed) 0.071 1.250 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_29_in SLICE_X58Y184 LUT3 (Prop_C6LUT_SLICEM_I2_O) 0.045 1.295 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__28/O net (fo=1, routed) 0.016 1.311 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[13] SLICE_X58Y184 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.223 1.375 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X58Y184 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C clock pessimism -0.160 1.215 SLICE_X58Y184 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.271 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13] ------------------------------------------------------------------- required time -1.271 arrival time 1.311 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.186ns (logic 0.104ns (55.914%) route 0.082ns (44.086%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.375ns Source Clock Delay (SCD): 1.130ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.014ns (routing 0.377ns, distribution 0.637ns) Clock Net Delay (Destination): 1.223ns (routing 0.443ns, distribution 0.780ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.130 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X57Y184 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y184 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.179 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Q net (fo=2, routed) 0.071 1.250 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_29_in SLICE_X58Y184 LUT3 (Prop_C5LUT_SLICEM_I0_O) 0.055 1.305 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__28/O net (fo=1, routed) 0.011 1.316 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[15] SLICE_X58Y184 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.223 1.375 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X58Y184 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C clock pessimism -0.160 1.215 SLICE_X58Y184 FDRE (Hold_CFF2_SLICEM_C_D) 0.056 1.271 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15] ------------------------------------------------------------------- required time -1.271 arrival time 1.316 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[29].rx_data_ngccm_reg[29][27]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.159ns (logic 0.048ns (30.189%) route 0.111ns (69.811%)) Logic Levels: 0 Clock Path Skew: 0.057ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.396ns Source Clock Delay (SCD): 1.145ns Clock Pessimism Removal (CPR): 0.194ns Clock Net Delay (Source): 1.029ns (routing 0.377ns, distribution 0.652ns) Clock Net Delay (Destination): 1.244ns (routing 0.443ns, distribution 0.801ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.029 1.145 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X62Y192 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y192 FDRE (Prop_EFF2_SLICEM_C_Q) 0.048 1.193 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/Q net (fo=1, routed) 0.111 1.304 rx_data[29][27] SLICE_X62Y195 FDCE r SFP_GEN[29].rx_data_ngccm_reg[29][27]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.244 1.396 g_gbt_bank[2].gbtbank_n_74 SLICE_X62Y195 FDCE r SFP_GEN[29].rx_data_ngccm_reg[29][27]/C clock pessimism -0.194 1.202 SLICE_X62Y195 FDCE (Hold_GFF2_SLICEM_C_D) 0.056 1.258 SFP_GEN[29].rx_data_ngccm_reg[29][27] ------------------------------------------------------------------- required time -1.258 arrival time 1.304 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.186ns (logic 0.095ns (51.075%) route 0.091ns (48.925%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.379ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.020ns (routing 0.377ns, distribution 0.643ns) Clock Net Delay (Destination): 1.227ns (routing 0.443ns, distribution 0.784ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.136 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X60Y191 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y191 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.185 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Q net (fo=1, routed) 0.075 1.260 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] SLICE_X61Y191 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.046 1.306 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__28/O net (fo=1, routed) 0.016 1.322 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[0] SLICE_X61Y191 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.227 1.379 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X61Y191 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.160 1.219 SLICE_X61Y191 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.275 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -1.275 arrival time 1.322 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/clkSlipProcess.timer_reg[1]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.152ns (logic 0.064ns (42.105%) route 0.088ns (57.895%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.047ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.352ns Source Clock Delay (SCD): 1.113ns Clock Pessimism Removal (CPR): 0.192ns Clock Net Delay (Source): 0.997ns (routing 0.377ns, distribution 0.620ns) Clock Net Delay (Destination): 1.200ns (routing 0.443ns, distribution 0.757ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.113 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X51Y200 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/clkSlipProcess.timer_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y200 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.162 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/clkSlipProcess.timer_reg[1]/Q net (fo=6, routed) 0.072 1.234 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/timer[1] SLICE_X51Y199 LUT6 (Prop_C6LUT_SLICEL_I5_O) 0.015 1.249 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__29/O net (fo=1, routed) 0.016 1.265 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__29_n_0 SLICE_X51Y199 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.200 1.352 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X51Y199 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C clock pessimism -0.192 1.160 SLICE_X51Y199 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.216 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/clkSlipProcess.timer_reg[5] ------------------------------------------------------------------- required time -1.216 arrival time 1.265 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.184ns (logic 0.095ns (51.630%) route 0.089ns (48.370%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.368ns Source Clock Delay (SCD): 1.129ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.013ns (routing 0.377ns, distribution 0.636ns) Clock Net Delay (Destination): 1.216ns (routing 0.443ns, distribution 0.773ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.013 1.129 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X54Y184 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y184 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.178 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Q net (fo=2, routed) 0.074 1.252 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_11_in SLICE_X55Y184 LUT3 (Prop_B6LUT_SLICEM_I2_O) 0.046 1.298 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__28/O net (fo=1, routed) 0.015 1.313 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[4] SLICE_X55Y184 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.216 1.368 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X55Y184 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.160 1.208 SLICE_X55Y184 FDRE (Hold_BFF_SLICEM_C_D) 0.056 1.264 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.264 arrival time 1.313 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[29].rx_data_ngccm_reg[29][39]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.048ns (32.877%) route 0.098ns (67.123%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.377ns Source Clock Delay (SCD): 1.142ns Clock Pessimism Removal (CPR): 0.194ns Clock Net Delay (Source): 1.026ns (routing 0.377ns, distribution 0.649ns) Clock Net Delay (Destination): 1.225ns (routing 0.443ns, distribution 0.782ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.026 1.142 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X61Y191 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y191 FDRE (Prop_GFF2_SLICEM_C_Q) 0.048 1.190 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/Q net (fo=1, routed) 0.098 1.288 rx_data[29][39] SLICE_X61Y190 FDCE r SFP_GEN[29].rx_data_ngccm_reg[29][39]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.225 1.377 g_gbt_bank[2].gbtbank_n_74 SLICE_X61Y190 FDCE r SFP_GEN[29].rx_data_ngccm_reg[29][39]/C clock pessimism -0.194 1.183 SLICE_X61Y190 FDCE (Hold_GFF_SLICEM_C_D) 0.056 1.239 SFP_GEN[29].rx_data_ngccm_reg[29][39] ------------------------------------------------------------------- required time -1.239 arrival time 1.288 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.112ns (logic 0.064ns (57.143%) route 0.048ns (42.857%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.128ns Clock Pessimism Removal (CPR): 0.226ns Clock Net Delay (Source): 1.012ns (routing 0.377ns, distribution 0.635ns) Clock Net Delay (Destination): 1.207ns (routing 0.443ns, distribution 0.764ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.012 1.128 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y195 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y195 FDRE (Prop_BFF_SLICEM_C_Q) 0.049 1.177 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/Q net (fo=4, routed) 0.036 1.213 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg_n_0_[2] SLICE_X53Y195 LUT6 (Prop_A6LUT_SLICEM_I2_O) 0.015 1.228 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__29/O net (fo=1, routed) 0.012 1.240 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__29_n_0 SLICE_X53Y195 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.207 1.359 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y195 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism -0.226 1.133 SLICE_X53Y195 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.189 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time -1.189 arrival time 1.240 ------------------------------------------------------------------- slack 0.051 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_31 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y91 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X69Y214 g_clock_rate_din[29].ngccm_status_cnt_reg[29][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X69Y214 g_clock_rate_din[29].ngccm_status_cnt_reg[29][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X69Y214 g_clock_rate_din[29].ngccm_status_cnt_reg[29][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X69Y214 g_clock_rate_din[29].ngccm_status_cnt_reg[29][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X69Y214 g_clock_rate_din[29].ngccm_status_cnt_reg[29][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X69Y214 g_clock_rate_din[29].ngccm_status_cnt_reg[29][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X69Y210 g_clock_rate_din[29].ngccm_status_cnt_reg[29][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDPE/C n/a 0.275 4.159 3.884 SLICE_X60Y195 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X56Y192 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[47]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X56Y192 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[53]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X56Y192 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[54]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X58Y194 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[37]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X58Y194 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[38]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X69Y210 g_clock_rate_din[29].ngccm_status_cnt_reg[29][6]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X62Y191 g_clock_rate_din[29].rx_frameclk_div2_reg[29]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X69Y210 g_clock_rate_din[29].rx_test_comm_cnt_reg[29]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X60Y191 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X61Y192 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X61Y192 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_32 To Clock: gtwiz_userclk_rx_srcclk_out[0]_32 Setup : 0 Failing Endpoints, Worst Slack 4.043ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.042ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.043ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].rx_data_ngccm_reg[30][67]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 3.983ns (logic 0.228ns (5.724%) route 3.755ns (94.276%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.201ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.435ns = ( 10.752 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 2.059ns (routing 0.693ns, distribution 1.366ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y214 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y214 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.644 4.632 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X28Y216 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.089 4.721 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/O net (fo=76, routed) 2.111 6.832 rx_data_ngccm[30] SLICE_X22Y202 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][67]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.059 10.752 g_gbt_bank[2].gbtbank_n_84 SLICE_X22Y202 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][67]/C clock pessimism 0.213 10.966 clock uncertainty -0.035 10.930 SLICE_X22Y202 FDCE (Setup_EFF_SLICEM_C_CE) -0.055 10.875 SFP_GEN[30].rx_data_ngccm_reg[30][67] ------------------------------------------------------------------- required time 10.875 arrival time -6.832 ------------------------------------------------------------------- slack 4.043 Slack (MET) : 4.071ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].rx_data_ngccm_reg[30][73]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 3.870ns (logic 0.228ns (5.891%) route 3.642ns (94.109%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.283ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.364ns = ( 10.681 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.988ns (routing 0.693ns, distribution 1.295ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y214 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y214 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.644 4.632 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X28Y216 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.089 4.721 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/O net (fo=76, routed) 1.998 6.719 rx_data_ngccm[30] SLICE_X24Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][73]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.988 10.681 g_gbt_bank[2].gbtbank_n_84 SLICE_X24Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][73]/C clock pessimism 0.202 10.883 clock uncertainty -0.035 10.848 SLICE_X24Y201 FDCE (Setup_EFF2_SLICEL_C_CE) -0.058 10.790 SFP_GEN[30].rx_data_ngccm_reg[30][73] ------------------------------------------------------------------- required time 10.790 arrival time -6.719 ------------------------------------------------------------------- slack 4.071 Slack (MET) : 4.073ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].rx_data_ngccm_reg[30][64]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 3.867ns (logic 0.228ns (5.896%) route 3.639ns (94.104%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.284ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.363ns = ( 10.680 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.987ns (routing 0.693ns, distribution 1.294ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y214 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y214 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.644 4.632 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X28Y216 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.089 4.721 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/O net (fo=76, routed) 1.995 6.716 rx_data_ngccm[30] SLICE_X23Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][64]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.987 10.680 g_gbt_bank[2].gbtbank_n_84 SLICE_X23Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][64]/C clock pessimism 0.202 10.882 clock uncertainty -0.035 10.847 SLICE_X23Y201 FDCE (Setup_EFF2_SLICEM_C_CE) -0.058 10.789 SFP_GEN[30].rx_data_ngccm_reg[30][64] ------------------------------------------------------------------- required time 10.789 arrival time -6.716 ------------------------------------------------------------------- slack 4.073 Slack (MET) : 4.078ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].rx_data_ngccm_reg[30][72]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 3.866ns (logic 0.228ns (5.898%) route 3.638ns (94.102%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.283ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.364ns = ( 10.681 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.988ns (routing 0.693ns, distribution 1.295ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y214 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y214 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.644 4.632 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X28Y216 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.089 4.721 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/O net (fo=76, routed) 1.994 6.715 rx_data_ngccm[30] SLICE_X24Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][72]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.988 10.681 g_gbt_bank[2].gbtbank_n_84 SLICE_X24Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][72]/C clock pessimism 0.202 10.883 clock uncertainty -0.035 10.848 SLICE_X24Y201 FDCE (Setup_EFF_SLICEL_C_CE) -0.055 10.793 SFP_GEN[30].rx_data_ngccm_reg[30][72] ------------------------------------------------------------------- required time 10.793 arrival time -6.715 ------------------------------------------------------------------- slack 4.078 Slack (MET) : 4.078ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].rx_data_ngccm_reg[30][74]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 3.866ns (logic 0.228ns (5.898%) route 3.638ns (94.102%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.283ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.364ns = ( 10.681 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.988ns (routing 0.693ns, distribution 1.295ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y214 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y214 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.644 4.632 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X28Y216 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.089 4.721 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/O net (fo=76, routed) 1.994 6.715 rx_data_ngccm[30] SLICE_X24Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][74]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.988 10.681 g_gbt_bank[2].gbtbank_n_84 SLICE_X24Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][74]/C clock pessimism 0.202 10.883 clock uncertainty -0.035 10.848 SLICE_X24Y201 FDCE (Setup_FFF_SLICEL_C_CE) -0.055 10.793 SFP_GEN[30].rx_data_ngccm_reg[30][74] ------------------------------------------------------------------- required time 10.793 arrival time -6.715 ------------------------------------------------------------------- slack 4.078 Slack (MET) : 4.079ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].rx_data_ngccm_reg[30][56]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 3.864ns (logic 0.228ns (5.901%) route 3.636ns (94.099%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.284ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.363ns = ( 10.680 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.987ns (routing 0.693ns, distribution 1.294ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y214 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y214 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.644 4.632 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X28Y216 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.089 4.721 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/O net (fo=76, routed) 1.992 6.713 rx_data_ngccm[30] SLICE_X23Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][56]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.987 10.680 g_gbt_bank[2].gbtbank_n_84 SLICE_X23Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][56]/C clock pessimism 0.202 10.882 clock uncertainty -0.035 10.847 SLICE_X23Y201 FDCE (Setup_EFF_SLICEM_C_CE) -0.055 10.792 SFP_GEN[30].rx_data_ngccm_reg[30][56] ------------------------------------------------------------------- required time 10.792 arrival time -6.713 ------------------------------------------------------------------- slack 4.079 Slack (MET) : 4.130ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].rx_data_ngccm_reg[30][68]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 3.815ns (logic 0.228ns (5.976%) route 3.587ns (94.024%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.282ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.365ns = ( 10.682 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.989ns (routing 0.693ns, distribution 1.296ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y214 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y214 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.644 4.632 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X28Y216 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.089 4.721 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/O net (fo=76, routed) 1.943 6.664 rx_data_ngccm[30] SLICE_X23Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][68]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.989 10.682 g_gbt_bank[2].gbtbank_n_84 SLICE_X23Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][68]/C clock pessimism 0.202 10.884 clock uncertainty -0.035 10.849 SLICE_X23Y201 FDCE (Setup_AFF2_SLICEM_C_CE) -0.055 10.794 SFP_GEN[30].rx_data_ngccm_reg[30][68] ------------------------------------------------------------------- required time 10.794 arrival time -6.664 ------------------------------------------------------------------- slack 4.130 Slack (MET) : 4.130ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].rx_data_ngccm_reg[30][70]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 3.815ns (logic 0.228ns (5.976%) route 3.587ns (94.024%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.282ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.365ns = ( 10.682 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.989ns (routing 0.693ns, distribution 1.296ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y214 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y214 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.644 4.632 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X28Y216 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.089 4.721 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/O net (fo=76, routed) 1.943 6.664 rx_data_ngccm[30] SLICE_X23Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][70]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.989 10.682 g_gbt_bank[2].gbtbank_n_84 SLICE_X23Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][70]/C clock pessimism 0.202 10.884 clock uncertainty -0.035 10.849 SLICE_X23Y201 FDCE (Setup_BFF2_SLICEM_C_CE) -0.055 10.794 SFP_GEN[30].rx_data_ngccm_reg[30][70] ------------------------------------------------------------------- required time 10.794 arrival time -6.664 ------------------------------------------------------------------- slack 4.130 Slack (MET) : 4.134ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].rx_data_ngccm_reg[30][66]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 3.812ns (logic 0.228ns (5.981%) route 3.584ns (94.019%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.282ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.365ns = ( 10.682 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.989ns (routing 0.693ns, distribution 1.296ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y214 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y214 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.644 4.632 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X28Y216 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.089 4.721 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/O net (fo=76, routed) 1.940 6.661 rx_data_ngccm[30] SLICE_X23Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][66]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.989 10.682 g_gbt_bank[2].gbtbank_n_84 SLICE_X23Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][66]/C clock pessimism 0.202 10.884 clock uncertainty -0.035 10.849 SLICE_X23Y201 FDCE (Setup_AFF_SLICEM_C_CE) -0.054 10.795 SFP_GEN[30].rx_data_ngccm_reg[30][66] ------------------------------------------------------------------- required time 10.795 arrival time -6.661 ------------------------------------------------------------------- slack 4.134 Slack (MET) : 4.134ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].rx_data_ngccm_reg[30][69]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 3.812ns (logic 0.228ns (5.981%) route 3.584ns (94.019%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.282ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.365ns = ( 10.682 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.989ns (routing 0.693ns, distribution 1.296ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y214 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y214 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.644 4.632 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X28Y216 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.089 4.721 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/O net (fo=76, routed) 1.940 6.661 rx_data_ngccm[30] SLICE_X23Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][69]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.989 10.682 g_gbt_bank[2].gbtbank_n_84 SLICE_X23Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][69]/C clock pessimism 0.202 10.884 clock uncertainty -0.035 10.849 SLICE_X23Y201 FDCE (Setup_BFF_SLICEM_C_CE) -0.054 10.795 SFP_GEN[30].rx_data_ngccm_reg[30][69] ------------------------------------------------------------------- required time 10.795 arrival time -6.661 ------------------------------------------------------------------- slack 4.134 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[26]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[26]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.165ns (logic 0.049ns (29.697%) route 0.116ns (70.303%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.197ns Source Clock Delay (SCD): 0.985ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.869ns (routing 0.368ns, distribution 0.501ns) Clock Net Delay (Destination): 1.045ns (routing 0.432ns, distribution 0.613ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.869 0.985 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X27Y210 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[26]/C ------------------------------------------------------------------- ------------------- SLICE_X27Y210 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 1.034 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[26]/Q net (fo=1, routed) 0.116 1.150 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[26] SLICE_X27Y208 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.045 1.197 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X27Y208 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[26]/C clock pessimism -0.144 1.053 SLICE_X27Y208 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.108 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[26] ------------------------------------------------------------------- required time -1.108 arrival time 1.150 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[11]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[11]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.197ns (logic 0.048ns (24.365%) route 0.149ns (75.634%)) Logic Levels: 0 Clock Path Skew: 0.096ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.227ns Source Clock Delay (SCD): 0.987ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.871ns (routing 0.368ns, distribution 0.503ns) Clock Net Delay (Destination): 1.075ns (routing 0.432ns, distribution 0.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.871 0.987 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X24Y208 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X24Y208 FDCE (Prop_GFF_SLICEL_C_Q) 0.048 1.035 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[11]/Q net (fo=1, routed) 0.149 1.184 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[11] SLICE_X25Y208 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.075 1.227 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X25Y208 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[11]/C clock pessimism -0.144 1.083 SLICE_X25Y208 FDCE (Hold_AFF2_SLICEM_C_D) 0.056 1.139 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[11] ------------------------------------------------------------------- required time -1.139 arrival time 1.184 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[32]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.141ns (logic 0.049ns (34.752%) route 0.092ns (65.248%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.217ns Source Clock Delay (SCD): 0.994ns Clock Pessimism Removal (CPR): 0.184ns Clock Net Delay (Source): 0.878ns (routing 0.368ns, distribution 0.510ns) Clock Net Delay (Destination): 1.065ns (routing 0.432ns, distribution 0.633ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.878 0.994 SFP_GEN[30].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X31Y209 FDCE r SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[32]/C ------------------------------------------------------------------- ------------------- SLICE_X31Y209 FDCE (Prop_DFF_SLICEM_C_Q) 0.049 1.043 r SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[32]/Q net (fo=1, routed) 0.092 1.135 SFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]_0[4] SLICE_X32Y209 FDRE r SFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.065 1.217 SFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X32Y209 FDRE r SFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C clock pessimism -0.184 1.033 SLICE_X32Y209 FDRE (Hold_DFF2_SLICEL_C_D) 0.056 1.089 SFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32] ------------------------------------------------------------------- required time -1.089 arrival time 1.135 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.237ns Source Clock Delay (SCD): 1.008ns Clock Pessimism Removal (CPR): 0.187ns Clock Net Delay (Source): 0.892ns (routing 0.368ns, distribution 0.524ns) Clock Net Delay (Destination): 1.085ns (routing 0.432ns, distribution 0.653ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.892 1.008 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X26Y200 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X26Y200 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.057 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Q net (fo=2, routed) 0.034 1.091 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_5_in SLICE_X26Y200 LUT3 (Prop_C6LUT_SLICEL_I2_O) 0.045 1.136 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__29/O net (fo=1, routed) 0.016 1.152 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[1] SLICE_X26Y200 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.085 1.237 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X26Y200 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.187 1.050 SLICE_X26Y200 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.106 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.106 arrival time 1.152 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].rx_data_ngccm_reg[30][37]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.048ns (33.566%) route 0.095ns (66.434%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.222ns Source Clock Delay (SCD): 0.998ns Clock Pessimism Removal (CPR): 0.184ns Clock Net Delay (Source): 0.882ns (routing 0.368ns, distribution 0.514ns) Clock Net Delay (Destination): 1.070ns (routing 0.432ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.882 0.998 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X29Y211 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y211 FDRE (Prop_GFF_SLICEM_C_Q) 0.048 1.046 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/Q net (fo=1, routed) 0.095 1.141 rx_data[30][37] SLICE_X30Y211 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][37]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.070 1.222 g_gbt_bank[2].gbtbank_n_84 SLICE_X30Y211 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][37]/C clock pessimism -0.184 1.038 SLICE_X30Y211 FDCE (Hold_BFF2_SLICEL_C_D) 0.056 1.094 SFP_GEN[30].rx_data_ngccm_reg[30][37] ------------------------------------------------------------------- required time -1.094 arrival time 1.141 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.047ns (arrival time - required time) Source: SFP_GEN[30].rx_data_ngccm_reg[30][72]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[72]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.187ns (logic 0.094ns (50.267%) route 0.093ns (49.733%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.236ns Source Clock Delay (SCD): 1.008ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.892ns (routing 0.368ns, distribution 0.524ns) Clock Net Delay (Destination): 1.084ns (routing 0.432ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.892 1.008 g_gbt_bank[2].gbtbank_n_84 SLICE_X24Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][72]/C ------------------------------------------------------------------- ------------------- SLICE_X24Y201 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.057 r SFP_GEN[30].rx_data_ngccm_reg[30][72]/Q net (fo=1, routed) 0.077 1.134 g_gbt_bank[2].gbtbank/RX_Word_rx40_reg[78]_1[48] SLICE_X26Y201 LUT3 (Prop_C6LUT_SLICEL_I1_O) 0.045 1.179 r g_gbt_bank[2].gbtbank/RX_Word_rx40[72]_i_1__6/O net (fo=1, routed) 0.016 1.195 SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[83]_0[40] SLICE_X26Y201 FDCE r SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[72]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.084 1.236 SFP_GEN[30].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X26Y201 FDCE r SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[72]/C clock pessimism -0.144 1.092 SLICE_X26Y201 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.148 SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[72] ------------------------------------------------------------------- required time -1.148 arrival time 1.195 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].rx_data_ngccm_reg[30][77]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.193ns (logic 0.048ns (24.870%) route 0.145ns (75.130%)) Logic Levels: 0 Clock Path Skew: 0.090ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.237ns Source Clock Delay (SCD): 1.003ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.887ns (routing 0.368ns, distribution 0.519ns) Clock Net Delay (Destination): 1.085ns (routing 0.432ns, distribution 0.653ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.887 1.003 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X24Y202 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X24Y202 FDRE (Prop_GFF2_SLICEL_C_Q) 0.048 1.051 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/Q net (fo=1, routed) 0.145 1.196 rx_data[30][77] SLICE_X25Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][77]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.085 1.237 g_gbt_bank[2].gbtbank_n_84 SLICE_X25Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][77]/C clock pessimism -0.144 1.093 SLICE_X25Y201 FDCE (Hold_CFF2_SLICEM_C_D) 0.056 1.149 SFP_GEN[30].rx_data_ngccm_reg[30][77] ------------------------------------------------------------------- required time -1.149 arrival time 1.196 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: SFP_GEN[30].ngccm_status_reg_reg[30][24]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].ngccm_status_reg_reg[30][24]/D (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.109ns (logic 0.064ns (58.716%) route 0.045ns (41.284%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.374ns Source Clock Delay (SCD): 1.139ns Clock Pessimism Removal (CPR): 0.230ns Clock Net Delay (Source): 1.023ns (routing 0.368ns, distribution 0.655ns) Clock Net Delay (Destination): 1.222ns (routing 0.432ns, distribution 0.790ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.023 1.139 g_gbt_bank[2].gbtbank_n_84 SLICE_X70Y219 FDPE r SFP_GEN[30].ngccm_status_reg_reg[30][24]/C ------------------------------------------------------------------- ------------------- SLICE_X70Y219 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.188 r SFP_GEN[30].ngccm_status_reg_reg[30][24]/Q net (fo=2, routed) 0.033 1.221 SFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg_reg[30][24]_0[8] SLICE_X70Y219 LUT2 (Prop_A6LUT_SLICEM_I0_O) 0.015 1.236 r SFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg[30][24]_i_2/O net (fo=1, routed) 0.012 1.248 SFP_GEN[30].ngCCM_gbt_n_392 SLICE_X70Y219 FDPE r SFP_GEN[30].ngccm_status_reg_reg[30][24]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.222 1.374 g_gbt_bank[2].gbtbank_n_84 SLICE_X70Y219 FDPE r SFP_GEN[30].ngccm_status_reg_reg[30][24]/C clock pessimism -0.230 1.144 SLICE_X70Y219 FDPE (Hold_AFF_SLICEM_C_D) 0.056 1.200 SFP_GEN[30].ngccm_status_reg_reg[30][24] ------------------------------------------------------------------- required time -1.200 arrival time 1.248 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].rx_data_ngccm_reg[30][74]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.159ns (logic 0.048ns (30.189%) route 0.111ns (69.811%)) Logic Levels: 0 Clock Path Skew: 0.055ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.234ns Source Clock Delay (SCD): 1.003ns Clock Pessimism Removal (CPR): 0.176ns Clock Net Delay (Source): 0.887ns (routing 0.368ns, distribution 0.519ns) Clock Net Delay (Destination): 1.082ns (routing 0.432ns, distribution 0.650ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.887 1.003 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X24Y202 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X24Y202 FDRE (Prop_HFF_SLICEL_C_Q) 0.048 1.051 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/Q net (fo=1, routed) 0.111 1.162 rx_data[30][74] SLICE_X24Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][74]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.082 1.234 g_gbt_bank[2].gbtbank_n_84 SLICE_X24Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][74]/C clock pessimism -0.176 1.058 SLICE_X24Y201 FDCE (Hold_FFF_SLICEL_C_D) 0.056 1.114 SFP_GEN[30].rx_data_ngccm_reg[30][74] ------------------------------------------------------------------- required time -1.114 arrival time 1.162 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.172ns (logic 0.079ns (45.930%) route 0.093ns (54.070%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.218ns Source Clock Delay (SCD): 1.007ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.891ns (routing 0.368ns, distribution 0.523ns) Clock Net Delay (Destination): 1.066ns (routing 0.432ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.891 1.007 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X24Y204 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X24Y204 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.056 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.077 1.133 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/O84[0] SLICE_X25Y204 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.030 1.163 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__29/O net (fo=1, routed) 0.016 1.179 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[0] SLICE_X25Y204 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.066 1.218 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X25Y204 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C clock pessimism -0.144 1.074 SLICE_X25Y204 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.130 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19] ------------------------------------------------------------------- required time -1.130 arrival time 1.179 ------------------------------------------------------------------- slack 0.049 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_32 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y88 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y218 g_clock_rate_din[30].ngccm_status_cnt_reg[30][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y218 g_clock_rate_din[30].ngccm_status_cnt_reg[30][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y218 g_clock_rate_din[30].ngccm_status_cnt_reg[30][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y219 g_clock_rate_din[30].ngccm_status_cnt_reg[30][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y219 g_clock_rate_din[30].ngccm_status_cnt_reg[30][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y219 g_clock_rate_din[30].ngccm_status_cnt_reg[30][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y218 g_clock_rate_din[30].ngccm_status_cnt_reg[30][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X27Y207 SFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X22Y205 SFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[52]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X27Y207 SFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[6]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X22Y205 SFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[72]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X23Y202 SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[56]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X23Y202 SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[58]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X30Y200 g_clock_rate_din[30].rx_frameclk_div2_reg[30]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X33Y211 SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[21]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X29Y203 SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[2]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X31Y209 SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[32]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X31Y209 SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[34]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X31Y209 SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[36]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_33 To Clock: gtwiz_userclk_rx_srcclk_out[0]_33 Setup : 0 Failing Endpoints, Worst Slack 2.793ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.040ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.793ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 5.583ns (logic 1.514ns (27.118%) route 4.069ns (72.882%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.149ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.667ns = ( 10.984 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.291ns (routing 0.697ns, distribution 1.594ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.830 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.142 6.972 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X69Y232 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.166 7.138 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/O net (fo=5, routed) 0.274 7.412 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X70Y233 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.092 7.504 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__30/O net (fo=1, routed) 0.082 7.586 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__30_n_0 SLICE_X70Y233 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.152 7.738 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__30/O net (fo=2, routed) 0.571 8.309 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__30_n_0 SLICE_X68Y232 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.291 10.984 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X68Y232 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.208 11.193 clock uncertainty -0.035 11.157 SLICE_X68Y232 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 11.102 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.102 arrival time -8.309 ------------------------------------------------------------------- slack 2.793 Slack (MET) : 2.808ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 5.571ns (logic 1.514ns (27.176%) route 4.057ns (72.824%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.151ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.669ns = ( 10.986 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.293ns (routing 0.697ns, distribution 1.596ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.830 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.142 6.972 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X69Y232 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.166 7.138 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/O net (fo=5, routed) 0.274 7.412 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X70Y233 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.092 7.504 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__30/O net (fo=1, routed) 0.082 7.586 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__30_n_0 SLICE_X70Y233 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.152 7.738 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__30/O net (fo=2, routed) 0.559 8.297 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__30_n_0 SLICE_X68Y232 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.293 10.986 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X68Y232 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.208 11.195 clock uncertainty -0.035 11.159 SLICE_X68Y232 FDCE (Setup_DFF_SLICEL_C_CE) -0.054 11.105 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.105 arrival time -8.297 ------------------------------------------------------------------- slack 2.808 Slack (MET) : 3.291ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 5.076ns (logic 1.360ns (26.793%) route 3.716ns (73.207%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.661ns = ( 10.978 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.285ns (routing 0.697ns, distribution 1.588ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.830 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.142 6.972 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X69Y232 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.166 7.138 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/O net (fo=5, routed) 0.273 7.411 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X70Y233 LUT5 (Prop_C6LUT_SLICEM_I3_O) 0.090 7.501 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/O net (fo=7, routed) 0.301 7.802 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X69Y233 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.285 10.978 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y233 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.208 11.187 clock uncertainty -0.035 11.151 SLICE_X69Y233 FDRE (Setup_EFF2_SLICEL_C_CE) -0.058 11.093 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 11.093 arrival time -7.802 ------------------------------------------------------------------- slack 3.291 Slack (MET) : 3.291ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 5.076ns (logic 1.360ns (26.793%) route 3.716ns (73.207%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.661ns = ( 10.978 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.285ns (routing 0.697ns, distribution 1.588ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.830 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.142 6.972 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X69Y232 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.166 7.138 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/O net (fo=5, routed) 0.273 7.411 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X70Y233 LUT5 (Prop_C6LUT_SLICEM_I3_O) 0.090 7.501 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/O net (fo=7, routed) 0.301 7.802 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X69Y233 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.285 10.978 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y233 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.208 11.187 clock uncertainty -0.035 11.151 SLICE_X69Y233 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 11.093 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.093 arrival time -7.802 ------------------------------------------------------------------- slack 3.291 Slack (MET) : 3.291ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 5.076ns (logic 1.360ns (26.793%) route 3.716ns (73.207%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.661ns = ( 10.978 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.285ns (routing 0.697ns, distribution 1.588ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.830 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.142 6.972 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X69Y232 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.166 7.138 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/O net (fo=5, routed) 0.273 7.411 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X70Y233 LUT5 (Prop_C6LUT_SLICEM_I3_O) 0.090 7.501 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/O net (fo=7, routed) 0.301 7.802 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X69Y233 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.285 10.978 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y233 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.208 11.187 clock uncertainty -0.035 11.151 SLICE_X69Y233 FDRE (Setup_GFF2_SLICEL_C_CE) -0.058 11.093 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.093 arrival time -7.802 ------------------------------------------------------------------- slack 3.291 Slack (MET) : 3.297ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 5.073ns (logic 1.360ns (26.809%) route 3.713ns (73.191%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.661ns = ( 10.978 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.285ns (routing 0.697ns, distribution 1.588ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.830 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.142 6.972 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X69Y232 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.166 7.138 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/O net (fo=5, routed) 0.273 7.411 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X70Y233 LUT5 (Prop_C6LUT_SLICEM_I3_O) 0.090 7.501 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/O net (fo=7, routed) 0.298 7.799 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X69Y233 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.285 10.978 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y233 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.208 11.187 clock uncertainty -0.035 11.151 SLICE_X69Y233 FDRE (Setup_EFF_SLICEL_C_CE) -0.055 11.096 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 11.096 arrival time -7.799 ------------------------------------------------------------------- slack 3.297 Slack (MET) : 3.297ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 5.073ns (logic 1.360ns (26.809%) route 3.713ns (73.191%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.661ns = ( 10.978 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.285ns (routing 0.697ns, distribution 1.588ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.830 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.142 6.972 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X69Y232 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.166 7.138 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/O net (fo=5, routed) 0.273 7.411 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X70Y233 LUT5 (Prop_C6LUT_SLICEM_I3_O) 0.090 7.501 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/O net (fo=7, routed) 0.298 7.799 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X69Y233 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.285 10.978 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y233 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.208 11.187 clock uncertainty -0.035 11.151 SLICE_X69Y233 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 11.096 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 11.096 arrival time -7.799 ------------------------------------------------------------------- slack 3.297 Slack (MET) : 3.297ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 5.073ns (logic 1.360ns (26.809%) route 3.713ns (73.191%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.661ns = ( 10.978 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.285ns (routing 0.697ns, distribution 1.588ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.830 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.142 6.972 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X69Y232 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.166 7.138 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/O net (fo=5, routed) 0.273 7.411 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X70Y233 LUT5 (Prop_C6LUT_SLICEM_I3_O) 0.090 7.501 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/O net (fo=7, routed) 0.298 7.799 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X69Y233 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.285 10.978 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y233 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.208 11.187 clock uncertainty -0.035 11.151 SLICE_X69Y233 FDRE (Setup_GFF_SLICEL_C_CE) -0.055 11.096 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.096 arrival time -7.799 ------------------------------------------------------------------- slack 3.297 Slack (MET) : 3.320ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 5.053ns (logic 1.360ns (26.915%) route 3.693ns (73.085%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.663ns = ( 10.980 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.287ns (routing 0.697ns, distribution 1.590ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.830 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.142 6.972 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X69Y232 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.166 7.138 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/O net (fo=5, routed) 0.273 7.411 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X70Y233 LUT5 (Prop_C6LUT_SLICEM_I3_O) 0.090 7.501 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/O net (fo=7, routed) 0.278 7.779 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X69Y233 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.287 10.980 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y233 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.208 11.189 clock uncertainty -0.035 11.153 SLICE_X69Y233 FDRE (Setup_BFF_SLICEL_C_CE) -0.054 11.099 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 11.099 arrival time -7.779 ------------------------------------------------------------------- slack 3.320 Slack (MET) : 3.322ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 5.065ns (logic 1.320ns (26.061%) route 3.745ns (73.939%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.160ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.678ns = ( 10.995 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.302ns (routing 0.697ns, distribution 1.605ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.830 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.142 6.972 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X69Y232 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.166 7.138 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/O net (fo=5, routed) 0.090 7.228 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X69Y232 LUT6 (Prop_E6LUT_SLICEL_I5_O) 0.050 7.278 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__31/O net (fo=3, routed) 0.513 7.791 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/consecFalseHeaders0 SLICE_X68Y234 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.302 10.995 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X68Y234 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.208 11.204 clock uncertainty -0.035 11.168 SLICE_X68Y234 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 11.113 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 11.113 arrival time -7.791 ------------------------------------------------------------------- slack 3.322 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[31].rx_data_ngccm_reg[31][74]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.161ns (logic 0.048ns (29.814%) route 0.113ns (70.186%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.137ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.021ns (routing 0.369ns, distribution 0.652ns) Clock Net Delay (Destination): 1.207ns (routing 0.431ns, distribution 0.776ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.021 1.137 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X67Y216 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y216 FDRE (Prop_HFF_SLICEM_C_Q) 0.048 1.185 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/Q net (fo=1, routed) 0.113 1.298 rx_data[31][74] SLICE_X66Y216 FDCE r SFP_GEN[31].rx_data_ngccm_reg[31][74]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.207 1.359 g_gbt_bank[2].gbtbank_n_94 SLICE_X66Y216 FDCE r SFP_GEN[31].rx_data_ngccm_reg[31][74]/C clock pessimism -0.157 1.202 SLICE_X66Y216 FDCE (Hold_FFF_SLICEL_C_D) 0.056 1.258 SFP_GEN[31].rx_data_ngccm_reg[31][74] ------------------------------------------------------------------- required time -1.258 arrival time 1.298 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.386ns Source Clock Delay (SCD): 1.143ns Clock Pessimism Removal (CPR): 0.199ns Clock Net Delay (Source): 1.027ns (routing 0.369ns, distribution 0.658ns) Clock Net Delay (Destination): 1.234ns (routing 0.431ns, distribution 0.803ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.027 1.143 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X66Y225 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y225 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.192 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.034 1.226 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_35_in SLICE_X66Y225 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.045 1.271 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__30/O net (fo=1, routed) 0.016 1.287 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[16] SLICE_X66Y225 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.234 1.386 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X66Y225 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.199 1.187 SLICE_X66Y225 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.243 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.243 arrival time 1.287 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.382ns Source Clock Delay (SCD): 1.140ns Clock Pessimism Removal (CPR): 0.198ns Clock Net Delay (Source): 1.024ns (routing 0.369ns, distribution 0.655ns) Clock Net Delay (Destination): 1.230ns (routing 0.431ns, distribution 0.799ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.024 1.140 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X66Y220 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y220 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.189 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Q net (fo=2, routed) 0.034 1.223 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_27_in SLICE_X66Y220 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.045 1.268 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__30/O net (fo=1, routed) 0.016 1.284 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[12] SLICE_X66Y220 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.230 1.382 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X66Y220 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C clock pessimism -0.198 1.184 SLICE_X66Y220 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.240 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12] ------------------------------------------------------------------- required time -1.240 arrival time 1.284 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.047ns (arrival time - required time) Source: SFP_GEN[31].rx_data_ngccm_reg[31][7]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[6]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.176ns (logic 0.088ns (50.000%) route 0.088ns (50.000%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.370ns Source Clock Delay (SCD): 1.140ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.024ns (routing 0.369ns, distribution 0.655ns) Clock Net Delay (Destination): 1.218ns (routing 0.431ns, distribution 0.787ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.024 1.140 g_gbt_bank[2].gbtbank_n_94 SLICE_X69Y225 FDCE r SFP_GEN[31].rx_data_ngccm_reg[31][7]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y225 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 1.188 r SFP_GEN[31].rx_data_ngccm_reg[31][7]/Q net (fo=1, routed) 0.076 1.264 SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[83]_0[7] SLICE_X70Y225 LUT3 (Prop_D5LUT_SLICEM_I0_O) 0.040 1.304 r SFP_GEN[31].ngCCM_gbt/RX_Word_rx40[6]_i_1/O net (fo=1, routed) 0.012 1.316 SFP_GEN[31].ngCCM_gbt/RX_Word_rx40[6]_i_1_n_0 SLICE_X70Y225 FDCE r SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[6]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.218 1.370 SFP_GEN[31].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X70Y225 FDCE r SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[6]/C clock pessimism -0.157 1.213 SLICE_X70Y225 FDCE (Hold_DFF2_SLICEM_C_D) 0.056 1.269 SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[6] ------------------------------------------------------------------- required time -1.269 arrival time 1.316 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.109ns (logic 0.064ns (58.716%) route 0.045ns (41.284%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.377ns Source Clock Delay (SCD): 1.142ns Clock Pessimism Removal (CPR): 0.230ns Clock Net Delay (Source): 1.026ns (routing 0.369ns, distribution 0.657ns) Clock Net Delay (Destination): 1.225ns (routing 0.431ns, distribution 0.794ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.026 1.142 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/CLK SLICE_X70Y223 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y223 FDRE (Prop_AFF_SLICEM_C_Q) 0.049 1.191 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/Q net (fo=4, routed) 0.033 1.224 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/error_detected_msb SLICE_X70Y223 LUT6 (Prop_A6LUT_SLICEM_I5_O) 0.015 1.239 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__61/O net (fo=1, routed) 0.012 1.251 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg_1 SLICE_X70Y223 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.225 1.377 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/CLK SLICE_X70Y223 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C clock pessimism -0.230 1.147 SLICE_X70Y223 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.203 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg ------------------------------------------------------------------- required time -1.203 arrival time 1.251 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.104ns (69.799%) route 0.045ns (30.201%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.386ns Source Clock Delay (SCD): 1.143ns Clock Pessimism Removal (CPR): 0.199ns Clock Net Delay (Source): 1.027ns (routing 0.369ns, distribution 0.658ns) Clock Net Delay (Destination): 1.234ns (routing 0.431ns, distribution 0.803ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.027 1.143 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X66Y225 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y225 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.192 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.034 1.226 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_35_in SLICE_X66Y225 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.055 1.281 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__30/O net (fo=1, routed) 0.011 1.292 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[18] SLICE_X66Y225 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.234 1.386 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X66Y225 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C clock pessimism -0.199 1.187 SLICE_X66Y225 FDRE (Hold_DFF2_SLICEL_C_D) 0.056 1.243 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18] ------------------------------------------------------------------- required time -1.243 arrival time 1.292 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.104ns (69.799%) route 0.045ns (30.201%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.382ns Source Clock Delay (SCD): 1.140ns Clock Pessimism Removal (CPR): 0.198ns Clock Net Delay (Source): 1.024ns (routing 0.369ns, distribution 0.655ns) Clock Net Delay (Destination): 1.230ns (routing 0.431ns, distribution 0.799ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.024 1.140 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X66Y220 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y220 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.189 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Q net (fo=2, routed) 0.034 1.223 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_27_in SLICE_X66Y220 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.055 1.278 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__30/O net (fo=1, routed) 0.011 1.289 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[14] SLICE_X66Y220 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.230 1.382 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X66Y220 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C clock pessimism -0.198 1.184 SLICE_X66Y220 FDRE (Hold_DFF2_SLICEL_C_D) 0.056 1.240 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14] ------------------------------------------------------------------- required time -1.240 arrival time 1.289 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[31].rx_data_ngccm_reg[31][47]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.048ns (33.103%) route 0.097ns (66.897%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.376ns Source Clock Delay (SCD): 1.145ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 1.029ns (routing 0.369ns, distribution 0.660ns) Clock Net Delay (Destination): 1.224ns (routing 0.431ns, distribution 0.793ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.029 1.145 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X68Y220 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X68Y220 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 1.193 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/Q net (fo=1, routed) 0.097 1.290 rx_data[31][47] SLICE_X68Y222 FDCE r SFP_GEN[31].rx_data_ngccm_reg[31][47]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.224 1.376 g_gbt_bank[2].gbtbank_n_94 SLICE_X68Y222 FDCE r SFP_GEN[31].rx_data_ngccm_reg[31][47]/C clock pessimism -0.190 1.186 SLICE_X68Y222 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.241 SFP_GEN[31].rx_data_ngccm_reg[31][47] ------------------------------------------------------------------- required time -1.241 arrival time 1.290 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[31].rx_data_ngccm_reg[31][63]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.049ns (34.028%) route 0.095ns (65.972%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.369ns Source Clock Delay (SCD): 1.139ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 1.023ns (routing 0.369ns, distribution 0.654ns) Clock Net Delay (Destination): 1.217ns (routing 0.431ns, distribution 0.786ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.023 1.139 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X66Y217 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y217 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.188 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/Q net (fo=1, routed) 0.095 1.283 rx_data[31][63] SLICE_X66Y218 FDCE r SFP_GEN[31].rx_data_ngccm_reg[31][63]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.217 1.369 g_gbt_bank[2].gbtbank_n_94 SLICE_X66Y218 FDCE r SFP_GEN[31].rx_data_ngccm_reg[31][63]/C clock pessimism -0.190 1.179 SLICE_X66Y218 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.234 SFP_GEN[31].rx_data_ngccm_reg[31][63] ------------------------------------------------------------------- required time -1.234 arrival time 1.283 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.151ns (logic 0.063ns (41.722%) route 0.088ns (58.278%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.045ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.378ns Source Clock Delay (SCD): 1.142ns Clock Pessimism Removal (CPR): 0.191ns Clock Net Delay (Source): 1.026ns (routing 0.369ns, distribution 0.657ns) Clock Net Delay (Destination): 1.226ns (routing 0.431ns, distribution 0.795ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.026 1.142 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4 SLICE_X69Y235 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y235 FDCE (Prop_GFF_SLICEL_C_Q) 0.048 1.190 r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/Q net (fo=9, routed) 0.076 1.266 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gbtBank_Clk_gen[7].cnt_reg[7][7]_0[4] SLICE_X69Y234 LUT6 (Prop_A6LUT_SLICEL_I4_O) 0.015 1.281 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gbtBank_Clk_gen[7].cnt[7][5]_i_1__1/O net (fo=1, routed) 0.012 1.293 g_gbt_bank[2].gbtbank/i_gbt_bank_n_326 SLICE_X69Y234 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.226 1.378 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4 SLICE_X69Y234 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/C clock pessimism -0.191 1.187 SLICE_X69Y234 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.243 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5] ------------------------------------------------------------------- required time -1.243 arrival time 1.293 ------------------------------------------------------------------- slack 0.050 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_33 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y89 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y223 g_clock_rate_din[31].ngccm_status_cnt_reg[31][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y223 g_clock_rate_din[31].ngccm_status_cnt_reg[31][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y223 g_clock_rate_din[31].ngccm_status_cnt_reg[31][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y223 g_clock_rate_din[31].ngccm_status_cnt_reg[31][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y221 g_clock_rate_din[31].ngccm_status_cnt_reg[31][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y223 g_clock_rate_din[31].ngccm_status_cnt_reg[31][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y223 g_clock_rate_din[31].ngccm_status_cnt_reg[31][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y228 SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[4]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y228 SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[52]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y228 SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[54]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y228 SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[56]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y228 SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[60]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y228 SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[70]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y181 g_clock_rate_din[31].rx_wordclk_div2_reg[31]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y234 SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y234 SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y234 SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[46]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y234 SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[48]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y234 SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[50]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_34 To Clock: gtwiz_userclk_rx_srcclk_out[0]_34 Setup : 0 Failing Endpoints, Worst Slack 3.873ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.036ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.873ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[32].rx_data_ngccm_reg[32][53]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 4.046ns (logic 0.305ns (7.538%) route 3.741ns (92.462%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.308ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.362ns = ( 10.679 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.201ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.446ns (routing 0.762ns, distribution 1.684ns) Clock Net Delay (Destination): 1.986ns (routing 0.684ns, distribution 1.302ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.446 2.871 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X2Y248 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X2Y248 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.884 4.894 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X36Y249 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.166 5.060 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/SFP_GEN[32].rx_data_ngccm[32][83]_i_1/O net (fo=76, routed) 1.857 6.917 rx_data_ngccm[32] SLICE_X23Y248 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][53]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.986 10.679 g_gbt_bank[2].gbtbank_n_104 SLICE_X23Y248 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][53]/C clock pessimism 0.201 10.881 clock uncertainty -0.035 10.845 SLICE_X23Y248 FDCE (Setup_EFF_SLICEM_C_CE) -0.055 10.790 SFP_GEN[32].rx_data_ngccm_reg[32][53] ------------------------------------------------------------------- required time 10.790 arrival time -6.917 ------------------------------------------------------------------- slack 3.873 Slack (MET) : 3.877ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[32].rx_data_ngccm_reg[32][80]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 4.043ns (logic 0.305ns (7.544%) route 3.738ns (92.456%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.307ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.363ns = ( 10.680 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.201ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.446ns (routing 0.762ns, distribution 1.684ns) Clock Net Delay (Destination): 1.987ns (routing 0.684ns, distribution 1.303ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.446 2.871 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X2Y248 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X2Y248 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.884 4.894 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X36Y249 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.166 5.060 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/SFP_GEN[32].rx_data_ngccm[32][83]_i_1/O net (fo=76, routed) 1.854 6.914 rx_data_ngccm[32] SLICE_X24Y248 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][80]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.987 10.680 g_gbt_bank[2].gbtbank_n_104 SLICE_X24Y248 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][80]/C clock pessimism 0.201 10.882 clock uncertainty -0.035 10.846 SLICE_X24Y248 FDCE (Setup_EFF_SLICEL_C_CE) -0.055 10.791 SFP_GEN[32].rx_data_ngccm_reg[32][80] ------------------------------------------------------------------- required time 10.791 arrival time -6.914 ------------------------------------------------------------------- slack 3.877 Slack (MET) : 4.060ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 4.018ns (logic 0.363ns (9.034%) route 3.655ns (90.966%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.149ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.340ns = ( 10.657 - 8.317 ) Source Clock Delay (SCD): 2.692ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.267ns (routing 0.762ns, distribution 1.505ns) Clock Net Delay (Destination): 1.964ns (routing 0.684ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.267 2.692 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 SLICE_X35Y252 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y252 FDCE (Prop_AFF2_SLICEM_C_Q) 0.139 2.831 r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/Q net (fo=137, routed) 2.144 4.975 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X22Y247 LUT2 (Prop_C6LUT_SLICEM_I1_O) 0.224 5.199 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__31/O net (fo=76, routed) 1.511 6.710 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X34Y242 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.964 10.657 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X34Y242 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C clock pessimism 0.203 10.861 clock uncertainty -0.035 10.825 SLICE_X34Y242 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 10.770 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14] ------------------------------------------------------------------- required time 10.770 arrival time -6.710 ------------------------------------------------------------------- slack 4.060 Slack (MET) : 4.064ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 4.015ns (logic 0.363ns (9.041%) route 3.652ns (90.959%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.149ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.340ns = ( 10.657 - 8.317 ) Source Clock Delay (SCD): 2.692ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.267ns (routing 0.762ns, distribution 1.505ns) Clock Net Delay (Destination): 1.964ns (routing 0.684ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.267 2.692 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 SLICE_X35Y252 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y252 FDCE (Prop_AFF2_SLICEM_C_Q) 0.139 2.831 r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/Q net (fo=137, routed) 2.144 4.975 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X22Y247 LUT2 (Prop_C6LUT_SLICEM_I1_O) 0.224 5.199 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__31/O net (fo=76, routed) 1.508 6.707 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X34Y242 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.964 10.657 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X34Y242 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C clock pessimism 0.203 10.861 clock uncertainty -0.035 10.825 SLICE_X34Y242 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 10.771 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12] ------------------------------------------------------------------- required time 10.771 arrival time -6.707 ------------------------------------------------------------------- slack 4.064 Slack (MET) : 4.148ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 3.930ns (logic 0.363ns (9.237%) route 3.567ns (90.763%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.146ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.343ns = ( 10.660 - 8.317 ) Source Clock Delay (SCD): 2.692ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.267ns (routing 0.762ns, distribution 1.505ns) Clock Net Delay (Destination): 1.967ns (routing 0.684ns, distribution 1.283ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.267 2.692 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 SLICE_X35Y252 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y252 FDCE (Prop_AFF2_SLICEM_C_Q) 0.139 2.831 r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/Q net (fo=137, routed) 2.144 4.975 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X22Y247 LUT2 (Prop_C6LUT_SLICEM_I1_O) 0.224 5.199 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__31/O net (fo=76, routed) 1.423 6.622 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X33Y241 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.967 10.660 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X33Y241 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C clock pessimism 0.203 10.864 clock uncertainty -0.035 10.828 SLICE_X33Y241 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 10.770 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18] ------------------------------------------------------------------- required time 10.770 arrival time -6.622 ------------------------------------------------------------------- slack 4.148 Slack (MET) : 4.155ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 3.926ns (logic 0.363ns (9.246%) route 3.563ns (90.754%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.146ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.343ns = ( 10.660 - 8.317 ) Source Clock Delay (SCD): 2.692ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.267ns (routing 0.762ns, distribution 1.505ns) Clock Net Delay (Destination): 1.967ns (routing 0.684ns, distribution 1.283ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.267 2.692 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 SLICE_X35Y252 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y252 FDCE (Prop_AFF2_SLICEM_C_Q) 0.139 2.831 r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/Q net (fo=137, routed) 2.144 4.975 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X22Y247 LUT2 (Prop_C6LUT_SLICEM_I1_O) 0.224 5.199 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__31/O net (fo=76, routed) 1.419 6.618 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X33Y241 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.967 10.660 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X33Y241 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism 0.203 10.864 clock uncertainty -0.035 10.828 SLICE_X33Y241 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 10.773 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time 10.773 arrival time -6.618 ------------------------------------------------------------------- slack 4.155 Slack (MET) : 4.230ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[32].rx_data_ngccm_reg[32][65]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 3.793ns (logic 0.305ns (8.041%) route 3.488ns (91.959%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.201ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.456ns = ( 10.773 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.446ns (routing 0.762ns, distribution 1.684ns) Clock Net Delay (Destination): 2.080ns (routing 0.684ns, distribution 1.396ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.446 2.871 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X2Y248 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X2Y248 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.884 4.894 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X36Y249 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.166 5.060 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/SFP_GEN[32].rx_data_ngccm[32][83]_i_1/O net (fo=76, routed) 1.604 6.664 rx_data_ngccm[32] SLICE_X21Y243 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][65]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.080 10.773 g_gbt_bank[2].gbtbank_n_104 SLICE_X21Y243 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][65]/C clock pessimism 0.214 10.987 clock uncertainty -0.035 10.952 SLICE_X21Y243 FDCE (Setup_EFF2_SLICEL_C_CE) -0.058 10.894 SFP_GEN[32].rx_data_ngccm_reg[32][65] ------------------------------------------------------------------- required time 10.894 arrival time -6.664 ------------------------------------------------------------------- slack 4.230 Slack (MET) : 4.230ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[32].rx_data_ngccm_reg[32][67]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 3.793ns (logic 0.305ns (8.041%) route 3.488ns (91.959%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.201ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.456ns = ( 10.773 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.446ns (routing 0.762ns, distribution 1.684ns) Clock Net Delay (Destination): 2.080ns (routing 0.684ns, distribution 1.396ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.446 2.871 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X2Y248 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X2Y248 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.884 4.894 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X36Y249 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.166 5.060 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/SFP_GEN[32].rx_data_ngccm[32][83]_i_1/O net (fo=76, routed) 1.604 6.664 rx_data_ngccm[32] SLICE_X21Y243 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][67]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.080 10.773 g_gbt_bank[2].gbtbank_n_104 SLICE_X21Y243 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][67]/C clock pessimism 0.214 10.987 clock uncertainty -0.035 10.952 SLICE_X21Y243 FDCE (Setup_FFF2_SLICEL_C_CE) -0.058 10.894 SFP_GEN[32].rx_data_ngccm_reg[32][67] ------------------------------------------------------------------- required time 10.894 arrival time -6.664 ------------------------------------------------------------------- slack 4.230 Slack (MET) : 4.230ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[32].rx_data_ngccm_reg[32][69]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 3.793ns (logic 0.305ns (8.041%) route 3.488ns (91.959%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.201ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.456ns = ( 10.773 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.446ns (routing 0.762ns, distribution 1.684ns) Clock Net Delay (Destination): 2.080ns (routing 0.684ns, distribution 1.396ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.446 2.871 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X2Y248 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X2Y248 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.884 4.894 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X36Y249 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.166 5.060 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/SFP_GEN[32].rx_data_ngccm[32][83]_i_1/O net (fo=76, routed) 1.604 6.664 rx_data_ngccm[32] SLICE_X21Y243 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][69]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.080 10.773 g_gbt_bank[2].gbtbank_n_104 SLICE_X21Y243 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][69]/C clock pessimism 0.214 10.987 clock uncertainty -0.035 10.952 SLICE_X21Y243 FDCE (Setup_GFF2_SLICEL_C_CE) -0.058 10.894 SFP_GEN[32].rx_data_ngccm_reg[32][69] ------------------------------------------------------------------- required time 10.894 arrival time -6.664 ------------------------------------------------------------------- slack 4.230 Slack (MET) : 4.230ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[32].rx_data_ngccm_reg[32][71]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 3.793ns (logic 0.305ns (8.041%) route 3.488ns (91.959%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.201ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.456ns = ( 10.773 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.446ns (routing 0.762ns, distribution 1.684ns) Clock Net Delay (Destination): 2.080ns (routing 0.684ns, distribution 1.396ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.446 2.871 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X2Y248 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X2Y248 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.884 4.894 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X36Y249 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.166 5.060 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/SFP_GEN[32].rx_data_ngccm[32][83]_i_1/O net (fo=76, routed) 1.604 6.664 rx_data_ngccm[32] SLICE_X21Y243 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][71]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.080 10.773 g_gbt_bank[2].gbtbank_n_104 SLICE_X21Y243 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][71]/C clock pessimism 0.214 10.987 clock uncertainty -0.035 10.952 SLICE_X21Y243 FDCE (Setup_HFF2_SLICEL_C_CE) -0.058 10.894 SFP_GEN[32].rx_data_ngccm_reg[32][71] ------------------------------------------------------------------- required time 10.894 arrival time -6.664 ------------------------------------------------------------------- slack 4.230 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.150ns (logic 0.064ns (42.667%) route 0.086ns (57.333%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.246ns Source Clock Delay (SCD): 1.017ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.901ns (routing 0.365ns, distribution 0.536ns) Clock Net Delay (Destination): 1.094ns (routing 0.426ns, distribution 0.668ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.901 1.017 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X23Y246 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X23Y246 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.066 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.070 1.136 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in SLICE_X23Y247 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.015 1.151 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__31/O net (fo=1, routed) 0.016 1.167 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] SLICE_X23Y247 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.094 1.246 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X23Y247 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.171 1.075 SLICE_X23Y247 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.131 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.131 arrival time 1.167 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[32].rx_data_ngccm_reg[32][52]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.169ns (logic 0.049ns (28.994%) route 0.120ns (71.006%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.273ns Source Clock Delay (SCD): 1.053ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 0.937ns (routing 0.365ns, distribution 0.572ns) Clock Net Delay (Destination): 1.121ns (routing 0.426ns, distribution 0.695ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.937 1.053 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X21Y247 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X21Y247 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.102 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/Q net (fo=1, routed) 0.120 1.222 rx_data[32][52] SLICE_X22Y247 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][52]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.121 1.273 g_gbt_bank[2].gbtbank_n_104 SLICE_X22Y247 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][52]/C clock pessimism -0.146 1.127 SLICE_X22Y247 FDCE (Hold_AFF_SLICEM_C_D) 0.056 1.183 SFP_GEN[32].rx_data_ngccm_reg[32][52] ------------------------------------------------------------------- required time -1.183 arrival time 1.222 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[32].rx_data_ngccm_reg[32][56]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.048ns (27.746%) route 0.125ns (72.254%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.273ns Source Clock Delay (SCD): 1.053ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 0.937ns (routing 0.365ns, distribution 0.572ns) Clock Net Delay (Destination): 1.121ns (routing 0.426ns, distribution 0.695ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.937 1.053 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X21Y247 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X21Y247 FDRE (Prop_CFF2_SLICEL_C_Q) 0.048 1.101 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/Q net (fo=1, routed) 0.125 1.226 rx_data[32][56] SLICE_X22Y247 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][56]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.121 1.273 g_gbt_bank[2].gbtbank_n_104 SLICE_X22Y247 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][56]/C clock pessimism -0.146 1.127 SLICE_X22Y247 FDCE (Hold_BFF_SLICEM_C_D) 0.056 1.183 SFP_GEN[32].rx_data_ngccm_reg[32][56] ------------------------------------------------------------------- required time -1.183 arrival time 1.226 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/psAddress_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/headerFlag_s_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.180ns (logic 0.087ns (48.333%) route 0.093ns (51.667%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.273ns Source Clock Delay (SCD): 1.046ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 0.930ns (routing 0.365ns, distribution 0.565ns) Clock Net Delay (Destination): 1.121ns (routing 0.426ns, distribution 0.695ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.930 1.046 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X22Y251 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/psAddress_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y251 FDCE (Prop_DFF_SLICEM_C_Q) 0.049 1.095 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/psAddress_reg[1]/Q net (fo=8, routed) 0.082 1.177 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/psAddress[1] SLICE_X21Y251 LUT3 (Prop_C5LUT_SLICEL_I1_O) 0.038 1.215 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/headerFlag_s_i_1__32/O net (fo=1, routed) 0.011 1.226 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/headerFlag_s_i_1__32_n_0 SLICE_X21Y251 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/headerFlag_s_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.121 1.273 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X21Y251 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/headerFlag_s_reg/C clock pessimism -0.146 1.127 SLICE_X21Y251 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 1.183 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/headerFlag_s_reg ------------------------------------------------------------------- required time -1.183 arrival time 1.226 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[32].rx_data_ngccm_reg[32][46]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.048ns (33.333%) route 0.096ns (66.667%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.245ns Source Clock Delay (SCD): 1.020ns Clock Pessimism Removal (CPR): 0.185ns Clock Net Delay (Source): 0.904ns (routing 0.365ns, distribution 0.539ns) Clock Net Delay (Destination): 1.093ns (routing 0.426ns, distribution 0.667ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.904 1.020 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X23Y247 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X23Y247 FDRE (Prop_HFF_SLICEM_C_Q) 0.048 1.068 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/Q net (fo=1, routed) 0.096 1.164 rx_data[32][46] SLICE_X24Y247 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][46]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.093 1.245 g_gbt_bank[2].gbtbank_n_104 SLICE_X24Y247 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][46]/C clock pessimism -0.185 1.060 SLICE_X24Y247 FDCE (Hold_AFF2_SLICEL_C_D) 0.056 1.116 SFP_GEN[32].rx_data_ngccm_reg[32][46] ------------------------------------------------------------------- required time -1.116 arrival time 1.164 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[39]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.176ns (logic 0.063ns (35.795%) route 0.113ns (64.205%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.226ns Source Clock Delay (SCD): 1.014ns Clock Pessimism Removal (CPR): 0.140ns Clock Net Delay (Source): 0.898ns (routing 0.365ns, distribution 0.533ns) Clock Net Delay (Destination): 1.074ns (routing 0.426ns, distribution 0.648ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.898 1.014 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X29Y244 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y244 FDCE (Prop_CFF_SLICEM_C_Q) 0.048 1.062 f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/Q net (fo=28, routed) 0.097 1.159 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] SLICE_X28Y244 LUT5 (Prop_C6LUT_SLICEM_I0_O) 0.015 1.174 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0[39]_i_2__29/O net (fo=1, routed) 0.016 1.190 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg00[39] SLICE_X28Y244 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[39]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.074 1.226 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X28Y244 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[39]/C clock pessimism -0.140 1.086 SLICE_X28Y244 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.142 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[39] ------------------------------------------------------------------- required time -1.142 arrival time 1.190 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.186ns (logic 0.094ns (50.538%) route 0.092ns (49.462%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.242ns Source Clock Delay (SCD): 1.021ns Clock Pessimism Removal (CPR): 0.140ns Clock Net Delay (Source): 0.905ns (routing 0.365ns, distribution 0.540ns) Clock Net Delay (Destination): 1.090ns (routing 0.426ns, distribution 0.664ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.905 1.021 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X25Y245 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X25Y245 FDCE (Prop_AFF2_SLICEM_C_Q) 0.049 1.070 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Q net (fo=2, routed) 0.080 1.150 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_23_in SLICE_X24Y245 LUT3 (Prop_F6LUT_SLICEL_I0_O) 0.045 1.195 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__31/O net (fo=1, routed) 0.012 1.207 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[12] SLICE_X24Y245 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.090 1.242 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X24Y245 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C clock pessimism -0.140 1.102 SLICE_X24Y245 FDRE (Hold_FFF_SLICEL_C_D) 0.056 1.158 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12] ------------------------------------------------------------------- required time -1.158 arrival time 1.207 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[22]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[32].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[6]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.049ns (33.793%) route 0.096ns (66.207%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.217ns Source Clock Delay (SCD): 1.007ns Clock Pessimism Removal (CPR): 0.170ns Clock Net Delay (Source): 0.891ns (routing 0.365ns, distribution 0.526ns) Clock Net Delay (Destination): 1.065ns (routing 0.426ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.891 1.007 SFP_GEN[32].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X32Y246 FDCE r SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X32Y246 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 1.056 r SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[22]/Q net (fo=5, routed) 0.096 1.152 SFP_GEN[32].ngCCM_gbt/gbt_rx_checker/Q[6] SLICE_X32Y248 FDRE r SFP_GEN[32].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[6]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.065 1.217 SFP_GEN[32].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X32Y248 FDRE r SFP_GEN[32].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[6]/C clock pessimism -0.170 1.047 SLICE_X32Y248 FDRE (Hold_HFF2_SLICEL_C_D) 0.056 1.103 SFP_GEN[32].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[6] ------------------------------------------------------------------- required time -1.103 arrival time 1.152 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.187ns (logic 0.094ns (50.267%) route 0.093ns (49.733%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.242ns Source Clock Delay (SCD): 1.021ns Clock Pessimism Removal (CPR): 0.140ns Clock Net Delay (Source): 0.905ns (routing 0.365ns, distribution 0.540ns) Clock Net Delay (Destination): 1.090ns (routing 0.426ns, distribution 0.664ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.905 1.021 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X25Y245 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X25Y245 FDCE (Prop_AFF2_SLICEM_C_Q) 0.049 1.070 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Q net (fo=2, routed) 0.079 1.149 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_23_in SLICE_X24Y245 LUT3 (Prop_G6LUT_SLICEL_I2_O) 0.045 1.194 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__31/O net (fo=1, routed) 0.014 1.208 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[10] SLICE_X24Y245 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.090 1.242 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X24Y245 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C clock pessimism -0.140 1.102 SLICE_X24Y245 FDRE (Hold_GFF_SLICEL_C_D) 0.056 1.158 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10] ------------------------------------------------------------------- required time -1.158 arrival time 1.208 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.186ns (logic 0.094ns (50.538%) route 0.092ns (49.462%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.237ns Source Clock Delay (SCD): 1.018ns Clock Pessimism Removal (CPR): 0.140ns Clock Net Delay (Source): 0.902ns (routing 0.365ns, distribution 0.537ns) Clock Net Delay (Destination): 1.085ns (routing 0.426ns, distribution 0.659ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.902 1.018 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X24Y247 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X24Y247 FDCE (Prop_GFF_SLICEL_C_Q) 0.048 1.066 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Q net (fo=2, routed) 0.076 1.142 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_3_in SLICE_X25Y247 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.046 1.188 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__31/O net (fo=1, routed) 0.016 1.204 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[0] SLICE_X25Y247 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.085 1.237 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X25Y247 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.140 1.097 SLICE_X25Y247 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.153 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -1.153 arrival time 1.204 ------------------------------------------------------------------- slack 0.051 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_34 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y113 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X57Y260 g_clock_rate_din[32].ngccm_status_cnt_reg[32][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X57Y260 g_clock_rate_din[32].ngccm_status_cnt_reg[32][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X57Y260 g_clock_rate_din[32].ngccm_status_cnt_reg[32][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X57Y263 g_clock_rate_din[32].ngccm_status_cnt_reg[32][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X57Y263 g_clock_rate_din[32].ngccm_status_cnt_reg[32][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X57Y263 g_clock_rate_din[32].ngccm_status_cnt_reg[32][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X59Y254 g_clock_rate_din[32].ngccm_status_cnt_reg[32][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X33Y241 SFP_GEN[32].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X32Y245 SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[20]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X27Y247 SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[40]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X27Y247 SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[42]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X27Y247 SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[44]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X27Y247 SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[46]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X57Y260 g_clock_rate_din[32].ngccm_status_cnt_reg[32][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X57Y260 g_clock_rate_din[32].ngccm_status_cnt_reg[32][1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X57Y260 g_clock_rate_din[32].ngccm_status_cnt_reg[32][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X59Y254 g_clock_rate_din[32].ngccm_status_cnt_reg[32][6]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X59Y254 g_clock_rate_din[32].rx_test_comm_cnt_reg[32]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X33Y241 SFP_GEN[32].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_35 To Clock: gtwiz_userclk_rx_srcclk_out[0]_35 Setup : 0 Failing Endpoints, Worst Slack 2.504ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.033ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.504ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 5.828ns (logic 1.544ns (26.493%) route 4.284ns (73.507%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.617ns = ( 10.934 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.299ns (routing 0.777ns, distribution 1.522ns) Clock Net Delay (Destination): 2.241ns (routing 0.696ns, distribution 1.545ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.299 2.724 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.885 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.582 7.467 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X56Y264 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.090 7.557 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/O net (fo=5, routed) 0.205 7.762 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X56Y266 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.146 7.908 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__32/O net (fo=1, routed) 0.074 7.982 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__32_n_0 SLICE_X56Y266 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 8.129 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__32/O net (fo=2, routed) 0.423 8.552 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__32_n_0 SLICE_X56Y264 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.241 10.934 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y264 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.212 11.146 clock uncertainty -0.035 11.111 SLICE_X56Y264 FDCE (Setup_GFF_SLICEL_C_CE) -0.055 11.056 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.056 arrival time -8.552 ------------------------------------------------------------------- slack 2.504 Slack (MET) : 2.504ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 5.828ns (logic 1.544ns (26.493%) route 4.284ns (73.507%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.617ns = ( 10.934 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.299ns (routing 0.777ns, distribution 1.522ns) Clock Net Delay (Destination): 2.241ns (routing 0.696ns, distribution 1.545ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.299 2.724 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.885 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.582 7.467 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X56Y264 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.090 7.557 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/O net (fo=5, routed) 0.205 7.762 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X56Y266 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.146 7.908 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__32/O net (fo=1, routed) 0.074 7.982 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__32_n_0 SLICE_X56Y266 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 8.129 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__32/O net (fo=2, routed) 0.423 8.552 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__32_n_0 SLICE_X56Y264 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.241 10.934 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y264 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.212 11.146 clock uncertainty -0.035 11.111 SLICE_X56Y264 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 11.056 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.056 arrival time -8.552 ------------------------------------------------------------------- slack 2.504 Slack (MET) : 2.590ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 5.730ns (logic 1.397ns (24.380%) route 4.333ns (75.620%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.608ns = ( 10.925 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.299ns (routing 0.777ns, distribution 1.522ns) Clock Net Delay (Destination): 2.232ns (routing 0.696ns, distribution 1.536ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.299 2.724 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.885 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.582 7.467 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X56Y264 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.090 7.557 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/O net (fo=5, routed) 0.173 7.730 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X56Y265 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.146 7.876 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__33/O net (fo=5, routed) 0.578 8.454 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/consecCorrectHeaders0 SLICE_X56Y265 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.232 10.925 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y265 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.212 11.137 clock uncertainty -0.035 11.102 SLICE_X56Y265 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 11.044 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 11.044 arrival time -8.454 ------------------------------------------------------------------- slack 2.590 Slack (MET) : 2.597ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 5.726ns (logic 1.397ns (24.397%) route 4.329ns (75.603%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.608ns = ( 10.925 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.299ns (routing 0.777ns, distribution 1.522ns) Clock Net Delay (Destination): 2.232ns (routing 0.696ns, distribution 1.536ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.299 2.724 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.885 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.582 7.467 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X56Y264 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.090 7.557 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/O net (fo=5, routed) 0.173 7.730 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X56Y265 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.146 7.876 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__33/O net (fo=5, routed) 0.574 8.450 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/consecCorrectHeaders0 SLICE_X56Y265 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.232 10.925 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y265 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C clock pessimism 0.212 11.137 clock uncertainty -0.035 11.102 SLICE_X56Y265 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 11.047 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2] ------------------------------------------------------------------- required time 11.047 arrival time -8.450 ------------------------------------------------------------------- slack 2.597 Slack (MET) : 2.597ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 5.726ns (logic 1.397ns (24.397%) route 4.329ns (75.603%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.608ns = ( 10.925 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.299ns (routing 0.777ns, distribution 1.522ns) Clock Net Delay (Destination): 2.232ns (routing 0.696ns, distribution 1.536ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.299 2.724 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.885 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.582 7.467 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X56Y264 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.090 7.557 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/O net (fo=5, routed) 0.173 7.730 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X56Y265 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.146 7.876 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__33/O net (fo=5, routed) 0.574 8.450 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/consecCorrectHeaders0 SLICE_X56Y265 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.232 10.925 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y265 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism 0.212 11.137 clock uncertainty -0.035 11.102 SLICE_X56Y265 FDRE (Setup_GFF_SLICEL_C_CE) -0.055 11.047 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time 11.047 arrival time -8.450 ------------------------------------------------------------------- slack 2.597 Slack (MET) : 2.634ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 5.685ns (logic 1.302ns (22.902%) route 4.383ns (77.098%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.095ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.607ns = ( 10.924 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.299ns (routing 0.777ns, distribution 1.522ns) Clock Net Delay (Destination): 2.231ns (routing 0.696ns, distribution 1.535ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.299 2.724 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.885 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.582 7.467 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X56Y264 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.090 7.557 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/O net (fo=5, routed) 0.207 7.764 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X56Y266 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.051 7.815 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__33/O net (fo=7, routed) 0.594 8.409 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 SLICE_X56Y266 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.231 10.924 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y266 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.212 11.136 clock uncertainty -0.035 11.101 SLICE_X56Y266 FDRE (Setup_EFF2_SLICEL_C_CE) -0.058 11.043 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 11.043 arrival time -8.409 ------------------------------------------------------------------- slack 2.634 Slack (MET) : 2.634ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 5.685ns (logic 1.302ns (22.902%) route 4.383ns (77.098%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.095ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.607ns = ( 10.924 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.299ns (routing 0.777ns, distribution 1.522ns) Clock Net Delay (Destination): 2.231ns (routing 0.696ns, distribution 1.535ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.299 2.724 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.885 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.582 7.467 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X56Y264 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.090 7.557 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/O net (fo=5, routed) 0.207 7.764 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X56Y266 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.051 7.815 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__33/O net (fo=7, routed) 0.594 8.409 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 SLICE_X56Y266 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.231 10.924 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y266 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.212 11.136 clock uncertainty -0.035 11.101 SLICE_X56Y266 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 11.043 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.043 arrival time -8.409 ------------------------------------------------------------------- slack 2.634 Slack (MET) : 2.641ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 5.681ns (logic 1.302ns (22.919%) route 4.379ns (77.082%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.095ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.607ns = ( 10.924 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.299ns (routing 0.777ns, distribution 1.522ns) Clock Net Delay (Destination): 2.231ns (routing 0.696ns, distribution 1.535ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.299 2.724 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.885 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.582 7.467 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X56Y264 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.090 7.557 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/O net (fo=5, routed) 0.207 7.764 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X56Y266 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.051 7.815 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__33/O net (fo=7, routed) 0.590 8.405 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 SLICE_X56Y266 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.231 10.924 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y266 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.212 11.136 clock uncertainty -0.035 11.101 SLICE_X56Y266 FDRE (Setup_EFF_SLICEL_C_CE) -0.055 11.046 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 11.046 arrival time -8.405 ------------------------------------------------------------------- slack 2.641 Slack (MET) : 2.641ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 5.681ns (logic 1.302ns (22.919%) route 4.379ns (77.082%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.095ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.607ns = ( 10.924 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.299ns (routing 0.777ns, distribution 1.522ns) Clock Net Delay (Destination): 2.231ns (routing 0.696ns, distribution 1.535ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.299 2.724 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.885 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.582 7.467 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X56Y264 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.090 7.557 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/O net (fo=5, routed) 0.207 7.764 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X56Y266 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.051 7.815 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__33/O net (fo=7, routed) 0.590 8.405 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 SLICE_X56Y266 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.231 10.924 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y266 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.212 11.136 clock uncertainty -0.035 11.101 SLICE_X56Y266 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 11.046 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.046 arrival time -8.405 ------------------------------------------------------------------- slack 2.641 Slack (MET) : 2.745ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 5.577ns (logic 1.397ns (25.049%) route 4.180ns (74.951%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.095ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.607ns = ( 10.924 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.299ns (routing 0.777ns, distribution 1.522ns) Clock Net Delay (Destination): 2.231ns (routing 0.696ns, distribution 1.535ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.299 2.724 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.885 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.582 7.467 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X56Y264 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.090 7.557 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/O net (fo=5, routed) 0.173 7.730 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X56Y265 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.146 7.876 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__33/O net (fo=5, routed) 0.425 8.301 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/consecCorrectHeaders0 SLICE_X56Y267 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.231 10.924 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y267 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.212 11.136 clock uncertainty -0.035 11.101 SLICE_X56Y267 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 11.046 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.046 arrival time -8.301 ------------------------------------------------------------------- slack 2.745 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.033ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[33].rx_data_ngccm_reg[33][67]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.049ns (33.562%) route 0.097ns (66.438%)) Logic Levels: 0 Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.366ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.187ns Clock Net Delay (Source): 1.005ns (routing 0.372ns, distribution 0.633ns) Clock Net Delay (Destination): 1.214ns (routing 0.435ns, distribution 0.779ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.005 1.121 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X60Y257 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y257 FDRE (Prop_BFF_SLICEL_C_Q) 0.049 1.170 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/Q net (fo=1, routed) 0.097 1.267 rx_data[33][67] SLICE_X60Y255 FDCE r SFP_GEN[33].rx_data_ngccm_reg[33][67]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.214 1.366 g_gbt_bank[2].gbtbank_n_114 SLICE_X60Y255 FDCE r SFP_GEN[33].rx_data_ngccm_reg[33][67]/C clock pessimism -0.187 1.179 SLICE_X60Y255 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.234 SFP_GEN[33].rx_data_ngccm_reg[33][67] ------------------------------------------------------------------- required time -1.234 arrival time 1.267 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.033ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.169ns (logic 0.079ns (46.746%) route 0.090ns (53.254%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.364ns Source Clock Delay (SCD): 1.128ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.012ns (routing 0.372ns, distribution 0.640ns) Clock Net Delay (Destination): 1.212ns (routing 0.435ns, distribution 0.777ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.012 1.128 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X60Y256 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y256 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.177 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Q net (fo=2, routed) 0.076 1.253 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_7_in SLICE_X61Y256 LUT3 (Prop_G6LUT_SLICEM_I0_O) 0.030 1.283 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__32/O net (fo=1, routed) 0.014 1.297 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[4] SLICE_X61Y256 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.212 1.364 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X61Y256 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.156 1.208 SLICE_X61Y256 FDRE (Hold_GFF_SLICEM_C_D) 0.056 1.264 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.264 arrival time 1.297 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.039ns (arrival time - required time) Source: SFP_GEN[33].rx_data_ngccm_reg[33][40]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[40]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.183ns (logic 0.094ns (51.366%) route 0.089ns (48.634%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.376ns Source Clock Delay (SCD): 1.132ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.016ns (routing 0.372ns, distribution 0.644ns) Clock Net Delay (Destination): 1.224ns (routing 0.435ns, distribution 0.789ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.016 1.132 g_gbt_bank[2].gbtbank_n_114 SLICE_X64Y256 FDCE r SFP_GEN[33].rx_data_ngccm_reg[33][40]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y256 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.181 r SFP_GEN[33].rx_data_ngccm_reg[33][40]/Q net (fo=1, routed) 0.073 1.254 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[83]_0[32] SLICE_X63Y256 LUT3 (Prop_D6LUT_SLICEL_I1_O) 0.045 1.299 r SFP_GEN[33].ngCCM_gbt/RX_Word_rx40[40]_i_1/O net (fo=1, routed) 0.016 1.315 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40[40]_i_1_n_0 SLICE_X63Y256 FDCE r SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[40]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.224 1.376 SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y256 FDCE r SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[40]/C clock pessimism -0.156 1.220 SLICE_X63Y256 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.276 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[40] ------------------------------------------------------------------- required time -1.276 arrival time 1.315 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[33].rx_data_ngccm_reg[33][70]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.049ns (31.613%) route 0.106ns (68.387%)) Logic Levels: 0 Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.366ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.187ns Clock Net Delay (Source): 1.005ns (routing 0.372ns, distribution 0.633ns) Clock Net Delay (Destination): 1.214ns (routing 0.435ns, distribution 0.779ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.005 1.121 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X60Y257 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y257 FDRE (Prop_AFF2_SLICEL_C_Q) 0.049 1.170 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/Q net (fo=1, routed) 0.106 1.276 rx_data[33][70] SLICE_X60Y255 FDCE r SFP_GEN[33].rx_data_ngccm_reg[33][70]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.214 1.366 g_gbt_bank[2].gbtbank_n_114 SLICE_X60Y255 FDCE r SFP_GEN[33].rx_data_ngccm_reg[33][70]/C clock pessimism -0.187 1.179 SLICE_X60Y255 FDCE (Hold_HFF_SLICEL_C_D) 0.056 1.235 SFP_GEN[33].rx_data_ngccm_reg[33][70] ------------------------------------------------------------------- required time -1.235 arrival time 1.276 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.041ns (arrival time - required time) Source: SFP_GEN[33].rx_data_ngccm_reg[33][49]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[48]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.150ns (logic 0.101ns (67.333%) route 0.049ns (32.667%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.370ns Source Clock Delay (SCD): 1.131ns Clock Pessimism Removal (CPR): 0.186ns Clock Net Delay (Source): 1.015ns (routing 0.372ns, distribution 0.643ns) Clock Net Delay (Destination): 1.218ns (routing 0.435ns, distribution 0.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.015 1.131 g_gbt_bank[2].gbtbank_n_114 SLICE_X59Y256 FDCE r SFP_GEN[33].rx_data_ngccm_reg[33][49]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y256 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.180 r SFP_GEN[33].rx_data_ngccm_reg[33][49]/Q net (fo=1, routed) 0.033 1.213 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[83]_0[41] SLICE_X59Y255 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.052 1.265 r SFP_GEN[33].ngCCM_gbt/RX_Word_rx40[48]_i_1/O net (fo=1, routed) 0.016 1.281 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40[48]_i_1_n_0 SLICE_X59Y255 FDCE r SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[48]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.218 1.370 SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y255 FDCE r SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[48]/C clock pessimism -0.186 1.184 SLICE_X59Y255 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.240 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[48] ------------------------------------------------------------------- required time -1.240 arrival time 1.281 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[33].rx_data_ngccm_reg[33][54]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.181ns (logic 0.048ns (26.519%) route 0.133ns (73.481%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.369ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.017ns (routing 0.372ns, distribution 0.645ns) Clock Net Delay (Destination): 1.217ns (routing 0.435ns, distribution 0.782ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.133 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X61Y256 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y256 FDRE (Prop_CFF_SLICEM_C_Q) 0.048 1.181 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/Q net (fo=1, routed) 0.133 1.314 rx_data[33][54] SLICE_X59Y256 FDCE r SFP_GEN[33].rx_data_ngccm_reg[33][54]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.217 1.369 g_gbt_bank[2].gbtbank_n_114 SLICE_X59Y256 FDCE r SFP_GEN[33].rx_data_ngccm_reg[33][54]/C clock pessimism -0.156 1.213 SLICE_X59Y256 FDCE (Hold_BFF_SLICEM_C_D) 0.056 1.269 SFP_GEN[33].rx_data_ngccm_reg[33][54] ------------------------------------------------------------------- required time -1.269 arrival time 1.314 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.094ns (63.946%) route 0.053ns (36.054%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.382ns Source Clock Delay (SCD): 1.139ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.023ns (routing 0.372ns, distribution 0.651ns) Clock Net Delay (Destination): 1.230ns (routing 0.435ns, distribution 0.795ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.023 1.139 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X63Y258 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y258 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.188 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.037 1.225 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/O85[0] SLICE_X63Y258 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.045 1.270 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__32/O net (fo=1, routed) 0.016 1.286 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[17] SLICE_X63Y258 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.230 1.382 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X63Y258 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.201 1.181 SLICE_X63Y258 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.237 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.237 arrival time 1.286 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.094ns (63.946%) route 0.053ns (36.054%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.382ns Source Clock Delay (SCD): 1.139ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.023ns (routing 0.372ns, distribution 0.651ns) Clock Net Delay (Destination): 1.230ns (routing 0.435ns, distribution 0.795ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.023 1.139 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X63Y258 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y258 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.188 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.037 1.225 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/O85[0] SLICE_X63Y258 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.045 1.270 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__32/O net (fo=1, routed) 0.016 1.286 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/I9[0] SLICE_X63Y258 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.230 1.382 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X63Y258 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C clock pessimism -0.201 1.181 SLICE_X63Y258 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.237 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19] ------------------------------------------------------------------- required time -1.237 arrival time 1.286 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[35]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[35]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.160ns (logic 0.048ns (30.000%) route 0.112ns (70.000%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.351ns Source Clock Delay (SCD): 1.139ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.023ns (routing 0.372ns, distribution 0.651ns) Clock Net Delay (Destination): 1.199ns (routing 0.435ns, distribution 0.764ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.023 1.139 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X62Y261 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[35]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y261 FDCE (Prop_CFF_SLICEM_C_Q) 0.048 1.187 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[35]/Q net (fo=1, routed) 0.112 1.299 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0[35] SLICE_X61Y261 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[35]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.199 1.351 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X61Y261 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[35]/C clock pessimism -0.156 1.195 SLICE_X61Y261 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.250 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[35] ------------------------------------------------------------------- required time -1.250 arrival time 1.299 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/READY_o_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/READY_o_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.111ns (logic 0.064ns (57.658%) route 0.047ns (42.342%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.341ns Source Clock Delay (SCD): 1.110ns Clock Pessimism Removal (CPR): 0.226ns Clock Net Delay (Source): 0.994ns (routing 0.372ns, distribution 0.622ns) Clock Net Delay (Destination): 1.189ns (routing 0.435ns, distribution 0.754ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.994 1.110 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y264 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/READY_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X56Y264 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.159 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/READY_o_reg/Q net (fo=2, routed) 0.035 1.194 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/ready_from_bitSlipCtrller_9 SLICE_X56Y264 LUT3 (Prop_A6LUT_SLICEL_I2_O) 0.015 1.209 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/READY_o_i_1__32/O net (fo=1, routed) 0.012 1.221 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/READY_o_i_1__32_n_0 SLICE_X56Y264 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/READY_o_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.189 1.341 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y264 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/READY_o_reg/C clock pessimism -0.226 1.115 SLICE_X56Y264 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.171 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/READY_o_reg ------------------------------------------------------------------- required time -1.171 arrival time 1.221 ------------------------------------------------------------------- slack 0.050 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_35 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y117 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X62Y264 g_clock_rate_din[33].ngccm_status_cnt_reg[33][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X63Y264 g_clock_rate_din[33].ngccm_status_cnt_reg[33][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X62Y264 g_clock_rate_din[33].ngccm_status_cnt_reg[33][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X62Y264 g_clock_rate_din[33].ngccm_status_cnt_reg[33][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X62Y264 g_clock_rate_din[33].ngccm_status_cnt_reg[33][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X63Y263 g_clock_rate_din[33].ngccm_status_cnt_reg[33][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X66Y263 g_clock_rate_din[33].ngccm_status_cnt_reg[33][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X69Y257 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X69Y257 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X69Y257 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X62Y264 g_clock_rate_din[33].ngccm_status_cnt_reg[33][0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X62Y264 g_clock_rate_din[33].ngccm_status_cnt_reg[33][0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X63Y264 g_clock_rate_din[33].ngccm_status_cnt_reg[33][1]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X63Y263 g_clock_rate_din[33].ngccm_status_cnt_reg[33][5]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X68Y255 SFP_GEN[33].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X68Y255 SFP_GEN[33].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X58Y257 SFP_GEN[33].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[6]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y256 SFP_GEN[33].ngCCM_gbt/CrossClock_DV_cnt/shiftA_reg[0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y256 SFP_GEN[33].ngCCM_gbt/CrossClock_DV_cnt/shiftA_reg[1]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_36 To Clock: gtwiz_userclk_rx_srcclk_out[0]_36 Setup : 0 Failing Endpoints, Worst Slack 3.184ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.039ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.184ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][17]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 5.012ns (logic 0.383ns (7.642%) route 4.629ns (92.358%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.656ns = ( 10.973 - 8.317 ) Source Clock Delay (SCD): 2.899ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.474ns (routing 0.794ns, distribution 1.680ns) Clock Net Delay (Destination): 2.280ns (routing 0.710ns, distribution 1.570ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.474 2.899 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y423 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.038 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.621 5.659 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X49Y421 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.244 5.903 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/O net (fo=76, routed) 2.008 7.911 rx_data_ngccm[36] SLICE_X55Y427 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][17]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.280 10.973 g_gbt_bank[3].gbtbank_n_0 SLICE_X55Y427 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][17]/C clock pessimism 0.212 11.185 clock uncertainty -0.035 11.150 SLICE_X55Y427 FDCE (Setup_AFF2_SLICEM_C_CE) -0.055 11.095 SFP_GEN[36].rx_data_ngccm_reg[36][17] ------------------------------------------------------------------- required time 11.095 arrival time -7.911 ------------------------------------------------------------------- slack 3.184 Slack (MET) : 3.188ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][16]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 5.009ns (logic 0.383ns (7.646%) route 4.626ns (92.354%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.656ns = ( 10.973 - 8.317 ) Source Clock Delay (SCD): 2.899ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.474ns (routing 0.794ns, distribution 1.680ns) Clock Net Delay (Destination): 2.280ns (routing 0.710ns, distribution 1.570ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.474 2.899 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y423 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.038 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.621 5.659 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X49Y421 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.244 5.903 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/O net (fo=76, routed) 2.005 7.908 rx_data_ngccm[36] SLICE_X55Y427 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][16]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.280 10.973 g_gbt_bank[3].gbtbank_n_0 SLICE_X55Y427 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][16]/C clock pessimism 0.212 11.185 clock uncertainty -0.035 11.150 SLICE_X55Y427 FDCE (Setup_AFF_SLICEM_C_CE) -0.054 11.096 SFP_GEN[36].rx_data_ngccm_reg[36][16] ------------------------------------------------------------------- required time 11.096 arrival time -7.908 ------------------------------------------------------------------- slack 3.188 Slack (MET) : 3.203ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][24]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 4.999ns (logic 0.383ns (7.662%) route 4.616ns (92.338%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.665ns = ( 10.982 - 8.317 ) Source Clock Delay (SCD): 2.899ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.474ns (routing 0.794ns, distribution 1.680ns) Clock Net Delay (Destination): 2.289ns (routing 0.710ns, distribution 1.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.474 2.899 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y423 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.038 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.621 5.659 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X49Y421 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.244 5.903 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/O net (fo=76, routed) 1.995 7.898 rx_data_ngccm[36] SLICE_X53Y426 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][24]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.289 10.982 g_gbt_bank[3].gbtbank_n_0 SLICE_X53Y426 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][24]/C clock pessimism 0.212 11.194 clock uncertainty -0.035 11.159 SLICE_X53Y426 FDCE (Setup_EFF2_SLICEM_C_CE) -0.058 11.101 SFP_GEN[36].rx_data_ngccm_reg[36][24] ------------------------------------------------------------------- required time 11.101 arrival time -7.898 ------------------------------------------------------------------- slack 3.203 Slack (MET) : 3.203ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][26]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 4.999ns (logic 0.383ns (7.662%) route 4.616ns (92.338%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.665ns = ( 10.982 - 8.317 ) Source Clock Delay (SCD): 2.899ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.474ns (routing 0.794ns, distribution 1.680ns) Clock Net Delay (Destination): 2.289ns (routing 0.710ns, distribution 1.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.474 2.899 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y423 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.038 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.621 5.659 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X49Y421 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.244 5.903 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/O net (fo=76, routed) 1.995 7.898 rx_data_ngccm[36] SLICE_X53Y426 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][26]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.289 10.982 g_gbt_bank[3].gbtbank_n_0 SLICE_X53Y426 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][26]/C clock pessimism 0.212 11.194 clock uncertainty -0.035 11.159 SLICE_X53Y426 FDCE (Setup_FFF2_SLICEM_C_CE) -0.058 11.101 SFP_GEN[36].rx_data_ngccm_reg[36][26] ------------------------------------------------------------------- required time 11.101 arrival time -7.898 ------------------------------------------------------------------- slack 3.203 Slack (MET) : 3.203ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][28]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 4.999ns (logic 0.383ns (7.662%) route 4.616ns (92.338%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.665ns = ( 10.982 - 8.317 ) Source Clock Delay (SCD): 2.899ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.474ns (routing 0.794ns, distribution 1.680ns) Clock Net Delay (Destination): 2.289ns (routing 0.710ns, distribution 1.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.474 2.899 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y423 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.038 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.621 5.659 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X49Y421 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.244 5.903 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/O net (fo=76, routed) 1.995 7.898 rx_data_ngccm[36] SLICE_X53Y426 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][28]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.289 10.982 g_gbt_bank[3].gbtbank_n_0 SLICE_X53Y426 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][28]/C clock pessimism 0.212 11.194 clock uncertainty -0.035 11.159 SLICE_X53Y426 FDCE (Setup_GFF2_SLICEM_C_CE) -0.058 11.101 SFP_GEN[36].rx_data_ngccm_reg[36][28] ------------------------------------------------------------------- required time 11.101 arrival time -7.898 ------------------------------------------------------------------- slack 3.203 Slack (MET) : 3.203ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][33]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 4.999ns (logic 0.383ns (7.662%) route 4.616ns (92.338%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.665ns = ( 10.982 - 8.317 ) Source Clock Delay (SCD): 2.899ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.474ns (routing 0.794ns, distribution 1.680ns) Clock Net Delay (Destination): 2.289ns (routing 0.710ns, distribution 1.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.474 2.899 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y423 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.038 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.621 5.659 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X49Y421 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.244 5.903 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/O net (fo=76, routed) 1.995 7.898 rx_data_ngccm[36] SLICE_X53Y426 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][33]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.289 10.982 g_gbt_bank[3].gbtbank_n_0 SLICE_X53Y426 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][33]/C clock pessimism 0.212 11.194 clock uncertainty -0.035 11.159 SLICE_X53Y426 FDCE (Setup_HFF2_SLICEM_C_CE) -0.058 11.101 SFP_GEN[36].rx_data_ngccm_reg[36][33] ------------------------------------------------------------------- required time 11.101 arrival time -7.898 ------------------------------------------------------------------- slack 3.203 Slack (MET) : 3.209ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][19]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 4.996ns (logic 0.383ns (7.666%) route 4.613ns (92.334%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.665ns = ( 10.982 - 8.317 ) Source Clock Delay (SCD): 2.899ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.474ns (routing 0.794ns, distribution 1.680ns) Clock Net Delay (Destination): 2.289ns (routing 0.710ns, distribution 1.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.474 2.899 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y423 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.038 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.621 5.659 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X49Y421 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.244 5.903 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/O net (fo=76, routed) 1.992 7.895 rx_data_ngccm[36] SLICE_X53Y426 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][19]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.289 10.982 g_gbt_bank[3].gbtbank_n_0 SLICE_X53Y426 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][19]/C clock pessimism 0.212 11.194 clock uncertainty -0.035 11.159 SLICE_X53Y426 FDCE (Setup_EFF_SLICEM_C_CE) -0.055 11.104 SFP_GEN[36].rx_data_ngccm_reg[36][19] ------------------------------------------------------------------- required time 11.104 arrival time -7.895 ------------------------------------------------------------------- slack 3.209 Slack (MET) : 3.209ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][25]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 4.996ns (logic 0.383ns (7.666%) route 4.613ns (92.334%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.665ns = ( 10.982 - 8.317 ) Source Clock Delay (SCD): 2.899ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.474ns (routing 0.794ns, distribution 1.680ns) Clock Net Delay (Destination): 2.289ns (routing 0.710ns, distribution 1.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.474 2.899 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y423 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.038 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.621 5.659 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X49Y421 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.244 5.903 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/O net (fo=76, routed) 1.992 7.895 rx_data_ngccm[36] SLICE_X53Y426 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][25]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.289 10.982 g_gbt_bank[3].gbtbank_n_0 SLICE_X53Y426 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][25]/C clock pessimism 0.212 11.194 clock uncertainty -0.035 11.159 SLICE_X53Y426 FDCE (Setup_FFF_SLICEM_C_CE) -0.055 11.104 SFP_GEN[36].rx_data_ngccm_reg[36][25] ------------------------------------------------------------------- required time 11.104 arrival time -7.895 ------------------------------------------------------------------- slack 3.209 Slack (MET) : 3.209ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][27]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 4.996ns (logic 0.383ns (7.666%) route 4.613ns (92.334%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.665ns = ( 10.982 - 8.317 ) Source Clock Delay (SCD): 2.899ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.474ns (routing 0.794ns, distribution 1.680ns) Clock Net Delay (Destination): 2.289ns (routing 0.710ns, distribution 1.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.474 2.899 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y423 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.038 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.621 5.659 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X49Y421 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.244 5.903 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/O net (fo=76, routed) 1.992 7.895 rx_data_ngccm[36] SLICE_X53Y426 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][27]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.289 10.982 g_gbt_bank[3].gbtbank_n_0 SLICE_X53Y426 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][27]/C clock pessimism 0.212 11.194 clock uncertainty -0.035 11.159 SLICE_X53Y426 FDCE (Setup_GFF_SLICEM_C_CE) -0.055 11.104 SFP_GEN[36].rx_data_ngccm_reg[36][27] ------------------------------------------------------------------- required time 11.104 arrival time -7.895 ------------------------------------------------------------------- slack 3.209 Slack (MET) : 3.209ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][29]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 4.996ns (logic 0.383ns (7.666%) route 4.613ns (92.334%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.665ns = ( 10.982 - 8.317 ) Source Clock Delay (SCD): 2.899ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.474ns (routing 0.794ns, distribution 1.680ns) Clock Net Delay (Destination): 2.289ns (routing 0.710ns, distribution 1.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.474 2.899 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y423 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.038 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.621 5.659 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X49Y421 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.244 5.903 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/O net (fo=76, routed) 1.992 7.895 rx_data_ngccm[36] SLICE_X53Y426 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][29]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.289 10.982 g_gbt_bank[3].gbtbank_n_0 SLICE_X53Y426 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][29]/C clock pessimism 0.212 11.194 clock uncertainty -0.035 11.159 SLICE_X53Y426 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 11.104 SFP_GEN[36].rx_data_ngccm_reg[36][29] ------------------------------------------------------------------- required time 11.104 arrival time -7.895 ------------------------------------------------------------------- slack 3.209 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.189ns (logic 0.094ns (49.735%) route 0.095ns (50.265%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.371ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.001ns (routing 0.377ns, distribution 0.624ns) Clock Net Delay (Destination): 1.219ns (routing 0.443ns, distribution 0.776ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.001 1.117 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X48Y434 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y434 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.166 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Q net (fo=2, routed) 0.079 1.245 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_25_in SLICE_X50Y434 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.045 1.290 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__35/O net (fo=1, routed) 0.016 1.306 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[13] SLICE_X50Y434 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.219 1.371 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X50Y434 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C clock pessimism -0.160 1.211 SLICE_X50Y434 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.267 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13] ------------------------------------------------------------------- required time -1.267 arrival time 1.306 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][24]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.194ns (logic 0.049ns (25.258%) route 0.145ns (74.742%)) Logic Levels: 0 Clock Path Skew: 0.092ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.378ns Source Clock Delay (SCD): 1.126ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.010ns (routing 0.377ns, distribution 0.633ns) Clock Net Delay (Destination): 1.226ns (routing 0.443ns, distribution 0.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.010 1.126 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X52Y428 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X52Y428 FDRE (Prop_DFF2_SLICEM_C_Q) 0.049 1.175 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/Q net (fo=1, routed) 0.145 1.320 rx_data[36][24] SLICE_X53Y426 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][24]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.226 1.378 g_gbt_bank[3].gbtbank_n_0 SLICE_X53Y426 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][24]/C clock pessimism -0.160 1.218 SLICE_X53Y426 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.273 SFP_GEN[36].rx_data_ngccm_reg[36][24] ------------------------------------------------------------------- required time -1.273 arrival time 1.320 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.152ns (logic 0.064ns (42.105%) route 0.088ns (57.895%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.049ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.369ns Source Clock Delay (SCD): 1.130ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 1.014ns (routing 0.377ns, distribution 0.637ns) Clock Net Delay (Destination): 1.217ns (routing 0.443ns, distribution 0.774ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.130 g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X49Y421 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y421 FDCE (Prop_AFF2_SLICEM_C_Q) 0.049 1.179 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/Q net (fo=7, routed) 0.072 1.251 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]_1[5] SLICE_X49Y420 LUT6 (Prop_C6LUT_SLICEM_I3_O) 0.015 1.266 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i[0]_i_1__2/O net (fo=1, routed) 0.016 1.282 g_gbt_bank[3].gbtbank/i_gbt_bank_n_144 SLICE_X49Y420 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.217 1.369 g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X49Y420 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/C clock pessimism -0.190 1.178 SLICE_X49Y420 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.234 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0] ------------------------------------------------------------------- required time -1.235 arrival time 1.282 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[21]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.181ns (logic 0.048ns (26.519%) route 0.133ns (73.481%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.373ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.020ns (routing 0.377ns, distribution 0.643ns) Clock Net Delay (Destination): 1.221ns (routing 0.443ns, distribution 0.778ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.136 SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X54Y427 FDCE r SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[21]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y427 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.184 r SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[21]/Q net (fo=4, routed) 0.133 1.317 SFP_GEN[36].ngCCM_gbt/gbt_rx_checker/Q[5] SLICE_X56Y427 FDRE r SFP_GEN[36].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.221 1.373 SFP_GEN[36].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y427 FDRE r SFP_GEN[36].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[5]/C clock pessimism -0.160 1.213 SLICE_X56Y427 FDRE (Hold_AFF2_SLICEL_C_D) 0.056 1.269 SFP_GEN[36].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[5] ------------------------------------------------------------------- required time -1.269 arrival time 1.317 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][75]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.167ns (logic 0.049ns (29.341%) route 0.118ns (70.659%)) Logic Levels: 0 Clock Path Skew: 0.063ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.353ns Source Clock Delay (SCD): 1.130ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.014ns (routing 0.377ns, distribution 0.637ns) Clock Net Delay (Destination): 1.201ns (routing 0.443ns, distribution 0.758ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.130 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X49Y434 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y434 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 1.179 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/Q net (fo=1, routed) 0.118 1.297 rx_data[36][75] SLICE_X48Y434 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][75]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.201 1.353 g_gbt_bank[3].gbtbank_n_0 SLICE_X48Y434 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][75]/C clock pessimism -0.160 1.193 SLICE_X48Y434 FDCE (Hold_BFF_SLICEL_C_D) 0.056 1.249 SFP_GEN[36].rx_data_ngccm_reg[36][75] ------------------------------------------------------------------- required time -1.249 arrival time 1.297 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.150ns (logic 0.063ns (42.000%) route 0.087ns (58.000%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.046ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.356ns Source Clock Delay (SCD): 1.119ns Clock Pessimism Removal (CPR): 0.191ns Clock Net Delay (Source): 1.003ns (routing 0.377ns, distribution 0.626ns) Clock Net Delay (Destination): 1.204ns (routing 0.443ns, distribution 0.761ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.003 1.119 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X51Y436 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y436 FDCE (Prop_EFF2_SLICEL_C_Q) 0.048 1.167 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.072 1.239 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in SLICE_X51Y435 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.015 1.254 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__35/O net (fo=1, routed) 0.015 1.269 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] SLICE_X51Y435 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.204 1.356 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X51Y435 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.191 1.165 SLICE_X51Y435 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.221 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.221 arrival time 1.269 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][28]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.197ns (logic 0.049ns (24.873%) route 0.148ns (75.127%)) Logic Levels: 0 Clock Path Skew: 0.092ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.378ns Source Clock Delay (SCD): 1.126ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.010ns (routing 0.377ns, distribution 0.633ns) Clock Net Delay (Destination): 1.226ns (routing 0.443ns, distribution 0.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.010 1.126 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X52Y427 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X52Y427 FDRE (Prop_DFF2_SLICEM_C_Q) 0.049 1.175 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/Q net (fo=1, routed) 0.148 1.323 rx_data[36][28] SLICE_X53Y426 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][28]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.226 1.378 g_gbt_bank[3].gbtbank_n_0 SLICE_X53Y426 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][28]/C clock pessimism -0.160 1.218 SLICE_X53Y426 FDCE (Hold_GFF2_SLICEM_C_D) 0.056 1.274 SFP_GEN[36].rx_data_ngccm_reg[36][28] ------------------------------------------------------------------- required time -1.274 arrival time 1.323 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: SFP_GEN[36].rx_data_ngccm_reg[36][66]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[66]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.087ns (50.289%) route 0.086ns (49.711%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.352ns Source Clock Delay (SCD): 1.125ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.009ns (routing 0.377ns, distribution 0.632ns) Clock Net Delay (Destination): 1.200ns (routing 0.443ns, distribution 0.757ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.009 1.125 g_gbt_bank[3].gbtbank_n_0 SLICE_X49Y436 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][66]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y436 FDCE (Prop_BFF_SLICEM_C_Q) 0.049 1.174 r SFP_GEN[36].rx_data_ngccm_reg[36][66]/Q net (fo=1, routed) 0.075 1.249 SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[83]_0[58] SLICE_X48Y436 LUT3 (Prop_D5LUT_SLICEL_I1_O) 0.038 1.287 r SFP_GEN[36].ngCCM_gbt/RX_Word_rx40[66]_i_1/O net (fo=1, routed) 0.011 1.298 SFP_GEN[36].ngCCM_gbt/RX_Word_rx40[66]_i_1_n_0 SLICE_X48Y436 FDCE r SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[66]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.200 1.352 SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y436 FDCE r SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[66]/C clock pessimism -0.160 1.192 SLICE_X48Y436 FDCE (Hold_DFF2_SLICEL_C_D) 0.056 1.248 SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[66] ------------------------------------------------------------------- required time -1.248 arrival time 1.298 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.148ns (logic 0.094ns (63.513%) route 0.054ns (36.486%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.372ns Source Clock Delay (SCD): 1.129ns Clock Pessimism Removal (CPR): 0.202ns Clock Net Delay (Source): 1.013ns (routing 0.377ns, distribution 0.636ns) Clock Net Delay (Destination): 1.220ns (routing 0.443ns, distribution 0.777ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.013 1.129 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X49Y434 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y434 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.178 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Q net (fo=2, routed) 0.038 1.216 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_31_in SLICE_X49Y434 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.045 1.261 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__35/O net (fo=1, routed) 0.016 1.277 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] SLICE_X49Y434 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.220 1.372 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X49Y434 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.202 1.170 SLICE_X49Y434 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.226 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.226 arrival time 1.277 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][38]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.048ns (32.877%) route 0.098ns (67.123%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.377ns Source Clock Delay (SCD): 1.137ns Clock Pessimism Removal (CPR): 0.202ns Clock Net Delay (Source): 1.021ns (routing 0.377ns, distribution 0.644ns) Clock Net Delay (Destination): 1.225ns (routing 0.443ns, distribution 0.782ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.021 1.137 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X53Y427 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y427 FDRE (Prop_CFF_SLICEM_C_Q) 0.048 1.185 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/Q net (fo=1, routed) 0.098 1.283 rx_data[36][38] SLICE_X54Y427 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][38]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.225 1.377 g_gbt_bank[3].gbtbank_n_0 SLICE_X54Y427 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][38]/C clock pessimism -0.202 1.175 SLICE_X54Y427 FDCE (Hold_HFF2_SLICEL_C_D) 0.056 1.231 SFP_GEN[36].rx_data_ngccm_reg[36][38] ------------------------------------------------------------------- required time -1.231 arrival time 1.283 ------------------------------------------------------------------- slack 0.052 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_36 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y187 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y422 g_clock_rate_din[36].ngccm_status_cnt_reg[36][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y422 g_clock_rate_din[36].ngccm_status_cnt_reg[36][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y422 g_clock_rate_din[36].ngccm_status_cnt_reg[36][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y422 g_clock_rate_din[36].ngccm_status_cnt_reg[36][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y422 g_clock_rate_din[36].ngccm_status_cnt_reg[36][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y422 g_clock_rate_din[36].ngccm_status_cnt_reg[36][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y422 g_clock_rate_din[36].ngccm_status_cnt_reg[36][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X56Y422 g_clock_rate_din[36].ngccm_status_cnt_reg[36][5]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X56Y422 g_clock_rate_din[36].ngccm_status_cnt_reg[36][7]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X54Y433 SFP_GEN[36].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X54Y433 SFP_GEN[36].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[42]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X54Y430 SFP_GEN[36].rx_data_ngccm_reg[36][0]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X52Y434 SFP_GEN[36].rx_data_ngccm_reg[36][1]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X55Y422 g_clock_rate_din[36].ngccm_status_cnt_reg[36][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X55Y422 g_clock_rate_din[36].ngccm_status_cnt_reg[36][1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X55Y422 g_clock_rate_din[36].ngccm_status_cnt_reg[36][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X54Y428 SFP_GEN[36].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X54Y428 SFP_GEN[36].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X54Y428 SFP_GEN[36].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_37 To Clock: gtwiz_userclk_rx_srcclk_out[0]_37 Setup : 0 Failing Endpoints, Worst Slack 2.885ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.036ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.885ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.514ns (logic 1.605ns (29.108%) route 3.909ns (70.892%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.172ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.978ns = ( 11.295 - 8.317 ) Source Clock Delay (SCD): 3.035ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.610ns (routing 1.081ns, distribution 1.529ns) Clock Net Delay (Destination): 2.602ns (routing 0.984ns, distribution 1.618ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.610 3.035 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 4.119 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.960 7.079 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X51Y571 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.238 7.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/O net (fo=5, routed) 0.268 7.585 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X51Y572 LUT4 (Prop_D5LUT_SLICEL_I2_O) 0.117 7.702 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__45/O net (fo=1, routed) 0.232 7.934 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__45_n_0 SLICE_X51Y574 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.166 8.100 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__45/O net (fo=2, routed) 0.449 8.549 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__45_n_0 SLICE_X51Y575 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.602 11.295 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK SLICE_X51Y575 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.229 11.524 clock uncertainty -0.035 11.489 SLICE_X51Y575 FDCE (Setup_GFF_SLICEL_C_CE) -0.055 11.434 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.434 arrival time -8.549 ------------------------------------------------------------------- slack 2.885 Slack (MET) : 2.885ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.514ns (logic 1.605ns (29.108%) route 3.909ns (70.892%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.172ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.978ns = ( 11.295 - 8.317 ) Source Clock Delay (SCD): 3.035ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.610ns (routing 1.081ns, distribution 1.529ns) Clock Net Delay (Destination): 2.602ns (routing 0.984ns, distribution 1.618ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.610 3.035 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 4.119 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.960 7.079 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X51Y571 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.238 7.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/O net (fo=5, routed) 0.268 7.585 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X51Y572 LUT4 (Prop_D5LUT_SLICEL_I2_O) 0.117 7.702 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__45/O net (fo=1, routed) 0.232 7.934 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__45_n_0 SLICE_X51Y574 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.166 8.100 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__45/O net (fo=2, routed) 0.449 8.549 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__45_n_0 SLICE_X51Y575 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.602 11.295 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK SLICE_X51Y575 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.229 11.524 clock uncertainty -0.035 11.489 SLICE_X51Y575 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 11.434 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.434 arrival time -8.549 ------------------------------------------------------------------- slack 2.885 Slack (MET) : 3.049ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.346ns (logic 1.557ns (29.125%) route 3.789ns (70.875%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.168ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.974ns = ( 11.291 - 8.317 ) Source Clock Delay (SCD): 3.035ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.610ns (routing 1.081ns, distribution 1.529ns) Clock Net Delay (Destination): 2.598ns (routing 0.984ns, distribution 1.614ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.610 3.035 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 4.119 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.960 7.079 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X51Y571 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.238 7.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/O net (fo=5, routed) 0.274 7.591 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X51Y574 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.235 7.826 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/O net (fo=7, routed) 0.555 8.381 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 SLICE_X50Y575 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.598 11.291 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK SLICE_X50Y575 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.229 11.520 clock uncertainty -0.035 11.485 SLICE_X50Y575 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 11.430 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.430 arrival time -8.381 ------------------------------------------------------------------- slack 3.049 Slack (MET) : 3.054ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.342ns (logic 1.557ns (29.146%) route 3.785ns (70.854%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.168ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.974ns = ( 11.291 - 8.317 ) Source Clock Delay (SCD): 3.035ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.610ns (routing 1.081ns, distribution 1.529ns) Clock Net Delay (Destination): 2.598ns (routing 0.984ns, distribution 1.614ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.610 3.035 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 4.119 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.960 7.079 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X51Y571 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.238 7.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/O net (fo=5, routed) 0.274 7.591 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X51Y574 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.235 7.826 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/O net (fo=7, routed) 0.551 8.377 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 SLICE_X50Y575 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.598 11.291 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK SLICE_X50Y575 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.229 11.520 clock uncertainty -0.035 11.485 SLICE_X50Y575 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 11.431 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.431 arrival time -8.377 ------------------------------------------------------------------- slack 3.054 Slack (MET) : 3.174ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.228ns (logic 1.557ns (29.782%) route 3.671ns (70.218%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.175ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.981ns = ( 11.298 - 8.317 ) Source Clock Delay (SCD): 3.035ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.610ns (routing 1.081ns, distribution 1.529ns) Clock Net Delay (Destination): 2.605ns (routing 0.984ns, distribution 1.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.610 3.035 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 4.119 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.960 7.079 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X51Y571 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.238 7.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/O net (fo=5, routed) 0.274 7.591 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X51Y574 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.235 7.826 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/O net (fo=7, routed) 0.437 8.263 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 SLICE_X51Y576 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.605 11.298 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK SLICE_X51Y576 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.229 11.527 clock uncertainty -0.035 11.492 SLICE_X51Y576 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 11.437 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.437 arrival time -8.263 ------------------------------------------------------------------- slack 3.174 Slack (MET) : 3.179ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.224ns (logic 1.557ns (29.805%) route 3.667ns (70.195%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.175ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.981ns = ( 11.298 - 8.317 ) Source Clock Delay (SCD): 3.035ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.610ns (routing 1.081ns, distribution 1.529ns) Clock Net Delay (Destination): 2.605ns (routing 0.984ns, distribution 1.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.610 3.035 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 4.119 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.960 7.079 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X51Y571 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.238 7.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/O net (fo=5, routed) 0.274 7.591 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X51Y574 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.235 7.826 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/O net (fo=7, routed) 0.433 8.259 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 SLICE_X51Y576 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.605 11.298 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK SLICE_X51Y576 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.229 11.527 clock uncertainty -0.035 11.492 SLICE_X51Y576 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 11.438 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 11.438 arrival time -8.259 ------------------------------------------------------------------- slack 3.179 Slack (MET) : 3.179ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.224ns (logic 1.557ns (29.805%) route 3.667ns (70.195%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.175ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.981ns = ( 11.298 - 8.317 ) Source Clock Delay (SCD): 3.035ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.610ns (routing 1.081ns, distribution 1.529ns) Clock Net Delay (Destination): 2.605ns (routing 0.984ns, distribution 1.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.610 3.035 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 4.119 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.960 7.079 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X51Y571 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.238 7.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/O net (fo=5, routed) 0.274 7.591 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X51Y574 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.235 7.826 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/O net (fo=7, routed) 0.433 8.259 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 SLICE_X51Y576 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.605 11.298 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK SLICE_X51Y576 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.229 11.527 clock uncertainty -0.035 11.492 SLICE_X51Y576 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 11.438 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 11.438 arrival time -8.259 ------------------------------------------------------------------- slack 3.179 Slack (MET) : 3.198ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.199ns (logic 1.557ns (29.948%) route 3.642ns (70.052%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.170ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.976ns = ( 11.293 - 8.317 ) Source Clock Delay (SCD): 3.035ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.610ns (routing 1.081ns, distribution 1.529ns) Clock Net Delay (Destination): 2.600ns (routing 0.984ns, distribution 1.616ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.610 3.035 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 4.119 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.960 7.079 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X51Y571 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.238 7.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/O net (fo=5, routed) 0.274 7.591 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X51Y574 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.235 7.826 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/O net (fo=7, routed) 0.408 8.234 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 SLICE_X51Y572 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.600 11.293 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK SLICE_X51Y572 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.229 11.522 clock uncertainty -0.035 11.487 SLICE_X51Y572 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 11.432 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 11.432 arrival time -8.234 ------------------------------------------------------------------- slack 3.198 Slack (MET) : 3.198ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.199ns (logic 1.557ns (29.948%) route 3.642ns (70.052%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.170ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.976ns = ( 11.293 - 8.317 ) Source Clock Delay (SCD): 3.035ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.610ns (routing 1.081ns, distribution 1.529ns) Clock Net Delay (Destination): 2.600ns (routing 0.984ns, distribution 1.616ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.610 3.035 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 4.119 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.960 7.079 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X51Y571 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.238 7.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/O net (fo=5, routed) 0.274 7.591 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X51Y574 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.235 7.826 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/O net (fo=7, routed) 0.408 8.234 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 SLICE_X51Y572 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.600 11.293 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK SLICE_X51Y572 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.229 11.522 clock uncertainty -0.035 11.487 SLICE_X51Y572 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 11.432 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 11.432 arrival time -8.234 ------------------------------------------------------------------- slack 3.198 Slack (MET) : 3.363ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.023ns (logic 1.469ns (29.245%) route 3.554ns (70.755%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.968ns = ( 11.285 - 8.317 ) Source Clock Delay (SCD): 3.035ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.610ns (routing 1.081ns, distribution 1.529ns) Clock Net Delay (Destination): 2.592ns (routing 0.984ns, distribution 1.608ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.610 3.035 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 4.119 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.960 7.079 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X51Y571 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.238 7.317 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/O net (fo=5, routed) 0.089 7.406 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X51Y571 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 7.553 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__46/O net (fo=5, routed) 0.505 8.058 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 SLICE_X52Y569 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.592 11.285 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK SLICE_X52Y569 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.229 11.514 clock uncertainty -0.035 11.479 SLICE_X52Y569 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 11.421 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 11.421 arrival time -8.058 ------------------------------------------------------------------- slack 3.363 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.186ns (logic 0.094ns (50.538%) route 0.092ns (49.462%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.507ns Source Clock Delay (SCD): 1.250ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 1.134ns (routing 0.463ns, distribution 0.671ns) Clock Net Delay (Destination): 1.355ns (routing 0.528ns, distribution 0.827ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.134 1.250 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X48Y566 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y566 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.299 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Q net (fo=2, routed) 0.076 1.375 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_23_in SLICE_X49Y566 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.045 1.420 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__45/O net (fo=1, routed) 0.016 1.436 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[12] SLICE_X49Y566 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.355 1.507 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X49Y566 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C clock pessimism -0.163 1.344 SLICE_X49Y566 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.400 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12] ------------------------------------------------------------------- required time -1.400 arrival time 1.436 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.038ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[46].rx_data_ngccm_reg[46][29]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.170ns (logic 0.049ns (28.824%) route 0.121ns (71.176%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.497ns Source Clock Delay (SCD): 1.258ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 1.142ns (routing 0.463ns, distribution 0.679ns) Clock Net Delay (Destination): 1.345ns (routing 0.528ns, distribution 0.817ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.142 1.258 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X48Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y561 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.307 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/Q net (fo=1, routed) 0.121 1.428 rx_data[46][29] SLICE_X49Y560 FDCE r SFP_GEN[46].rx_data_ngccm_reg[46][29]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.345 1.497 g_gbt_bank[3].gbtbank_n_124 SLICE_X49Y560 FDCE r SFP_GEN[46].rx_data_ngccm_reg[46][29]/C clock pessimism -0.163 1.334 SLICE_X49Y560 FDCE (Hold_EFF_SLICEM_C_D) 0.056 1.390 SFP_GEN[46].rx_data_ngccm_reg[46][29] ------------------------------------------------------------------- required time -1.390 arrival time 1.428 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[26]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[26]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.049ns (31.613%) route 0.106ns (68.387%)) Logic Levels: 0 Clock Path Skew: 0.061ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.482ns Source Clock Delay (SCD): 1.257ns Clock Pessimism Removal (CPR): 0.164ns Clock Net Delay (Source): 1.141ns (routing 0.463ns, distribution 0.678ns) Clock Net Delay (Destination): 1.330ns (routing 0.528ns, distribution 0.802ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.141 1.257 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X51Y565 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[26]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y565 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 1.306 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[26]/Q net (fo=1, routed) 0.106 1.412 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0[26] SLICE_X52Y565 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.330 1.482 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X52Y565 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[26]/C clock pessimism -0.164 1.318 SLICE_X52Y565 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.373 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[26] ------------------------------------------------------------------- required time -1.373 arrival time 1.412 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.044ns (arrival time - required time) Source: SFP_GEN[46].rx_data_ngccm_reg[46][44]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[44]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.193ns (logic 0.095ns (49.223%) route 0.098ns (50.777%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.093ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.519ns Source Clock Delay (SCD): 1.263ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 1.147ns (routing 0.463ns, distribution 0.684ns) Clock Net Delay (Destination): 1.367ns (routing 0.528ns, distribution 0.839ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.147 1.263 g_gbt_bank[3].gbtbank_n_124 SLICE_X52Y558 FDCE r SFP_GEN[46].rx_data_ngccm_reg[46][44]/C ------------------------------------------------------------------- ------------------- SLICE_X52Y558 FDCE (Prop_AFF2_SLICEM_C_Q) 0.049 1.312 r SFP_GEN[46].rx_data_ngccm_reg[46][44]/Q net (fo=1, routed) 0.082 1.394 SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[83]_0[36] SLICE_X53Y558 LUT3 (Prop_D6LUT_SLICEM_I1_O) 0.046 1.440 r SFP_GEN[46].ngCCM_gbt/RX_Word_rx40[44]_i_1/O net (fo=1, routed) 0.016 1.456 SFP_GEN[46].ngCCM_gbt/RX_Word_rx40[44]_i_1_n_0 SLICE_X53Y558 FDCE r SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[44]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.367 1.519 SFP_GEN[46].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y558 FDCE r SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[44]/C clock pessimism -0.163 1.356 SLICE_X53Y558 FDCE (Hold_DFF_SLICEM_C_D) 0.056 1.412 SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[44] ------------------------------------------------------------------- required time -1.412 arrival time 1.456 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.044ns (arrival time - required time) Source: SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[46].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.200ns (logic 0.049ns (24.500%) route 0.151ns (75.500%)) Logic Levels: 0 Clock Path Skew: 0.100ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.521ns Source Clock Delay (SCD): 1.258ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 1.142ns (routing 0.463ns, distribution 0.679ns) Clock Net Delay (Destination): 1.369ns (routing 0.528ns, distribution 0.841ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.142 1.258 SFP_GEN[46].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y553 FDCE r SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y553 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.307 r SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[18]/Q net (fo=5, routed) 0.151 1.458 SFP_GEN[46].ngCCM_gbt/gbt_rx_checker/Q[2] SLICE_X49Y553 FDRE r SFP_GEN[46].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.369 1.521 SFP_GEN[46].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X49Y553 FDRE r SFP_GEN[46].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/C clock pessimism -0.163 1.358 SLICE_X49Y553 FDRE (Hold_AFF2_SLICEM_C_D) 0.056 1.414 SFP_GEN[46].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2] ------------------------------------------------------------------- required time -1.414 arrival time 1.458 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.094ns (64.384%) route 0.052ns (35.616%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.518ns Source Clock Delay (SCD): 1.270ns Clock Pessimism Removal (CPR): 0.206ns Clock Net Delay (Source): 1.154ns (routing 0.463ns, distribution 0.691ns) Clock Net Delay (Destination): 1.366ns (routing 0.528ns, distribution 0.838ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.154 1.270 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X54Y558 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y558 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.319 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.037 1.356 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/O85[0] SLICE_X54Y558 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.045 1.401 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__45/O net (fo=1, routed) 0.015 1.416 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/I9[0] SLICE_X54Y558 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.366 1.518 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X54Y558 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C clock pessimism -0.206 1.312 SLICE_X54Y558 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.368 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19] ------------------------------------------------------------------- required time -1.368 arrival time 1.416 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/RX_BITSLIPCMD_o_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.109ns (logic 0.064ns (58.716%) route 0.045ns (41.284%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.481ns Source Clock Delay (SCD): 1.251ns Clock Pessimism Removal (CPR): 0.225ns Clock Net Delay (Source): 1.135ns (routing 0.463ns, distribution 0.672ns) Clock Net Delay (Destination): 1.329ns (routing 0.528ns, distribution 0.801ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.135 1.251 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/CLK SLICE_X49Y574 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X49Y574 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.300 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/RX_BITSLIPCMD_o_reg/Q net (fo=2, routed) 0.033 1.333 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/rxslide_in[0] SLICE_X49Y574 LUT3 (Prop_A6LUT_SLICEM_I2_O) 0.015 1.348 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__45/O net (fo=1, routed) 0.012 1.360 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__45_n_0 SLICE_X49Y574 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/RX_BITSLIPCMD_o_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.329 1.481 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/CLK SLICE_X49Y574 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C clock pessimism -0.225 1.256 SLICE_X49Y574 FDCE (Hold_AFF_SLICEM_C_D) 0.056 1.312 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/RX_BITSLIPCMD_o_reg ------------------------------------------------------------------- required time -1.312 arrival time 1.360 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[25]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[25]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.168ns (logic 0.048ns (28.571%) route 0.120ns (71.429%)) Logic Levels: 0 Clock Path Skew: 0.063ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.482ns Source Clock Delay (SCD): 1.255ns Clock Pessimism Removal (CPR): 0.164ns Clock Net Delay (Source): 1.139ns (routing 0.463ns, distribution 0.676ns) Clock Net Delay (Destination): 1.330ns (routing 0.528ns, distribution 0.802ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.139 1.255 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X51Y565 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[25]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y565 FDCE (Prop_GFF_SLICEL_C_Q) 0.048 1.303 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[25]/Q net (fo=1, routed) 0.120 1.423 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0[25] SLICE_X52Y565 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.330 1.482 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X52Y565 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[25]/C clock pessimism -0.164 1.318 SLICE_X52Y565 FDCE (Hold_EFF_SLICEM_C_D) 0.056 1.374 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[25] ------------------------------------------------------------------- required time -1.374 arrival time 1.423 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.095ns (64.626%) route 0.052ns (35.374%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.506ns Source Clock Delay (SCD): 1.261ns Clock Pessimism Removal (CPR): 0.204ns Clock Net Delay (Source): 1.145ns (routing 0.463ns, distribution 0.682ns) Clock Net Delay (Destination): 1.354ns (routing 0.528ns, distribution 0.826ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.145 1.261 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X49Y567 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y567 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.310 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Q net (fo=2, routed) 0.036 1.346 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_13_in SLICE_X49Y567 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.046 1.392 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__45/O net (fo=1, routed) 0.016 1.408 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[5] SLICE_X49Y567 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.354 1.506 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X49Y567 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism -0.204 1.302 SLICE_X49Y567 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.358 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time -1.358 arrival time 1.408 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.111ns (logic 0.064ns (57.658%) route 0.047ns (42.342%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.481ns Source Clock Delay (SCD): 1.249ns Clock Pessimism Removal (CPR): 0.227ns Clock Net Delay (Source): 1.133ns (routing 0.463ns, distribution 0.670ns) Clock Net Delay (Destination): 1.329ns (routing 0.528ns, distribution 0.801ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.133 1.249 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/CLK SLICE_X51Y571 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X51Y571 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.298 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_reg/Q net (fo=2, routed) 0.035 1.333 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/ready_from_bitSlipCtrller_10 SLICE_X51Y571 LUT3 (Prop_A6LUT_SLICEL_I2_O) 0.015 1.348 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_i_1__45/O net (fo=1, routed) 0.012 1.360 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_i_1__45_n_0 SLICE_X51Y571 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.329 1.481 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/CLK SLICE_X51Y571 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_reg/C clock pessimism -0.227 1.254 SLICE_X51Y571 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.310 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_reg ------------------------------------------------------------------- required time -1.310 arrival time 1.360 ------------------------------------------------------------------- slack 0.050 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_37 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y216 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y533 g_clock_rate_din[46].ngccm_status_cnt_reg[46][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y532 g_clock_rate_din[46].ngccm_status_cnt_reg[46][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y532 g_clock_rate_din[46].ngccm_status_cnt_reg[46][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y532 g_clock_rate_din[46].ngccm_status_cnt_reg[46][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y532 g_clock_rate_din[46].ngccm_status_cnt_reg[46][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y532 g_clock_rate_din[46].ngccm_status_cnt_reg[46][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y531 g_clock_rate_din[46].ngccm_status_cnt_reg[46][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X53Y540 SFP_GEN[46].ngCCM_gbt/RX_Clock_20MHz_dl_reg[0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X53Y540 SFP_GEN[46].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/C Low Pulse Width Slow FDPE/C n/a 0.275 4.159 3.884 SLICE_X53Y541 SFP_GEN[46].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[0]/C Low Pulse Width Slow FDPE/C n/a 0.275 4.159 3.884 SLICE_X53Y541 SFP_GEN[46].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[1]/C Low Pulse Width Slow FDPE/C n/a 0.275 4.159 3.884 SLICE_X53Y541 SFP_GEN[46].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[2]/C Low Pulse Width Slow FDPE/C n/a 0.275 4.159 3.884 SLICE_X53Y541 SFP_GEN[46].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X56Y532 g_clock_rate_din[46].ngccm_status_cnt_reg[46][1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X56Y532 g_clock_rate_din[46].ngccm_status_cnt_reg[46][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X56Y532 g_clock_rate_din[46].ngccm_status_cnt_reg[46][3]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X56Y532 g_clock_rate_din[46].ngccm_status_cnt_reg[46][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X56Y532 g_clock_rate_din[46].ngccm_status_cnt_reg[46][5]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X69Y480 g_clock_rate_din[46].rx_wordclk_div2_reg[46]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_38 To Clock: gtwiz_userclk_rx_srcclk_out[0]_38 Setup : 0 Failing Endpoints, Worst Slack 2.468ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.037ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.468ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 5.865ns (logic 1.630ns (27.792%) route 4.235ns (72.208%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.106ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.617ns = ( 10.934 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.294ns (routing 0.788ns, distribution 1.506ns) Clock Net Delay (Destination): 2.241ns (routing 0.707ns, distribution 1.534ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.294 2.719 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.823 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.342 7.165 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X57Y598 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.166 7.331 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/O net (fo=5, routed) 0.310 7.641 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X58Y598 LUT4 (Prop_D5LUT_SLICEM_I2_O) 0.193 7.834 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__46/O net (fo=1, routed) 0.222 8.056 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__46_n_0 SLICE_X58Y598 LUT6 (Prop_C6LUT_SLICEM_I5_O) 0.167 8.223 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__46/O net (fo=2, routed) 0.361 8.584 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__46_n_0 SLICE_X59Y598 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.241 10.934 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X59Y598 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.208 11.143 clock uncertainty -0.035 11.107 SLICE_X59Y598 FDCE (Setup_GFF_SLICEM_C_CE) -0.055 11.052 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.052 arrival time -8.584 ------------------------------------------------------------------- slack 2.468 Slack (MET) : 2.468ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 5.865ns (logic 1.630ns (27.792%) route 4.235ns (72.208%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.106ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.617ns = ( 10.934 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.294ns (routing 0.788ns, distribution 1.506ns) Clock Net Delay (Destination): 2.241ns (routing 0.707ns, distribution 1.534ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.294 2.719 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.823 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.342 7.165 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X57Y598 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.166 7.331 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/O net (fo=5, routed) 0.310 7.641 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X58Y598 LUT4 (Prop_D5LUT_SLICEM_I2_O) 0.193 7.834 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__46/O net (fo=1, routed) 0.222 8.056 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__46_n_0 SLICE_X58Y598 LUT6 (Prop_C6LUT_SLICEM_I5_O) 0.167 8.223 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__46/O net (fo=2, routed) 0.361 8.584 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__46_n_0 SLICE_X59Y598 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.241 10.934 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X59Y598 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.208 11.143 clock uncertainty -0.035 11.107 SLICE_X59Y598 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 11.052 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.052 arrival time -8.584 ------------------------------------------------------------------- slack 2.468 Slack (MET) : 2.754ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 5.574ns (logic 1.416ns (25.404%) route 4.158ns (74.596%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.104ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.615ns = ( 10.932 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.294ns (routing 0.788ns, distribution 1.506ns) Clock Net Delay (Destination): 2.239ns (routing 0.707ns, distribution 1.532ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.294 2.719 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.823 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.342 7.165 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X57Y598 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.166 7.331 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/O net (fo=5, routed) 0.418 7.749 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X58Y599 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 7.895 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__47/O net (fo=3, routed) 0.398 8.293 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 SLICE_X58Y594 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.239 10.932 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X58Y594 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.208 11.141 clock uncertainty -0.035 11.105 SLICE_X58Y594 FDRE (Setup_GFF2_SLICEM_C_CE) -0.058 11.047 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 11.047 arrival time -8.293 ------------------------------------------------------------------- slack 2.754 Slack (MET) : 2.754ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 5.574ns (logic 1.416ns (25.404%) route 4.158ns (74.596%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.104ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.615ns = ( 10.932 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.294ns (routing 0.788ns, distribution 1.506ns) Clock Net Delay (Destination): 2.239ns (routing 0.707ns, distribution 1.532ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.294 2.719 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.823 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.342 7.165 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X57Y598 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.166 7.331 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/O net (fo=5, routed) 0.418 7.749 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X58Y599 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 7.895 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__47/O net (fo=3, routed) 0.398 8.293 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 SLICE_X58Y594 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.239 10.932 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X58Y594 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C clock pessimism 0.208 11.141 clock uncertainty -0.035 11.105 SLICE_X58Y594 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 11.047 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2] ------------------------------------------------------------------- required time 11.047 arrival time -8.293 ------------------------------------------------------------------- slack 2.754 Slack (MET) : 2.760ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 5.571ns (logic 1.416ns (25.417%) route 4.155ns (74.583%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.104ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.615ns = ( 10.932 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.294ns (routing 0.788ns, distribution 1.506ns) Clock Net Delay (Destination): 2.239ns (routing 0.707ns, distribution 1.532ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.294 2.719 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.823 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.342 7.165 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X57Y598 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.166 7.331 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/O net (fo=5, routed) 0.418 7.749 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X58Y599 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 7.895 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__47/O net (fo=3, routed) 0.395 8.290 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 SLICE_X58Y594 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.239 10.932 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X58Y594 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.208 11.141 clock uncertainty -0.035 11.105 SLICE_X58Y594 FDRE (Setup_GFF_SLICEM_C_CE) -0.055 11.050 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 11.050 arrival time -8.290 ------------------------------------------------------------------- slack 2.760 Slack (MET) : 2.988ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 5.335ns (logic 1.362ns (25.530%) route 3.973ns (74.470%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.607ns = ( 10.924 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.294ns (routing 0.788ns, distribution 1.506ns) Clock Net Delay (Destination): 2.231ns (routing 0.707ns, distribution 1.524ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.294 2.719 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.823 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.342 7.165 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X57Y598 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.166 7.331 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/O net (fo=5, routed) 0.186 7.517 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X58Y598 LUT5 (Prop_B6LUT_SLICEM_I3_O) 0.092 7.609 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/O net (fo=7, routed) 0.445 8.054 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 SLICE_X58Y597 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.231 10.924 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X58Y597 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.208 11.133 clock uncertainty -0.035 11.097 SLICE_X58Y597 FDRE (Setup_EFF_SLICEM_C_CE) -0.055 11.042 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 11.042 arrival time -8.054 ------------------------------------------------------------------- slack 2.988 Slack (MET) : 2.988ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 5.335ns (logic 1.362ns (25.530%) route 3.973ns (74.470%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.607ns = ( 10.924 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.294ns (routing 0.788ns, distribution 1.506ns) Clock Net Delay (Destination): 2.231ns (routing 0.707ns, distribution 1.524ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.294 2.719 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.823 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.342 7.165 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X57Y598 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.166 7.331 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/O net (fo=5, routed) 0.186 7.517 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X58Y598 LUT5 (Prop_B6LUT_SLICEM_I3_O) 0.092 7.609 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/O net (fo=7, routed) 0.445 8.054 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 SLICE_X58Y597 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.231 10.924 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X58Y597 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.208 11.133 clock uncertainty -0.035 11.097 SLICE_X58Y597 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 11.042 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 11.042 arrival time -8.054 ------------------------------------------------------------------- slack 2.988 Slack (MET) : 3.012ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 5.318ns (logic 1.362ns (25.611%) route 3.956ns (74.389%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.103ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.614ns = ( 10.931 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.294ns (routing 0.788ns, distribution 1.506ns) Clock Net Delay (Destination): 2.238ns (routing 0.707ns, distribution 1.531ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.294 2.719 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.823 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.342 7.165 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X57Y598 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.166 7.331 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/O net (fo=5, routed) 0.186 7.517 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X58Y598 LUT5 (Prop_B6LUT_SLICEM_I3_O) 0.092 7.609 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/O net (fo=7, routed) 0.428 8.037 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 SLICE_X56Y598 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.238 10.931 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X56Y598 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.208 11.140 clock uncertainty -0.035 11.104 SLICE_X56Y598 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 11.049 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.049 arrival time -8.037 ------------------------------------------------------------------- slack 3.012 Slack (MET) : 3.017ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 5.314ns (logic 1.362ns (25.630%) route 3.952ns (74.370%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.103ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.614ns = ( 10.931 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.294ns (routing 0.788ns, distribution 1.506ns) Clock Net Delay (Destination): 2.238ns (routing 0.707ns, distribution 1.531ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.294 2.719 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.823 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.342 7.165 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X57Y598 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.166 7.331 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/O net (fo=5, routed) 0.186 7.517 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X58Y598 LUT5 (Prop_B6LUT_SLICEM_I3_O) 0.092 7.609 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/O net (fo=7, routed) 0.424 8.033 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 SLICE_X56Y598 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.238 10.931 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X56Y598 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.208 11.140 clock uncertainty -0.035 11.104 SLICE_X56Y598 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 11.050 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.050 arrival time -8.033 ------------------------------------------------------------------- slack 3.017 Slack (MET) : 3.045ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 5.290ns (logic 1.362ns (25.747%) route 3.928ns (74.253%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.619ns = ( 10.936 - 8.317 ) Source Clock Delay (SCD): 2.719ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.294ns (routing 0.788ns, distribution 1.506ns) Clock Net Delay (Destination): 2.243ns (routing 0.707ns, distribution 1.536ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.294 2.719 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.823 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.342 7.165 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X57Y598 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.166 7.331 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/O net (fo=5, routed) 0.186 7.517 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X58Y598 LUT5 (Prop_B6LUT_SLICEM_I3_O) 0.092 7.609 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/O net (fo=7, routed) 0.400 8.009 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 SLICE_X59Y598 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.243 10.936 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X59Y598 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.208 11.145 clock uncertainty -0.035 11.109 SLICE_X59Y598 FDRE (Setup_BFF2_SLICEM_C_CE) -0.055 11.054 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.054 arrival time -8.009 ------------------------------------------------------------------- slack 3.045 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.037ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[27]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[27]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.168ns (logic 0.048ns (28.571%) route 0.120ns (71.429%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.367ns Source Clock Delay (SCD): 1.135ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.019ns (routing 0.376ns, distribution 0.643ns) Clock Net Delay (Destination): 1.215ns (routing 0.440ns, distribution 0.775ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.019 1.135 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X63Y594 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y594 FDCE (Prop_HFF_SLICEL_C_Q) 0.048 1.183 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[27]/Q net (fo=1, routed) 0.120 1.303 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[27] SLICE_X64Y594 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[27]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.215 1.367 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X64Y594 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[27]/C clock pessimism -0.157 1.210 SLICE_X64Y594 FDCE (Hold_EFF_SLICEM_C_D) 0.056 1.266 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[27] ------------------------------------------------------------------- required time -1.266 arrival time 1.303 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.152ns (logic 0.101ns (66.447%) route 0.051ns (33.553%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.383ns Source Clock Delay (SCD): 1.140ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 1.024ns (routing 0.376ns, distribution 0.648ns) Clock Net Delay (Destination): 1.231ns (routing 0.440ns, distribution 0.791ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.024 1.140 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X62Y589 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y589 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.189 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Q net (fo=2, routed) 0.035 1.224 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_25_in SLICE_X62Y588 LUT3 (Prop_C6LUT_SLICEM_I2_O) 0.052 1.276 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__46/O net (fo=1, routed) 0.016 1.292 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[11] SLICE_X62Y588 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.231 1.383 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X62Y588 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C clock pessimism -0.190 1.193 SLICE_X62Y588 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.249 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11] ------------------------------------------------------------------- required time -1.249 arrival time 1.292 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.046ns (arrival time - required time) Source: SFP_GEN[47].rx_data_ngccm_reg[47][41]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[40]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.139ns (logic 0.093ns (66.906%) route 0.046ns (33.094%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.379ns Source Clock Delay (SCD): 1.139ns Clock Pessimism Removal (CPR): 0.203ns Clock Net Delay (Source): 1.023ns (routing 0.376ns, distribution 0.647ns) Clock Net Delay (Destination): 1.227ns (routing 0.440ns, distribution 0.787ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.023 1.139 g_gbt_bank[3].gbtbank_n_134 SLICE_X63Y588 FDCE r SFP_GEN[47].rx_data_ngccm_reg[47][41]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y588 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.187 r SFP_GEN[47].rx_data_ngccm_reg[47][41]/Q net (fo=1, routed) 0.034 1.221 SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[83]_0[33] SLICE_X63Y588 LUT3 (Prop_F6LUT_SLICEL_I0_O) 0.045 1.266 r SFP_GEN[47].ngCCM_gbt/RX_Word_rx40[40]_i_1/O net (fo=1, routed) 0.012 1.278 SFP_GEN[47].ngCCM_gbt/RX_Word_rx40[40]_i_1_n_0 SLICE_X63Y588 FDCE r SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[40]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.227 1.379 SFP_GEN[47].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y588 FDCE r SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[40]/C clock pessimism -0.203 1.176 SLICE_X63Y588 FDCE (Hold_FFF_SLICEL_C_D) 0.056 1.232 SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[40] ------------------------------------------------------------------- required time -1.232 arrival time 1.278 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.386ns Source Clock Delay (SCD): 1.141ns Clock Pessimism Removal (CPR): 0.203ns Clock Net Delay (Source): 1.025ns (routing 0.376ns, distribution 0.649ns) Clock Net Delay (Destination): 1.234ns (routing 0.440ns, distribution 0.794ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.025 1.141 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X66Y589 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y589 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.190 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Q net (fo=2, routed) 0.034 1.224 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_5_in SLICE_X66Y589 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.045 1.269 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__46/O net (fo=1, routed) 0.016 1.285 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[1] SLICE_X66Y589 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.234 1.386 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X66Y589 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.203 1.183 SLICE_X66Y589 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.239 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.239 arrival time 1.285 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.150ns (logic 0.101ns (67.333%) route 0.049ns (32.667%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.048ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.364ns Source Clock Delay (SCD): 1.125ns Clock Pessimism Removal (CPR): 0.191ns Clock Net Delay (Source): 1.009ns (routing 0.376ns, distribution 0.633ns) Clock Net Delay (Destination): 1.212ns (routing 0.440ns, distribution 0.772ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.009 1.125 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X61Y588 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y588 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.174 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Q net (fo=1, routed) 0.033 1.207 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] SLICE_X61Y587 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.052 1.259 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__46/O net (fo=1, routed) 0.016 1.275 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[1] SLICE_X61Y587 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.212 1.364 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X61Y587 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.191 1.173 SLICE_X61Y587 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.229 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.229 arrival time 1.275 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.063ns (42.857%) route 0.084ns (57.143%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.045ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.371ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 1.020ns (routing 0.376ns, distribution 0.644ns) Clock Net Delay (Destination): 1.219ns (routing 0.440ns, distribution 0.779ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.136 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X68Y587 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X68Y587 FDCE (Prop_GFF_SLICEL_C_Q) 0.048 1.184 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.072 1.256 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/O85[0] SLICE_X68Y586 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.015 1.271 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__46/O net (fo=1, routed) 0.012 1.283 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/I9[0] SLICE_X68Y586 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.219 1.371 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X68Y586 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C clock pessimism -0.190 1.181 SLICE_X68Y586 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.237 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19] ------------------------------------------------------------------- required time -1.237 arrival time 1.283 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.175ns (logic 0.086ns (49.143%) route 0.089ns (50.857%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.371ns Source Clock Delay (SCD): 1.142ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.026ns (routing 0.376ns, distribution 0.650ns) Clock Net Delay (Destination): 1.219ns (routing 0.440ns, distribution 0.779ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.026 1.142 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X70Y585 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X70Y585 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.190 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[8]/Q net (fo=2, routed) 0.077 1.267 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_15_in SLICE_X69Y585 LUT3 (Prop_G5LUT_SLICEL_I2_O) 0.038 1.305 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__46/O net (fo=1, routed) 0.012 1.317 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[6] SLICE_X69Y585 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.219 1.371 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X69Y585 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C clock pessimism -0.157 1.214 SLICE_X69Y585 FDRE (Hold_GFF2_SLICEL_C_D) 0.056 1.270 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6] ------------------------------------------------------------------- required time -1.270 arrival time 1.317 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.382ns Source Clock Delay (SCD): 1.140ns Clock Pessimism Removal (CPR): 0.204ns Clock Net Delay (Source): 1.024ns (routing 0.376ns, distribution 0.648ns) Clock Net Delay (Destination): 1.230ns (routing 0.440ns, distribution 0.790ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.024 1.140 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X62Y589 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y589 FDCE (Prop_BFF2_SLICEM_C_Q) 0.048 1.188 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.038 1.226 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_33_in SLICE_X62Y589 LUT3 (Prop_F6LUT_SLICEM_I0_O) 0.046 1.272 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__46/O net (fo=1, routed) 0.012 1.284 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[17] SLICE_X62Y589 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.230 1.382 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X62Y589 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.204 1.178 SLICE_X62Y589 FDRE (Hold_FFF_SLICEM_C_D) 0.056 1.234 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.234 arrival time 1.284 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.120ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.004ns (routing 0.376ns, distribution 0.628ns) Clock Net Delay (Destination): 1.207ns (routing 0.440ns, distribution 0.767ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.004 1.120 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X60Y589 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y589 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.169 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Q net (fo=1, routed) 0.034 1.203 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] SLICE_X60Y589 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.045 1.248 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__46/O net (fo=1, routed) 0.016 1.264 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[1] SLICE_X60Y589 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.207 1.359 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X60Y589 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.201 1.158 SLICE_X60Y589 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.214 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.214 arrival time 1.264 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.104ns (69.799%) route 0.045ns (30.201%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.386ns Source Clock Delay (SCD): 1.141ns Clock Pessimism Removal (CPR): 0.203ns Clock Net Delay (Source): 1.025ns (routing 0.376ns, distribution 0.649ns) Clock Net Delay (Destination): 1.234ns (routing 0.440ns, distribution 0.794ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.025 1.141 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X66Y589 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y589 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.190 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Q net (fo=2, routed) 0.034 1.224 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_5_in SLICE_X66Y589 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.055 1.279 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[3]_i_1__46/O net (fo=1, routed) 0.011 1.290 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[3] SLICE_X66Y589 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.234 1.386 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X66Y589 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C clock pessimism -0.203 1.183 SLICE_X66Y589 FDRE (Hold_DFF2_SLICEL_C_D) 0.056 1.239 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3] ------------------------------------------------------------------- required time -1.239 arrival time 1.290 ------------------------------------------------------------------- slack 0.051 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_38 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y237 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X68Y540 g_clock_rate_din[47].ngccm_status_cnt_reg[47][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X68Y540 g_clock_rate_din[47].ngccm_status_cnt_reg[47][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X68Y540 g_clock_rate_din[47].ngccm_status_cnt_reg[47][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X68Y540 g_clock_rate_din[47].ngccm_status_cnt_reg[47][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X68Y541 g_clock_rate_din[47].ngccm_status_cnt_reg[47][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X68Y541 g_clock_rate_din[47].ngccm_status_cnt_reg[47][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y540 g_clock_rate_din[47].ngccm_status_cnt_reg[47][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X64Y562 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X64Y562 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X65Y589 SFP_GEN[47].rx_data_ngccm_reg[47][43]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X65Y589 SFP_GEN[47].rx_data_ngccm_reg[47][45]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X65Y589 SFP_GEN[47].rx_data_ngccm_reg[47][47]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X65Y589 SFP_GEN[47].rx_data_ngccm_reg[47][49]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X68Y579 g_clock_rate_din[47].rx_frameclk_div2_reg[47]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X62Y540 SFP_GEN[47].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X63Y572 SFP_GEN[47].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X64Y566 SFP_GEN[47].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X63Y572 SFP_GEN[47].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[42]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X62Y540 SFP_GEN[47].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[48]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_39 To Clock: gtwiz_userclk_rx_srcclk_out[0]_39 Setup : 0 Failing Endpoints, Worst Slack 3.526ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.034ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.526ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].rx_data_ngccm_reg[37][69]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 4.522ns (logic 0.383ns (8.470%) route 4.139ns (91.530%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.179ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.479ns = ( 10.796 - 8.317 ) Source Clock Delay (SCD): 2.873ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.448ns (routing 0.789ns, distribution 1.659ns) Clock Net Delay (Destination): 2.103ns (routing 0.708ns, distribution 1.395ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.448 2.873 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y441 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.012 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.983 4.995 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X39Y422 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 5.239 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/O net (fo=76, routed) 2.156 7.395 rx_data_ngccm[37] SLICE_X20Y426 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][69]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.103 10.796 g_gbt_bank[3].gbtbank_n_34 SLICE_X20Y426 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][69]/C clock pessimism 0.215 11.011 clock uncertainty -0.035 10.976 SLICE_X20Y426 FDCE (Setup_AFF2_SLICEL_C_CE) -0.055 10.921 SFP_GEN[37].rx_data_ngccm_reg[37][69] ------------------------------------------------------------------- required time 10.921 arrival time -7.395 ------------------------------------------------------------------- slack 3.526 Slack (MET) : 3.531ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].rx_data_ngccm_reg[37][68]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 4.518ns (logic 0.383ns (8.477%) route 4.135ns (91.523%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.179ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.479ns = ( 10.796 - 8.317 ) Source Clock Delay (SCD): 2.873ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.448ns (routing 0.789ns, distribution 1.659ns) Clock Net Delay (Destination): 2.103ns (routing 0.708ns, distribution 1.395ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.448 2.873 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y441 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.012 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.983 4.995 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X39Y422 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 5.239 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/O net (fo=76, routed) 2.152 7.391 rx_data_ngccm[37] SLICE_X20Y426 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][68]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.103 10.796 g_gbt_bank[3].gbtbank_n_34 SLICE_X20Y426 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][68]/C clock pessimism 0.215 11.011 clock uncertainty -0.035 10.976 SLICE_X20Y426 FDCE (Setup_AFF_SLICEL_C_CE) -0.054 10.922 SFP_GEN[37].rx_data_ngccm_reg[37][68] ------------------------------------------------------------------- required time 10.922 arrival time -7.391 ------------------------------------------------------------------- slack 3.531 Slack (MET) : 3.531ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].rx_data_ngccm_reg[37][70]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 4.518ns (logic 0.383ns (8.477%) route 4.135ns (91.523%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.179ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.479ns = ( 10.796 - 8.317 ) Source Clock Delay (SCD): 2.873ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.448ns (routing 0.789ns, distribution 1.659ns) Clock Net Delay (Destination): 2.103ns (routing 0.708ns, distribution 1.395ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.448 2.873 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y441 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.012 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.983 4.995 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X39Y422 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 5.239 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/O net (fo=76, routed) 2.152 7.391 rx_data_ngccm[37] SLICE_X20Y426 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][70]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.103 10.796 g_gbt_bank[3].gbtbank_n_34 SLICE_X20Y426 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][70]/C clock pessimism 0.215 11.011 clock uncertainty -0.035 10.976 SLICE_X20Y426 FDCE (Setup_BFF_SLICEL_C_CE) -0.054 10.922 SFP_GEN[37].rx_data_ngccm_reg[37][70] ------------------------------------------------------------------- required time 10.922 arrival time -7.391 ------------------------------------------------------------------- slack 3.531 Slack (MET) : 3.684ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].rx_data_ngccm_reg[37][65]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 4.372ns (logic 0.383ns (8.760%) route 3.989ns (91.240%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.171ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.487ns = ( 10.804 - 8.317 ) Source Clock Delay (SCD): 2.873ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.448ns (routing 0.789ns, distribution 1.659ns) Clock Net Delay (Destination): 2.111ns (routing 0.708ns, distribution 1.403ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.448 2.873 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y441 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.012 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.983 4.995 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X39Y422 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 5.239 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/O net (fo=76, routed) 2.006 7.245 rx_data_ngccm[37] SLICE_X20Y424 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][65]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.111 10.804 g_gbt_bank[3].gbtbank_n_34 SLICE_X20Y424 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][65]/C clock pessimism 0.215 11.019 clock uncertainty -0.035 10.984 SLICE_X20Y424 FDCE (Setup_AFF2_SLICEL_C_CE) -0.055 10.929 SFP_GEN[37].rx_data_ngccm_reg[37][65] ------------------------------------------------------------------- required time 10.929 arrival time -7.245 ------------------------------------------------------------------- slack 3.684 Slack (MET) : 3.684ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].rx_data_ngccm_reg[37][71]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 4.372ns (logic 0.383ns (8.760%) route 3.989ns (91.240%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.171ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.487ns = ( 10.804 - 8.317 ) Source Clock Delay (SCD): 2.873ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.448ns (routing 0.789ns, distribution 1.659ns) Clock Net Delay (Destination): 2.111ns (routing 0.708ns, distribution 1.403ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.448 2.873 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y441 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.012 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.983 4.995 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X39Y422 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 5.239 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/O net (fo=76, routed) 2.006 7.245 rx_data_ngccm[37] SLICE_X20Y424 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][71]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.111 10.804 g_gbt_bank[3].gbtbank_n_34 SLICE_X20Y424 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][71]/C clock pessimism 0.215 11.019 clock uncertainty -0.035 10.984 SLICE_X20Y424 FDCE (Setup_BFF2_SLICEL_C_CE) -0.055 10.929 SFP_GEN[37].rx_data_ngccm_reg[37][71] ------------------------------------------------------------------- required time 10.929 arrival time -7.245 ------------------------------------------------------------------- slack 3.684 Slack (MET) : 3.684ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].rx_data_ngccm_reg[37][73]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 4.372ns (logic 0.383ns (8.760%) route 3.989ns (91.240%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.171ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.487ns = ( 10.804 - 8.317 ) Source Clock Delay (SCD): 2.873ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.448ns (routing 0.789ns, distribution 1.659ns) Clock Net Delay (Destination): 2.111ns (routing 0.708ns, distribution 1.403ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.448 2.873 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y441 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.012 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.983 4.995 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X39Y422 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 5.239 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/O net (fo=76, routed) 2.006 7.245 rx_data_ngccm[37] SLICE_X20Y424 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][73]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.111 10.804 g_gbt_bank[3].gbtbank_n_34 SLICE_X20Y424 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][73]/C clock pessimism 0.215 11.019 clock uncertainty -0.035 10.984 SLICE_X20Y424 FDCE (Setup_CFF2_SLICEL_C_CE) -0.055 10.929 SFP_GEN[37].rx_data_ngccm_reg[37][73] ------------------------------------------------------------------- required time 10.929 arrival time -7.245 ------------------------------------------------------------------- slack 3.684 Slack (MET) : 3.684ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].rx_data_ngccm_reg[37][75]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 4.372ns (logic 0.383ns (8.760%) route 3.989ns (91.240%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.171ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.487ns = ( 10.804 - 8.317 ) Source Clock Delay (SCD): 2.873ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.448ns (routing 0.789ns, distribution 1.659ns) Clock Net Delay (Destination): 2.111ns (routing 0.708ns, distribution 1.403ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.448 2.873 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y441 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.012 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.983 4.995 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X39Y422 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 5.239 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/O net (fo=76, routed) 2.006 7.245 rx_data_ngccm[37] SLICE_X20Y424 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][75]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.111 10.804 g_gbt_bank[3].gbtbank_n_34 SLICE_X20Y424 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][75]/C clock pessimism 0.215 11.019 clock uncertainty -0.035 10.984 SLICE_X20Y424 FDCE (Setup_DFF2_SLICEL_C_CE) -0.055 10.929 SFP_GEN[37].rx_data_ngccm_reg[37][75] ------------------------------------------------------------------- required time 10.929 arrival time -7.245 ------------------------------------------------------------------- slack 3.684 Slack (MET) : 3.689ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].rx_data_ngccm_reg[37][64]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 4.368ns (logic 0.383ns (8.768%) route 3.985ns (91.232%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.171ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.487ns = ( 10.804 - 8.317 ) Source Clock Delay (SCD): 2.873ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.448ns (routing 0.789ns, distribution 1.659ns) Clock Net Delay (Destination): 2.111ns (routing 0.708ns, distribution 1.403ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.448 2.873 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y441 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.012 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.983 4.995 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X39Y422 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 5.239 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/O net (fo=76, routed) 2.002 7.241 rx_data_ngccm[37] SLICE_X20Y424 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][64]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.111 10.804 g_gbt_bank[3].gbtbank_n_34 SLICE_X20Y424 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][64]/C clock pessimism 0.215 11.019 clock uncertainty -0.035 10.984 SLICE_X20Y424 FDCE (Setup_AFF_SLICEL_C_CE) -0.054 10.930 SFP_GEN[37].rx_data_ngccm_reg[37][64] ------------------------------------------------------------------- required time 10.930 arrival time -7.241 ------------------------------------------------------------------- slack 3.689 Slack (MET) : 3.689ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].rx_data_ngccm_reg[37][66]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 4.368ns (logic 0.383ns (8.768%) route 3.985ns (91.232%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.171ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.487ns = ( 10.804 - 8.317 ) Source Clock Delay (SCD): 2.873ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.448ns (routing 0.789ns, distribution 1.659ns) Clock Net Delay (Destination): 2.111ns (routing 0.708ns, distribution 1.403ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.448 2.873 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y441 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.012 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.983 4.995 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X39Y422 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 5.239 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/O net (fo=76, routed) 2.002 7.241 rx_data_ngccm[37] SLICE_X20Y424 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][66]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.111 10.804 g_gbt_bank[3].gbtbank_n_34 SLICE_X20Y424 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][66]/C clock pessimism 0.215 11.019 clock uncertainty -0.035 10.984 SLICE_X20Y424 FDCE (Setup_BFF_SLICEL_C_CE) -0.054 10.930 SFP_GEN[37].rx_data_ngccm_reg[37][66] ------------------------------------------------------------------- required time 10.930 arrival time -7.241 ------------------------------------------------------------------- slack 3.689 Slack (MET) : 3.689ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].rx_data_ngccm_reg[37][72]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 4.368ns (logic 0.383ns (8.768%) route 3.985ns (91.232%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.171ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.487ns = ( 10.804 - 8.317 ) Source Clock Delay (SCD): 2.873ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.448ns (routing 0.789ns, distribution 1.659ns) Clock Net Delay (Destination): 2.111ns (routing 0.708ns, distribution 1.403ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.448 2.873 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y441 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.012 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.983 4.995 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X39Y422 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 5.239 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/O net (fo=76, routed) 2.002 7.241 rx_data_ngccm[37] SLICE_X20Y424 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][72]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.111 10.804 g_gbt_bank[3].gbtbank_n_34 SLICE_X20Y424 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][72]/C clock pessimism 0.215 11.019 clock uncertainty -0.035 10.984 SLICE_X20Y424 FDCE (Setup_CFF_SLICEL_C_CE) -0.054 10.930 SFP_GEN[37].rx_data_ngccm_reg[37][72] ------------------------------------------------------------------- required time 10.930 arrival time -7.241 ------------------------------------------------------------------- slack 3.689 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.034ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].rx_data_ngccm_reg[37][33]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.162ns (logic 0.049ns (30.247%) route 0.113ns (69.753%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.240ns Source Clock Delay (SCD): 1.024ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.908ns (routing 0.376ns, distribution 0.532ns) Clock Net Delay (Destination): 1.088ns (routing 0.440ns, distribution 0.648ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.908 1.024 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X28Y420 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X28Y420 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 1.073 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/Q net (fo=1, routed) 0.113 1.186 rx_data[37][33] SLICE_X29Y420 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][33]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.088 1.240 g_gbt_bank[3].gbtbank_n_34 SLICE_X29Y420 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][33]/C clock pessimism -0.143 1.097 SLICE_X29Y420 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.152 SFP_GEN[37].rx_data_ngccm_reg[37][33] ------------------------------------------------------------------- required time -1.152 arrival time 1.186 ------------------------------------------------------------------- slack 0.034 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.191ns (logic 0.094ns (49.215%) route 0.097ns (50.785%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.096ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.257ns Source Clock Delay (SCD): 1.018ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.902ns (routing 0.376ns, distribution 0.526ns) Clock Net Delay (Destination): 1.105ns (routing 0.440ns, distribution 0.665ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.902 1.018 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X28Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X28Y423 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.067 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Q net (fo=2, routed) 0.081 1.148 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_13_in SLICE_X29Y423 LUT3 (Prop_C6LUT_SLICEM_I2_O) 0.045 1.193 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__36/O net (fo=1, routed) 0.016 1.209 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[5] SLICE_X29Y423 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.105 1.257 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X29Y423 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism -0.143 1.114 SLICE_X29Y423 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.170 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time -1.170 arrival time 1.209 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.180ns (logic 0.079ns (43.889%) route 0.101ns (56.111%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.250ns Source Clock Delay (SCD): 1.023ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.907ns (routing 0.376ns, distribution 0.531ns) Clock Net Delay (Destination): 1.098ns (routing 0.440ns, distribution 0.658ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.907 1.023 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X28Y420 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X28Y420 FDCE (Prop_EFF2_SLICEM_C_Q) 0.048 1.071 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Q net (fo=2, routed) 0.085 1.156 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_25_in SLICE_X29Y421 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.031 1.187 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__36/O net (fo=1, routed) 0.016 1.203 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[11] SLICE_X29Y421 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.098 1.250 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X29Y421 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C clock pessimism -0.143 1.107 SLICE_X29Y421 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.163 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11] ------------------------------------------------------------------- required time -1.163 arrival time 1.203 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.041ns (arrival time - required time) Source: SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[82]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[18]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.162ns (logic 0.049ns (30.247%) route 0.113ns (69.753%)) Logic Levels: 0 Clock Path Skew: 0.066ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.238ns Source Clock Delay (SCD): 1.029ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.913ns (routing 0.376ns, distribution 0.537ns) Clock Net Delay (Destination): 1.086ns (routing 0.440ns, distribution 0.646ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.913 1.029 SFP_GEN[37].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X30Y423 FDCE r SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[82]/C ------------------------------------------------------------------- ------------------- SLICE_X30Y423 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 1.078 r SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[82]/Q net (fo=2, routed) 0.113 1.191 SFP_GEN[37].ngCCM_gbt/gbt_rx_checker/Q[18] SLICE_X31Y423 FDRE r SFP_GEN[37].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[18]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.086 1.238 SFP_GEN[37].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X31Y423 FDRE r SFP_GEN[37].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[18]/C clock pessimism -0.143 1.095 SLICE_X31Y423 FDRE (Hold_FFF2_SLICEM_C_D) 0.055 1.150 SFP_GEN[37].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[18] ------------------------------------------------------------------- required time -1.150 arrival time 1.191 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.196ns (logic 0.104ns (53.061%) route 0.092ns (46.939%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.096ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.257ns Source Clock Delay (SCD): 1.018ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.902ns (routing 0.376ns, distribution 0.526ns) Clock Net Delay (Destination): 1.105ns (routing 0.440ns, distribution 0.665ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.902 1.018 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X28Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X28Y423 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.067 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Q net (fo=2, routed) 0.081 1.148 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_13_in SLICE_X29Y423 LUT3 (Prop_C5LUT_SLICEM_I0_O) 0.055 1.203 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[7]_i_1__36/O net (fo=1, routed) 0.011 1.214 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[7] SLICE_X29Y423 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.105 1.257 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X29Y423 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C clock pessimism -0.143 1.114 SLICE_X29Y423 FDRE (Hold_CFF2_SLICEM_C_D) 0.056 1.170 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7] ------------------------------------------------------------------- required time -1.170 arrival time 1.214 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.064ns (41.290%) route 0.091ns (58.710%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.055ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.263ns Source Clock Delay (SCD): 1.034ns Clock Pessimism Removal (CPR): 0.174ns Clock Net Delay (Source): 0.918ns (routing 0.376ns, distribution 0.542ns) Clock Net Delay (Destination): 1.111ns (routing 0.440ns, distribution 0.671ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.918 1.034 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X23Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X23Y423 FDCE (Prop_HFF_SLICEM_C_Q) 0.048 1.082 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.076 1.158 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in SLICE_X23Y422 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.016 1.174 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__36/O net (fo=1, routed) 0.015 1.189 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] SLICE_X23Y422 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.111 1.263 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X23Y422 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.174 1.089 SLICE_X23Y422 FDRE (Hold_BFF_SLICEM_C_D) 0.056 1.145 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.145 arrival time 1.189 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].rx_data_ngccm_reg[37][39]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.048ns (33.333%) route 0.096ns (66.667%)) Logic Levels: 0 Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.242ns Source Clock Delay (SCD): 1.023ns Clock Pessimism Removal (CPR): 0.176ns Clock Net Delay (Source): 0.907ns (routing 0.376ns, distribution 0.531ns) Clock Net Delay (Destination): 1.090ns (routing 0.440ns, distribution 0.650ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.907 1.023 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X27Y421 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X27Y421 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 1.071 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/Q net (fo=1, routed) 0.096 1.167 rx_data[37][39] SLICE_X27Y420 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][39]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.090 1.242 g_gbt_bank[3].gbtbank_n_34 SLICE_X27Y420 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][39]/C clock pessimism -0.176 1.066 SLICE_X27Y420 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.121 SFP_GEN[37].rx_data_ngccm_reg[37][39] ------------------------------------------------------------------- required time -1.121 arrival time 1.167 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.180ns (logic 0.089ns (49.444%) route 0.091ns (50.556%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.244ns Source Clock Delay (SCD): 1.025ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.909ns (routing 0.376ns, distribution 0.533ns) Clock Net Delay (Destination): 1.092ns (routing 0.440ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.909 1.025 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X27Y420 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X27Y420 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.074 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Q net (fo=2, routed) 0.079 1.153 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_31_in SLICE_X28Y420 LUT3 (Prop_D5LUT_SLICEM_I2_O) 0.040 1.193 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__36/O net (fo=1, routed) 0.012 1.205 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[14] SLICE_X28Y420 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.092 1.244 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X28Y420 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C clock pessimism -0.143 1.101 SLICE_X28Y420 FDRE (Hold_DFF2_SLICEM_C_D) 0.056 1.157 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14] ------------------------------------------------------------------- required time -1.157 arrival time 1.205 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].rx_data_ngccm_reg[37][69]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.048ns (33.803%) route 0.094ns (66.197%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.291ns Source Clock Delay (SCD): 1.071ns Clock Pessimism Removal (CPR): 0.182ns Clock Net Delay (Source): 0.955ns (routing 0.376ns, distribution 0.579ns) Clock Net Delay (Destination): 1.139ns (routing 0.440ns, distribution 0.699ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.955 1.071 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X20Y425 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y425 FDRE (Prop_GFF2_SLICEL_C_Q) 0.048 1.119 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/Q net (fo=1, routed) 0.094 1.213 rx_data[37][69] SLICE_X20Y426 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][69]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.139 1.291 g_gbt_bank[3].gbtbank_n_34 SLICE_X20Y426 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][69]/C clock pessimism -0.182 1.109 SLICE_X20Y426 FDCE (Hold_AFF2_SLICEL_C_D) 0.056 1.165 SFP_GEN[37].rx_data_ngccm_reg[37][69] ------------------------------------------------------------------- required time -1.165 arrival time 1.213 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.170ns (logic 0.086ns (50.588%) route 0.084ns (49.412%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.062ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.307ns Source Clock Delay (SCD): 1.063ns Clock Pessimism Removal (CPR): 0.182ns Clock Net Delay (Source): 0.947ns (routing 0.376ns, distribution 0.571ns) Clock Net Delay (Destination): 1.155ns (routing 0.440ns, distribution 0.715ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.947 1.063 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X20Y426 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y426 FDCE (Prop_HFF_SLICEL_C_Q) 0.048 1.111 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[9]/Q net (fo=2, routed) 0.073 1.184 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_17_in SLICE_X20Y425 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.038 1.222 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[9]_i_1__36/O net (fo=1, routed) 0.011 1.233 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[9] SLICE_X20Y425 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.155 1.307 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X20Y425 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C clock pessimism -0.182 1.125 SLICE_X20Y425 FDRE (Hold_DFF2_SLICEL_C_D) 0.056 1.181 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9] ------------------------------------------------------------------- required time -1.181 arrival time 1.233 ------------------------------------------------------------------- slack 0.052 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_39 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y189 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y420 g_clock_rate_din[37].ngccm_status_cnt_reg[37][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y420 g_clock_rate_din[37].ngccm_status_cnt_reg[37][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y420 g_clock_rate_din[37].ngccm_status_cnt_reg[37][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y420 g_clock_rate_din[37].ngccm_status_cnt_reg[37][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y421 g_clock_rate_din[37].ngccm_status_cnt_reg[37][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y421 g_clock_rate_din[37].ngccm_status_cnt_reg[37][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y421 g_clock_rate_din[37].ngccm_status_cnt_reg[37][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X20Y420 SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X20Y420 SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X20Y421 SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[46]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X20Y421 SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[4]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X20Y420 SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[58]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X20Y420 SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[60]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X53Y420 g_clock_rate_din[37].ngccm_status_cnt_reg[37][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X53Y420 g_clock_rate_din[37].ngccm_status_cnt_reg[37][1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X53Y420 g_clock_rate_din[37].ngccm_status_cnt_reg[37][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X53Y420 g_clock_rate_din[37].ngccm_status_cnt_reg[37][3]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X20Y420 SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[44]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X23Y420 SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[48]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_40 To Clock: gtwiz_userclk_rx_srcclk_out[0]_40 Setup : 0 Failing Endpoints, Worst Slack 3.965ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.036ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.965ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 4.062ns (logic 1.475ns (36.312%) route 2.587ns (63.688%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.200ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.315ns = ( 10.632 - 8.317 ) Source Clock Delay (SCD): 2.717ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.292ns (routing 0.775ns, distribution 1.517ns) Clock Net Delay (Destination): 1.939ns (routing 0.697ns, distribution 1.242ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.292 2.717 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.801 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.931 5.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X34Y454 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.244 5.976 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/O net (fo=5, routed) 0.319 6.295 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X35Y454 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.092 6.387 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__37/O net (fo=1, routed) 0.079 6.466 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__37_n_0 SLICE_X35Y454 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.055 6.521 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__37/O net (fo=2, routed) 0.258 6.779 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__37_n_0 SLICE_X35Y454 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.939 10.632 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X35Y454 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.202 10.834 clock uncertainty -0.035 10.799 SLICE_X35Y454 FDCE (Setup_GFF_SLICEM_C_CE) -0.055 10.744 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.744 arrival time -6.779 ------------------------------------------------------------------- slack 3.965 Slack (MET) : 3.965ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 4.062ns (logic 1.475ns (36.312%) route 2.587ns (63.688%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.200ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.315ns = ( 10.632 - 8.317 ) Source Clock Delay (SCD): 2.717ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.292ns (routing 0.775ns, distribution 1.517ns) Clock Net Delay (Destination): 1.939ns (routing 0.697ns, distribution 1.242ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.292 2.717 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.801 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.931 5.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X34Y454 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.244 5.976 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/O net (fo=5, routed) 0.319 6.295 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X35Y454 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.092 6.387 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__37/O net (fo=1, routed) 0.079 6.466 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__37_n_0 SLICE_X35Y454 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.055 6.521 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__37/O net (fo=2, routed) 0.258 6.779 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__37_n_0 SLICE_X35Y454 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.939 10.632 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X35Y454 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.202 10.834 clock uncertainty -0.035 10.799 SLICE_X35Y454 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 10.744 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.744 arrival time -6.779 ------------------------------------------------------------------- slack 3.965 Slack (MET) : 4.001ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 4.041ns (logic 1.572ns (38.901%) route 2.469ns (61.099%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.185ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.330ns = ( 10.647 - 8.317 ) Source Clock Delay (SCD): 2.717ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.292ns (routing 0.775ns, distribution 1.517ns) Clock Net Delay (Destination): 1.954ns (routing 0.697ns, distribution 1.257ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.292 2.717 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.801 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.931 5.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X34Y454 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.244 5.976 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/O net (fo=5, routed) 0.229 6.205 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X35Y454 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.244 6.449 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__38/O net (fo=7, routed) 0.309 6.758 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X34Y454 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.954 10.647 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X34Y454 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.202 10.849 clock uncertainty -0.035 10.814 SLICE_X34Y454 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 10.759 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 10.759 arrival time -6.758 ------------------------------------------------------------------- slack 4.001 Slack (MET) : 4.001ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 4.041ns (logic 1.572ns (38.901%) route 2.469ns (61.099%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.185ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.330ns = ( 10.647 - 8.317 ) Source Clock Delay (SCD): 2.717ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.292ns (routing 0.775ns, distribution 1.517ns) Clock Net Delay (Destination): 1.954ns (routing 0.697ns, distribution 1.257ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.292 2.717 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.801 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.931 5.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X34Y454 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.244 5.976 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/O net (fo=5, routed) 0.229 6.205 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X35Y454 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.244 6.449 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__38/O net (fo=7, routed) 0.309 6.758 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X34Y454 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.954 10.647 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X34Y454 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.202 10.849 clock uncertainty -0.035 10.814 SLICE_X34Y454 FDRE (Setup_BFF2_SLICEM_C_CE) -0.055 10.759 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 10.759 arrival time -6.758 ------------------------------------------------------------------- slack 4.001 Slack (MET) : 4.001ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 4.041ns (logic 1.572ns (38.901%) route 2.469ns (61.099%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.185ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.330ns = ( 10.647 - 8.317 ) Source Clock Delay (SCD): 2.717ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.292ns (routing 0.775ns, distribution 1.517ns) Clock Net Delay (Destination): 1.954ns (routing 0.697ns, distribution 1.257ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.292 2.717 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.801 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.931 5.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X34Y454 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.244 5.976 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/O net (fo=5, routed) 0.229 6.205 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X35Y454 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.244 6.449 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__38/O net (fo=7, routed) 0.309 6.758 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X34Y454 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.954 10.647 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X34Y454 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.202 10.849 clock uncertainty -0.035 10.814 SLICE_X34Y454 FDRE (Setup_AFF2_SLICEM_C_CE) -0.055 10.759 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 10.759 arrival time -6.758 ------------------------------------------------------------------- slack 4.001 Slack (MET) : 4.005ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 4.038ns (logic 1.572ns (38.930%) route 2.466ns (61.070%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.185ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.330ns = ( 10.647 - 8.317 ) Source Clock Delay (SCD): 2.717ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.292ns (routing 0.775ns, distribution 1.517ns) Clock Net Delay (Destination): 1.954ns (routing 0.697ns, distribution 1.257ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.292 2.717 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.801 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.931 5.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X34Y454 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.244 5.976 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/O net (fo=5, routed) 0.229 6.205 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X35Y454 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.244 6.449 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__38/O net (fo=7, routed) 0.306 6.755 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X34Y454 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.954 10.647 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X34Y454 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.202 10.849 clock uncertainty -0.035 10.814 SLICE_X34Y454 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 10.760 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 10.760 arrival time -6.755 ------------------------------------------------------------------- slack 4.005 Slack (MET) : 4.005ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 4.038ns (logic 1.572ns (38.930%) route 2.466ns (61.070%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.185ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.330ns = ( 10.647 - 8.317 ) Source Clock Delay (SCD): 2.717ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.292ns (routing 0.775ns, distribution 1.517ns) Clock Net Delay (Destination): 1.954ns (routing 0.697ns, distribution 1.257ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.292 2.717 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.801 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.931 5.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X34Y454 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.244 5.976 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/O net (fo=5, routed) 0.229 6.205 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X35Y454 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.244 6.449 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__38/O net (fo=7, routed) 0.306 6.755 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X34Y454 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.954 10.647 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X34Y454 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.202 10.849 clock uncertainty -0.035 10.814 SLICE_X34Y454 FDRE (Setup_BFF_SLICEM_C_CE) -0.054 10.760 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 10.760 arrival time -6.755 ------------------------------------------------------------------- slack 4.005 Slack (MET) : 4.005ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 4.038ns (logic 1.572ns (38.930%) route 2.466ns (61.070%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.185ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.330ns = ( 10.647 - 8.317 ) Source Clock Delay (SCD): 2.717ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.292ns (routing 0.775ns, distribution 1.517ns) Clock Net Delay (Destination): 1.954ns (routing 0.697ns, distribution 1.257ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.292 2.717 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.801 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.931 5.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X34Y454 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.244 5.976 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/O net (fo=5, routed) 0.229 6.205 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X35Y454 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.244 6.449 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__38/O net (fo=7, routed) 0.306 6.755 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X34Y454 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.954 10.647 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X34Y454 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.202 10.849 clock uncertainty -0.035 10.814 SLICE_X34Y454 FDRE (Setup_AFF_SLICEM_C_CE) -0.054 10.760 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 10.760 arrival time -6.755 ------------------------------------------------------------------- slack 4.005 Slack (MET) : 4.013ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 4.027ns (logic 1.572ns (39.037%) route 2.455ns (60.964%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.187ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.328ns = ( 10.645 - 8.317 ) Source Clock Delay (SCD): 2.717ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.292ns (routing 0.775ns, distribution 1.517ns) Clock Net Delay (Destination): 1.952ns (routing 0.697ns, distribution 1.255ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.292 2.717 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.801 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.931 5.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X34Y454 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.244 5.976 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/O net (fo=5, routed) 0.229 6.205 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X35Y454 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.244 6.449 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__38/O net (fo=7, routed) 0.295 6.744 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X34Y454 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.952 10.645 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X34Y454 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.202 10.847 clock uncertainty -0.035 10.812 SLICE_X34Y454 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 10.757 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 10.757 arrival time -6.744 ------------------------------------------------------------------- slack 4.013 Slack (MET) : 4.096ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 3.943ns (logic 1.417ns (35.937%) route 2.526ns (64.063%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.188ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.327ns = ( 10.644 - 8.317 ) Source Clock Delay (SCD): 2.717ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.292ns (routing 0.775ns, distribution 1.517ns) Clock Net Delay (Destination): 1.951ns (routing 0.697ns, distribution 1.254ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.292 2.717 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.801 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.931 5.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X34Y454 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.244 5.976 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/O net (fo=5, routed) 0.166 6.142 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X34Y453 LUT6 (Prop_A6LUT_SLICEM_I0_O) 0.089 6.231 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__38/O net (fo=5, routed) 0.429 6.660 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecCorrectHeaders0 SLICE_X34Y452 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.951 10.644 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X34Y452 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.202 10.846 clock uncertainty -0.035 10.811 SLICE_X34Y452 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 10.756 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 10.756 arrival time -6.660 ------------------------------------------------------------------- slack 4.096 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.186ns (logic 0.095ns (51.075%) route 0.091ns (48.925%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.224ns Source Clock Delay (SCD): 0.988ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.872ns (routing 0.369ns, distribution 0.503ns) Clock Net Delay (Destination): 1.072ns (routing 0.431ns, distribution 0.641ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.872 0.988 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X36Y466 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y466 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.037 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Q net (fo=2, routed) 0.075 1.112 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_21_in SLICE_X37Y466 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.046 1.158 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__37/O net (fo=1, routed) 0.016 1.174 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[11] SLICE_X37Y466 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.072 1.224 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X37Y466 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C clock pessimism -0.142 1.082 SLICE_X37Y466 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.138 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11] ------------------------------------------------------------------- required time -1.138 arrival time 1.174 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.037ns (arrival time - required time) Source: SFP_GEN[38].rx_data_ngccm_reg[38][64]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[64]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.150ns (logic 0.101ns (67.333%) route 0.049ns (32.667%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.057ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.226ns Source Clock Delay (SCD): 0.998ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.882ns (routing 0.369ns, distribution 0.513ns) Clock Net Delay (Destination): 1.074ns (routing 0.431ns, distribution 0.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.882 0.998 g_gbt_bank[3].gbtbank_n_44 SLICE_X37Y471 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][64]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y471 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.047 r SFP_GEN[38].rx_data_ngccm_reg[38][64]/Q net (fo=1, routed) 0.033 1.080 SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[83]_0[56] SLICE_X37Y470 LUT3 (Prop_C6LUT_SLICEM_I1_O) 0.052 1.132 r SFP_GEN[38].ngCCM_gbt/RX_Word_rx40[64]_i_1/O net (fo=1, routed) 0.016 1.148 SFP_GEN[38].ngCCM_gbt/RX_Word_rx40[64]_i_1_n_0 SLICE_X37Y470 FDCE r SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[64]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.074 1.226 SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X37Y470 FDCE r SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[64]/C clock pessimism -0.171 1.055 SLICE_X37Y470 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.111 SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[64] ------------------------------------------------------------------- required time -1.111 arrival time 1.148 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.148ns (logic 0.063ns (42.568%) route 0.085ns (57.432%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.051ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.216ns Source Clock Delay (SCD): 0.993ns Clock Pessimism Removal (CPR): 0.172ns Clock Net Delay (Source): 0.877ns (routing 0.369ns, distribution 0.508ns) Clock Net Delay (Destination): 1.064ns (routing 0.431ns, distribution 0.633ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.877 0.993 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X37Y458 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y458 FDCE (Prop_EFF2_SLICEM_C_Q) 0.048 1.041 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.073 1.114 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/feedbackRegister[1] SLICE_X37Y457 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.015 1.129 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[20]_i_2__37/O net (fo=1, routed) 0.012 1.141 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[1] SLICE_X37Y457 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.064 1.216 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X37Y457 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C clock pessimism -0.172 1.044 SLICE_X37Y457 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.100 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20] ------------------------------------------------------------------- required time -1.100 arrival time 1.141 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].rx_data_ngccm_reg[38][70]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.048ns (32.215%) route 0.101ns (67.785%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.224ns Source Clock Delay (SCD): 1.000ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.884ns (routing 0.369ns, distribution 0.515ns) Clock Net Delay (Destination): 1.072ns (routing 0.431ns, distribution 0.641ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.884 1.000 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X37Y468 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y468 FDRE (Prop_HFF2_SLICEM_C_Q) 0.048 1.048 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/Q net (fo=1, routed) 0.101 1.149 rx_data[38][70] SLICE_X37Y469 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][70]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.072 1.224 g_gbt_bank[3].gbtbank_n_44 SLICE_X37Y469 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][70]/C clock pessimism -0.171 1.053 SLICE_X37Y469 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.108 SFP_GEN[38].rx_data_ngccm_reg[38][70] ------------------------------------------------------------------- required time -1.108 arrival time 1.149 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.193ns (logic 0.106ns (54.922%) route 0.087ns (45.078%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.224ns Source Clock Delay (SCD): 0.988ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.872ns (routing 0.369ns, distribution 0.503ns) Clock Net Delay (Destination): 1.072ns (routing 0.431ns, distribution 0.641ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.872 0.988 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X36Y466 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y466 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.037 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Q net (fo=2, routed) 0.075 1.112 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_21_in SLICE_X37Y466 LUT3 (Prop_D5LUT_SLICEM_I2_O) 0.057 1.169 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[9]_i_1__37/O net (fo=1, routed) 0.012 1.181 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[9] SLICE_X37Y466 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.072 1.224 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X37Y466 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C clock pessimism -0.142 1.082 SLICE_X37Y466 FDRE (Hold_DFF2_SLICEM_C_D) 0.056 1.138 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9] ------------------------------------------------------------------- required time -1.138 arrival time 1.181 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.044ns (arrival time - required time) Source: SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[34]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.171ns (logic 0.048ns (28.070%) route 0.123ns (71.930%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.194ns Source Clock Delay (SCD): 0.980ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.864ns (routing 0.369ns, distribution 0.495ns) Clock Net Delay (Destination): 1.042ns (routing 0.431ns, distribution 0.611ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.864 0.980 SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y456 FDCE r SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[34]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y456 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.028 r SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[34]/Q net (fo=1, routed) 0.123 1.151 SFP_GEN[38].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]_0[5] SLICE_X42Y456 FDRE r SFP_GEN[38].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.042 1.194 SFP_GEN[38].ngCCM_gbt/CrossClock_DV_cnt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y456 FDRE r SFP_GEN[38].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C clock pessimism -0.143 1.051 SLICE_X42Y456 FDRE (Hold_AFF2_SLICEM_C_D) 0.056 1.107 SFP_GEN[38].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34] ------------------------------------------------------------------- required time -1.107 arrival time 1.151 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.044ns (arrival time - required time) Source: SFP_GEN[38].rx_data_ngccm_reg[38][38]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[38]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.170ns (logic 0.086ns (50.588%) route 0.084ns (49.412%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.192ns Source Clock Delay (SCD): 0.979ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.863ns (routing 0.369ns, distribution 0.494ns) Clock Net Delay (Destination): 1.040ns (routing 0.431ns, distribution 0.609ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.863 0.979 g_gbt_bank[3].gbtbank_n_44 SLICE_X40Y456 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][38]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y456 FDCE (Prop_HFF_SLICEL_C_Q) 0.048 1.027 r SFP_GEN[38].rx_data_ngccm_reg[38][38]/Q net (fo=1, routed) 0.071 1.098 SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[83]_0[30] SLICE_X41Y456 LUT3 (Prop_G5LUT_SLICEM_I1_O) 0.038 1.136 r SFP_GEN[38].ngCCM_gbt/RX_Word_rx40[38]_i_1/O net (fo=1, routed) 0.013 1.149 SFP_GEN[38].ngCCM_gbt/RX_Word_rx40[38]_i_1_n_0 SLICE_X41Y456 FDCE r SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[38]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.040 1.192 SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y456 FDCE r SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[38]/C clock pessimism -0.143 1.049 SLICE_X41Y456 FDCE (Hold_GFF2_SLICEM_C_D) 0.056 1.105 SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[38] ------------------------------------------------------------------- required time -1.105 arrival time 1.149 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.192ns (logic 0.096ns (50.000%) route 0.096ns (50.000%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.214ns Source Clock Delay (SCD): 0.981ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.865ns (routing 0.369ns, distribution 0.496ns) Clock Net Delay (Destination): 1.062ns (routing 0.431ns, distribution 0.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.865 0.981 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X36Y457 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y457 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.030 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/Q net (fo=2, routed) 0.080 1.110 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_9_in SLICE_X37Y457 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.047 1.157 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__37/O net (fo=1, routed) 0.016 1.173 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[5] SLICE_X37Y457 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.062 1.214 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X37Y457 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism -0.142 1.072 SLICE_X37Y457 FDRE (Hold_HFF_SLICEM_C_D) 0.056 1.128 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time -1.128 arrival time 1.173 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.103ns (66.883%) route 0.051ns (33.117%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.225ns Source Clock Delay (SCD): 1.001ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.885ns (routing 0.369ns, distribution 0.516ns) Clock Net Delay (Destination): 1.073ns (routing 0.431ns, distribution 0.642ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.885 1.001 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X37Y468 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y468 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.050 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Q net (fo=2, routed) 0.035 1.085 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_21_in SLICE_X37Y467 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.054 1.139 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__37/O net (fo=1, routed) 0.016 1.155 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[11] SLICE_X37Y467 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.073 1.225 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X37Y467 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C clock pessimism -0.171 1.054 SLICE_X37Y467 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.110 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11] ------------------------------------------------------------------- required time -1.110 arrival time 1.155 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[38]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.048ns (27.746%) route 0.125ns (72.254%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.194ns Source Clock Delay (SCD): 0.980ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.864ns (routing 0.369ns, distribution 0.495ns) Clock Net Delay (Destination): 1.042ns (routing 0.431ns, distribution 0.611ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.864 0.980 SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y456 FDCE r SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[38]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y456 FDCE (Prop_GFF2_SLICEM_C_Q) 0.048 1.028 r SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[38]/Q net (fo=3, routed) 0.125 1.153 SFP_GEN[38].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]_0[7] SLICE_X42Y456 FDRE r SFP_GEN[38].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.042 1.194 SFP_GEN[38].ngCCM_gbt/CrossClock_DV_cnt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y456 FDRE r SFP_GEN[38].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C clock pessimism -0.143 1.051 SLICE_X42Y456 FDRE (Hold_BFF2_SLICEM_C_D) 0.056 1.107 SFP_GEN[38].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38] ------------------------------------------------------------------- required time -1.107 arrival time 1.153 ------------------------------------------------------------------- slack 0.046 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_40 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y185 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y420 g_clock_rate_din[38].ngccm_status_cnt_reg[38][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y420 g_clock_rate_din[38].ngccm_status_cnt_reg[38][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y420 g_clock_rate_din[38].ngccm_status_cnt_reg[38][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y420 g_clock_rate_din[38].ngccm_status_cnt_reg[38][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y420 g_clock_rate_din[38].ngccm_status_cnt_reg[38][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y420 g_clock_rate_din[38].ngccm_status_cnt_reg[38][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y420 g_clock_rate_din[38].ngccm_status_cnt_reg[38][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X39Y459 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X39Y459 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X38Y459 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X38Y459 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X38Y459 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X38Y459 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X56Y421 g_clock_rate_din[38].ngccm_status_cnt_reg[38][7]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X43Y421 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X43Y421 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X43Y420 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X43Y420 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X43Y421 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_41 To Clock: gtwiz_userclk_rx_srcclk_out[0]_41 Setup : 0 Failing Endpoints, Worst Slack 3.176ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.033ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.176ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 4.939ns (logic 1.729ns (35.007%) route 3.210ns (64.993%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.112ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.711ns = ( 11.028 - 8.317 ) Source Clock Delay (SCD): 3.044ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.619ns (routing 1.081ns, distribution 1.538ns) Clock Net Delay (Destination): 2.335ns (routing 0.984ns, distribution 1.351ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.619 3.044 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 4.128 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.190 6.318 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X44Y448 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 6.562 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__38/O net (fo=5, routed) 0.328 6.890 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X45Y450 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.235 7.125 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__38/O net (fo=1, routed) 0.078 7.203 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__38_n_0 SLICE_X45Y450 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.166 7.369 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__38/O net (fo=2, routed) 0.614 7.983 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__38_n_0 SLICE_X44Y450 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.335 11.028 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X44Y450 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.221 11.249 clock uncertainty -0.035 11.214 SLICE_X44Y450 FDCE (Setup_GFF_SLICEM_C_CE) -0.055 11.159 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.159 arrival time -7.983 ------------------------------------------------------------------- slack 3.176 Slack (MET) : 3.176ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 4.939ns (logic 1.729ns (35.007%) route 3.210ns (64.993%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.112ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.711ns = ( 11.028 - 8.317 ) Source Clock Delay (SCD): 3.044ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.619ns (routing 1.081ns, distribution 1.538ns) Clock Net Delay (Destination): 2.335ns (routing 0.984ns, distribution 1.351ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.619 3.044 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 4.128 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.190 6.318 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X44Y448 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 6.562 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__38/O net (fo=5, routed) 0.328 6.890 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X45Y450 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.235 7.125 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__38/O net (fo=1, routed) 0.078 7.203 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__38_n_0 SLICE_X45Y450 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.166 7.369 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__38/O net (fo=2, routed) 0.614 7.983 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__38_n_0 SLICE_X44Y450 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.335 11.028 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X44Y450 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.221 11.249 clock uncertainty -0.035 11.214 SLICE_X44Y450 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 11.159 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.159 arrival time -7.983 ------------------------------------------------------------------- slack 3.176 Slack (MET) : 3.415ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 4.952ns (logic 0.400ns (8.078%) route 4.552ns (91.922%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.999ns = ( 11.316 - 8.317 ) Source Clock Delay (SCD): 3.088ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.663ns (routing 1.081ns, distribution 1.582ns) Clock Net Delay (Destination): 2.623ns (routing 0.984ns, distribution 1.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.663 3.088 g_gbt_bank[3].gbtbank/CLK SLICE_X45Y446 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C ------------------------------------------------------------------- ------------------- SLICE_X45Y446 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 3.228 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Q net (fo=137, routed) 2.422 5.650 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X43Y441 LUT2 (Prop_D5LUT_SLICEL_I1_O) 0.260 5.910 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__38/O net (fo=76, routed) 2.130 8.040 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X50Y446 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.623 11.316 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X50Y446 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C clock pessimism 0.229 11.545 clock uncertainty -0.035 11.510 SLICE_X50Y446 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 11.455 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2] ------------------------------------------------------------------- required time 11.455 arrival time -8.040 ------------------------------------------------------------------- slack 3.415 Slack (MET) : 3.415ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 4.952ns (logic 0.400ns (8.078%) route 4.552ns (91.922%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.999ns = ( 11.316 - 8.317 ) Source Clock Delay (SCD): 3.088ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.663ns (routing 1.081ns, distribution 1.582ns) Clock Net Delay (Destination): 2.623ns (routing 0.984ns, distribution 1.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.663 3.088 g_gbt_bank[3].gbtbank/CLK SLICE_X45Y446 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C ------------------------------------------------------------------- ------------------- SLICE_X45Y446 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 3.228 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Q net (fo=137, routed) 2.422 5.650 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X43Y441 LUT2 (Prop_D5LUT_SLICEL_I1_O) 0.260 5.910 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__38/O net (fo=76, routed) 2.130 8.040 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X50Y446 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.623 11.316 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X50Y446 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C clock pessimism 0.229 11.545 clock uncertainty -0.035 11.510 SLICE_X50Y446 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 11.455 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6] ------------------------------------------------------------------- required time 11.455 arrival time -8.040 ------------------------------------------------------------------- slack 3.415 Slack (MET) : 3.420ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 4.948ns (logic 0.400ns (8.084%) route 4.548ns (91.916%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.999ns = ( 11.316 - 8.317 ) Source Clock Delay (SCD): 3.088ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.663ns (routing 1.081ns, distribution 1.582ns) Clock Net Delay (Destination): 2.623ns (routing 0.984ns, distribution 1.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.663 3.088 g_gbt_bank[3].gbtbank/CLK SLICE_X45Y446 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C ------------------------------------------------------------------- ------------------- SLICE_X45Y446 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 3.228 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Q net (fo=137, routed) 2.422 5.650 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X43Y441 LUT2 (Prop_D5LUT_SLICEL_I1_O) 0.260 5.910 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__38/O net (fo=76, routed) 2.126 8.036 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X50Y446 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.623 11.316 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X50Y446 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism 0.229 11.545 clock uncertainty -0.035 11.510 SLICE_X50Y446 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 11.456 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time 11.456 arrival time -8.036 ------------------------------------------------------------------- slack 3.420 Slack (MET) : 3.420ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 4.948ns (logic 0.400ns (8.084%) route 4.548ns (91.916%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.999ns = ( 11.316 - 8.317 ) Source Clock Delay (SCD): 3.088ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.663ns (routing 1.081ns, distribution 1.582ns) Clock Net Delay (Destination): 2.623ns (routing 0.984ns, distribution 1.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.663 3.088 g_gbt_bank[3].gbtbank/CLK SLICE_X45Y446 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C ------------------------------------------------------------------- ------------------- SLICE_X45Y446 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 3.228 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Q net (fo=137, routed) 2.422 5.650 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X43Y441 LUT2 (Prop_D5LUT_SLICEL_I1_O) 0.260 5.910 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__38/O net (fo=76, routed) 2.126 8.036 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X50Y446 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.623 11.316 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X50Y446 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism 0.229 11.545 clock uncertainty -0.035 11.510 SLICE_X50Y446 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 11.456 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time 11.456 arrival time -8.036 ------------------------------------------------------------------- slack 3.420 Slack (MET) : 3.532ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 4.835ns (logic 0.400ns (8.273%) route 4.435ns (91.727%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.002ns = ( 11.319 - 8.317 ) Source Clock Delay (SCD): 3.088ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.663ns (routing 1.081ns, distribution 1.582ns) Clock Net Delay (Destination): 2.626ns (routing 0.984ns, distribution 1.642ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.663 3.088 g_gbt_bank[3].gbtbank/CLK SLICE_X45Y446 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C ------------------------------------------------------------------- ------------------- SLICE_X45Y446 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 3.228 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Q net (fo=137, routed) 2.422 5.650 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X43Y441 LUT2 (Prop_D5LUT_SLICEL_I1_O) 0.260 5.910 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__38/O net (fo=76, routed) 2.013 7.923 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X49Y446 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.626 11.319 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X49Y446 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C clock pessimism 0.229 11.548 clock uncertainty -0.035 11.513 SLICE_X49Y446 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 11.455 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3] ------------------------------------------------------------------- required time 11.455 arrival time -7.923 ------------------------------------------------------------------- slack 3.532 Slack (MET) : 3.532ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 4.835ns (logic 0.400ns (8.273%) route 4.435ns (91.727%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.002ns = ( 11.319 - 8.317 ) Source Clock Delay (SCD): 3.088ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.663ns (routing 1.081ns, distribution 1.582ns) Clock Net Delay (Destination): 2.626ns (routing 0.984ns, distribution 1.642ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.663 3.088 g_gbt_bank[3].gbtbank/CLK SLICE_X45Y446 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C ------------------------------------------------------------------- ------------------- SLICE_X45Y446 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 3.228 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Q net (fo=137, routed) 2.422 5.650 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X43Y441 LUT2 (Prop_D5LUT_SLICEL_I1_O) 0.260 5.910 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__38/O net (fo=76, routed) 2.013 7.923 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X49Y446 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.626 11.319 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X49Y446 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C clock pessimism 0.229 11.548 clock uncertainty -0.035 11.513 SLICE_X49Y446 FDRE (Setup_GFF2_SLICEM_C_CE) -0.058 11.455 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7] ------------------------------------------------------------------- required time 11.455 arrival time -7.923 ------------------------------------------------------------------- slack 3.532 Slack (MET) : 3.538ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 4.832ns (logic 0.400ns (8.278%) route 4.432ns (91.722%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.002ns = ( 11.319 - 8.317 ) Source Clock Delay (SCD): 3.088ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.663ns (routing 1.081ns, distribution 1.582ns) Clock Net Delay (Destination): 2.626ns (routing 0.984ns, distribution 1.642ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.663 3.088 g_gbt_bank[3].gbtbank/CLK SLICE_X45Y446 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C ------------------------------------------------------------------- ------------------- SLICE_X45Y446 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 3.228 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Q net (fo=137, routed) 2.422 5.650 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X43Y441 LUT2 (Prop_D5LUT_SLICEL_I1_O) 0.260 5.910 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__38/O net (fo=76, routed) 2.010 7.920 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X49Y446 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.626 11.319 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X49Y446 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism 0.229 11.548 clock uncertainty -0.035 11.513 SLICE_X49Y446 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 11.458 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time 11.458 arrival time -7.920 ------------------------------------------------------------------- slack 3.538 Slack (MET) : 3.538ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 4.832ns (logic 0.400ns (8.278%) route 4.432ns (91.722%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.002ns = ( 11.319 - 8.317 ) Source Clock Delay (SCD): 3.088ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.663ns (routing 1.081ns, distribution 1.582ns) Clock Net Delay (Destination): 2.626ns (routing 0.984ns, distribution 1.642ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.663 3.088 g_gbt_bank[3].gbtbank/CLK SLICE_X45Y446 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C ------------------------------------------------------------------- ------------------- SLICE_X45Y446 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 3.228 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Q net (fo=137, routed) 2.422 5.650 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X43Y441 LUT2 (Prop_D5LUT_SLICEL_I1_O) 0.260 5.910 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__38/O net (fo=76, routed) 2.010 7.920 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X49Y446 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.626 11.319 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X49Y446 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism 0.229 11.548 clock uncertainty -0.035 11.513 SLICE_X49Y446 FDRE (Setup_GFF_SLICEM_C_CE) -0.055 11.458 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time 11.458 arrival time -7.920 ------------------------------------------------------------------- slack 3.538 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.033ns (arrival time - required time) Source: SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[34]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.048ns (33.103%) route 0.097ns (66.897%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.513ns Source Clock Delay (SCD): 1.263ns Clock Pessimism Removal (CPR): 0.194ns Clock Net Delay (Source): 1.147ns (routing 0.463ns, distribution 0.684ns) Clock Net Delay (Destination): 1.361ns (routing 0.528ns, distribution 0.833ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.147 1.263 SFP_GEN[39].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X50Y444 FDCE r SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[34]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y444 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.311 r SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[34]/Q net (fo=1, routed) 0.097 1.408 SFP_GEN[39].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]_0[5] SLICE_X50Y442 FDRE r SFP_GEN[39].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.361 1.513 SFP_GEN[39].ngCCM_gbt/CrossClock_DV_cnt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X50Y442 FDRE r SFP_GEN[39].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C clock pessimism -0.194 1.319 SLICE_X50Y442 FDRE (Hold_CFF2_SLICEL_C_D) 0.056 1.375 SFP_GEN[39].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34] ------------------------------------------------------------------- required time -1.375 arrival time 1.408 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.033ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.182ns (logic 0.081ns (44.506%) route 0.101ns (55.495%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.093ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.380ns Source Clock Delay (SCD): 1.142ns Clock Pessimism Removal (CPR): 0.145ns Clock Net Delay (Source): 1.026ns (routing 0.463ns, distribution 0.563ns) Clock Net Delay (Destination): 1.228ns (routing 0.528ns, distribution 0.700ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.026 1.142 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X41Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y441 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.191 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.085 1.276 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in SLICE_X42Y441 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.032 1.308 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__38/O net (fo=1, routed) 0.016 1.324 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] SLICE_X42Y441 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.228 1.380 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X42Y441 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.145 1.235 SLICE_X42Y441 FDRE (Hold_HFF_SLICEM_C_D) 0.056 1.291 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.291 arrival time 1.324 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.034ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].rx_data_ngccm_reg[39][83]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.174ns (logic 0.048ns (27.586%) route 0.126ns (72.414%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.381ns Source Clock Delay (SCD): 1.152ns Clock Pessimism Removal (CPR): 0.145ns Clock Net Delay (Source): 1.036ns (routing 0.463ns, distribution 0.573ns) Clock Net Delay (Destination): 1.229ns (routing 0.528ns, distribution 0.701ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.036 1.152 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X42Y440 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y440 FDRE (Prop_GFF_SLICEM_C_Q) 0.048 1.200 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/Q net (fo=1, routed) 0.126 1.326 rx_data[39][83] SLICE_X44Y440 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][83]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.229 1.381 g_gbt_bank[3].gbtbank_n_54 SLICE_X44Y440 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][83]/C clock pessimism -0.145 1.236 SLICE_X44Y440 FDCE (Hold_FFF_SLICEM_C_D) 0.056 1.292 SFP_GEN[39].rx_data_ngccm_reg[39][83] ------------------------------------------------------------------- required time -1.292 arrival time 1.326 ------------------------------------------------------------------- slack 0.034 Slack (MET) : 0.038ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].rx_data_ngccm_reg[39][66]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.160ns (logic 0.048ns (30.000%) route 0.112ns (70.000%)) Logic Levels: 0 Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.365ns Source Clock Delay (SCD): 1.153ns Clock Pessimism Removal (CPR): 0.145ns Clock Net Delay (Source): 1.037ns (routing 0.463ns, distribution 0.574ns) Clock Net Delay (Destination): 1.213ns (routing 0.528ns, distribution 0.685ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.037 1.153 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X42Y440 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y440 FDRE (Prop_BFF2_SLICEM_C_Q) 0.048 1.201 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/Q net (fo=1, routed) 0.112 1.313 rx_data[39][66] SLICE_X41Y440 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][66]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.213 1.365 g_gbt_bank[3].gbtbank_n_54 SLICE_X41Y440 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][66]/C clock pessimism -0.145 1.220 SLICE_X41Y440 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.275 SFP_GEN[39].rx_data_ngccm_reg[39][66] ------------------------------------------------------------------- required time -1.275 arrival time 1.313 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.064ns (44.444%) route 0.080ns (55.556%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.048ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.383ns Source Clock Delay (SCD): 1.154ns Clock Pessimism Removal (CPR): 0.181ns Clock Net Delay (Source): 1.038ns (routing 0.463ns, distribution 0.575ns) Clock Net Delay (Destination): 1.231ns (routing 0.528ns, distribution 0.703ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.038 1.154 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X42Y439 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y439 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.203 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.068 1.271 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/O85[0] SLICE_X42Y440 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.015 1.286 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__38/O net (fo=1, routed) 0.012 1.298 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/I9[0] SLICE_X42Y440 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.231 1.383 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X42Y440 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C clock pessimism -0.181 1.202 SLICE_X42Y440 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.258 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19] ------------------------------------------------------------------- required time -1.258 arrival time 1.298 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.041ns (arrival time - required time) Source: SFP_GEN[39].rx_data_ngccm_reg[39][77]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[76]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.181ns (logic 0.094ns (51.934%) route 0.087ns (48.066%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.380ns Source Clock Delay (SCD): 1.151ns Clock Pessimism Removal (CPR): 0.145ns Clock Net Delay (Source): 1.035ns (routing 0.463ns, distribution 0.572ns) Clock Net Delay (Destination): 1.228ns (routing 0.528ns, distribution 0.700ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.035 1.151 g_gbt_bank[3].gbtbank_n_54 SLICE_X43Y441 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][77]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y441 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 1.200 r SFP_GEN[39].rx_data_ngccm_reg[39][77]/Q net (fo=1, routed) 0.073 1.273 SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[83]_0[69] SLICE_X44Y441 LUT3 (Prop_G6LUT_SLICEM_I0_O) 0.045 1.318 r SFP_GEN[39].ngCCM_gbt/RX_Word_rx40[76]_i_1/O net (fo=1, routed) 0.014 1.332 SFP_GEN[39].ngCCM_gbt/RX_Word_rx40[76]_i_1_n_0 SLICE_X44Y441 FDCE r SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[76]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.228 1.380 SFP_GEN[39].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X44Y441 FDCE r SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[76]/C clock pessimism -0.145 1.235 SLICE_X44Y441 FDCE (Hold_GFF_SLICEM_C_D) 0.056 1.291 SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[76] ------------------------------------------------------------------- required time -1.291 arrival time 1.332 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.190ns (logic 0.104ns (54.737%) route 0.086ns (45.263%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.092ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.379ns Source Clock Delay (SCD): 1.142ns Clock Pessimism Removal (CPR): 0.145ns Clock Net Delay (Source): 1.026ns (routing 0.463ns, distribution 0.563ns) Clock Net Delay (Destination): 1.227ns (routing 0.528ns, distribution 0.699ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.026 1.142 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X41Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y441 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.191 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.075 1.266 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in SLICE_X40Y441 LUT3 (Prop_C5LUT_SLICEL_I2_O) 0.055 1.321 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__38/O net (fo=1, routed) 0.011 1.332 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[15] SLICE_X40Y441 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.227 1.379 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X40Y441 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C clock pessimism -0.145 1.234 SLICE_X40Y441 FDRE (Hold_CFF2_SLICEL_C_D) 0.056 1.290 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15] ------------------------------------------------------------------- required time -1.290 arrival time 1.332 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[28]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.180ns (logic 0.080ns (44.444%) route 0.100ns (55.556%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.366ns Source Clock Delay (SCD): 1.139ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 1.023ns (routing 0.463ns, distribution 0.560ns) Clock Net Delay (Destination): 1.214ns (routing 0.528ns, distribution 0.686ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.023 1.139 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X46Y445 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X46Y445 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 1.188 f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Q net (fo=27, routed) 0.084 1.272 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] SLICE_X47Y445 LUT5 (Prop_D6LUT_SLICEM_I1_O) 0.031 1.303 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[28]_i_1__46/O net (fo=1, routed) 0.016 1.319 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg00[28] SLICE_X47Y445 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[28]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.214 1.366 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X47Y445 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[28]/C clock pessimism -0.146 1.220 SLICE_X47Y445 FDCE (Hold_DFF_SLICEM_C_D) 0.056 1.276 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[28] ------------------------------------------------------------------- required time -1.276 arrival time 1.319 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.507ns Source Clock Delay (SCD): 1.261ns Clock Pessimism Removal (CPR): 0.202ns Clock Net Delay (Source): 1.145ns (routing 0.463ns, distribution 0.682ns) Clock Net Delay (Destination): 1.355ns (routing 0.528ns, distribution 0.827ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.145 1.261 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X50Y446 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y446 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.310 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Q net (fo=2, routed) 0.034 1.344 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_11_in SLICE_X50Y446 LUT3 (Prop_C6LUT_SLICEL_I2_O) 0.045 1.389 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__38/O net (fo=1, routed) 0.016 1.405 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[4] SLICE_X50Y446 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.355 1.507 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X50Y446 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.202 1.305 SLICE_X50Y446 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.361 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.361 arrival time 1.405 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].rx_data_ngccm_reg[39][76]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.049ns (34.266%) route 0.094ns (65.734%)) Logic Levels: 0 Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.383ns Source Clock Delay (SCD): 1.151ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 1.035ns (routing 0.463ns, distribution 0.572ns) Clock Net Delay (Destination): 1.231ns (routing 0.528ns, distribution 0.703ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.035 1.151 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X42Y441 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y441 FDRE (Prop_FFF_SLICEM_C_Q) 0.049 1.200 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/Q net (fo=1, routed) 0.094 1.294 rx_data[39][76] SLICE_X43Y441 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][76]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.231 1.383 g_gbt_bank[3].gbtbank_n_54 SLICE_X43Y441 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][76]/C clock pessimism -0.190 1.193 SLICE_X43Y441 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 1.249 SFP_GEN[39].rx_data_ngccm_reg[39][76] ------------------------------------------------------------------- required time -1.249 arrival time 1.294 ------------------------------------------------------------------- slack 0.045 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_41 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y168 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y406 g_clock_rate_din[39].ngccm_status_cnt_reg[39][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y406 g_clock_rate_din[39].ngccm_status_cnt_reg[39][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y407 g_clock_rate_din[39].ngccm_status_cnt_reg[39][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y407 g_clock_rate_din[39].ngccm_status_cnt_reg[39][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y407 g_clock_rate_din[39].ngccm_status_cnt_reg[39][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y407 g_clock_rate_din[39].ngccm_status_cnt_reg[39][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y406 g_clock_rate_din[39].ngccm_status_cnt_reg[39][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X41Y440 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X50Y445 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X48Y442 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X48Y442 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X48Y442 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X48Y442 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X46Y446 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X46Y446 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X45Y446 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X45Y446 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X45Y446 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X45Y446 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_42 To Clock: gtwiz_userclk_rx_srcclk_out[0]_42 Setup : 0 Failing Endpoints, Worst Slack 3.224ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.032ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.224ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 5.127ns (logic 1.689ns (32.943%) route 3.438ns (67.057%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.123ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.641ns = ( 10.958 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.265ns (routing 0.697ns, distribution 1.568ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.812 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.543 6.355 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X50Y490 LUT4 (Prop_C6LUT_SLICEL_I0_O) 0.219 6.574 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/O net (fo=5, routed) 0.211 6.785 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X48Y490 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 7.023 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__39/O net (fo=1, routed) 0.174 7.197 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__39_n_0 SLICE_X49Y490 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 7.343 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__39/O net (fo=2, routed) 0.510 7.853 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__39_n_0 SLICE_X50Y490 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.265 10.958 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK SLICE_X50Y490 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.208 11.167 clock uncertainty -0.035 11.131 SLICE_X50Y490 FDCE (Setup_BFF_SLICEL_C_CE) -0.054 11.077 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.077 arrival time -7.853 ------------------------------------------------------------------- slack 3.224 Slack (MET) : 3.224ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 5.127ns (logic 1.689ns (32.943%) route 3.438ns (67.057%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.123ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.641ns = ( 10.958 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.265ns (routing 0.697ns, distribution 1.568ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.812 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.543 6.355 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X50Y490 LUT4 (Prop_C6LUT_SLICEL_I0_O) 0.219 6.574 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/O net (fo=5, routed) 0.211 6.785 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X48Y490 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 7.023 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__39/O net (fo=1, routed) 0.174 7.197 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__39_n_0 SLICE_X49Y490 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 7.343 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__39/O net (fo=2, routed) 0.510 7.853 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__39_n_0 SLICE_X50Y490 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.265 10.958 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK SLICE_X50Y490 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.208 11.167 clock uncertainty -0.035 11.131 SLICE_X50Y490 FDCE (Setup_DFF_SLICEL_C_CE) -0.054 11.077 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.077 arrival time -7.853 ------------------------------------------------------------------- slack 3.224 Slack (MET) : 3.671ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 4.657ns (logic 1.550ns (33.283%) route 3.107ns (66.717%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.104ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.622ns = ( 10.939 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.246ns (routing 0.697ns, distribution 1.549ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.812 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.543 6.355 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X50Y490 LUT4 (Prop_C6LUT_SLICEL_I0_O) 0.219 6.574 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/O net (fo=5, routed) 0.201 6.775 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X49Y490 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.245 7.020 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/O net (fo=7, routed) 0.363 7.383 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X49Y489 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.246 10.939 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK SLICE_X49Y489 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.208 11.148 clock uncertainty -0.035 11.112 SLICE_X49Y489 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 11.054 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.054 arrival time -7.383 ------------------------------------------------------------------- slack 3.671 Slack (MET) : 3.677ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 4.654ns (logic 1.550ns (33.305%) route 3.104ns (66.695%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.104ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.622ns = ( 10.939 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.246ns (routing 0.697ns, distribution 1.549ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.812 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.543 6.355 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X50Y490 LUT4 (Prop_C6LUT_SLICEL_I0_O) 0.219 6.574 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/O net (fo=5, routed) 0.201 6.775 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X49Y490 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.245 7.020 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/O net (fo=7, routed) 0.360 7.380 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X49Y489 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.246 10.939 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK SLICE_X49Y489 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.208 11.148 clock uncertainty -0.035 11.112 SLICE_X49Y489 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 11.057 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.057 arrival time -7.380 ------------------------------------------------------------------- slack 3.677 Slack (MET) : 3.681ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 4.652ns (logic 1.550ns (33.319%) route 3.102ns (66.681%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.106ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.624ns = ( 10.941 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.248ns (routing 0.697ns, distribution 1.551ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.812 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.543 6.355 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X50Y490 LUT4 (Prop_C6LUT_SLICEL_I0_O) 0.219 6.574 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/O net (fo=5, routed) 0.201 6.775 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X49Y490 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.245 7.020 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/O net (fo=7, routed) 0.358 7.378 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X49Y489 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.248 10.941 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK SLICE_X49Y489 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.208 11.150 clock uncertainty -0.035 11.114 SLICE_X49Y489 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 11.059 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.059 arrival time -7.378 ------------------------------------------------------------------- slack 3.681 Slack (MET) : 3.685ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 4.649ns (logic 1.550ns (33.341%) route 3.099ns (66.660%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.106ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.624ns = ( 10.941 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.248ns (routing 0.697ns, distribution 1.551ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.812 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.543 6.355 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X50Y490 LUT4 (Prop_C6LUT_SLICEL_I0_O) 0.219 6.574 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/O net (fo=5, routed) 0.201 6.775 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X49Y490 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.245 7.020 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/O net (fo=7, routed) 0.355 7.375 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X49Y489 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.248 10.941 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK SLICE_X49Y489 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.208 11.150 clock uncertainty -0.035 11.114 SLICE_X49Y489 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 11.060 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 11.060 arrival time -7.375 ------------------------------------------------------------------- slack 3.685 Slack (MET) : 3.685ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 4.649ns (logic 1.550ns (33.341%) route 3.099ns (66.660%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.106ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.624ns = ( 10.941 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.248ns (routing 0.697ns, distribution 1.551ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.812 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.543 6.355 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X50Y490 LUT4 (Prop_C6LUT_SLICEL_I0_O) 0.219 6.574 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/O net (fo=5, routed) 0.201 6.775 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X49Y490 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.245 7.020 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/O net (fo=7, routed) 0.355 7.375 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X49Y489 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.248 10.941 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK SLICE_X49Y489 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.208 11.150 clock uncertainty -0.035 11.114 SLICE_X49Y489 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 11.060 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 11.060 arrival time -7.375 ------------------------------------------------------------------- slack 3.685 Slack (MET) : 3.721ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 4.622ns (logic 1.471ns (31.826%) route 3.151ns (68.174%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.637ns = ( 10.954 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.261ns (routing 0.697ns, distribution 1.564ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.812 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.543 6.355 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X50Y490 LUT4 (Prop_C6LUT_SLICEL_I0_O) 0.219 6.574 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/O net (fo=5, routed) 0.093 6.667 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X50Y490 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.166 6.833 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__40/O net (fo=3, routed) 0.515 7.348 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecFalseHeaders0 SLICE_X49Y491 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.261 10.954 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK SLICE_X49Y491 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.208 11.163 clock uncertainty -0.035 11.127 SLICE_X49Y491 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 11.069 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 11.069 arrival time -7.348 ------------------------------------------------------------------- slack 3.721 Slack (MET) : 3.727ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 4.619ns (logic 1.471ns (31.847%) route 3.148ns (68.153%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.637ns = ( 10.954 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.261ns (routing 0.697ns, distribution 1.564ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.812 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.543 6.355 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X50Y490 LUT4 (Prop_C6LUT_SLICEL_I0_O) 0.219 6.574 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/O net (fo=5, routed) 0.093 6.667 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X50Y490 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.166 6.833 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__40/O net (fo=3, routed) 0.512 7.345 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecFalseHeaders0 SLICE_X49Y491 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.261 10.954 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK SLICE_X49Y491 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.208 11.163 clock uncertainty -0.035 11.127 SLICE_X49Y491 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 11.072 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 11.072 arrival time -7.345 ------------------------------------------------------------------- slack 3.727 Slack (MET) : 3.727ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 4.619ns (logic 1.471ns (31.847%) route 3.148ns (68.153%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.637ns = ( 10.954 - 8.317 ) Source Clock Delay (SCD): 2.726ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.301ns (routing 0.775ns, distribution 1.526ns) Clock Net Delay (Destination): 2.261ns (routing 0.697ns, distribution 1.564ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.301 2.726 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.812 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.543 6.355 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X50Y490 LUT4 (Prop_C6LUT_SLICEL_I0_O) 0.219 6.574 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/O net (fo=5, routed) 0.093 6.667 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X50Y490 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.166 6.833 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__40/O net (fo=3, routed) 0.512 7.345 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecFalseHeaders0 SLICE_X49Y491 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.261 10.954 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK SLICE_X49Y491 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C clock pessimism 0.208 11.163 clock uncertainty -0.035 11.127 SLICE_X49Y491 FDRE (Setup_EFF_SLICEM_C_CE) -0.055 11.072 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2] ------------------------------------------------------------------- required time 11.072 arrival time -7.345 ------------------------------------------------------------------- slack 3.727 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.032ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.170ns (logic 0.079ns (46.471%) route 0.091ns (53.529%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.362ns Source Clock Delay (SCD): 1.123ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.007ns (routing 0.369ns, distribution 0.638ns) Clock Net Delay (Destination): 1.210ns (routing 0.431ns, distribution 0.779ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.123 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X57Y483 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y483 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 1.172 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.075 1.247 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_33_in SLICE_X58Y483 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.030 1.277 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__39/O net (fo=1, routed) 0.016 1.293 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[17] SLICE_X58Y483 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.210 1.362 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X58Y483 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.157 1.205 SLICE_X58Y483 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.261 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.261 arrival time 1.293 ------------------------------------------------------------------- slack 0.032 Slack (MET) : 0.033ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.063ns (42.282%) route 0.086ns (57.718%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.374ns Source Clock Delay (SCD): 1.124ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 1.008ns (routing 0.369ns, distribution 0.639ns) Clock Net Delay (Destination): 1.222ns (routing 0.431ns, distribution 0.791ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.124 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X56Y486 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y486 FDCE (Prop_EFF2_SLICEL_C_Q) 0.048 1.172 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.070 1.242 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/O84[0] SLICE_X56Y485 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.015 1.257 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__39/O net (fo=1, routed) 0.016 1.273 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[0] SLICE_X56Y485 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.222 1.374 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X56Y485 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C clock pessimism -0.190 1.184 SLICE_X56Y485 FDRE (Hold_HFF_SLICEL_C_D) 0.056 1.240 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19] ------------------------------------------------------------------- required time -1.240 arrival time 1.273 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.191ns (logic 0.105ns (54.974%) route 0.086ns (45.026%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.096ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.374ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.005ns (routing 0.369ns, distribution 0.636ns) Clock Net Delay (Destination): 1.222ns (routing 0.431ns, distribution 0.791ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.005 1.121 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X54Y491 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y491 FDCE (Prop_GFF2_SLICEL_C_Q) 0.048 1.169 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/Q net (fo=2, routed) 0.074 1.243 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_17_in SLICE_X55Y491 LUT3 (Prop_D5LUT_SLICEM_I0_O) 0.057 1.300 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[9]_i_1__39/O net (fo=1, routed) 0.012 1.312 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[9] SLICE_X55Y491 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.222 1.374 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X55Y491 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C clock pessimism -0.157 1.217 SLICE_X55Y491 FDRE (Hold_DFF2_SLICEM_C_D) 0.056 1.273 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9] ------------------------------------------------------------------- required time -1.273 arrival time 1.312 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.040ns (arrival time - required time) Source: SFP_GEN[40].ngCCM_gbt/pwr_good_pre_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_reg/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.103ns (66.883%) route 0.051ns (33.117%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.367ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.188ns Clock Net Delay (Source): 1.005ns (routing 0.369ns, distribution 0.636ns) Clock Net Delay (Destination): 1.215ns (routing 0.431ns, distribution 0.784ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.005 1.121 SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y483 FDCE r SFP_GEN[40].ngCCM_gbt/pwr_good_pre_reg/C ------------------------------------------------------------------- ------------------- SLICE_X59Y483 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.170 r SFP_GEN[40].ngCCM_gbt/pwr_good_pre_reg/Q net (fo=1, routed) 0.035 1.205 SFP_GEN[40].ngCCM_gbt/pwr_good_pre SLICE_X59Y482 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.054 1.259 r SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_i_1__12/O net (fo=1, routed) 0.016 1.275 SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_i_1__12_n_0 SLICE_X59Y482 FDRE r SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.215 1.367 SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y482 FDRE r SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_reg/C clock pessimism -0.188 1.179 SLICE_X59Y482 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.235 SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_reg ------------------------------------------------------------------- required time -1.235 arrival time 1.275 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.191ns (logic 0.104ns (54.450%) route 0.087ns (45.550%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.372ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.005ns (routing 0.369ns, distribution 0.636ns) Clock Net Delay (Destination): 1.220ns (routing 0.431ns, distribution 0.789ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.005 1.121 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X54Y491 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y491 FDCE (Prop_GFF2_SLICEL_C_Q) 0.048 1.169 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/Q net (fo=2, routed) 0.074 1.243 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_17_in SLICE_X55Y491 LUT3 (Prop_G5LUT_SLICEM_I2_O) 0.056 1.299 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[7]_i_1__39/O net (fo=1, routed) 0.013 1.312 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[7] SLICE_X55Y491 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.220 1.372 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X55Y491 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C clock pessimism -0.157 1.215 SLICE_X55Y491 FDRE (Hold_GFF2_SLICEM_C_D) 0.056 1.271 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7] ------------------------------------------------------------------- required time -1.271 arrival time 1.312 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.183ns (logic 0.094ns (51.366%) route 0.089ns (48.634%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.362ns Source Clock Delay (SCD): 1.120ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.004ns (routing 0.369ns, distribution 0.635ns) Clock Net Delay (Destination): 1.210ns (routing 0.431ns, distribution 0.779ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.004 1.120 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X57Y484 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y484 FDCE (Prop_GFF2_SLICEL_C_Q) 0.048 1.168 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Q net (fo=2, routed) 0.074 1.242 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_5_in SLICE_X58Y484 LUT3 (Prop_B6LUT_SLICEM_I2_O) 0.046 1.288 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__39/O net (fo=1, routed) 0.015 1.303 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[1] SLICE_X58Y484 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.210 1.362 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X58Y484 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.157 1.205 SLICE_X58Y484 FDRE (Hold_BFF_SLICEM_C_D) 0.056 1.261 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.261 arrival time 1.303 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[40].rx_data_ngccm_reg[40][53]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.049ns (34.028%) route 0.095ns (65.972%)) Logic Levels: 0 Clock Path Skew: 0.045ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.366ns Source Clock Delay (SCD): 1.131ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 1.015ns (routing 0.369ns, distribution 0.646ns) Clock Net Delay (Destination): 1.214ns (routing 0.431ns, distribution 0.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.015 1.131 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X56Y481 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y481 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.180 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/Q net (fo=1, routed) 0.095 1.275 rx_data[40][53] SLICE_X56Y482 FDCE r SFP_GEN[40].rx_data_ngccm_reg[40][53]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.214 1.366 g_gbt_bank[3].gbtbank_n_64 SLICE_X56Y482 FDCE r SFP_GEN[40].rx_data_ngccm_reg[40][53]/C clock pessimism -0.190 1.176 SLICE_X56Y482 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.231 SFP_GEN[40].rx_data_ngccm_reg[40][53] ------------------------------------------------------------------- required time -1.231 arrival time 1.275 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[40].rx_data_ngccm_reg[40][27]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.188ns (logic 0.048ns (25.532%) route 0.140ns (74.468%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.363ns Source Clock Delay (SCD): 1.118ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.002ns (routing 0.369ns, distribution 0.633ns) Clock Net Delay (Destination): 1.211ns (routing 0.431ns, distribution 0.780ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.002 1.118 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X57Y492 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y492 FDRE (Prop_GFF2_SLICEL_C_Q) 0.048 1.166 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/Q net (fo=1, routed) 0.140 1.306 rx_data[40][27] SLICE_X56Y492 FDCE r SFP_GEN[40].rx_data_ngccm_reg[40][27]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.211 1.363 g_gbt_bank[3].gbtbank_n_64 SLICE_X56Y492 FDCE r SFP_GEN[40].rx_data_ngccm_reg[40][27]/C clock pessimism -0.157 1.206 SLICE_X56Y492 FDCE (Hold_EFF_SLICEL_C_D) 0.056 1.262 SFP_GEN[40].rx_data_ngccm_reg[40][27] ------------------------------------------------------------------- required time -1.262 arrival time 1.306 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/READY_o_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.094ns (65.734%) route 0.049ns (34.266%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.361ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.199ns Clock Net Delay (Source): 1.005ns (routing 0.369ns, distribution 0.636ns) Clock Net Delay (Destination): 1.209ns (routing 0.431ns, distribution 0.778ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.005 1.121 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/CLK SLICE_X49Y490 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y490 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.170 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0]/Q net (fo=5, routed) 0.037 1.207 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg_n_0_[0] SLICE_X49Y490 LUT3 (Prop_A6LUT_SLICEM_I1_O) 0.045 1.252 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/READY_o_i_1__39/O net (fo=1, routed) 0.012 1.264 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/READY_o_i_1__39_n_0 SLICE_X49Y490 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/READY_o_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.209 1.361 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/CLK SLICE_X49Y490 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/READY_o_reg/C clock pessimism -0.199 1.162 SLICE_X49Y490 FDCE (Hold_AFF_SLICEM_C_D) 0.056 1.218 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/READY_o_reg ------------------------------------------------------------------- required time -1.218 arrival time 1.264 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[40].rx_data_ngccm_reg[40][48]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.195ns (logic 0.049ns (25.128%) route 0.146ns (74.872%)) Logic Levels: 0 Clock Path Skew: 0.093ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.376ns Source Clock Delay (SCD): 1.126ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.010ns (routing 0.369ns, distribution 0.641ns) Clock Net Delay (Destination): 1.224ns (routing 0.431ns, distribution 0.793ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.010 1.126 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X54Y483 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y483 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.175 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/Q net (fo=1, routed) 0.146 1.321 rx_data[40][48] SLICE_X55Y483 FDCE r SFP_GEN[40].rx_data_ngccm_reg[40][48]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.224 1.376 g_gbt_bank[3].gbtbank_n_64 SLICE_X55Y483 FDCE r SFP_GEN[40].rx_data_ngccm_reg[40][48]/C clock pessimism -0.157 1.219 SLICE_X55Y483 FDCE (Hold_AFF2_SLICEM_C_D) 0.056 1.275 SFP_GEN[40].rx_data_ngccm_reg[40][48] ------------------------------------------------------------------- required time -1.275 arrival time 1.321 ------------------------------------------------------------------- slack 0.046 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_42 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y209 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y480 SFP_GEN[40].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y480 SFP_GEN[40].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X58Y482 SFP_GEN[40].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X58Y482 SFP_GEN[40].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X58Y482 SFP_GEN[40].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X59Y482 SFP_GEN[40].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y480 SFP_GEN[40].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X61Y480 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X61Y480 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X61Y481 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X0Y484 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_meta_reg/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X0Y484 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X54Y480 SFP_GEN[40].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X55Y481 SFP_GEN[40].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X55Y481 SFP_GEN[40].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[70]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X60Y481 SFP_GEN[40].ngCCM_gbt/RX_Clock_40MHz_reg/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X61Y490 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[26]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X56Y495 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[36]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X56Y495 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[38]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_43 To Clock: gtwiz_userclk_rx_srcclk_out[0]_43 Setup : 0 Failing Endpoints, Worst Slack 3.968ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.035ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.968ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].rx_data_ngccm_reg[41][55]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 3.931ns (logic 0.360ns (9.158%) route 3.571ns (90.842%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.329ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.318ns = ( 10.635 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.942ns (routing 0.693ns, distribution 1.249ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y503 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y503 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.187 5.175 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X40Y499 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.221 5.396 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[41].rx_data_ngccm[41][83]_i_1/O net (fo=76, routed) 1.384 6.780 rx_data_ngccm[41] SLICE_X34Y514 FDCE r SFP_GEN[41].rx_data_ngccm_reg[41][55]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.942 10.635 g_gbt_bank[3].gbtbank_n_74 SLICE_X34Y514 FDCE r SFP_GEN[41].rx_data_ngccm_reg[41][55]/C clock pessimism 0.202 10.837 clock uncertainty -0.035 10.802 SLICE_X34Y514 FDCE (Setup_AFF_SLICEM_C_CE) -0.054 10.748 SFP_GEN[41].rx_data_ngccm_reg[41][55] ------------------------------------------------------------------- required time 10.748 arrival time -6.780 ------------------------------------------------------------------- slack 3.968 Slack (MET) : 4.017ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].rx_data_ngccm_reg[41][59]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 3.891ns (logic 0.360ns (9.252%) route 3.531ns (90.748%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.319ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.328ns = ( 10.645 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.952ns (routing 0.693ns, distribution 1.259ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y503 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y503 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.187 5.175 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X40Y499 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.221 5.396 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[41].rx_data_ngccm[41][83]_i_1/O net (fo=76, routed) 1.344 6.740 rx_data_ngccm[41] SLICE_X33Y513 FDCE r SFP_GEN[41].rx_data_ngccm_reg[41][59]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.952 10.645 g_gbt_bank[3].gbtbank_n_74 SLICE_X33Y513 FDCE r SFP_GEN[41].rx_data_ngccm_reg[41][59]/C clock pessimism 0.202 10.847 clock uncertainty -0.035 10.812 SLICE_X33Y513 FDCE (Setup_AFF2_SLICEL_C_CE) -0.055 10.757 SFP_GEN[41].rx_data_ngccm_reg[41][59] ------------------------------------------------------------------- required time 10.757 arrival time -6.740 ------------------------------------------------------------------- slack 4.017 Slack (MET) : 4.022ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].rx_data_ngccm_reg[41][57]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 3.887ns (logic 0.360ns (9.262%) route 3.527ns (90.738%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.319ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.328ns = ( 10.645 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.952ns (routing 0.693ns, distribution 1.259ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y503 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y503 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.187 5.175 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X40Y499 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.221 5.396 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[41].rx_data_ngccm[41][83]_i_1/O net (fo=76, routed) 1.340 6.736 rx_data_ngccm[41] SLICE_X33Y513 FDCE r SFP_GEN[41].rx_data_ngccm_reg[41][57]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.952 10.645 g_gbt_bank[3].gbtbank_n_74 SLICE_X33Y513 FDCE r SFP_GEN[41].rx_data_ngccm_reg[41][57]/C clock pessimism 0.202 10.847 clock uncertainty -0.035 10.812 SLICE_X33Y513 FDCE (Setup_AFF_SLICEL_C_CE) -0.054 10.758 SFP_GEN[41].rx_data_ngccm_reg[41][57] ------------------------------------------------------------------- required time 10.758 arrival time -6.736 ------------------------------------------------------------------- slack 4.022 Slack (MET) : 4.028ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 4.055ns (logic 1.520ns (37.485%) route 2.535ns (62.515%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.352ns = ( 10.669 - 8.317 ) Source Clock Delay (SCD): 2.698ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.273ns (routing 0.772ns, distribution 1.501ns) Clock Net Delay (Destination): 1.976ns (routing 0.693ns, distribution 1.283ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.273 2.698 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.802 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 1.702 5.504 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X31Y497 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.171 5.675 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/O net (fo=5, routed) 0.208 5.883 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X31Y498 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.245 6.128 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/O net (fo=7, routed) 0.625 6.753 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 SLICE_X31Y498 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.976 10.669 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X31Y498 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.202 10.872 clock uncertainty -0.035 10.836 SLICE_X31Y498 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 10.781 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 10.781 arrival time -6.753 ------------------------------------------------------------------- slack 4.028 Slack (MET) : 4.032ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 4.052ns (logic 1.520ns (37.512%) route 2.532ns (62.488%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.353ns = ( 10.670 - 8.317 ) Source Clock Delay (SCD): 2.698ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.273ns (routing 0.772ns, distribution 1.501ns) Clock Net Delay (Destination): 1.977ns (routing 0.693ns, distribution 1.284ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.273 2.698 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.802 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 1.702 5.504 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X31Y497 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.171 5.675 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/O net (fo=5, routed) 0.208 5.883 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X31Y498 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.245 6.128 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/O net (fo=7, routed) 0.622 6.750 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 SLICE_X32Y498 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.977 10.670 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X32Y498 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.202 10.873 clock uncertainty -0.035 10.837 SLICE_X32Y498 FDRE (Setup_AFF2_SLICEL_C_CE) -0.055 10.782 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 10.782 arrival time -6.750 ------------------------------------------------------------------- slack 4.032 Slack (MET) : 4.032ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 4.052ns (logic 1.520ns (37.512%) route 2.532ns (62.488%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.353ns = ( 10.670 - 8.317 ) Source Clock Delay (SCD): 2.698ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.273ns (routing 0.772ns, distribution 1.501ns) Clock Net Delay (Destination): 1.977ns (routing 0.693ns, distribution 1.284ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.273 2.698 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.802 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 1.702 5.504 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X31Y497 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.171 5.675 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/O net (fo=5, routed) 0.208 5.883 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X31Y498 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.245 6.128 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/O net (fo=7, routed) 0.622 6.750 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 SLICE_X32Y498 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.977 10.670 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X32Y498 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.202 10.873 clock uncertainty -0.035 10.837 SLICE_X32Y498 FDRE (Setup_BFF2_SLICEL_C_CE) -0.055 10.782 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 10.782 arrival time -6.750 ------------------------------------------------------------------- slack 4.032 Slack (MET) : 4.032ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 4.052ns (logic 1.520ns (37.512%) route 2.532ns (62.488%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.352ns = ( 10.669 - 8.317 ) Source Clock Delay (SCD): 2.698ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.273ns (routing 0.772ns, distribution 1.501ns) Clock Net Delay (Destination): 1.976ns (routing 0.693ns, distribution 1.283ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.273 2.698 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.802 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 1.702 5.504 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X31Y497 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.171 5.675 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/O net (fo=5, routed) 0.208 5.883 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X31Y498 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.245 6.128 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/O net (fo=7, routed) 0.622 6.750 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 SLICE_X31Y498 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.976 10.669 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X31Y498 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.202 10.872 clock uncertainty -0.035 10.836 SLICE_X31Y498 FDRE (Setup_BFF_SLICEM_C_CE) -0.054 10.782 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 10.782 arrival time -6.750 ------------------------------------------------------------------- slack 4.032 Slack (MET) : 4.032ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 4.052ns (logic 1.520ns (37.512%) route 2.532ns (62.488%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.352ns = ( 10.669 - 8.317 ) Source Clock Delay (SCD): 2.698ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.273ns (routing 0.772ns, distribution 1.501ns) Clock Net Delay (Destination): 1.976ns (routing 0.693ns, distribution 1.283ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.273 2.698 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.802 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 1.702 5.504 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X31Y497 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.171 5.675 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/O net (fo=5, routed) 0.208 5.883 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X31Y498 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.245 6.128 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/O net (fo=7, routed) 0.622 6.750 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 SLICE_X31Y498 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.976 10.669 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X31Y498 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.202 10.872 clock uncertainty -0.035 10.836 SLICE_X31Y498 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 10.782 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 10.782 arrival time -6.750 ------------------------------------------------------------------- slack 4.032 Slack (MET) : 4.034ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].rx_data_ngccm_reg[41][83]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 3.849ns (logic 0.360ns (9.353%) route 3.489ns (90.647%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.341ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.306ns = ( 10.623 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.930ns (routing 0.693ns, distribution 1.237ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y503 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y503 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.187 5.175 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X40Y499 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.221 5.396 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[41].rx_data_ngccm[41][83]_i_1/O net (fo=76, routed) 1.302 6.698 rx_data_ngccm[41] SLICE_X41Y508 FDCE r SFP_GEN[41].rx_data_ngccm_reg[41][83]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.930 10.623 g_gbt_bank[3].gbtbank_n_74 SLICE_X41Y508 FDCE r SFP_GEN[41].rx_data_ngccm_reg[41][83]/C clock pessimism 0.202 10.825 clock uncertainty -0.035 10.790 SLICE_X41Y508 FDCE (Setup_EFF2_SLICEM_C_CE) -0.058 10.732 SFP_GEN[41].rx_data_ngccm_reg[41][83] ------------------------------------------------------------------- required time 10.732 arrival time -6.698 ------------------------------------------------------------------- slack 4.034 Slack (MET) : 4.037ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 4.048ns (logic 1.520ns (37.549%) route 2.528ns (62.451%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.353ns = ( 10.670 - 8.317 ) Source Clock Delay (SCD): 2.698ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.273ns (routing 0.772ns, distribution 1.501ns) Clock Net Delay (Destination): 1.977ns (routing 0.693ns, distribution 1.284ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.273 2.698 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.802 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 1.702 5.504 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X31Y497 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.171 5.675 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/O net (fo=5, routed) 0.208 5.883 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X31Y498 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.245 6.128 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/O net (fo=7, routed) 0.618 6.746 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 SLICE_X32Y498 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.977 10.670 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X32Y498 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.202 10.873 clock uncertainty -0.035 10.837 SLICE_X32Y498 FDRE (Setup_AFF_SLICEL_C_CE) -0.054 10.783 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 10.783 arrival time -6.746 ------------------------------------------------------------------- slack 4.037 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.035ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].rx_data_ngccm_reg[41][46]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.168ns (logic 0.048ns (28.571%) route 0.120ns (71.429%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.207ns Source Clock Delay (SCD): 0.986ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.870ns (routing 0.368ns, distribution 0.502ns) Clock Net Delay (Destination): 1.055ns (routing 0.432ns, distribution 0.623ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.870 0.986 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X36Y511 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y511 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 1.034 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/Q net (fo=1, routed) 0.120 1.154 rx_data[41][46] SLICE_X38Y511 FDCE r SFP_GEN[41].rx_data_ngccm_reg[41][46]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.055 1.207 g_gbt_bank[3].gbtbank_n_74 SLICE_X38Y511 FDCE r SFP_GEN[41].rx_data_ngccm_reg[41][46]/C clock pessimism -0.144 1.063 SLICE_X38Y511 FDCE (Hold_BFF_SLICEL_C_D) 0.056 1.119 SFP_GEN[41].rx_data_ngccm_reg[41][46] ------------------------------------------------------------------- required time -1.119 arrival time 1.154 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].rx_data_ngccm_reg[41][37]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.049ns (34.507%) route 0.093ns (65.493%)) Logic Levels: 0 Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.222ns Source Clock Delay (SCD): 0.998ns Clock Pessimism Removal (CPR): 0.174ns Clock Net Delay (Source): 0.882ns (routing 0.368ns, distribution 0.514ns) Clock Net Delay (Destination): 1.070ns (routing 0.432ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.882 0.998 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X36Y497 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y497 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.047 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/Q net (fo=1, routed) 0.093 1.140 rx_data[41][37] SLICE_X36Y498 FDCE r SFP_GEN[41].rx_data_ngccm_reg[41][37]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.070 1.222 g_gbt_bank[3].gbtbank_n_74 SLICE_X36Y498 FDCE r SFP_GEN[41].rx_data_ngccm_reg[41][37]/C clock pessimism -0.174 1.048 SLICE_X36Y498 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 1.104 SFP_GEN[41].rx_data_ngccm_reg[41][37] ------------------------------------------------------------------- required time -1.104 arrival time 1.140 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/psAddress_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.191ns (logic 0.095ns (49.738%) route 0.096ns (50.262%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.092ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.234ns Source Clock Delay (SCD): 0.998ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.882ns (routing 0.368ns, distribution 0.514ns) Clock Net Delay (Destination): 1.082ns (routing 0.432ns, distribution 0.650ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.882 0.998 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X30Y497 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/psAddress_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X30Y497 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 1.047 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/psAddress_reg[0]/Q net (fo=9, routed) 0.081 1.128 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/psAddress[0] SLICE_X31Y497 LUT6 (Prop_B6LUT_SLICEM_I5_O) 0.046 1.174 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_i_1__40/O net (fo=1, routed) 0.015 1.189 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd SLICE_X31Y497 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.082 1.234 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X31Y497 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_reg/C clock pessimism -0.144 1.090 SLICE_X31Y497 FDCE (Hold_BFF_SLICEM_C_D) 0.056 1.146 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_reg ------------------------------------------------------------------- required time -1.146 arrival time 1.189 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.043ns (arrival time - required time) Source: SFP_GEN[41].ngCCM_gbt/RX_Clock_40MHz_reg/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/strbAtoB_o_reg/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.186ns (logic 0.080ns (43.011%) route 0.106ns (56.989%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.214ns Source Clock Delay (SCD): 0.983ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.867ns (routing 0.368ns, distribution 0.499ns) Clock Net Delay (Destination): 1.062ns (routing 0.432ns, distribution 0.630ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.867 0.983 SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X44Y499 FDRE r SFP_GEN[41].ngCCM_gbt/RX_Clock_40MHz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X44Y499 FDRE (Prop_DFF2_SLICEM_C_Q) 0.049 1.032 r SFP_GEN[41].ngCCM_gbt/RX_Clock_40MHz_reg/Q net (fo=14, routed) 0.090 1.122 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/RX_Clock_40MHz SLICE_X42Y499 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.031 1.153 r SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/strbAtoB_o_i_1__15/O net (fo=1, routed) 0.016 1.169 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/strbAtoB_o_i_1__15_n_0 SLICE_X42Y499 FDRE r SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/strbAtoB_o_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.062 1.214 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y499 FDRE r SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/strbAtoB_o_reg/C clock pessimism -0.144 1.070 SLICE_X42Y499 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.126 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/strbAtoB_o_reg ------------------------------------------------------------------- required time -1.126 arrival time 1.169 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.094ns (65.734%) route 0.049ns (34.266%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.208ns Source Clock Delay (SCD): 0.983ns Clock Pessimism Removal (CPR): 0.184ns Clock Net Delay (Source): 0.867ns (routing 0.368ns, distribution 0.499ns) Clock Net Delay (Destination): 1.056ns (routing 0.432ns, distribution 0.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.867 0.983 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X37Y511 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y511 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.032 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.037 1.069 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/O84[1] SLICE_X37Y511 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.045 1.114 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__40/O net (fo=1, routed) 0.012 1.126 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[1] SLICE_X37Y511 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.056 1.208 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X37Y511 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C clock pessimism -0.184 1.024 SLICE_X37Y511 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.080 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20] ------------------------------------------------------------------- required time -1.080 arrival time 1.126 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.210ns Source Clock Delay (SCD): 0.984ns Clock Pessimism Removal (CPR): 0.184ns Clock Net Delay (Source): 0.868ns (routing 0.368ns, distribution 0.500ns) Clock Net Delay (Destination): 1.058ns (routing 0.432ns, distribution 0.626ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.868 0.984 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X36Y511 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y511 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.033 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Q net (fo=2, routed) 0.034 1.067 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_11_in SLICE_X36Y511 LUT3 (Prop_C6LUT_SLICEL_I2_O) 0.045 1.112 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__40/O net (fo=1, routed) 0.016 1.128 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[4] SLICE_X36Y511 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.058 1.210 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X36Y511 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.184 1.026 SLICE_X36Y511 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.082 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.082 arrival time 1.128 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.223ns Source Clock Delay (SCD): 0.996ns Clock Pessimism Removal (CPR): 0.185ns Clock Net Delay (Source): 0.880ns (routing 0.368ns, distribution 0.512ns) Clock Net Delay (Destination): 1.071ns (routing 0.432ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.880 0.996 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X36Y497 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y497 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.045 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.034 1.079 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_35_in SLICE_X36Y497 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.045 1.124 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__40/O net (fo=1, routed) 0.016 1.140 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[16] SLICE_X36Y497 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.071 1.223 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X36Y497 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.185 1.038 SLICE_X36Y497 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.094 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.094 arrival time 1.140 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].rx_data_ngccm_reg[41][76]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.049ns (34.266%) route 0.094ns (65.734%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.207ns Source Clock Delay (SCD): 0.984ns Clock Pessimism Removal (CPR): 0.184ns Clock Net Delay (Source): 0.868ns (routing 0.368ns, distribution 0.500ns) Clock Net Delay (Destination): 1.055ns (routing 0.432ns, distribution 0.623ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.868 0.984 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X37Y511 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y511 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 1.033 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/Q net (fo=1, routed) 0.094 1.127 rx_data[41][76] SLICE_X38Y511 FDCE r SFP_GEN[41].rx_data_ngccm_reg[41][76]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.055 1.207 g_gbt_bank[3].gbtbank_n_74 SLICE_X38Y511 FDCE r SFP_GEN[41].rx_data_ngccm_reg[41][76]/C clock pessimism -0.184 1.023 SLICE_X38Y511 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 1.079 SFP_GEN[41].rx_data_ngccm_reg[41][76] ------------------------------------------------------------------- required time -1.079 arrival time 1.127 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.094ns (64.828%) route 0.051ns (35.172%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.221ns Source Clock Delay (SCD): 0.995ns Clock Pessimism Removal (CPR): 0.185ns Clock Net Delay (Source): 0.879ns (routing 0.368ns, distribution 0.511ns) Clock Net Delay (Destination): 1.069ns (routing 0.432ns, distribution 0.637ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.879 0.995 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X37Y497 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y497 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.044 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Q net (fo=2, routed) 0.035 1.079 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_27_in SLICE_X37Y497 LUT3 (Prop_C6LUT_SLICEM_I2_O) 0.045 1.124 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__40/O net (fo=1, routed) 0.016 1.140 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[12] SLICE_X37Y497 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.069 1.221 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X37Y497 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C clock pessimism -0.185 1.036 SLICE_X37Y497 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.092 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12] ------------------------------------------------------------------- required time -1.092 arrival time 1.140 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].rx_data_ngccm_reg[41][39]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.049ns (31.613%) route 0.106ns (68.387%)) Logic Levels: 0 Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.222ns Source Clock Delay (SCD): 0.998ns Clock Pessimism Removal (CPR): 0.174ns Clock Net Delay (Source): 0.882ns (routing 0.368ns, distribution 0.514ns) Clock Net Delay (Destination): 1.070ns (routing 0.432ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.882 0.998 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X36Y497 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y497 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.047 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/Q net (fo=1, routed) 0.106 1.153 rx_data[41][39] SLICE_X36Y498 FDCE r SFP_GEN[41].rx_data_ngccm_reg[41][39]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.070 1.222 g_gbt_bank[3].gbtbank_n_74 SLICE_X36Y498 FDCE r SFP_GEN[41].rx_data_ngccm_reg[41][39]/C clock pessimism -0.174 1.048 SLICE_X36Y498 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.104 SFP_GEN[41].rx_data_ngccm_reg[41][39] ------------------------------------------------------------------- required time -1.104 arrival time 1.153 ------------------------------------------------------------------- slack 0.049 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_43 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y208 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X39Y501 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X39Y501 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X42Y496 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X42Y496 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X42Y499 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X41Y498 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X39Y501 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X41Y498 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X41Y497 SFP_GEN[41].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X41Y497 SFP_GEN[41].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X41Y498 SFP_GEN[41].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[12]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X41Y498 SFP_GEN[41].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[19]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X41Y497 SFP_GEN[41].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[1]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X39Y508 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[44]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X39Y508 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[46]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X39Y508 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[50]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X38Y503 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[54]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X39Y508 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[58]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X39Y508 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[70]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_44 To Clock: gtwiz_userclk_rx_srcclk_out[0]_44 Setup : 0 Failing Endpoints, Worst Slack 2.774ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.034ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.774ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.564ns (logic 1.474ns (26.492%) route 4.090ns (73.508%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.111ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.636ns = ( 10.953 - 8.317 ) Source Clock Delay (SCD): 2.738ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.313ns (routing 0.794ns, distribution 1.519ns) Clock Net Delay (Destination): 2.260ns (routing 0.710ns, distribution 1.550ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.313 2.738 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.822 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.195 7.017 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X57Y506 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.146 7.163 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/O net (fo=5, routed) 0.306 7.469 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X58Y506 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.092 7.561 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__41/O net (fo=1, routed) 0.167 7.728 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__41_n_0 SLICE_X58Y505 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.152 7.880 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__41/O net (fo=2, routed) 0.422 8.302 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__41_n_0 SLICE_X57Y506 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.260 10.953 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X57Y506 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.213 11.166 clock uncertainty -0.035 11.131 SLICE_X57Y506 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 11.076 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.076 arrival time -8.302 ------------------------------------------------------------------- slack 2.774 Slack (MET) : 2.781ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.560ns (logic 1.474ns (26.511%) route 4.086ns (73.489%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.638ns = ( 10.955 - 8.317 ) Source Clock Delay (SCD): 2.738ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.313ns (routing 0.794ns, distribution 1.519ns) Clock Net Delay (Destination): 2.262ns (routing 0.710ns, distribution 1.552ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.313 2.738 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.822 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.195 7.017 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X57Y506 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.146 7.163 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/O net (fo=5, routed) 0.306 7.469 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X58Y506 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.092 7.561 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__41/O net (fo=1, routed) 0.167 7.728 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__41_n_0 SLICE_X58Y505 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.152 7.880 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__41/O net (fo=2, routed) 0.418 8.298 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__41_n_0 SLICE_X57Y506 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.262 10.955 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X57Y506 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.213 11.168 clock uncertainty -0.035 11.133 SLICE_X57Y506 FDCE (Setup_CFF_SLICEL_C_CE) -0.054 11.079 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.079 arrival time -8.298 ------------------------------------------------------------------- slack 2.781 Slack (MET) : 2.965ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.376ns (logic 1.398ns (26.004%) route 3.978ns (73.996%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.639ns = ( 10.956 - 8.317 ) Source Clock Delay (SCD): 2.738ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.313ns (routing 0.794ns, distribution 1.519ns) Clock Net Delay (Destination): 2.263ns (routing 0.710ns, distribution 1.553ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.313 2.738 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.822 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.195 7.017 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X57Y506 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.146 7.163 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/O net (fo=5, routed) 0.264 7.427 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X58Y505 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.168 7.595 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__42/O net (fo=3, routed) 0.519 8.114 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/consecFalseHeaders0 SLICE_X58Y505 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.263 10.956 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y505 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.213 11.169 clock uncertainty -0.035 11.134 SLICE_X58Y505 FDRE (Setup_BFF2_SLICEM_C_CE) -0.055 11.079 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 11.079 arrival time -8.114 ------------------------------------------------------------------- slack 2.965 Slack (MET) : 2.965ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.376ns (logic 1.398ns (26.004%) route 3.978ns (73.996%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.639ns = ( 10.956 - 8.317 ) Source Clock Delay (SCD): 2.738ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.313ns (routing 0.794ns, distribution 1.519ns) Clock Net Delay (Destination): 2.263ns (routing 0.710ns, distribution 1.553ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.313 2.738 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.822 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.195 7.017 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X57Y506 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.146 7.163 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/O net (fo=5, routed) 0.264 7.427 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X58Y505 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.168 7.595 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__42/O net (fo=3, routed) 0.519 8.114 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/consecFalseHeaders0 SLICE_X58Y505 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.263 10.956 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y505 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C clock pessimism 0.213 11.169 clock uncertainty -0.035 11.134 SLICE_X58Y505 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 11.079 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2] ------------------------------------------------------------------- required time 11.079 arrival time -8.114 ------------------------------------------------------------------- slack 2.965 Slack (MET) : 2.969ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.373ns (logic 1.398ns (26.019%) route 3.975ns (73.981%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.639ns = ( 10.956 - 8.317 ) Source Clock Delay (SCD): 2.738ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.313ns (routing 0.794ns, distribution 1.519ns) Clock Net Delay (Destination): 2.263ns (routing 0.710ns, distribution 1.553ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.313 2.738 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.822 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.195 7.017 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X57Y506 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.146 7.163 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/O net (fo=5, routed) 0.264 7.427 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X58Y505 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.168 7.595 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__42/O net (fo=3, routed) 0.516 8.111 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/consecFalseHeaders0 SLICE_X58Y505 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.263 10.956 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y505 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.213 11.169 clock uncertainty -0.035 11.134 SLICE_X58Y505 FDRE (Setup_BFF_SLICEM_C_CE) -0.054 11.080 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 11.080 arrival time -8.111 ------------------------------------------------------------------- slack 2.969 Slack (MET) : 3.061ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.275ns (logic 1.376ns (26.085%) route 3.899ns (73.915%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.634ns = ( 10.951 - 8.317 ) Source Clock Delay (SCD): 2.738ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.313ns (routing 0.794ns, distribution 1.519ns) Clock Net Delay (Destination): 2.258ns (routing 0.710ns, distribution 1.548ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.313 2.738 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.822 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.195 7.017 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X57Y506 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.146 7.163 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/O net (fo=5, routed) 0.271 7.434 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X58Y504 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.146 7.580 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__42/O net (fo=7, routed) 0.433 8.013 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 SLICE_X58Y503 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.258 10.951 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y503 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.213 11.164 clock uncertainty -0.035 11.129 SLICE_X58Y503 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 11.074 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.074 arrival time -8.013 ------------------------------------------------------------------- slack 3.061 Slack (MET) : 3.065ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.272ns (logic 1.376ns (26.100%) route 3.896ns (73.900%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.634ns = ( 10.951 - 8.317 ) Source Clock Delay (SCD): 2.738ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.313ns (routing 0.794ns, distribution 1.519ns) Clock Net Delay (Destination): 2.258ns (routing 0.710ns, distribution 1.548ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.313 2.738 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.822 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.195 7.017 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X57Y506 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.146 7.163 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/O net (fo=5, routed) 0.271 7.434 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X58Y504 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.146 7.580 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__42/O net (fo=7, routed) 0.430 8.010 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 SLICE_X58Y503 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.258 10.951 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y503 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.213 11.164 clock uncertainty -0.035 11.129 SLICE_X58Y503 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 11.075 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 11.075 arrival time -8.010 ------------------------------------------------------------------- slack 3.065 Slack (MET) : 3.065ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.272ns (logic 1.376ns (26.100%) route 3.896ns (73.900%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.634ns = ( 10.951 - 8.317 ) Source Clock Delay (SCD): 2.738ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.313ns (routing 0.794ns, distribution 1.519ns) Clock Net Delay (Destination): 2.258ns (routing 0.710ns, distribution 1.548ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.313 2.738 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.822 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.195 7.017 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X57Y506 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.146 7.163 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/O net (fo=5, routed) 0.271 7.434 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X58Y504 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.146 7.580 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__42/O net (fo=7, routed) 0.430 8.010 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 SLICE_X58Y503 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.258 10.951 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y503 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.213 11.164 clock uncertainty -0.035 11.129 SLICE_X58Y503 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 11.075 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 11.075 arrival time -8.010 ------------------------------------------------------------------- slack 3.065 Slack (MET) : 3.140ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.198ns (logic 1.376ns (26.472%) route 3.822ns (73.528%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.111ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.636ns = ( 10.953 - 8.317 ) Source Clock Delay (SCD): 2.738ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.313ns (routing 0.794ns, distribution 1.519ns) Clock Net Delay (Destination): 2.260ns (routing 0.710ns, distribution 1.550ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.313 2.738 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.822 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.195 7.017 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X57Y506 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.146 7.163 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/O net (fo=5, routed) 0.271 7.434 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X58Y504 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.146 7.580 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__42/O net (fo=7, routed) 0.356 7.936 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 SLICE_X58Y506 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.260 10.953 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y506 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.213 11.166 clock uncertainty -0.035 11.131 SLICE_X58Y506 FDRE (Setup_EFF_SLICEM_C_CE) -0.055 11.076 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 11.076 arrival time -7.936 ------------------------------------------------------------------- slack 3.140 Slack (MET) : 3.152ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.187ns (logic 1.376ns (26.528%) route 3.811ns (73.472%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.112ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.637ns = ( 10.954 - 8.317 ) Source Clock Delay (SCD): 2.738ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.313ns (routing 0.794ns, distribution 1.519ns) Clock Net Delay (Destination): 2.261ns (routing 0.710ns, distribution 1.551ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.313 2.738 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.822 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 3.195 7.017 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X57Y506 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.146 7.163 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/O net (fo=5, routed) 0.271 7.434 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X58Y504 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.146 7.580 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__42/O net (fo=7, routed) 0.345 7.925 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 SLICE_X58Y505 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.261 10.954 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y505 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.213 11.167 clock uncertainty -0.035 11.132 SLICE_X58Y505 FDRE (Setup_EFF_SLICEM_C_CE) -0.055 11.077 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 11.077 arrival time -7.925 ------------------------------------------------------------------- slack 3.152 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.034ns (arrival time - required time) Source: SFP_GEN[42].rx_data_ngccm_reg[42][56]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[56]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.176ns (logic 0.080ns (45.455%) route 0.096ns (54.545%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.380ns Source Clock Delay (SCD): 1.134ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.018ns (routing 0.377ns, distribution 0.641ns) Clock Net Delay (Destination): 1.228ns (routing 0.443ns, distribution 0.785ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.018 1.134 g_gbt_bank[3].gbtbank_n_84 SLICE_X61Y519 FDCE r SFP_GEN[42].rx_data_ngccm_reg[42][56]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y519 FDCE (Prop_BFF_SLICEM_C_Q) 0.049 1.183 r SFP_GEN[42].rx_data_ngccm_reg[42][56]/Q net (fo=1, routed) 0.081 1.264 g_gbt_bank[3].gbtbank/RX_Word_rx40_reg[78][32] SLICE_X62Y519 LUT3 (Prop_B6LUT_SLICEM_I1_O) 0.031 1.295 r g_gbt_bank[3].gbtbank/RX_Word_rx40[56]_i_1__8/O net (fo=1, routed) 0.015 1.310 SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[83]_0[32] SLICE_X62Y519 FDCE r SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[56]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.228 1.380 SFP_GEN[42].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X62Y519 FDCE r SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[56]/C clock pessimism -0.160 1.220 SLICE_X62Y519 FDCE (Hold_BFF_SLICEM_C_D) 0.056 1.276 SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[56] ------------------------------------------------------------------- required time -1.276 arrival time 1.310 ------------------------------------------------------------------- slack 0.034 Slack (MET) : 0.036ns (arrival time - required time) Source: SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[74]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[74]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.163ns (logic 0.048ns (29.448%) route 0.115ns (70.552%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.364ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.017ns (routing 0.377ns, distribution 0.640ns) Clock Net Delay (Destination): 1.212ns (routing 0.443ns, distribution 0.769ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.133 SFP_GEN[42].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X60Y523 FDCE r SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[74]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y523 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.181 r SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[74]/Q net (fo=6, routed) 0.115 1.296 SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]_0[25] SLICE_X61Y523 FDRE r SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[74]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.212 1.364 SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X61Y523 FDRE r SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[74]/C clock pessimism -0.160 1.204 SLICE_X61Y523 FDRE (Hold_CFF2_SLICEM_C_D) 0.056 1.260 SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[74] ------------------------------------------------------------------- required time -1.260 arrival time 1.296 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[25]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[25]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.048ns (33.566%) route 0.095ns (66.434%)) Logic Levels: 0 Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.351ns Source Clock Delay (SCD): 1.115ns Clock Pessimism Removal (CPR): 0.192ns Clock Net Delay (Source): 0.999ns (routing 0.377ns, distribution 0.622ns) Clock Net Delay (Destination): 1.199ns (routing 0.443ns, distribution 0.756ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.115 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X57Y515 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[25]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y515 FDCE (Prop_HFF_SLICEL_C_Q) 0.048 1.163 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[25]/Q net (fo=1, routed) 0.095 1.258 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[25] SLICE_X57Y516 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.199 1.351 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X57Y516 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[25]/C clock pessimism -0.192 1.159 SLICE_X57Y516 FDCE (Hold_AFF2_SLICEL_C_D) 0.056 1.215 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[25] ------------------------------------------------------------------- required time -1.215 arrival time 1.258 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[33]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[33]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.049ns (34.266%) route 0.094ns (65.734%)) Logic Levels: 0 Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.351ns Source Clock Delay (SCD): 1.115ns Clock Pessimism Removal (CPR): 0.192ns Clock Net Delay (Source): 0.999ns (routing 0.377ns, distribution 0.622ns) Clock Net Delay (Destination): 1.199ns (routing 0.443ns, distribution 0.756ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.115 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X57Y515 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[33]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y515 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.164 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[33]/Q net (fo=1, routed) 0.094 1.258 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[33] SLICE_X57Y516 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[33]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.199 1.351 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X57Y516 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[33]/C clock pessimism -0.192 1.159 SLICE_X57Y516 FDCE (Hold_BFF2_SLICEL_C_D) 0.056 1.215 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[33] ------------------------------------------------------------------- required time -1.215 arrival time 1.258 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.194ns (logic 0.094ns (48.454%) route 0.100ns (51.546%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.095ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.375ns Source Clock Delay (SCD): 1.120ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.004ns (routing 0.377ns, distribution 0.627ns) Clock Net Delay (Destination): 1.223ns (routing 0.443ns, distribution 0.780ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.004 1.120 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X58Y523 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X58Y523 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.169 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Q net (fo=2, routed) 0.084 1.253 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_31_in SLICE_X59Y523 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.045 1.298 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__41/O net (fo=1, routed) 0.016 1.314 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] SLICE_X59Y523 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.223 1.375 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X59Y523 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.160 1.215 SLICE_X59Y523 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.271 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.271 arrival time 1.314 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.190ns (logic 0.096ns (50.526%) route 0.094ns (49.474%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.090ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.366ns Source Clock Delay (SCD): 1.116ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.000ns (routing 0.377ns, distribution 0.623ns) Clock Net Delay (Destination): 1.214ns (routing 0.443ns, distribution 0.771ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.000 1.116 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X60Y503 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y503 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.165 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/Q net (fo=1, routed) 0.078 1.243 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gbtBank_Clk_gen[6].cnt_reg[6][0]_0[0] SLICE_X61Y503 LUT2 (Prop_H6LUT_SLICEM_I0_O) 0.047 1.290 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gbtBank_Clk_gen[6].rx_clken_sr[6][1]_i_1__2/O net (fo=1, routed) 0.016 1.306 g_gbt_bank[3].gbtbank/i_gbt_bank_n_319 SLICE_X61Y503 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.214 1.366 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X61Y503 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/C clock pessimism -0.160 1.206 SLICE_X61Y503 FDCE (Hold_HFF_SLICEM_C_D) 0.056 1.262 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1] ------------------------------------------------------------------- required time -1.262 arrival time 1.306 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.094ns (63.946%) route 0.053ns (36.054%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.374ns Source Clock Delay (SCD): 1.130ns Clock Pessimism Removal (CPR): 0.200ns Clock Net Delay (Source): 1.014ns (routing 0.377ns, distribution 0.637ns) Clock Net Delay (Destination): 1.222ns (routing 0.443ns, distribution 0.779ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.130 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X60Y520 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y520 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.179 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.037 1.216 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in SLICE_X60Y520 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.045 1.261 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__41/O net (fo=1, routed) 0.016 1.277 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] SLICE_X60Y520 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.222 1.374 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X60Y520 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.200 1.174 SLICE_X60Y520 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.230 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.230 arrival time 1.277 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.047ns (arrival time - required time) Source: SFP_GEN[42].rx_data_ngccm_reg[42][65]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[64]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.153ns (logic 0.101ns (66.013%) route 0.052ns (33.987%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.376ns Source Clock Delay (SCD): 1.135ns Clock Pessimism Removal (CPR): 0.191ns Clock Net Delay (Source): 1.019ns (routing 0.377ns, distribution 0.642ns) Clock Net Delay (Destination): 1.224ns (routing 0.443ns, distribution 0.781ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.019 1.135 g_gbt_bank[3].gbtbank_n_84 SLICE_X60Y524 FDCE r SFP_GEN[42].rx_data_ngccm_reg[42][65]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y524 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.184 r SFP_GEN[42].rx_data_ngccm_reg[42][65]/Q net (fo=1, routed) 0.036 1.220 g_gbt_bank[3].gbtbank/RX_Word_rx40_reg[78][41] SLICE_X60Y523 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.052 1.272 r g_gbt_bank[3].gbtbank/RX_Word_rx40[64]_i_1__8/O net (fo=1, routed) 0.016 1.288 SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[83]_0[36] SLICE_X60Y523 FDCE r SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[64]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.224 1.376 SFP_GEN[42].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X60Y523 FDCE r SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[64]/C clock pessimism -0.191 1.185 SLICE_X60Y523 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.241 SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[64] ------------------------------------------------------------------- required time -1.241 arrival time 1.288 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.109ns (logic 0.064ns (58.716%) route 0.045ns (41.284%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.351ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.229ns Clock Net Delay (Source): 1.001ns (routing 0.377ns, distribution 0.624ns) Clock Net Delay (Destination): 1.199ns (routing 0.443ns, distribution 0.756ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.001 1.117 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y506 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X58Y506 FDRE (Prop_AFF_SLICEM_C_Q) 0.049 1.166 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/Q net (fo=2, routed) 0.033 1.199 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg_n_0_[4] SLICE_X58Y506 LUT6 (Prop_A6LUT_SLICEM_I5_O) 0.015 1.214 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__42/O net (fo=1, routed) 0.012 1.226 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__42_n_0 SLICE_X58Y506 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.199 1.351 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y506 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism -0.229 1.122 SLICE_X58Y506 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.178 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time -1.178 arrival time 1.226 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[42].rx_data_ngccm_reg[42][60]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.156ns (logic 0.048ns (30.769%) route 0.108ns (69.231%)) Logic Levels: 0 Clock Path Skew: 0.051ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.374ns Source Clock Delay (SCD): 1.132ns Clock Pessimism Removal (CPR): 0.191ns Clock Net Delay (Source): 1.016ns (routing 0.377ns, distribution 0.639ns) Clock Net Delay (Destination): 1.222ns (routing 0.443ns, distribution 0.779ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.016 1.132 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X60Y522 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y522 FDRE (Prop_FFF2_SLICEL_C_Q) 0.048 1.180 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/Q net (fo=1, routed) 0.108 1.288 rx_data[42][60] SLICE_X60Y524 FDCE r SFP_GEN[42].rx_data_ngccm_reg[42][60]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.222 1.374 g_gbt_bank[3].gbtbank_n_84 SLICE_X60Y524 FDCE r SFP_GEN[42].rx_data_ngccm_reg[42][60]/C clock pessimism -0.191 1.183 SLICE_X60Y524 FDCE (Hold_FFF_SLICEL_C_D) 0.056 1.239 SFP_GEN[42].rx_data_ngccm_reg[42][60] ------------------------------------------------------------------- required time -1.239 arrival time 1.288 ------------------------------------------------------------------- slack 0.049 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_44 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y211 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X64Y480 g_clock_rate_din[42].ngccm_status_cnt_reg[42][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X64Y480 g_clock_rate_din[42].ngccm_status_cnt_reg[42][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X64Y480 g_clock_rate_din[42].ngccm_status_cnt_reg[42][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X66Y480 g_clock_rate_din[42].ngccm_status_cnt_reg[42][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X64Y480 g_clock_rate_din[42].ngccm_status_cnt_reg[42][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X66Y480 g_clock_rate_din[42].ngccm_status_cnt_reg[42][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X66Y480 g_clock_rate_din[42].ngccm_status_cnt_reg[42][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X58Y524 SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[60]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X58Y524 SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[62]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X61Y511 SFP_GEN[42].rx_data_ngccm_reg[42][33]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X61Y511 SFP_GEN[42].rx_data_ngccm_reg[42][34]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X61Y511 SFP_GEN[42].rx_data_ngccm_reg[42][35]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X61Y511 SFP_GEN[42].rx_data_ngccm_reg[42][36]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X61Y523 SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[54]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X61Y523 SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[60]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X61Y523 SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[62]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X61Y523 SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[64]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X64Y518 SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[6]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X61Y523 SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[70]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_45 To Clock: gtwiz_userclk_rx_srcclk_out[0]_45 Setup : 0 Failing Endpoints, Worst Slack 2.659ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.034ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.659ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][64]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 5.573ns (logic 0.285ns (5.114%) route 5.288ns (94.886%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.008ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.677ns = ( 10.994 - 8.317 ) Source Clock Delay (SCD): 2.879ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.454ns (routing 0.789ns, distribution 1.665ns) Clock Net Delay (Destination): 2.301ns (routing 0.708ns, distribution 1.593ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.454 2.879 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y534 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y534 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.018 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.690 6.708 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X61Y505 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.146 6.854 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/O net (fo=76, routed) 1.598 8.452 rx_data_ngccm[43] SLICE_X65Y536 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][64]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.301 10.994 g_gbt_bank[3].gbtbank_n_94 SLICE_X65Y536 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][64]/C clock pessimism 0.210 11.204 clock uncertainty -0.035 11.169 SLICE_X65Y536 FDCE (Setup_EFF2_SLICEM_C_CE) -0.058 11.111 SFP_GEN[43].rx_data_ngccm_reg[43][64] ------------------------------------------------------------------- required time 11.111 arrival time -8.452 ------------------------------------------------------------------- slack 2.659 Slack (MET) : 2.659ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][66]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 5.573ns (logic 0.285ns (5.114%) route 5.288ns (94.886%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.008ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.677ns = ( 10.994 - 8.317 ) Source Clock Delay (SCD): 2.879ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.454ns (routing 0.789ns, distribution 1.665ns) Clock Net Delay (Destination): 2.301ns (routing 0.708ns, distribution 1.593ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.454 2.879 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y534 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y534 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.018 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.690 6.708 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X61Y505 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.146 6.854 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/O net (fo=76, routed) 1.598 8.452 rx_data_ngccm[43] SLICE_X65Y536 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][66]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.301 10.994 g_gbt_bank[3].gbtbank_n_94 SLICE_X65Y536 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][66]/C clock pessimism 0.210 11.204 clock uncertainty -0.035 11.169 SLICE_X65Y536 FDCE (Setup_FFF2_SLICEM_C_CE) -0.058 11.111 SFP_GEN[43].rx_data_ngccm_reg[43][66] ------------------------------------------------------------------- required time 11.111 arrival time -8.452 ------------------------------------------------------------------- slack 2.659 Slack (MET) : 2.659ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][69]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 5.573ns (logic 0.285ns (5.114%) route 5.288ns (94.886%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.008ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.677ns = ( 10.994 - 8.317 ) Source Clock Delay (SCD): 2.879ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.454ns (routing 0.789ns, distribution 1.665ns) Clock Net Delay (Destination): 2.301ns (routing 0.708ns, distribution 1.593ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.454 2.879 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y534 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y534 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.018 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.690 6.708 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X61Y505 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.146 6.854 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/O net (fo=76, routed) 1.598 8.452 rx_data_ngccm[43] SLICE_X65Y536 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][69]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.301 10.994 g_gbt_bank[3].gbtbank_n_94 SLICE_X65Y536 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][69]/C clock pessimism 0.210 11.204 clock uncertainty -0.035 11.169 SLICE_X65Y536 FDCE (Setup_GFF2_SLICEM_C_CE) -0.058 11.111 SFP_GEN[43].rx_data_ngccm_reg[43][69] ------------------------------------------------------------------- required time 11.111 arrival time -8.452 ------------------------------------------------------------------- slack 2.659 Slack (MET) : 2.665ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][63]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 5.570ns (logic 0.285ns (5.117%) route 5.285ns (94.883%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.008ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.677ns = ( 10.994 - 8.317 ) Source Clock Delay (SCD): 2.879ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.454ns (routing 0.789ns, distribution 1.665ns) Clock Net Delay (Destination): 2.301ns (routing 0.708ns, distribution 1.593ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.454 2.879 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y534 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y534 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.018 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.690 6.708 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X61Y505 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.146 6.854 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/O net (fo=76, routed) 1.595 8.449 rx_data_ngccm[43] SLICE_X65Y536 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][63]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.301 10.994 g_gbt_bank[3].gbtbank_n_94 SLICE_X65Y536 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][63]/C clock pessimism 0.210 11.204 clock uncertainty -0.035 11.169 SLICE_X65Y536 FDCE (Setup_EFF_SLICEM_C_CE) -0.055 11.114 SFP_GEN[43].rx_data_ngccm_reg[43][63] ------------------------------------------------------------------- required time 11.114 arrival time -8.449 ------------------------------------------------------------------- slack 2.665 Slack (MET) : 2.665ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][65]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 5.570ns (logic 0.285ns (5.117%) route 5.285ns (94.883%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.008ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.677ns = ( 10.994 - 8.317 ) Source Clock Delay (SCD): 2.879ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.454ns (routing 0.789ns, distribution 1.665ns) Clock Net Delay (Destination): 2.301ns (routing 0.708ns, distribution 1.593ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.454 2.879 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y534 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y534 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.018 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.690 6.708 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X61Y505 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.146 6.854 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/O net (fo=76, routed) 1.595 8.449 rx_data_ngccm[43] SLICE_X65Y536 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][65]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.301 10.994 g_gbt_bank[3].gbtbank_n_94 SLICE_X65Y536 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][65]/C clock pessimism 0.210 11.204 clock uncertainty -0.035 11.169 SLICE_X65Y536 FDCE (Setup_FFF_SLICEM_C_CE) -0.055 11.114 SFP_GEN[43].rx_data_ngccm_reg[43][65] ------------------------------------------------------------------- required time 11.114 arrival time -8.449 ------------------------------------------------------------------- slack 2.665 Slack (MET) : 2.665ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][67]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 5.570ns (logic 0.285ns (5.117%) route 5.285ns (94.883%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.008ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.677ns = ( 10.994 - 8.317 ) Source Clock Delay (SCD): 2.879ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.454ns (routing 0.789ns, distribution 1.665ns) Clock Net Delay (Destination): 2.301ns (routing 0.708ns, distribution 1.593ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.454 2.879 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y534 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y534 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.018 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.690 6.708 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X61Y505 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.146 6.854 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/O net (fo=76, routed) 1.595 8.449 rx_data_ngccm[43] SLICE_X65Y536 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][67]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.301 10.994 g_gbt_bank[3].gbtbank_n_94 SLICE_X65Y536 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][67]/C clock pessimism 0.210 11.204 clock uncertainty -0.035 11.169 SLICE_X65Y536 FDCE (Setup_GFF_SLICEM_C_CE) -0.055 11.114 SFP_GEN[43].rx_data_ngccm_reg[43][67] ------------------------------------------------------------------- required time 11.114 arrival time -8.449 ------------------------------------------------------------------- slack 2.665 Slack (MET) : 2.875ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][75]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 5.353ns (logic 0.285ns (5.324%) route 5.068ns (94.676%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.004ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.673ns = ( 10.990 - 8.317 ) Source Clock Delay (SCD): 2.879ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.454ns (routing 0.789ns, distribution 1.665ns) Clock Net Delay (Destination): 2.297ns (routing 0.708ns, distribution 1.589ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.454 2.879 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y534 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y534 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.018 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.690 6.708 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X61Y505 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.146 6.854 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/O net (fo=76, routed) 1.378 8.232 rx_data_ngccm[43] SLICE_X63Y535 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][75]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.297 10.990 g_gbt_bank[3].gbtbank_n_94 SLICE_X63Y535 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][75]/C clock pessimism 0.210 11.200 clock uncertainty -0.035 11.165 SLICE_X63Y535 FDCE (Setup_EFF2_SLICEL_C_CE) -0.058 11.107 SFP_GEN[43].rx_data_ngccm_reg[43][75] ------------------------------------------------------------------- required time 11.107 arrival time -8.232 ------------------------------------------------------------------- slack 2.875 Slack (MET) : 2.881ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][59]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 5.350ns (logic 0.285ns (5.327%) route 5.065ns (94.673%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.004ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.673ns = ( 10.990 - 8.317 ) Source Clock Delay (SCD): 2.879ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.454ns (routing 0.789ns, distribution 1.665ns) Clock Net Delay (Destination): 2.297ns (routing 0.708ns, distribution 1.589ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.454 2.879 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y534 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y534 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.018 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.690 6.708 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X61Y505 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.146 6.854 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/O net (fo=76, routed) 1.375 8.229 rx_data_ngccm[43] SLICE_X63Y535 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][59]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.297 10.990 g_gbt_bank[3].gbtbank_n_94 SLICE_X63Y535 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][59]/C clock pessimism 0.210 11.200 clock uncertainty -0.035 11.165 SLICE_X63Y535 FDCE (Setup_EFF_SLICEL_C_CE) -0.055 11.110 SFP_GEN[43].rx_data_ngccm_reg[43][59] ------------------------------------------------------------------- required time 11.110 arrival time -8.229 ------------------------------------------------------------------- slack 2.881 Slack (MET) : 2.881ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][79]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 5.350ns (logic 0.285ns (5.327%) route 5.065ns (94.673%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.004ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.673ns = ( 10.990 - 8.317 ) Source Clock Delay (SCD): 2.879ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.454ns (routing 0.789ns, distribution 1.665ns) Clock Net Delay (Destination): 2.297ns (routing 0.708ns, distribution 1.589ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.454 2.879 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y534 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y534 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.018 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.690 6.708 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X61Y505 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.146 6.854 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/O net (fo=76, routed) 1.375 8.229 rx_data_ngccm[43] SLICE_X63Y535 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][79]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.297 10.990 g_gbt_bank[3].gbtbank_n_94 SLICE_X63Y535 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][79]/C clock pessimism 0.210 11.200 clock uncertainty -0.035 11.165 SLICE_X63Y535 FDCE (Setup_FFF_SLICEL_C_CE) -0.055 11.110 SFP_GEN[43].rx_data_ngccm_reg[43][79] ------------------------------------------------------------------- required time 11.110 arrival time -8.229 ------------------------------------------------------------------- slack 2.881 Slack (MET) : 2.926ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][45]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 5.290ns (logic 0.285ns (5.388%) route 5.005ns (94.612%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.011ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.658ns = ( 10.975 - 8.317 ) Source Clock Delay (SCD): 2.879ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.454ns (routing 0.789ns, distribution 1.665ns) Clock Net Delay (Destination): 2.282ns (routing 0.708ns, distribution 1.574ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.454 2.879 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y534 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y534 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.018 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.690 6.708 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X61Y505 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.146 6.854 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/O net (fo=76, routed) 1.315 8.169 rx_data_ngccm[43] SLICE_X64Y533 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][45]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.282 10.975 g_gbt_bank[3].gbtbank_n_94 SLICE_X64Y533 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][45]/C clock pessimism 0.210 11.185 clock uncertainty -0.035 11.150 SLICE_X64Y533 FDCE (Setup_AFF2_SLICEM_C_CE) -0.055 11.095 SFP_GEN[43].rx_data_ngccm_reg[43][45] ------------------------------------------------------------------- required time 11.095 arrival time -8.169 ------------------------------------------------------------------- slack 2.926 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.034ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][1]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.049ns (34.266%) route 0.094ns (65.734%)) Logic Levels: 0 Clock Path Skew: 0.054ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.387ns Source Clock Delay (SCD): 1.142ns Clock Pessimism Removal (CPR): 0.191ns Clock Net Delay (Source): 1.026ns (routing 0.376ns, distribution 0.650ns) Clock Net Delay (Destination): 1.235ns (routing 0.440ns, distribution 0.795ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.026 1.142 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X63Y530 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y530 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.191 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/Q net (fo=1, routed) 0.094 1.285 rx_data[43][1] SLICE_X63Y529 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.235 1.387 g_gbt_bank[3].gbtbank_n_94 SLICE_X63Y529 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][1]/C clock pessimism -0.191 1.196 SLICE_X63Y529 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.251 SFP_GEN[43].rx_data_ngccm_reg[43][1] ------------------------------------------------------------------- required time -1.251 arrival time 1.285 ------------------------------------------------------------------- slack 0.034 Slack (MET) : 0.038ns (arrival time - required time) Source: SFP_GEN[43].rx_data_ngccm_reg[43][37]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[36]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.169ns (logic 0.080ns (47.337%) route 0.089ns (52.663%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.374ns Source Clock Delay (SCD): 1.141ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.025ns (routing 0.376ns, distribution 0.649ns) Clock Net Delay (Destination): 1.222ns (routing 0.440ns, distribution 0.782ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.025 1.141 g_gbt_bank[3].gbtbank_n_94 SLICE_X63Y528 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][37]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y528 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 1.190 r SFP_GEN[43].rx_data_ngccm_reg[43][37]/Q net (fo=1, routed) 0.073 1.263 g_gbt_bank[3].gbtbank/RX_Word_rx40_reg[78]_0[13] SLICE_X64Y528 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.031 1.294 r g_gbt_bank[3].gbtbank/RX_Word_rx40[36]_i_1__9/O net (fo=1, routed) 0.016 1.310 SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[83]_0[22] SLICE_X64Y528 FDCE r SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[36]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.222 1.374 SFP_GEN[43].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X64Y528 FDCE r SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[36]/C clock pessimism -0.158 1.216 SLICE_X64Y528 FDCE (Hold_DFF_SLICEM_C_D) 0.056 1.272 SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[36] ------------------------------------------------------------------- required time -1.272 arrival time 1.310 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[37]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[37]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.148ns (logic 0.049ns (33.108%) route 0.099ns (66.892%)) Logic Levels: 0 Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.373ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.188ns Clock Net Delay (Source): 1.017ns (routing 0.376ns, distribution 0.641ns) Clock Net Delay (Destination): 1.221ns (routing 0.440ns, distribution 0.781ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.133 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y532 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[37]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y532 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.182 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[37]/Q net (fo=1, routed) 0.099 1.281 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0[37] SLICE_X59Y531 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[37]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.221 1.373 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y531 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[37]/C clock pessimism -0.188 1.185 SLICE_X59Y531 FDCE (Hold_GFF_SLICEM_C_D) 0.056 1.241 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[37] ------------------------------------------------------------------- required time -1.241 arrival time 1.281 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[41]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[41]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.152ns (logic 0.048ns (31.579%) route 0.104ns (68.421%)) Logic Levels: 0 Clock Path Skew: 0.055ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.376ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.188ns Clock Net Delay (Source): 1.017ns (routing 0.376ns, distribution 0.641ns) Clock Net Delay (Destination): 1.224ns (routing 0.440ns, distribution 0.784ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.133 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y532 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[41]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y532 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.181 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[41]/Q net (fo=1, routed) 0.104 1.285 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0[41] SLICE_X59Y533 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[41]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.224 1.376 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y533 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[41]/C clock pessimism -0.188 1.188 SLICE_X59Y533 FDCE (Hold_DFF2_SLICEM_C_D) 0.056 1.244 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[41] ------------------------------------------------------------------- required time -1.244 arrival time 1.285 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][64]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.191ns (logic 0.049ns (25.654%) route 0.142ns (74.346%)) Logic Levels: 0 Clock Path Skew: 0.095ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.393ns Source Clock Delay (SCD): 1.141ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.025ns (routing 0.376ns, distribution 0.649ns) Clock Net Delay (Destination): 1.241ns (routing 0.440ns, distribution 0.801ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.025 1.141 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X64Y536 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y536 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 1.190 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/Q net (fo=1, routed) 0.142 1.332 rx_data[43][64] SLICE_X65Y536 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][64]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.241 1.393 g_gbt_bank[3].gbtbank_n_94 SLICE_X65Y536 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][64]/C clock pessimism -0.157 1.236 SLICE_X65Y536 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.291 SFP_GEN[43].rx_data_ngccm_reg[43][64] ------------------------------------------------------------------- required time -1.291 arrival time 1.332 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.041ns (arrival time - required time) Source: SFP_GEN[43].rx_data_ngccm_reg[43][32]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[32]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.102ns (66.234%) route 0.052ns (33.766%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.057ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.389ns Source Clock Delay (SCD): 1.141ns Clock Pessimism Removal (CPR): 0.191ns Clock Net Delay (Source): 1.025ns (routing 0.376ns, distribution 0.649ns) Clock Net Delay (Destination): 1.237ns (routing 0.440ns, distribution 0.797ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.025 1.141 g_gbt_bank[3].gbtbank_n_94 SLICE_X63Y528 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][32]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y528 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.190 r SFP_GEN[43].rx_data_ngccm_reg[43][32]/Q net (fo=1, routed) 0.036 1.226 g_gbt_bank[3].gbtbank/RX_Word_rx40_reg[78]_0[8] SLICE_X63Y527 LUT3 (Prop_D6LUT_SLICEL_I1_O) 0.053 1.279 r g_gbt_bank[3].gbtbank/RX_Word_rx40[32]_i_1__9/O net (fo=1, routed) 0.016 1.295 SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[83]_0[20] SLICE_X63Y527 FDCE r SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[32]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.237 1.389 SFP_GEN[43].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y527 FDCE r SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[32]/C clock pessimism -0.191 1.198 SLICE_X63Y527 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.254 SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[32] ------------------------------------------------------------------- required time -1.254 arrival time 1.295 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[21]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[21]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.049ns (32.886%) route 0.100ns (67.114%)) Logic Levels: 0 Clock Path Skew: 0.051ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.373ns Source Clock Delay (SCD): 1.134ns Clock Pessimism Removal (CPR): 0.188ns Clock Net Delay (Source): 1.018ns (routing 0.376ns, distribution 0.642ns) Clock Net Delay (Destination): 1.221ns (routing 0.440ns, distribution 0.781ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.018 1.134 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y532 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[21]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y532 FDCE (Prop_DFF_SLICEM_C_Q) 0.049 1.183 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[21]/Q net (fo=1, routed) 0.100 1.283 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0[21] SLICE_X59Y531 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.221 1.373 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y531 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[21]/C clock pessimism -0.188 1.185 SLICE_X59Y531 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.240 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[21] ------------------------------------------------------------------- required time -1.240 arrival time 1.283 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][78]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.193ns (logic 0.049ns (25.389%) route 0.144ns (74.611%)) Logic Levels: 0 Clock Path Skew: 0.093ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.391ns Source Clock Delay (SCD): 1.141ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.025ns (routing 0.376ns, distribution 0.649ns) Clock Net Delay (Destination): 1.239ns (routing 0.440ns, distribution 0.799ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.025 1.141 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X64Y534 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y534 FDRE (Prop_DFF2_SLICEM_C_Q) 0.049 1.190 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/Q net (fo=1, routed) 0.144 1.334 rx_data[43][78] SLICE_X63Y534 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][78]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.239 1.391 g_gbt_bank[3].gbtbank_n_94 SLICE_X63Y534 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][78]/C clock pessimism -0.157 1.234 SLICE_X63Y534 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 1.290 SFP_GEN[43].rx_data_ngccm_reg[43][78] ------------------------------------------------------------------- required time -1.290 arrival time 1.334 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][59]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.048ns (31.169%) route 0.106ns (68.831%)) Logic Levels: 0 Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.388ns Source Clock Delay (SCD): 1.145ns Clock Pessimism Removal (CPR): 0.191ns Clock Net Delay (Source): 1.029ns (routing 0.376ns, distribution 0.653ns) Clock Net Delay (Destination): 1.236ns (routing 0.440ns, distribution 0.796ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.029 1.145 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X63Y536 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y536 FDRE (Prop_GFF_SLICEL_C_Q) 0.048 1.193 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/Q net (fo=1, routed) 0.106 1.299 rx_data[43][59] SLICE_X63Y535 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][59]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.236 1.388 g_gbt_bank[3].gbtbank_n_94 SLICE_X63Y535 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][59]/C clock pessimism -0.191 1.197 SLICE_X63Y535 FDCE (Hold_EFF_SLICEL_C_D) 0.056 1.253 SFP_GEN[43].rx_data_ngccm_reg[43][59] ------------------------------------------------------------------- required time -1.253 arrival time 1.299 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][49]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.048ns (33.566%) route 0.095ns (66.434%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.391ns Source Clock Delay (SCD): 1.147ns Clock Pessimism Removal (CPR): 0.204ns Clock Net Delay (Source): 1.031ns (routing 0.376ns, distribution 0.655ns) Clock Net Delay (Destination): 1.239ns (routing 0.440ns, distribution 0.799ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.031 1.147 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X62Y534 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y534 FDRE (Prop_GFF2_SLICEM_C_Q) 0.048 1.195 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/Q net (fo=1, routed) 0.095 1.290 rx_data[43][49] SLICE_X63Y534 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][49]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.239 1.391 g_gbt_bank[3].gbtbank_n_94 SLICE_X63Y534 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][49]/C clock pessimism -0.204 1.187 SLICE_X63Y534 FDCE (Hold_AFF2_SLICEL_C_D) 0.056 1.243 SFP_GEN[43].rx_data_ngccm_reg[43][49] ------------------------------------------------------------------- required time -1.243 arrival time 1.290 ------------------------------------------------------------------- slack 0.047 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_45 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y213 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X62Y480 g_clock_rate_din[43].ngccm_status_cnt_reg[43][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X62Y480 g_clock_rate_din[43].ngccm_status_cnt_reg[43][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X62Y480 g_clock_rate_din[43].ngccm_status_cnt_reg[43][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X62Y480 g_clock_rate_din[43].ngccm_status_cnt_reg[43][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X62Y480 g_clock_rate_din[43].ngccm_status_cnt_reg[43][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X62Y480 g_clock_rate_din[43].ngccm_status_cnt_reg[43][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X63Y481 g_clock_rate_din[43].ngccm_status_cnt_reg[43][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X63Y527 SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[32]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X63Y527 SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[34]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X60Y527 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X60Y527 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X63Y532 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X62Y529 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X65Y539 SFP_GEN[43].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X65Y526 SFP_GEN[43].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X65Y526 SFP_GEN[43].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X65Y526 SFP_GEN[43].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X65Y526 SFP_GEN[43].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X65Y539 SFP_GEN[43].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[66]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_46 To Clock: gtwiz_userclk_rx_srcclk_out[0]_46 Setup : 0 Failing Endpoints, Worst Slack 3.024ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.036ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.024ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 5.303ns (logic 1.546ns (29.153%) route 3.757ns (70.847%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.100ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.621ns = ( 10.938 - 8.317 ) Source Clock Delay (SCD): 2.732ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.307ns (routing 0.793ns, distribution 1.514ns) Clock Net Delay (Destination): 2.245ns (routing 0.709ns, distribution 1.536ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.307 2.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.818 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.821 6.639 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X56Y545 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.090 6.729 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/O net (fo=5, routed) 0.301 7.030 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X56Y544 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.223 7.253 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__43/O net (fo=1, routed) 0.223 7.476 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__43_n_0 SLICE_X57Y544 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 7.623 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__43/O net (fo=2, routed) 0.412 8.035 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__43_n_0 SLICE_X57Y545 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.245 10.938 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X57Y545 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.211 11.150 clock uncertainty -0.035 11.114 SLICE_X57Y545 FDCE (Setup_GFF_SLICEL_C_CE) -0.055 11.059 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.059 arrival time -8.035 ------------------------------------------------------------------- slack 3.024 Slack (MET) : 3.024ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 5.303ns (logic 1.546ns (29.153%) route 3.757ns (70.847%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.100ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.621ns = ( 10.938 - 8.317 ) Source Clock Delay (SCD): 2.732ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.307ns (routing 0.793ns, distribution 1.514ns) Clock Net Delay (Destination): 2.245ns (routing 0.709ns, distribution 1.536ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.307 2.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.818 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.821 6.639 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X56Y545 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.090 6.729 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/O net (fo=5, routed) 0.301 7.030 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X56Y544 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.223 7.253 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__43/O net (fo=1, routed) 0.223 7.476 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__43_n_0 SLICE_X57Y544 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 7.623 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__43/O net (fo=2, routed) 0.412 8.035 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__43_n_0 SLICE_X57Y545 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.245 10.938 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X57Y545 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.211 11.150 clock uncertainty -0.035 11.114 SLICE_X57Y545 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 11.059 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.059 arrival time -8.035 ------------------------------------------------------------------- slack 3.024 Slack (MET) : 3.158ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 5.171ns (logic 1.411ns (27.287%) route 3.760ns (72.713%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.626ns = ( 10.943 - 8.317 ) Source Clock Delay (SCD): 2.732ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.307ns (routing 0.793ns, distribution 1.514ns) Clock Net Delay (Destination): 2.250ns (routing 0.709ns, distribution 1.541ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.307 2.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.818 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.821 6.639 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X56Y545 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.090 6.729 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/O net (fo=5, routed) 0.337 7.066 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X57Y544 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.235 7.301 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/O net (fo=7, routed) 0.602 7.903 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X56Y545 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.250 10.943 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X56Y545 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.211 11.155 clock uncertainty -0.035 11.119 SLICE_X56Y545 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 11.061 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.061 arrival time -7.903 ------------------------------------------------------------------- slack 3.158 Slack (MET) : 3.165ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 5.167ns (logic 1.411ns (27.308%) route 3.756ns (72.692%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.626ns = ( 10.943 - 8.317 ) Source Clock Delay (SCD): 2.732ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.307ns (routing 0.793ns, distribution 1.514ns) Clock Net Delay (Destination): 2.250ns (routing 0.709ns, distribution 1.541ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.307 2.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.818 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.821 6.639 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X56Y545 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.090 6.729 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/O net (fo=5, routed) 0.337 7.066 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X57Y544 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.235 7.301 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/O net (fo=7, routed) 0.598 7.899 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X56Y545 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.250 10.943 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X56Y545 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.211 11.155 clock uncertainty -0.035 11.119 SLICE_X56Y545 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 11.064 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 11.064 arrival time -7.899 ------------------------------------------------------------------- slack 3.165 Slack (MET) : 3.243ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 5.089ns (logic 1.411ns (27.726%) route 3.678ns (72.274%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.629ns = ( 10.946 - 8.317 ) Source Clock Delay (SCD): 2.732ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.307ns (routing 0.793ns, distribution 1.514ns) Clock Net Delay (Destination): 2.253ns (routing 0.709ns, distribution 1.544ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.307 2.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.818 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.821 6.639 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X56Y545 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.090 6.729 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/O net (fo=5, routed) 0.337 7.066 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X57Y544 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.235 7.301 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/O net (fo=7, routed) 0.520 7.821 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X57Y544 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.253 10.946 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X57Y544 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.211 11.158 clock uncertainty -0.035 11.122 SLICE_X57Y544 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 11.064 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.064 arrival time -7.821 ------------------------------------------------------------------- slack 3.243 Slack (MET) : 3.250ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 5.085ns (logic 1.411ns (27.748%) route 3.674ns (72.252%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.629ns = ( 10.946 - 8.317 ) Source Clock Delay (SCD): 2.732ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.307ns (routing 0.793ns, distribution 1.514ns) Clock Net Delay (Destination): 2.253ns (routing 0.709ns, distribution 1.544ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.307 2.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.818 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.821 6.639 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X56Y545 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.090 6.729 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/O net (fo=5, routed) 0.337 7.066 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X57Y544 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.235 7.301 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/O net (fo=7, routed) 0.516 7.817 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X57Y544 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.253 10.946 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X57Y544 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.211 11.158 clock uncertainty -0.035 11.122 SLICE_X57Y544 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 11.067 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.067 arrival time -7.817 ------------------------------------------------------------------- slack 3.250 Slack (MET) : 3.339ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 4.990ns (logic 1.411ns (28.277%) route 3.579ns (71.723%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.626ns = ( 10.943 - 8.317 ) Source Clock Delay (SCD): 2.732ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.307ns (routing 0.793ns, distribution 1.514ns) Clock Net Delay (Destination): 2.250ns (routing 0.709ns, distribution 1.541ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.307 2.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.818 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.821 6.639 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X56Y545 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.090 6.729 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/O net (fo=5, routed) 0.337 7.066 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X57Y544 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.235 7.301 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/O net (fo=7, routed) 0.421 7.722 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X56Y544 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.250 10.943 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X56Y544 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.211 11.155 clock uncertainty -0.035 11.119 SLICE_X56Y544 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 11.061 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 11.061 arrival time -7.722 ------------------------------------------------------------------- slack 3.339 Slack (MET) : 3.339ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 4.990ns (logic 1.411ns (28.277%) route 3.579ns (71.723%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.626ns = ( 10.943 - 8.317 ) Source Clock Delay (SCD): 2.732ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.307ns (routing 0.793ns, distribution 1.514ns) Clock Net Delay (Destination): 2.250ns (routing 0.709ns, distribution 1.541ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.307 2.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.818 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.821 6.639 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X56Y545 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.090 6.729 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/O net (fo=5, routed) 0.337 7.066 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X57Y544 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.235 7.301 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/O net (fo=7, routed) 0.421 7.722 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X56Y544 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.250 10.943 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X56Y544 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.211 11.155 clock uncertainty -0.035 11.119 SLICE_X56Y544 FDRE (Setup_GFF2_SLICEL_C_CE) -0.058 11.061 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 11.061 arrival time -7.722 ------------------------------------------------------------------- slack 3.339 Slack (MET) : 3.361ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 4.974ns (logic 1.411ns (28.368%) route 3.563ns (71.632%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.107ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.628ns = ( 10.945 - 8.317 ) Source Clock Delay (SCD): 2.732ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.307ns (routing 0.793ns, distribution 1.514ns) Clock Net Delay (Destination): 2.252ns (routing 0.709ns, distribution 1.543ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.307 2.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.818 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.821 6.639 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X56Y545 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.090 6.729 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/O net (fo=5, routed) 0.337 7.066 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X57Y544 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.235 7.301 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/O net (fo=7, routed) 0.405 7.706 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X56Y544 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.252 10.945 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X56Y544 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.211 11.157 clock uncertainty -0.035 11.121 SLICE_X56Y544 FDRE (Setup_BFF_SLICEL_C_CE) -0.054 11.067 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 11.067 arrival time -7.706 ------------------------------------------------------------------- slack 3.361 Slack (MET) : 3.506ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[109]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 4.938ns (logic 0.918ns (18.591%) route 4.020ns (81.409%)) Logic Levels: 0 Clock Path Skew: 0.098ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.619ns = ( 10.936 - 8.317 ) Source Clock Delay (SCD): 2.732ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.307ns (routing 0.793ns, distribution 1.514ns) Clock Net Delay (Destination): 2.243ns (routing 0.709ns, distribution 1.534ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.307 2.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXCTRL1[0]) 0.918 3.650 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXCTRL1[0] net (fo=6, routed) 4.020 7.670 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/D[9] SLICE_X59Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[109]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.243 10.936 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X59Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[109]/C clock pessimism 0.211 11.148 clock uncertainty -0.035 11.112 SLICE_X59Y569 FDCE (Setup_EFF_SLICEM_C_D) 0.064 11.176 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[109] ------------------------------------------------------------------- required time 11.176 arrival time -7.670 ------------------------------------------------------------------- slack 3.506 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[44].rx_data_ngccm_reg[44][66]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.178ns (logic 0.048ns (26.966%) route 0.130ns (73.034%)) Logic Levels: 0 Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.372ns Source Clock Delay (SCD): 1.127ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 1.011ns (routing 0.377ns, distribution 0.634ns) Clock Net Delay (Destination): 1.220ns (routing 0.443ns, distribution 0.777ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.011 1.127 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X63Y570 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y570 FDRE (Prop_BFF2_SLICEL_C_Q) 0.048 1.175 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/Q net (fo=1, routed) 0.130 1.305 rx_data[44][66] SLICE_X63Y569 FDCE r SFP_GEN[44].rx_data_ngccm_reg[44][66]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.220 1.372 g_gbt_bank[3].gbtbank_n_104 SLICE_X63Y569 FDCE r SFP_GEN[44].rx_data_ngccm_reg[44][66]/C clock pessimism -0.159 1.213 SLICE_X63Y569 FDCE (Hold_BFF_SLICEL_C_D) 0.056 1.269 SFP_GEN[44].rx_data_ngccm_reg[44][66] ------------------------------------------------------------------- required time -1.269 arrival time 1.305 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.190ns (logic 0.094ns (49.474%) route 0.096ns (50.526%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.098ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.373ns Source Clock Delay (SCD): 1.116ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 1.000ns (routing 0.377ns, distribution 0.623ns) Clock Net Delay (Destination): 1.221ns (routing 0.443ns, distribution 0.778ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.000 1.116 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X61Y568 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y568 FDCE (Prop_AFF2_SLICEM_C_Q) 0.049 1.165 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.084 1.249 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/O85[1] SLICE_X62Y568 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.045 1.294 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__43/O net (fo=1, routed) 0.012 1.306 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/I9[1] SLICE_X62Y568 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.221 1.373 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X62Y568 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C clock pessimism -0.159 1.214 SLICE_X62Y568 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.270 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20] ------------------------------------------------------------------- required time -1.270 arrival time 1.306 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.150ns (logic 0.101ns (67.333%) route 0.049ns (32.667%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.049ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.373ns Source Clock Delay (SCD): 1.130ns Clock Pessimism Removal (CPR): 0.194ns Clock Net Delay (Source): 1.014ns (routing 0.377ns, distribution 0.637ns) Clock Net Delay (Destination): 1.221ns (routing 0.443ns, distribution 0.778ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.130 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X62Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y569 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.179 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.033 1.212 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_35_in SLICE_X62Y568 LUT3 (Prop_C6LUT_SLICEM_I2_O) 0.052 1.264 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__43/O net (fo=1, routed) 0.016 1.280 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] SLICE_X62Y568 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.221 1.373 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X62Y568 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.194 1.179 SLICE_X62Y568 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.235 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.235 arrival time 1.280 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.199ns (logic 0.104ns (52.261%) route 0.095ns (47.739%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.098ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.373ns Source Clock Delay (SCD): 1.116ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 1.000ns (routing 0.377ns, distribution 0.623ns) Clock Net Delay (Destination): 1.221ns (routing 0.443ns, distribution 0.778ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.000 1.116 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X61Y568 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y568 FDCE (Prop_AFF2_SLICEM_C_Q) 0.049 1.165 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.084 1.249 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/O85[1] SLICE_X62Y568 LUT3 (Prop_C5LUT_SLICEM_I2_O) 0.055 1.304 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__43/O net (fo=1, routed) 0.011 1.315 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[18] SLICE_X62Y568 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.221 1.373 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X62Y568 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C clock pessimism -0.159 1.214 SLICE_X62Y568 FDRE (Hold_CFF2_SLICEM_C_D) 0.056 1.270 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18] ------------------------------------------------------------------- required time -1.270 arrival time 1.315 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[44].rx_data_ngccm_reg[44][70]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.171ns (logic 0.048ns (28.070%) route 0.123ns (71.930%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.348ns Source Clock Delay (SCD): 1.119ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 1.003ns (routing 0.377ns, distribution 0.626ns) Clock Net Delay (Destination): 1.196ns (routing 0.443ns, distribution 0.753ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.003 1.119 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X64Y570 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y570 FDRE (Prop_FFF2_SLICEM_C_Q) 0.048 1.167 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/Q net (fo=1, routed) 0.123 1.290 rx_data[44][70] SLICE_X65Y570 FDCE r SFP_GEN[44].rx_data_ngccm_reg[44][70]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.196 1.348 g_gbt_bank[3].gbtbank_n_104 SLICE_X65Y570 FDCE r SFP_GEN[44].rx_data_ngccm_reg[44][70]/C clock pessimism -0.159 1.189 SLICE_X65Y570 FDCE (Hold_AFF2_SLICEM_C_D) 0.056 1.245 SFP_GEN[44].rx_data_ngccm_reg[44][70] ------------------------------------------------------------------- required time -1.245 arrival time 1.290 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: SFP_GEN[44].rx_data_ngccm_reg[44][68]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[44].ngCCM_gbt/RX_Word_rx40_reg[68]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.176ns (logic 0.103ns (58.523%) route 0.073ns (41.477%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.352ns Source Clock Delay (SCD): 1.119ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 1.003ns (routing 0.377ns, distribution 0.626ns) Clock Net Delay (Destination): 1.200ns (routing 0.443ns, distribution 0.757ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.003 1.119 g_gbt_bank[3].gbtbank_n_104 SLICE_X65Y570 FDCE r SFP_GEN[44].rx_data_ngccm_reg[44][68]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y570 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.168 r SFP_GEN[44].rx_data_ngccm_reg[44][68]/Q net (fo=1, routed) 0.057 1.225 SFP_GEN[44].ngCCM_gbt/RX_Word_rx40_reg[83]_0[60] SLICE_X65Y569 LUT3 (Prop_D6LUT_SLICEM_I1_O) 0.054 1.279 r SFP_GEN[44].ngCCM_gbt/RX_Word_rx40[68]_i_1/O net (fo=1, routed) 0.016 1.295 SFP_GEN[44].ngCCM_gbt/RX_Word_rx40[68]_i_1_n_0 SLICE_X65Y569 FDCE r SFP_GEN[44].ngCCM_gbt/RX_Word_rx40_reg[68]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.200 1.352 SFP_GEN[44].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X65Y569 FDCE r SFP_GEN[44].ngCCM_gbt/RX_Word_rx40_reg[68]/C clock pessimism -0.159 1.193 SLICE_X65Y569 FDCE (Hold_DFF_SLICEM_C_D) 0.056 1.249 SFP_GEN[44].ngCCM_gbt/RX_Word_rx40_reg[68] ------------------------------------------------------------------- required time -1.249 arrival time 1.295 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[31]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[31]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.178ns (logic 0.048ns (26.966%) route 0.130ns (73.034%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.337ns Source Clock Delay (SCD): 1.103ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.987ns (routing 0.377ns, distribution 0.610ns) Clock Net Delay (Destination): 1.185ns (routing 0.443ns, distribution 0.742ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.987 1.103 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X56Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[31]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y569 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 1.151 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[31]/Q net (fo=1, routed) 0.130 1.281 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0[31] SLICE_X57Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.185 1.337 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X57Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[31]/C clock pessimism -0.159 1.178 SLICE_X57Y569 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 1.234 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[31] ------------------------------------------------------------------- required time -1.234 arrival time 1.281 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.111ns (logic 0.064ns (57.658%) route 0.047ns (42.342%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.351ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.225ns Clock Net Delay (Source): 1.005ns (routing 0.377ns, distribution 0.628ns) Clock Net Delay (Destination): 1.199ns (routing 0.443ns, distribution 0.756ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.005 1.121 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/CLK SLICE_X57Y543 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y543 FDRE (Prop_AFF_SLICEL_C_Q) 0.049 1.170 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]/Q net (fo=2, routed) 0.035 1.205 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/timer[5] SLICE_X57Y543 LUT6 (Prop_A6LUT_SLICEL_I0_O) 0.015 1.220 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__44/O net (fo=1, routed) 0.012 1.232 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__44_n_0 SLICE_X57Y543 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.199 1.351 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/CLK SLICE_X57Y543 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C clock pessimism -0.225 1.126 SLICE_X57Y543 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.182 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5] ------------------------------------------------------------------- required time -1.182 arrival time 1.232 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.051ns (arrival time - required time) Source: SFP_GEN[44].ngCCM_gbt/pwr_good_pre_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_reg/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.153ns (logic 0.101ns (66.013%) route 0.052ns (33.987%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.046ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.378ns Source Clock Delay (SCD): 1.138ns Clock Pessimism Removal (CPR): 0.194ns Clock Net Delay (Source): 1.022ns (routing 0.377ns, distribution 0.645ns) Clock Net Delay (Destination): 1.226ns (routing 0.443ns, distribution 0.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.022 1.138 SFP_GEN[44].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y562 FDCE r SFP_GEN[44].ngCCM_gbt/pwr_good_pre_reg/C ------------------------------------------------------------------- ------------------- SLICE_X69Y562 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.187 r SFP_GEN[44].ngCCM_gbt/pwr_good_pre_reg/Q net (fo=1, routed) 0.036 1.223 SFP_GEN[44].ngCCM_gbt/pwr_good_pre SLICE_X69Y561 LUT4 (Prop_C6LUT_SLICEL_I1_O) 0.052 1.275 r SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_i_1__45/O net (fo=1, routed) 0.016 1.291 SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_i_1__45_n_0 SLICE_X69Y561 FDRE r SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.226 1.378 SFP_GEN[44].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y561 FDRE r SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_reg/C clock pessimism -0.194 1.184 SLICE_X69Y561 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.240 SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_reg ------------------------------------------------------------------- required time -1.240 arrival time 1.291 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.111ns (logic 0.064ns (57.658%) route 0.047ns (42.342%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.004ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.355ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.230ns Clock Net Delay (Source): 1.005ns (routing 0.377ns, distribution 0.628ns) Clock Net Delay (Destination): 1.203ns (routing 0.443ns, distribution 0.760ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.005 1.121 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/CLK SLICE_X56Y543 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X56Y543 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.170 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_reg/Q net (fo=2, routed) 0.035 1.205 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/rxslide_in[0] SLICE_X56Y543 LUT3 (Prop_E6LUT_SLICEL_I2_O) 0.015 1.220 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__43/O net (fo=1, routed) 0.012 1.232 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__43_n_0 SLICE_X56Y543 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.203 1.355 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/CLK SLICE_X56Y543 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C clock pessimism -0.230 1.125 SLICE_X56Y543 FDCE (Hold_EFF_SLICEL_C_D) 0.056 1.181 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_reg ------------------------------------------------------------------- required time -1.181 arrival time 1.232 ------------------------------------------------------------------- slack 0.051 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_46 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y235 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X63Y541 g_clock_rate_din[44].ngccm_status_cnt_reg[44][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X64Y542 g_clock_rate_din[44].ngccm_status_cnt_reg[44][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X64Y542 g_clock_rate_din[44].ngccm_status_cnt_reg[44][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X64Y542 g_clock_rate_din[44].ngccm_status_cnt_reg[44][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X64Y542 g_clock_rate_din[44].ngccm_status_cnt_reg[44][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X64Y542 g_clock_rate_din[44].ngccm_status_cnt_reg[44][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X66Y541 g_clock_rate_din[44].ngccm_status_cnt_reg[44][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X64Y568 SFP_GEN[44].ngCCM_gbt/RX_Word_rx40_reg[76]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X64Y568 SFP_GEN[44].ngCCM_gbt/RX_Word_rx40_reg[78]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X58Y563 SFP_GEN[44].rx_data_ngccm_reg[44][32]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X58Y563 SFP_GEN[44].rx_data_ngccm_reg[44][35]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X58Y563 SFP_GEN[44].rx_data_ngccm_reg[44][36]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X58Y563 SFP_GEN[44].rx_data_ngccm_reg[44][37]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X64Y542 g_clock_rate_din[44].ngccm_status_cnt_reg[44][1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X64Y542 g_clock_rate_din[44].ngccm_status_cnt_reg[44][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X64Y542 g_clock_rate_din[44].ngccm_status_cnt_reg[44][3]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X64Y542 g_clock_rate_din[44].ngccm_status_cnt_reg[44][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X64Y542 g_clock_rate_din[44].ngccm_status_cnt_reg[44][5]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X68Y558 SFP_GEN[44].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_47 To Clock: gtwiz_userclk_rx_srcclk_out[0]_47 Setup : 0 Failing Endpoints, Worst Slack 3.309ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.031ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.309ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[11]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 4.883ns (logic 0.958ns (19.619%) route 3.925ns (80.381%)) Logic Levels: 5 (LUT2=1 LUT4=1 LUT6=3) Clock Path Skew: -0.153ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.296ns = ( 10.613 - 8.317 ) Source Clock Delay (SCD): 2.650ns Clock Pessimism Removal (CPR): 0.201ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.225ns (routing 0.773ns, distribution 1.452ns) Clock Net Delay (Destination): 1.920ns (routing 0.695ns, distribution 1.225ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.225 2.650 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X45Y560 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X45Y560 FDCE (Prop_GFF2_SLICEL_C_Q) 0.139 2.789 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[11]/Q net (fo=12, routed) 0.564 3.353 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/Q[7] SLICE_X42Y563 LUT2 (Prop_D5LUT_SLICEM_I0_O) 0.265 3.618 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___6_i_5__44/O net (fo=2, routed) 0.637 4.255 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___6_i_5__44_n_0 SLICE_X45Y565 LUT6 (Prop_G6LUT_SLICEL_I1_O) 0.147 4.402 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___32_i_2__44/O net (fo=36, routed) 1.484 5.886 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/s2_from_syndromes[1] SLICE_X48Y559 LUT4 (Prop_C6LUT_SLICEL_I0_O) 0.088 5.974 f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/i___38_i_1__44/O net (fo=22, routed) 0.954 6.928 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___32_i_5__44_0 SLICE_X47Y562 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 7.101 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__89/O net (fo=1, routed) 0.251 7.352 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__89_n_0 SLICE_X46Y561 LUT6 (Prop_D6LUT_SLICEL_I3_O) 0.146 7.498 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__89/O net (fo=1, routed) 0.035 7.533 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg_1 SLICE_X46Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.920 10.613 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/CLK SLICE_X46Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C clock pessimism 0.201 10.814 clock uncertainty -0.035 10.779 SLICE_X46Y561 FDRE (Setup_DFF_SLICEL_C_D) 0.063 10.842 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg ------------------------------------------------------------------- required time 10.842 arrival time -7.533 ------------------------------------------------------------------- slack 3.309 Slack (MET) : 4.098ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 3.970ns (logic 1.650ns (41.562%) route 2.320ns (58.438%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.160ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.318ns = ( 10.635 - 8.317 ) Source Clock Delay (SCD): 2.678ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.253ns (routing 0.773ns, distribution 1.480ns) Clock Net Delay (Destination): 1.942ns (routing 0.695ns, distribution 1.247ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.253 2.678 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.764 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.519 5.283 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X33Y556 LUT4 (Prop_A6LUT_SLICEL_I0_O) 0.166 5.449 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__44/O net (fo=5, routed) 0.283 5.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X34Y555 LUT4 (Prop_B6LUT_SLICEM_I2_O) 0.225 5.957 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__44/O net (fo=1, routed) 0.086 6.043 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__44_n_0 SLICE_X34Y555 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 6.216 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__44/O net (fo=2, routed) 0.432 6.648 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__44_n_0 SLICE_X34Y556 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.942 10.635 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X34Y556 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.200 10.835 clock uncertainty -0.035 10.800 SLICE_X34Y556 FDCE (Setup_DFF_SLICEM_C_CE) -0.054 10.746 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.746 arrival time -6.648 ------------------------------------------------------------------- slack 4.098 Slack (MET) : 4.113ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[83]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 4.055ns (logic 1.161ns (28.631%) route 2.894ns (71.369%)) Logic Levels: 0 Clock Path Skew: -0.177ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.301ns = ( 10.618 - 8.317 ) Source Clock Delay (SCD): 2.678ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.253ns (routing 0.773ns, distribution 1.480ns) Clock Net Delay (Destination): 1.925ns (routing 0.695ns, distribution 1.230ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.253 2.678 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.839 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.894 6.733 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/D[3] SLICE_X45Y562 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[83]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.925 10.618 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X45Y562 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[83]/C clock pessimism 0.200 10.818 clock uncertainty -0.035 10.783 SLICE_X45Y562 FDCE (Setup_CFF_SLICEL_C_D) 0.063 10.846 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[83] ------------------------------------------------------------------- required time 10.846 arrival time -6.733 ------------------------------------------------------------------- slack 4.113 Slack (MET) : 4.115ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 3.950ns (logic 1.650ns (41.772%) route 2.300ns (58.228%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.316ns = ( 10.633 - 8.317 ) Source Clock Delay (SCD): 2.678ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.253ns (routing 0.773ns, distribution 1.480ns) Clock Net Delay (Destination): 1.940ns (routing 0.695ns, distribution 1.245ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.253 2.678 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.764 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.519 5.283 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X33Y556 LUT4 (Prop_A6LUT_SLICEL_I0_O) 0.166 5.449 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__44/O net (fo=5, routed) 0.283 5.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X34Y555 LUT4 (Prop_B6LUT_SLICEM_I2_O) 0.225 5.957 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__44/O net (fo=1, routed) 0.086 6.043 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__44_n_0 SLICE_X34Y555 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 6.216 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__44/O net (fo=2, routed) 0.412 6.628 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__44_n_0 SLICE_X34Y557 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.940 10.633 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X34Y557 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.200 10.833 clock uncertainty -0.035 10.798 SLICE_X34Y557 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 10.743 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.743 arrival time -6.628 ------------------------------------------------------------------- slack 4.115 Slack (MET) : 4.202ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[3]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 3.964ns (logic 1.161ns (29.289%) route 2.803ns (70.711%)) Logic Levels: 0 Clock Path Skew: -0.179ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.299ns = ( 10.616 - 8.317 ) Source Clock Delay (SCD): 2.678ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.253ns (routing 0.773ns, distribution 1.480ns) Clock Net Delay (Destination): 1.923ns (routing 0.695ns, distribution 1.228ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.253 2.678 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.839 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.803 6.642 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/D[3] SLICE_X45Y562 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.923 10.616 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X45Y562 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[3]/C clock pessimism 0.200 10.816 clock uncertainty -0.035 10.781 SLICE_X45Y562 FDCE (Setup_FFF_SLICEL_C_D) 0.063 10.844 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[3] ------------------------------------------------------------------- required time 10.844 arrival time -6.642 ------------------------------------------------------------------- slack 4.202 Slack (MET) : 4.383ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[43]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 3.783ns (logic 1.161ns (30.690%) route 2.622ns (69.310%)) Logic Levels: 0 Clock Path Skew: -0.180ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.298ns = ( 10.615 - 8.317 ) Source Clock Delay (SCD): 2.678ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.253ns (routing 0.773ns, distribution 1.480ns) Clock Net Delay (Destination): 1.922ns (routing 0.695ns, distribution 1.227ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.253 2.678 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.839 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.622 6.461 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/D[3] SLICE_X45Y563 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[43]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.922 10.615 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X45Y563 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[43]/C clock pessimism 0.200 10.815 clock uncertainty -0.035 10.780 SLICE_X45Y563 FDCE (Setup_GFF_SLICEL_C_D) 0.064 10.844 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[43] ------------------------------------------------------------------- required time 10.844 arrival time -6.461 ------------------------------------------------------------------- slack 4.383 Slack (MET) : 4.389ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 3.663ns (logic 1.345ns (36.719%) route 2.318ns (63.281%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.172ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.306ns = ( 10.623 - 8.317 ) Source Clock Delay (SCD): 2.678ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.253ns (routing 0.773ns, distribution 1.480ns) Clock Net Delay (Destination): 1.930ns (routing 0.695ns, distribution 1.235ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.253 2.678 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.764 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.519 5.283 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X33Y556 LUT4 (Prop_A6LUT_SLICEL_I0_O) 0.166 5.449 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__44/O net (fo=5, routed) 0.199 5.648 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X34Y555 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.093 5.741 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__45/O net (fo=7, routed) 0.600 6.341 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 SLICE_X34Y559 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.930 10.623 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X34Y559 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.200 10.823 clock uncertainty -0.035 10.788 SLICE_X34Y559 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 10.730 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 10.730 arrival time -6.341 ------------------------------------------------------------------- slack 4.389 Slack (MET) : 4.390ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[16]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 3.776ns (logic 1.087ns (28.787%) route 2.689ns (71.213%)) Logic Levels: 0 Clock Path Skew: -0.179ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.299ns = ( 10.616 - 8.317 ) Source Clock Delay (SCD): 2.678ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.253ns (routing 0.773ns, distribution 1.480ns) Clock Net Delay (Destination): 1.923ns (routing 0.695ns, distribution 1.228ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.253 2.678 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[14]) 1.087 3.765 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[14] net (fo=6, routed) 2.689 6.454 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/D[16] SLICE_X45Y562 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.923 10.616 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X45Y562 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[16]/C clock pessimism 0.200 10.816 clock uncertainty -0.035 10.781 SLICE_X45Y562 FDCE (Setup_HFF_SLICEL_C_D) 0.063 10.844 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[16] ------------------------------------------------------------------- required time 10.844 arrival time -6.454 ------------------------------------------------------------------- slack 4.390 Slack (MET) : 4.395ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 3.660ns (logic 1.345ns (36.749%) route 2.315ns (63.251%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.172ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.306ns = ( 10.623 - 8.317 ) Source Clock Delay (SCD): 2.678ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.253ns (routing 0.773ns, distribution 1.480ns) Clock Net Delay (Destination): 1.930ns (routing 0.695ns, distribution 1.235ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.253 2.678 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.764 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.519 5.283 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X33Y556 LUT4 (Prop_A6LUT_SLICEL_I0_O) 0.166 5.449 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__44/O net (fo=5, routed) 0.199 5.648 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X34Y555 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.093 5.741 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__45/O net (fo=7, routed) 0.597 6.338 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 SLICE_X34Y559 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.930 10.623 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X34Y559 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.200 10.823 clock uncertainty -0.035 10.788 SLICE_X34Y559 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 10.733 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 10.733 arrival time -6.338 ------------------------------------------------------------------- slack 4.395 Slack (MET) : 4.395ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 3.660ns (logic 1.345ns (36.749%) route 2.315ns (63.251%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.172ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.306ns = ( 10.623 - 8.317 ) Source Clock Delay (SCD): 2.678ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.253ns (routing 0.773ns, distribution 1.480ns) Clock Net Delay (Destination): 1.930ns (routing 0.695ns, distribution 1.235ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.253 2.678 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.764 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.519 5.283 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X33Y556 LUT4 (Prop_A6LUT_SLICEL_I0_O) 0.166 5.449 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__44/O net (fo=5, routed) 0.199 5.648 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X34Y555 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.093 5.741 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__45/O net (fo=7, routed) 0.597 6.338 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 SLICE_X34Y559 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.930 10.623 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X34Y559 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.200 10.823 clock uncertainty -0.035 10.788 SLICE_X34Y559 FDRE (Setup_GFF_SLICEM_C_CE) -0.055 10.733 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 10.733 arrival time -6.338 ------------------------------------------------------------------- slack 4.395 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.031ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[45].rx_data_ngccm_reg[45][46]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.048ns (33.566%) route 0.095ns (66.434%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.204ns Source Clock Delay (SCD): 0.978ns Clock Pessimism Removal (CPR): 0.170ns Clock Net Delay (Source): 0.862ns (routing 0.368ns, distribution 0.494ns) Clock Net Delay (Destination): 1.052ns (routing 0.430ns, distribution 0.622ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.862 0.978 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X40Y560 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y560 FDRE (Prop_GFF_SLICEL_C_Q) 0.048 1.026 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/Q net (fo=1, routed) 0.095 1.121 rx_data[45][46] SLICE_X40Y561 FDCE r SFP_GEN[45].rx_data_ngccm_reg[45][46]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.052 1.204 g_gbt_bank[3].gbtbank_n_114 SLICE_X40Y561 FDCE r SFP_GEN[45].rx_data_ngccm_reg[45][46]/C clock pessimism -0.170 1.034 SLICE_X40Y561 FDCE (Hold_AFF2_SLICEL_C_D) 0.056 1.090 SFP_GEN[45].rx_data_ngccm_reg[45][46] ------------------------------------------------------------------- required time -1.090 arrival time 1.121 ------------------------------------------------------------------- slack 0.031 Slack (MET) : 0.032ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[45].rx_data_ngccm_reg[45][69]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.171ns (logic 0.048ns (28.070%) route 0.123ns (71.930%)) Logic Levels: 0 Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.203ns Source Clock Delay (SCD): 0.979ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 0.863ns (routing 0.368ns, distribution 0.495ns) Clock Net Delay (Destination): 1.051ns (routing 0.430ns, distribution 0.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.863 0.979 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X38Y563 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y563 FDRE (Prop_CFF2_SLICEL_C_Q) 0.048 1.027 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/Q net (fo=1, routed) 0.123 1.150 rx_data[45][69] SLICE_X39Y563 FDCE r SFP_GEN[45].rx_data_ngccm_reg[45][69]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.051 1.203 g_gbt_bank[3].gbtbank_n_114 SLICE_X39Y563 FDCE r SFP_GEN[45].rx_data_ngccm_reg[45][69]/C clock pessimism -0.141 1.062 SLICE_X39Y563 FDCE (Hold_BFF_SLICEM_C_D) 0.056 1.118 SFP_GEN[45].rx_data_ngccm_reg[45][69] ------------------------------------------------------------------- required time -1.118 arrival time 1.150 ------------------------------------------------------------------- slack 0.032 Slack (MET) : 0.043ns (arrival time - required time) Source: SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[29]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[45].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.174ns (logic 0.048ns (27.586%) route 0.126ns (72.414%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.198ns Source Clock Delay (SCD): 0.982ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 0.866ns (routing 0.368ns, distribution 0.498ns) Clock Net Delay (Destination): 1.046ns (routing 0.430ns, distribution 0.616ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.866 0.982 SFP_GEN[45].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X46Y553 FDCE r SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[29]/C ------------------------------------------------------------------- ------------------- SLICE_X46Y553 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.030 r SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[29]/Q net (fo=2, routed) 0.126 1.156 SFP_GEN[45].ngCCM_gbt/gbt_rx_checker/Q[13] SLICE_X47Y553 FDRE r SFP_GEN[45].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.046 1.198 SFP_GEN[45].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X47Y553 FDRE r SFP_GEN[45].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/C clock pessimism -0.141 1.057 SLICE_X47Y553 FDRE (Hold_BFF_SLICEM_C_D) 0.056 1.113 SFP_GEN[45].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13] ------------------------------------------------------------------- required time -1.113 arrival time 1.156 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[45].rx_data_ngccm_reg[45][51]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.156ns (logic 0.048ns (30.769%) route 0.108ns (69.231%)) Logic Levels: 0 Clock Path Skew: 0.054ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.204ns Source Clock Delay (SCD): 0.980ns Clock Pessimism Removal (CPR): 0.170ns Clock Net Delay (Source): 0.864ns (routing 0.368ns, distribution 0.496ns) Clock Net Delay (Destination): 1.052ns (routing 0.430ns, distribution 0.622ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.864 0.980 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X40Y560 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y560 FDRE (Prop_CFF2_SLICEL_C_Q) 0.048 1.028 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/Q net (fo=1, routed) 0.108 1.136 rx_data[45][51] SLICE_X40Y561 FDCE r SFP_GEN[45].rx_data_ngccm_reg[45][51]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.052 1.204 g_gbt_bank[3].gbtbank_n_114 SLICE_X40Y561 FDCE r SFP_GEN[45].rx_data_ngccm_reg[45][51]/C clock pessimism -0.170 1.034 SLICE_X40Y561 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.090 SFP_GEN[45].rx_data_ngccm_reg[45][51] ------------------------------------------------------------------- required time -1.090 arrival time 1.136 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[45].rx_data_ngccm_reg[45][63]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.186ns (logic 0.049ns (26.344%) route 0.137ns (73.656%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.204ns Source Clock Delay (SCD): 0.979ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 0.863ns (routing 0.368ns, distribution 0.495ns) Clock Net Delay (Destination): 1.052ns (routing 0.430ns, distribution 0.622ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.863 0.979 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X38Y563 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y563 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.028 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/Q net (fo=1, routed) 0.137 1.165 rx_data[45][63] SLICE_X40Y561 FDCE r SFP_GEN[45].rx_data_ngccm_reg[45][63]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.052 1.204 g_gbt_bank[3].gbtbank_n_114 SLICE_X40Y561 FDCE r SFP_GEN[45].rx_data_ngccm_reg[45][63]/C clock pessimism -0.141 1.063 SLICE_X40Y561 FDCE (Hold_DFF2_SLICEL_C_D) 0.056 1.119 SFP_GEN[45].rx_data_ngccm_reg[45][63] ------------------------------------------------------------------- required time -1.119 arrival time 1.165 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: SFP_GEN[45].ngCCM_gbt/pwr_good_pre_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[45].ngCCM_gbt/pwr_good_cnt_reg/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.064ns (43.537%) route 0.083ns (56.463%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.198ns Source Clock Delay (SCD): 0.984ns Clock Pessimism Removal (CPR): 0.170ns Clock Net Delay (Source): 0.868ns (routing 0.368ns, distribution 0.500ns) Clock Net Delay (Destination): 1.046ns (routing 0.430ns, distribution 0.616ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.868 0.984 SFP_GEN[45].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X46Y548 FDCE r SFP_GEN[45].ngCCM_gbt/pwr_good_pre_reg/C ------------------------------------------------------------------- ------------------- SLICE_X46Y548 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 1.033 r SFP_GEN[45].ngCCM_gbt/pwr_good_pre_reg/Q net (fo=1, routed) 0.067 1.100 SFP_GEN[45].ngCCM_gbt/pwr_good_pre SLICE_X46Y549 LUT4 (Prop_C6LUT_SLICEL_I1_O) 0.015 1.115 r SFP_GEN[45].ngCCM_gbt/pwr_good_cnt_i_1__11/O net (fo=1, routed) 0.016 1.131 SFP_GEN[45].ngCCM_gbt/pwr_good_cnt_i_1__11_n_0 SLICE_X46Y549 FDRE r SFP_GEN[45].ngCCM_gbt/pwr_good_cnt_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.046 1.198 SFP_GEN[45].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X46Y549 FDRE r SFP_GEN[45].ngCCM_gbt/pwr_good_cnt_reg/C clock pessimism -0.170 1.028 SLICE_X46Y549 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.084 SFP_GEN[45].ngCCM_gbt/pwr_good_cnt_reg ------------------------------------------------------------------- required time -1.084 arrival time 1.131 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.192ns (logic 0.064ns (33.333%) route 0.128ns (66.667%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.211ns Source Clock Delay (SCD): 0.981ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 0.865ns (routing 0.368ns, distribution 0.497ns) Clock Net Delay (Destination): 1.059ns (routing 0.430ns, distribution 0.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.865 0.981 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X41Y551 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y551 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.030 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.112 1.142 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_33_in SLICE_X42Y551 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.015 1.157 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__44/O net (fo=1, routed) 0.016 1.173 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[17] SLICE_X42Y551 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.059 1.211 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X42Y551 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.141 1.070 SLICE_X42Y551 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.126 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.126 arrival time 1.173 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: SFP_GEN[45].rx_data_ngccm_reg[45][35]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[34]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.164ns (logic 0.086ns (52.439%) route 0.078ns (47.561%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.211ns Source Clock Delay (SCD): 0.982ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 0.866ns (routing 0.368ns, distribution 0.498ns) Clock Net Delay (Destination): 1.059ns (routing 0.430ns, distribution 0.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.866 0.982 g_gbt_bank[3].gbtbank_n_114 SLICE_X43Y550 FDCE r SFP_GEN[45].rx_data_ngccm_reg[45][35]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y550 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.030 r SFP_GEN[45].rx_data_ngccm_reg[45][35]/Q net (fo=1, routed) 0.067 1.097 SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[83]_0[27] SLICE_X43Y549 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.038 1.135 r SFP_GEN[45].ngCCM_gbt/RX_Word_rx40[34]_i_1/O net (fo=1, routed) 0.011 1.146 SFP_GEN[45].ngCCM_gbt/RX_Word_rx40[34]_i_1_n_0 SLICE_X43Y549 FDCE r SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[34]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.059 1.211 SFP_GEN[45].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y549 FDCE r SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[34]/C clock pessimism -0.169 1.042 SLICE_X43Y549 FDCE (Hold_DFF2_SLICEL_C_D) 0.056 1.098 SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[34] ------------------------------------------------------------------- required time -1.098 arrival time 1.146 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[45].rx_data_ngccm_reg[45][0]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.156ns (logic 0.049ns (31.410%) route 0.107ns (68.590%)) Logic Levels: 0 Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.205ns Source Clock Delay (SCD): 0.983ns Clock Pessimism Removal (CPR): 0.170ns Clock Net Delay (Source): 0.867ns (routing 0.368ns, distribution 0.499ns) Clock Net Delay (Destination): 1.053ns (routing 0.430ns, distribution 0.623ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.867 0.983 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X40Y549 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y549 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.032 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/Q net (fo=1, routed) 0.107 1.139 rx_data[45][0] SLICE_X40Y548 FDCE r SFP_GEN[45].rx_data_ngccm_reg[45][0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.053 1.205 g_gbt_bank[3].gbtbank_n_114 SLICE_X40Y548 FDCE r SFP_GEN[45].rx_data_ngccm_reg[45][0]/C clock pessimism -0.170 1.035 SLICE_X40Y548 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.091 SFP_GEN[45].rx_data_ngccm_reg[45][0] ------------------------------------------------------------------- required time -1.091 arrival time 1.139 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[32]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[32]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.159ns (logic 0.048ns (30.189%) route 0.111ns (69.811%)) Logic Levels: 0 Clock Path Skew: 0.055ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.202ns Source Clock Delay (SCD): 0.978ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 0.862ns (routing 0.368ns, distribution 0.494ns) Clock Net Delay (Destination): 1.050ns (routing 0.430ns, distribution 0.620ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.862 0.978 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X42Y558 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[32]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y558 FDCE (Prop_CFF_SLICEM_C_Q) 0.048 1.026 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[32]/Q net (fo=1, routed) 0.111 1.137 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0[32] SLICE_X42Y560 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.050 1.202 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X42Y560 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[32]/C clock pessimism -0.169 1.033 SLICE_X42Y560 FDCE (Hold_FFF2_SLICEM_C_D) 0.055 1.088 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[32] ------------------------------------------------------------------- required time -1.088 arrival time 1.137 ------------------------------------------------------------------- slack 0.049 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_47 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y233 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y541 g_clock_rate_din[45].ngccm_status_cnt_reg[45][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y541 g_clock_rate_din[45].ngccm_status_cnt_reg[45][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y541 g_clock_rate_din[45].ngccm_status_cnt_reg[45][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y541 g_clock_rate_din[45].ngccm_status_cnt_reg[45][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y541 g_clock_rate_din[45].ngccm_status_cnt_reg[45][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y541 g_clock_rate_din[45].ngccm_status_cnt_reg[45][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y541 g_clock_rate_din[45].ngccm_status_cnt_reg[45][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X38Y545 SFP_GEN[45].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X38Y545 SFP_GEN[45].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X46Y549 SFP_GEN[45].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X46Y549 SFP_GEN[45].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X46Y549 SFP_GEN[45].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X46Y549 SFP_GEN[45].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X70Y540 g_clock_rate_din[45].rx_wordclk_div2_reg[45]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X39Y548 SFP_GEN[45].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[46]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X36Y549 SFP_GEN[45].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[58]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X47Y552 SFP_GEN[45].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X47Y553 SFP_GEN[45].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[12]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X47Y553 SFP_GEN[45].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: rxoutclk_out[0]_1 To Clock: rxoutclk_out[0]_1 Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 1.532ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: rxoutclk_out[0]_1 Waveform(ns): { 0.000 1.559 } Period(ns): 3.119 Sources: { i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG_GT/I n/a 1.587 3.119 1.532 BUFG_GT_X1Y1 i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I --------------------------------------------------------------------------------------------------- From Clock: TTC_rxusrclk To Clock: TTC_rxusrclk Setup : 0 Failing Endpoints, Worst Slack 0.160ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.033ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.407ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.160ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[5]/CE (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.833ns (logic 0.138ns (4.871%) route 2.695ns (95.129%)) Logic Levels: 0 Clock Path Skew: -0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.694ns = ( 6.813 - 3.119 ) Source Clock Delay (SCD): 3.888ns Clock Pessimism Removal (CPR): 0.157ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.888ns (routing 1.620ns, distribution 2.268ns) Clock Net Delay (Destination): 3.694ns (routing 1.478ns, distribution 2.216ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.888 3.888 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X108Y78 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y78 FDCE (Prop_EFF2_SLICEL_C_Q) 0.138 4.026 r i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/Q net (fo=708, routed) 2.695 6.721 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[233]_0 SLICE_X137Y25 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y1 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.694 6.813 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/rxusrclk_out SLICE_X137Y25 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[5]/C clock pessimism 0.157 6.970 clock uncertainty -0.035 6.935 SLICE_X137Y25 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 6.881 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[5] ------------------------------------------------------------------- required time 6.881 arrival time -6.721 ------------------------------------------------------------------- slack 0.160 Slack (MET) : 0.160ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[95]/CE (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.833ns (logic 0.138ns (4.871%) route 2.695ns (95.129%)) Logic Levels: 0 Clock Path Skew: -0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.694ns = ( 6.813 - 3.119 ) Source Clock Delay (SCD): 3.888ns Clock Pessimism Removal (CPR): 0.157ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.888ns (routing 1.620ns, distribution 2.268ns) Clock Net Delay (Destination): 3.694ns (routing 1.478ns, distribution 2.216ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.888 3.888 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X108Y78 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y78 FDCE (Prop_EFF2_SLICEL_C_Q) 0.138 4.026 r i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/Q net (fo=708, routed) 2.695 6.721 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[233]_0 SLICE_X137Y25 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[95]/CE ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y1 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.694 6.813 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/rxusrclk_out SLICE_X137Y25 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[95]/C clock pessimism 0.157 6.970 clock uncertainty -0.035 6.935 SLICE_X137Y25 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 6.881 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[95] ------------------------------------------------------------------- required time 6.881 arrival time -6.721 ------------------------------------------------------------------- slack 0.160 Slack (MET) : 0.167ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[19]/CE (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.828ns (logic 0.138ns (4.880%) route 2.690ns (95.120%)) Logic Levels: 0 Clock Path Skew: -0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.700ns = ( 6.819 - 3.119 ) Source Clock Delay (SCD): 3.888ns Clock Pessimism Removal (CPR): 0.157ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.888ns (routing 1.620ns, distribution 2.268ns) Clock Net Delay (Destination): 3.700ns (routing 1.478ns, distribution 2.222ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.888 3.888 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X108Y78 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y78 FDCE (Prop_EFF2_SLICEL_C_Q) 0.138 4.026 r i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/Q net (fo=708, routed) 2.690 6.716 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[0]_0 SLICE_X135Y30 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[19]/CE ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y1 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.700 6.819 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/rxusrclk_out SLICE_X135Y30 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[19]/C clock pessimism 0.157 6.976 clock uncertainty -0.035 6.941 SLICE_X135Y30 FDRE (Setup_EFF2_SLICEL_C_CE) -0.058 6.883 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[19] ------------------------------------------------------------------- required time 6.883 arrival time -6.716 ------------------------------------------------------------------- slack 0.167 Slack (MET) : 0.167ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[57]/CE (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.828ns (logic 0.138ns (4.880%) route 2.690ns (95.120%)) Logic Levels: 0 Clock Path Skew: -0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.700ns = ( 6.819 - 3.119 ) Source Clock Delay (SCD): 3.888ns Clock Pessimism Removal (CPR): 0.157ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.888ns (routing 1.620ns, distribution 2.268ns) Clock Net Delay (Destination): 3.700ns (routing 1.478ns, distribution 2.222ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.888 3.888 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X108Y78 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y78 FDCE (Prop_EFF2_SLICEL_C_Q) 0.138 4.026 r i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/Q net (fo=708, routed) 2.690 6.716 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[0]_0 SLICE_X135Y30 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[57]/CE ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y1 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.700 6.819 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/rxusrclk_out SLICE_X135Y30 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[57]/C clock pessimism 0.157 6.976 clock uncertainty -0.035 6.941 SLICE_X135Y30 FDRE (Setup_FFF2_SLICEL_C_CE) -0.058 6.883 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[57] ------------------------------------------------------------------- required time 6.883 arrival time -6.716 ------------------------------------------------------------------- slack 0.167 Slack (MET) : 0.167ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[12]/CE (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.828ns (logic 0.138ns (4.880%) route 2.690ns (95.120%)) Logic Levels: 0 Clock Path Skew: -0.035ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.696ns = ( 6.815 - 3.119 ) Source Clock Delay (SCD): 3.888ns Clock Pessimism Removal (CPR): 0.157ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.888ns (routing 1.620ns, distribution 2.268ns) Clock Net Delay (Destination): 3.696ns (routing 1.478ns, distribution 2.218ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.888 3.888 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X108Y78 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y78 FDCE (Prop_EFF2_SLICEL_C_Q) 0.138 4.026 r i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/Q net (fo=708, routed) 2.690 6.716 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[0]_0 SLICE_X135Y31 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[12]/CE ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y1 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.696 6.815 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/rxusrclk_out SLICE_X135Y31 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[12]/C clock pessimism 0.157 6.972 clock uncertainty -0.035 6.937 SLICE_X135Y31 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 6.883 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[12] ------------------------------------------------------------------- required time 6.883 arrival time -6.716 ------------------------------------------------------------------- slack 0.167 Slack (MET) : 0.167ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[31]/CE (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.828ns (logic 0.138ns (4.880%) route 2.690ns (95.120%)) Logic Levels: 0 Clock Path Skew: -0.035ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.696ns = ( 6.815 - 3.119 ) Source Clock Delay (SCD): 3.888ns Clock Pessimism Removal (CPR): 0.157ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.888ns (routing 1.620ns, distribution 2.268ns) Clock Net Delay (Destination): 3.696ns (routing 1.478ns, distribution 2.218ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.888 3.888 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X108Y78 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y78 FDCE (Prop_EFF2_SLICEL_C_Q) 0.138 4.026 r i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/Q net (fo=708, routed) 2.690 6.716 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[0]_0 SLICE_X135Y31 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[31]/CE ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y1 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.696 6.815 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/rxusrclk_out SLICE_X135Y31 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[31]/C clock pessimism 0.157 6.972 clock uncertainty -0.035 6.937 SLICE_X135Y31 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 6.883 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[31] ------------------------------------------------------------------- required time 6.883 arrival time -6.716 ------------------------------------------------------------------- slack 0.167 Slack (MET) : 0.167ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[47]/CE (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.828ns (logic 0.138ns (4.880%) route 2.690ns (95.120%)) Logic Levels: 0 Clock Path Skew: -0.035ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.696ns = ( 6.815 - 3.119 ) Source Clock Delay (SCD): 3.888ns Clock Pessimism Removal (CPR): 0.157ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.888ns (routing 1.620ns, distribution 2.268ns) Clock Net Delay (Destination): 3.696ns (routing 1.478ns, distribution 2.218ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.888 3.888 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X108Y78 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y78 FDCE (Prop_EFF2_SLICEL_C_Q) 0.138 4.026 r i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/Q net (fo=708, routed) 2.690 6.716 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[0]_0 SLICE_X135Y31 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[47]/CE ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y1 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.696 6.815 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/rxusrclk_out SLICE_X135Y31 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[47]/C clock pessimism 0.157 6.972 clock uncertainty -0.035 6.937 SLICE_X135Y31 FDRE (Setup_BFF_SLICEL_C_CE) -0.054 6.883 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[47] ------------------------------------------------------------------- required time 6.883 arrival time -6.716 ------------------------------------------------------------------- slack 0.167 Slack (MET) : 0.167ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[50]/CE (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.828ns (logic 0.138ns (4.880%) route 2.690ns (95.120%)) Logic Levels: 0 Clock Path Skew: -0.035ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.696ns = ( 6.815 - 3.119 ) Source Clock Delay (SCD): 3.888ns Clock Pessimism Removal (CPR): 0.157ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.888ns (routing 1.620ns, distribution 2.268ns) Clock Net Delay (Destination): 3.696ns (routing 1.478ns, distribution 2.218ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.888 3.888 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X108Y78 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y78 FDCE (Prop_EFF2_SLICEL_C_Q) 0.138 4.026 r i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/Q net (fo=708, routed) 2.690 6.716 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[0]_0 SLICE_X135Y31 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[50]/CE ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y1 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.696 6.815 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/rxusrclk_out SLICE_X135Y31 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[50]/C clock pessimism 0.157 6.972 clock uncertainty -0.035 6.937 SLICE_X135Y31 FDRE (Setup_AFF_SLICEL_C_CE) -0.054 6.883 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[50] ------------------------------------------------------------------- required time 6.883 arrival time -6.716 ------------------------------------------------------------------- slack 0.167 Slack (MET) : 0.169ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[11]/R (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.787ns (logic 0.140ns (5.023%) route 2.647ns (94.977%)) Logic Levels: 0 Clock Path Skew: -0.033ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.693ns = ( 6.812 - 3.119 ) Source Clock Delay (SCD): 3.883ns Clock Pessimism Removal (CPR): 0.157ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.883ns (routing 1.620ns, distribution 2.263ns) Clock Net Delay (Destination): 3.693ns (routing 1.478ns, distribution 2.215ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.883 3.883 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X101Y80 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X101Y80 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 4.023 f i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.647 6.670 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/reset_i SLICE_X132Y36 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[11]/R (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y1 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.693 6.812 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/rxusrclk_out SLICE_X132Y36 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[11]/C clock pessimism 0.157 6.969 clock uncertainty -0.035 6.934 SLICE_X132Y36 FDRE (Setup_HFF_SLICEL_C_R) -0.095 6.839 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[11] ------------------------------------------------------------------- required time 6.839 arrival time -6.670 ------------------------------------------------------------------- slack 0.169 Slack (MET) : 0.169ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[30]/R (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.787ns (logic 0.140ns (5.023%) route 2.647ns (94.977%)) Logic Levels: 0 Clock Path Skew: -0.033ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.693ns = ( 6.812 - 3.119 ) Source Clock Delay (SCD): 3.883ns Clock Pessimism Removal (CPR): 0.157ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.883ns (routing 1.620ns, distribution 2.263ns) Clock Net Delay (Destination): 3.693ns (routing 1.478ns, distribution 2.215ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.883 3.883 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X101Y80 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X101Y80 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 4.023 f i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.647 6.670 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/reset_i SLICE_X132Y36 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[30]/R (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y1 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.693 6.812 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/rxusrclk_out SLICE_X132Y36 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[30]/C clock pessimism 0.157 6.969 clock uncertainty -0.035 6.934 SLICE_X132Y36 FDRE (Setup_GFF_SLICEL_C_R) -0.095 6.839 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[30] ------------------------------------------------------------------- required time 6.839 arrival time -6.670 ------------------------------------------------------------------- slack 0.169 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.033ns (arrival time - required time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[248]/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg1_reg[248]/D (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.174ns (logic 0.049ns (28.161%) route 0.125ns (71.839%)) Logic Levels: 0 Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.890ns Source Clock Delay (SCD): 1.637ns Clock Pessimism Removal (CPR): 0.167ns Clock Net Delay (Source): 1.637ns (routing 0.691ns, distribution 0.946ns) Clock Net Delay (Destination): 1.890ns (routing 0.772ns, distribution 1.118ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.637 1.637 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X140Y44 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[248]/C ------------------------------------------------------------------- ------------------- SLICE_X140Y44 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.686 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[248]/Q net (fo=1, routed) 0.125 1.811 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0[248] SLICE_X139Y44 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg1_reg[248]/D ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.890 1.890 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X139Y44 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg1_reg[248]/C clock pessimism -0.167 1.723 SLICE_X139Y44 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.778 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg1_reg[248] ------------------------------------------------------------------- required time -1.778 arrival time 1.811 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.036ns (arrival time - required time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[142]/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[67]/D (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@6.238ns - TTC_rxusrclk rise@6.238ns) Data Path Delay: 0.184ns (logic 0.094ns (51.087%) route 0.090ns (48.913%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.092ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.876ns Source Clock Delay (SCD): 1.617ns Clock Pessimism Removal (CPR): 0.167ns Clock Net Delay (Source): 1.617ns (routing 0.691ns, distribution 0.926ns) Clock Net Delay (Destination): 1.876ns (routing 0.772ns, distribution 1.104ns) Timing Exception: MultiCycle Path Setup -end 3 Hold -start 2 Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 6.238 6.238 r BUFG_GT_X1Y1 BUFG_GT 0.000 6.238 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.617 7.855 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X140Y29 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[142]/C ------------------------------------------------------------------- ------------------- SLICE_X140Y29 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 7.904 r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[142]/Q net (fo=11, routed) 0.078 7.982 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/Q[142] SLICE_X139Y29 LUT6 (Prop_A6LUT_SLICEL_I3_O) 0.045 8.027 r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o[67]_i_1/O net (fo=1, routed) 0.012 8.039 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o[67]_i_1_n_0 SLICE_X139Y29 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[67]/D ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 6.238 6.238 r BUFG_GT_X1Y1 BUFG_GT 0.000 6.238 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.876 8.114 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/rxusrclk_out SLICE_X139Y29 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[67]/C clock pessimism -0.167 7.947 SLICE_X139Y29 FDRE (Hold_AFF_SLICEL_C_D) 0.056 8.003 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[67] ------------------------------------------------------------------- required time -8.003 arrival time 8.039 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.041ns (arrival time - required time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[138]/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[138]/D (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.143ns (logic 0.049ns (34.266%) route 0.094ns (65.734%)) Logic Levels: 0 Clock Path Skew: 0.046ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.878ns Source Clock Delay (SCD): 1.633ns Clock Pessimism Removal (CPR): 0.199ns Clock Net Delay (Source): 1.633ns (routing 0.691ns, distribution 0.942ns) Clock Net Delay (Destination): 1.878ns (routing 0.772ns, distribution 1.106ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.633 1.633 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X132Y47 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[138]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y47 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.682 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[138]/Q net (fo=1, routed) 0.094 1.776 i_tcds2_if/cmp_lpgbtfpga_uplink/gbxFrame_s[138] SLICE_X131Y46 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[138]/D ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.878 1.878 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X131Y46 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[138]/C clock pessimism -0.199 1.679 SLICE_X131Y46 FDCE (Hold_AFF2_SLICEL_C_D) 0.056 1.735 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[138] ------------------------------------------------------------------- required time -1.735 arrival time 1.776 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.042ns (arrival time - required time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[94]/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[94]/D (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.186ns (logic 0.048ns (25.806%) route 0.138ns (74.194%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.879ns Source Clock Delay (SCD): 1.624ns Clock Pessimism Removal (CPR): 0.167ns Clock Net Delay (Source): 1.624ns (routing 0.691ns, distribution 0.933ns) Clock Net Delay (Destination): 1.879ns (routing 0.772ns, distribution 1.107ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.624 1.624 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X140Y34 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[94]/C ------------------------------------------------------------------- ------------------- SLICE_X140Y34 FDCE (Prop_HFF_SLICEL_C_Q) 0.048 1.672 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[94]/Q net (fo=1, routed) 0.138 1.810 i_tcds2_if/cmp_lpgbtfpga_uplink/gbxFrame_s[94] SLICE_X139Y34 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[94]/D ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.879 1.879 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X139Y34 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[94]/C clock pessimism -0.167 1.712 SLICE_X139Y34 FDCE (Hold_HFF2_SLICEL_C_D) 0.056 1.768 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[94] ------------------------------------------------------------------- required time -1.768 arrival time 1.810 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.043ns (arrival time - required time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[91]/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[91]/D (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.178ns (logic 0.048ns (26.966%) route 0.130ns (73.034%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.877ns Source Clock Delay (SCD): 1.630ns Clock Pessimism Removal (CPR): 0.167ns Clock Net Delay (Source): 1.630ns (routing 0.691ns, distribution 0.939ns) Clock Net Delay (Destination): 1.877ns (routing 0.772ns, distribution 1.105ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.630 1.630 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X140Y35 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[91]/C ------------------------------------------------------------------- ------------------- SLICE_X140Y35 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.678 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[91]/Q net (fo=1, routed) 0.130 1.808 i_tcds2_if/cmp_lpgbtfpga_uplink/gbxFrame_s[91] SLICE_X139Y33 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[91]/D ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.877 1.877 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X139Y33 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[91]/C clock pessimism -0.167 1.710 SLICE_X139Y33 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.765 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[91] ------------------------------------------------------------------- required time -1.765 arrival time 1.808 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.045ns (arrival time - required time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[61]/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[11]/D (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@6.238ns - TTC_rxusrclk rise@6.238ns) Data Path Delay: 0.154ns (logic 0.064ns (41.558%) route 0.090ns (58.442%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.880ns Source Clock Delay (SCD): 1.623ns Clock Pessimism Removal (CPR): 0.204ns Clock Net Delay (Source): 1.623ns (routing 0.691ns, distribution 0.932ns) Clock Net Delay (Destination): 1.880ns (routing 0.772ns, distribution 1.108ns) Timing Exception: MultiCycle Path Setup -end 3 Hold -start 2 Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 6.238 6.238 r BUFG_GT_X1Y1 BUFG_GT 0.000 6.238 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.623 7.861 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X139Y32 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[61]/C ------------------------------------------------------------------- ------------------- SLICE_X139Y32 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 7.910 r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[61]/Q net (fo=12, routed) 0.074 7.984 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/Q[61] SLICE_X139Y33 LUT6 (Prop_D6LUT_SLICEL_I3_O) 0.015 7.999 r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o[11]_i_1/O net (fo=1, routed) 0.016 8.015 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o[11]_i_1_n_0 SLICE_X139Y33 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[11]/D ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 6.238 6.238 r BUFG_GT_X1Y1 BUFG_GT 0.000 6.238 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.880 8.118 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/rxusrclk_out SLICE_X139Y33 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[11]/C clock pessimism -0.204 7.914 SLICE_X139Y33 FDRE (Hold_DFF_SLICEL_C_D) 0.056 7.970 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[11] ------------------------------------------------------------------- required time -7.970 arrival time 8.015 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/memory_register_reg[24]/C (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[5]/D (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.141ns (logic 0.094ns (66.667%) route 0.047ns (33.333%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.868ns Source Clock Delay (SCD): 1.621ns Clock Pessimism Removal (CPR): 0.207ns Clock Net Delay (Source): 1.621ns (routing 0.691ns, distribution 0.930ns) Clock Net Delay (Destination): 1.868ns (routing 0.772ns, distribution 1.096ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.621 1.621 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/rxusrclk_out SLICE_X132Y38 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/memory_register_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y38 FDRE (Prop_EFF_SLICEL_C_Q) 0.049 1.670 r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/memory_register_reg[24]/Q net (fo=2, routed) 0.035 1.705 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/memory_register[24] SLICE_X132Y38 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.045 1.750 r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData[5]_i_1/O net (fo=1, routed) 0.012 1.762 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/p_0_out[5] SLICE_X132Y38 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[5]/D ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.868 1.868 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/rxusrclk_out SLICE_X132Y38 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[5]/C clock pessimism -0.207 1.661 SLICE_X132Y38 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.717 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[5] ------------------------------------------------------------------- required time -1.717 arrival time 1.762 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[96]/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[168]/D (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@6.238ns - TTC_rxusrclk rise@6.238ns) Data Path Delay: 0.152ns (logic 0.064ns (42.105%) route 0.088ns (57.895%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.051ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.881ns Source Clock Delay (SCD): 1.629ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.629ns (routing 0.691ns, distribution 0.938ns) Clock Net Delay (Destination): 1.881ns (routing 0.772ns, distribution 1.109ns) Timing Exception: MultiCycle Path Setup -end 3 Hold -start 2 Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 6.238 6.238 r BUFG_GT_X1Y1 BUFG_GT 0.000 6.238 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.629 7.867 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X134Y43 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[96]/C ------------------------------------------------------------------- ------------------- SLICE_X134Y43 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 7.916 r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[96]/Q net (fo=12, routed) 0.076 7.992 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/Q[96] SLICE_X134Y42 LUT6 (Prop_A6LUT_SLICEL_I1_O) 0.015 8.007 r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o[168]_i_1/O net (fo=1, routed) 0.012 8.019 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o[168]_i_1_n_0 SLICE_X134Y42 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[168]/D ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 6.238 6.238 r BUFG_GT_X1Y1 BUFG_GT 0.000 6.238 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.881 8.119 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/rxusrclk_out SLICE_X134Y42 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[168]/C clock pessimism -0.201 7.918 SLICE_X134Y42 FDRE (Hold_AFF_SLICEL_C_D) 0.056 7.974 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[168] ------------------------------------------------------------------- required time -7.974 arrival time 8.019 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[236]/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[236]/D (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.181ns (logic 0.049ns (27.072%) route 0.132ns (72.928%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.883ns Source Clock Delay (SCD): 1.635ns Clock Pessimism Removal (CPR): 0.167ns Clock Net Delay (Source): 1.635ns (routing 0.691ns, distribution 0.944ns) Clock Net Delay (Destination): 1.883ns (routing 0.772ns, distribution 1.111ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.635 1.635 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X141Y39 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[236]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y39 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 1.684 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[236]/Q net (fo=1, routed) 0.132 1.816 i_tcds2_if/cmp_lpgbtfpga_uplink/gbxFrame_s[236] SLICE_X138Y39 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[236]/D ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.883 1.883 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X138Y39 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[236]/C clock pessimism -0.167 1.716 SLICE_X138Y39 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.771 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[236] ------------------------------------------------------------------- required time -1.771 arrival time 1.816 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[48]/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[48]/D (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.189ns (logic 0.049ns (25.926%) route 0.140ns (74.074%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.883ns Source Clock Delay (SCD): 1.628ns Clock Pessimism Removal (CPR): 0.167ns Clock Net Delay (Source): 1.628ns (routing 0.691ns, distribution 0.937ns) Clock Net Delay (Destination): 1.883ns (routing 0.772ns, distribution 1.111ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.628 1.628 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X133Y46 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[48]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y46 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.677 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[48]/Q net (fo=1, routed) 0.140 1.817 i_tcds2_if/cmp_lpgbtfpga_uplink/gbxFrame_s[48] SLICE_X132Y46 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[48]/D ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.883 1.883 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X132Y46 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[48]/C clock pessimism -0.167 1.716 SLICE_X132Y46 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.772 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[48] ------------------------------------------------------------------- required time -1.772 arrival time 1.817 ------------------------------------------------------------------- slack 0.045 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: TTC_rxusrclk Waveform(ns): { 0.000 1.559 } Period(ns): 3.119 Sources: { i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 2.560 3.119 0.559 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 2.560 3.119 0.559 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFGCE_DIV/I n/a 1.250 3.119 1.869 BUFGCE_DIV_X1Y16 i_tcds2_if/bufgce_clk_40_rx/I Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X108Y78 i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X135Y29 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[0]/C Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X140Y31 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[100]/C Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X137Y34 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[101]/C Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X139Y34 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[102]/C Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X123Y46 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[103]/C Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X140Y32 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[104]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.152 1.559 0.407 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.152 1.559 0.407 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.152 1.559 0.407 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.152 1.559 0.407 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDCE/C n/a 0.275 1.559 1.284 SLICE_X135Y29 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[0]/C Low Pulse Width Fast FDCE/C n/a 0.275 1.559 1.284 SLICE_X140Y31 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[100]/C Low Pulse Width Slow FDCE/C n/a 0.275 1.559 1.284 SLICE_X137Y34 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[101]/C Low Pulse Width Slow FDCE/C n/a 0.275 1.559 1.284 SLICE_X135Y45 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[107]/C Low Pulse Width Slow FDCE/C n/a 0.275 1.559 1.284 SLICE_X131Y45 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[108]/C Low Pulse Width Slow FDCE/C n/a 0.275 1.559 1.284 SLICE_X141Y30 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[113]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.152 1.560 0.408 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.152 1.560 0.408 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.152 1.560 0.408 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.152 1.560 0.408 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast FDCE/C n/a 0.275 1.559 1.284 SLICE_X135Y43 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[106]/C High Pulse Width Fast FDCE/C n/a 0.275 1.559 1.284 SLICE_X135Y45 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[107]/C High Pulse Width Fast FDCE/C n/a 0.275 1.559 1.284 SLICE_X139Y35 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[110]/C High Pulse Width Fast FDCE/C n/a 0.275 1.559 1.284 SLICE_X141Y29 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[112]/C High Pulse Width Fast FDCE/C n/a 0.275 1.559 1.284 SLICE_X141Y28 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[114]/C High Pulse Width Fast FDCE/C n/a 0.275 1.559 1.284 SLICE_X134Y44 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[117]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: fabric_clk_in To Clock: fabric_clk_in Setup : 0 Failing Endpoints, Worst Slack 17.640ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.045ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 6.238ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 17.640ns (required time - arrival time) Source: i_tcds2_if/bcnt_reg[8]/C (rising edge-triggered cell FDCE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/local_ttc_reg[sync_flags_and_commands][0]/D (rising edge-triggered cell FDCE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000ns) Data Path Delay: 7.227ns (logic 0.794ns (10.987%) route 6.433ns (89.013%)) Logic Levels: 3 (LUT2=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 6.741ns = ( 31.693 - 24.952 ) Source Clock Delay (SCD): 7.384ns Clock Pessimism Removal (CPR): 0.529ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.927ns (routing 1.980ns, distribution 1.947ns) Clock Net Delay (Destination): 3.662ns (routing 1.829ns, distribution 1.833ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 3.112 3.112 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.345 3.457 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 3.927 7.384 i_tcds2_if/fabric_clk_in SLICE_X97Y247 FDCE r i_tcds2_if/bcnt_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y247 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 7.524 r i_tcds2_if/bcnt_reg[8]/Q net (fo=5, routed) 0.389 7.913 i_tcds2_if/bcnt_reg_n_0_[8] SLICE_X97Y246 LUT6 (Prop_E6LUT_SLICEM_I4_O) 0.244 8.157 f i_tcds2_if/local_ttc[sync_flags_and_commands][0]_i_3/O net (fo=1, routed) 0.252 8.409 i_tcds2_if/local_ttc[sync_flags_and_commands][0]_i_3_n_0 SLICE_X97Y246 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.226 8.635 f i_tcds2_if/local_ttc[sync_flags_and_commands][0]_i_2/O net (fo=4, routed) 1.340 9.975 ctrl_regs_inst/local_ttc_reg[sync_flags_and_commands]_0_sn_1 SLICE_X92Y217 LUT2 (Prop_B5LUT_SLICEM_I1_O) 0.184 10.159 r ctrl_regs_inst/local_ttc[sync_flags_and_commands][0]_i_1/O net (fo=1, routed) 4.452 14.611 i_tcds2_if/local_ttc[sync_flags_and_commands][0] SLICE_X133Y62 FDCE r i_tcds2_if/local_ttc_reg[sync_flags_and_commands][0]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 24.952 24.952 r BUFG_GT_X1Y1 BUFG_GT 0.000 24.952 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 2.819 27.771 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.260 28.031 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 3.662 31.693 i_tcds2_if/fabric_clk_in SLICE_X133Y62 FDCE r i_tcds2_if/local_ttc_reg[sync_flags_and_commands][0]/C clock pessimism 0.529 32.222 clock uncertainty -0.035 32.187 SLICE_X133Y62 FDCE (Setup_EFF_SLICEL_C_D) 0.064 32.251 i_tcds2_if/local_ttc_reg[sync_flags_and_commands][0] ------------------------------------------------------------------- required time 32.251 arrival time -14.611 ------------------------------------------------------------------- slack 17.640 Slack (MET) : 20.101ns (required time - arrival time) Source: i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[2]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[127]/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000ns) Data Path Delay: 4.693ns (logic 0.689ns (14.681%) route 4.004ns (85.319%)) Logic Levels: 3 (LUT2=1 LUT5=1 LUT6=1) Clock Path Skew: -0.187ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 6.662ns = ( 31.614 - 24.952 ) Source Clock Delay (SCD): 7.499ns Clock Pessimism Removal (CPR): 0.650ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 4.042ns (routing 1.980ns, distribution 2.062ns) Clock Net Delay (Destination): 3.583ns (routing 1.829ns, distribution 1.754ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 3.112 3.112 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.345 3.457 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 4.042 7.499 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X129Y22 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y22 FDRE (Prop_CFF_SLICEL_C_Q) 0.138 7.637 r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[2]/Q net (fo=47, routed) 1.944 9.581 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[1] SLICE_X130Y26 LUT2 (Prop_A6LUT_SLICEL_I1_O) 0.166 9.747 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[228]_i_2/O net (fo=22, routed) 0.908 10.655 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[228]_i_2_n_0 SLICE_X124Y24 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.166 10.821 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[167]_i_2/O net (fo=4, routed) 0.346 11.167 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[167]_i_2_n_0 SLICE_X124Y27 LUT5 (Prop_C6LUT_SLICEL_I4_O) 0.219 11.386 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[127]_i_1__0/O net (fo=1, routed) 0.806 12.192 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[115]_4[12] SLICE_X124Y28 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[127]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 24.952 24.952 r BUFG_GT_X1Y1 BUFG_GT 0.000 24.952 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 2.819 27.771 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.260 28.031 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 3.583 31.614 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X124Y28 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[127]/C clock pessimism 0.650 32.264 clock uncertainty -0.035 32.229 SLICE_X124Y28 FDRE (Setup_EFF_SLICEL_C_D) 0.064 32.293 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[127] ------------------------------------------------------------------- required time 32.293 arrival time -12.192 ------------------------------------------------------------------- slack 20.101 Slack (MET) : 20.281ns (required time - arrival time) Source: i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[130]/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000ns) Data Path Delay: 4.478ns (logic 0.593ns (13.243%) route 3.885ns (86.757%)) Logic Levels: 3 (LUT2=1 LUT6=2) Clock Path Skew: -0.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 6.663ns = ( 31.615 - 24.952 ) Source Clock Delay (SCD): 7.532ns Clock Pessimism Removal (CPR): 0.650ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 4.075ns (routing 1.980ns, distribution 2.095ns) Clock Net Delay (Destination): 3.584ns (routing 1.829ns, distribution 1.755ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 3.112 3.112 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.345 3.457 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 4.075 7.532 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X130Y23 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X130Y23 FDRE (Prop_HFF_SLICEL_C_Q) 0.138 7.670 r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/Q net (fo=49, routed) 1.677 9.347 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[16] SLICE_X124Y24 LUT2 (Prop_D6LUT_SLICEL_I0_O) 0.238 9.585 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[231]_i_6/O net (fo=8, routed) 1.876 11.461 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[231]_i_6_n_0 SLICE_X124Y32 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.051 11.512 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[210]_i_2__0/O net (fo=3, routed) 0.299 11.811 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[210]_i_2__0_n_0 SLICE_X124Y29 LUT6 (Prop_B6LUT_SLICEL_I5_O) 0.166 11.977 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[130]_i_1__0/O net (fo=1, routed) 0.033 12.010 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[115]_4[15] SLICE_X124Y29 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[130]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 24.952 24.952 r BUFG_GT_X1Y1 BUFG_GT 0.000 24.952 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 2.819 27.771 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.260 28.031 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 3.584 31.615 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X124Y29 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[130]/C clock pessimism 0.650 32.265 clock uncertainty -0.035 32.229 SLICE_X124Y29 FDRE (Setup_BFF_SLICEL_C_D) 0.062 32.291 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[130] ------------------------------------------------------------------- required time 32.291 arrival time -12.010 ------------------------------------------------------------------- slack 20.281 Slack (MET) : 20.306ns (required time - arrival time) Source: i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[86]/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000ns) Data Path Delay: 4.473ns (logic 0.649ns (14.509%) route 3.824ns (85.491%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.201ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 6.681ns = ( 31.633 - 24.952 ) Source Clock Delay (SCD): 7.532ns Clock Pessimism Removal (CPR): 0.650ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 4.075ns (routing 1.980ns, distribution 2.095ns) Clock Net Delay (Destination): 3.602ns (routing 1.829ns, distribution 1.773ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 3.112 3.112 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.345 3.457 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 4.075 7.532 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X130Y23 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X130Y23 FDRE (Prop_HFF_SLICEL_C_Q) 0.138 7.670 r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/Q net (fo=49, routed) 1.582 9.252 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[16] SLICE_X124Y27 LUT4 (Prop_B5LUT_SLICEL_I3_O) 0.272 9.524 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[230]_i_4/O net (fo=15, routed) 2.208 11.732 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[230]_i_4_n_0 SLICE_X125Y27 LUT6 (Prop_G6LUT_SLICEL_I2_O) 0.239 11.971 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[86]_i_1__0/O net (fo=1, routed) 0.034 12.005 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[77]_1[9] SLICE_X125Y27 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[86]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 24.952 24.952 r BUFG_GT_X1Y1 BUFG_GT 0.000 24.952 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 2.819 27.771 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.260 28.031 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 3.602 31.633 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X125Y27 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[86]/C clock pessimism 0.650 32.283 clock uncertainty -0.035 32.247 SLICE_X125Y27 FDRE (Setup_GFF_SLICEL_C_D) 0.064 32.311 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[86] ------------------------------------------------------------------- required time 32.311 arrival time -12.005 ------------------------------------------------------------------- slack 20.306 Slack (MET) : 20.320ns (required time - arrival time) Source: i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[170]/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000ns) Data Path Delay: 4.440ns (logic 0.665ns (14.977%) route 3.775ns (85.023%)) Logic Levels: 3 (LUT2=1 LUT6=2) Clock Path Skew: -0.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 6.663ns = ( 31.615 - 24.952 ) Source Clock Delay (SCD): 7.532ns Clock Pessimism Removal (CPR): 0.650ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 4.075ns (routing 1.980ns, distribution 2.095ns) Clock Net Delay (Destination): 3.584ns (routing 1.829ns, distribution 1.755ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 3.112 3.112 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.345 3.457 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 4.075 7.532 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X130Y23 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X130Y23 FDRE (Prop_HFF_SLICEL_C_Q) 0.138 7.670 r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/Q net (fo=49, routed) 1.677 9.347 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[16] SLICE_X124Y24 LUT2 (Prop_D6LUT_SLICEL_I0_O) 0.238 9.585 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[231]_i_6/O net (fo=8, routed) 1.876 11.461 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[231]_i_6_n_0 SLICE_X124Y32 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.051 11.512 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[210]_i_2__0/O net (fo=3, routed) 0.187 11.699 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[210]_i_2__0_n_0 SLICE_X124Y31 LUT6 (Prop_D6LUT_SLICEL_I5_O) 0.238 11.937 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[170]_i_1__0/O net (fo=1, routed) 0.035 11.972 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[153]_5[17] SLICE_X124Y31 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[170]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 24.952 24.952 r BUFG_GT_X1Y1 BUFG_GT 0.000 24.952 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 2.819 27.771 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.260 28.031 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 3.584 31.615 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X124Y31 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[170]/C clock pessimism 0.650 32.265 clock uncertainty -0.035 32.229 SLICE_X124Y31 FDRE (Setup_DFF_SLICEL_C_D) 0.063 32.292 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[170] ------------------------------------------------------------------- required time 32.292 arrival time -11.972 ------------------------------------------------------------------- slack 20.320 Slack (MET) : 20.372ns (required time - arrival time) Source: i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[91]/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000ns) Data Path Delay: 4.420ns (logic 0.576ns (13.032%) route 3.844ns (86.968%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.187ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 6.696ns = ( 31.648 - 24.952 ) Source Clock Delay (SCD): 7.532ns Clock Pessimism Removal (CPR): 0.649ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 4.075ns (routing 1.980ns, distribution 2.095ns) Clock Net Delay (Destination): 3.617ns (routing 1.829ns, distribution 1.788ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 3.112 3.112 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.345 3.457 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 4.075 7.532 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X130Y23 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X130Y23 FDRE (Prop_HFF_SLICEL_C_Q) 0.138 7.670 r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/Q net (fo=49, routed) 1.582 9.252 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[16] SLICE_X124Y27 LUT4 (Prop_B5LUT_SLICEL_I3_O) 0.272 9.524 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[230]_i_4/O net (fo=15, routed) 2.229 11.753 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[230]_i_4_n_0 SLICE_X127Y23 LUT6 (Prop_B6LUT_SLICEL_I0_O) 0.166 11.919 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[91]_i_1__0/O net (fo=1, routed) 0.033 11.952 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[77]_1[14] SLICE_X127Y23 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[91]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 24.952 24.952 r BUFG_GT_X1Y1 BUFG_GT 0.000 24.952 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 2.819 27.771 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.260 28.031 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 3.617 31.648 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X127Y23 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[91]/C clock pessimism 0.649 32.297 clock uncertainty -0.035 32.262 SLICE_X127Y23 FDRE (Setup_BFF_SLICEL_C_D) 0.062 32.324 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[91] ------------------------------------------------------------------- required time 32.324 arrival time -11.952 ------------------------------------------------------------------- slack 20.372 Slack (MET) : 20.416ns (required time - arrival time) Source: i_tcds2_if/prbs_checker/data_r2_reg[53]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0]/CE (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000ns) Data Path Delay: 4.323ns (logic 1.141ns (26.394%) route 3.182ns (73.606%)) Logic Levels: 10 (CARRY8=8 LUT5=1 LUT6=1) Clock Path Skew: -0.123ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 6.733ns = ( 31.685 - 24.952 ) Source Clock Delay (SCD): 7.505ns Clock Pessimism Removal (CPR): 0.649ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 4.048ns (routing 1.980ns, distribution 2.068ns) Clock Net Delay (Destination): 3.654ns (routing 1.829ns, distribution 1.825ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 3.112 3.112 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.345 3.457 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 4.048 7.505 i_tcds2_if/prbs_checker/node_ff_reg[22] SLICE_X128Y26 FDRE r i_tcds2_if/prbs_checker/data_r2_reg[53]/C ------------------------------------------------------------------- ------------------- SLICE_X128Y26 FDRE (Prop_EFF2_SLICEL_C_Q) 0.138 7.643 r i_tcds2_if/prbs_checker/data_r2_reg[53]/Q net (fo=1, routed) 1.460 9.103 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59_4 SLICE_X127Y26 LUT6 (Prop_B6LUT_SLICEL_I2_O) 0.053 9.156 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_75/O net (fo=1, routed) 0.000 9.156 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_75_n_0 SLICE_X127Y26 CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[7]) 0.408 9.564 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59/CO[7] net (fo=1, routed) 0.030 9.594 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59_n_0 SLICE_X127Y27 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) 0.028 9.622 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50/CO[7] net (fo=1, routed) 0.030 9.652 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50_n_0 SLICE_X127Y28 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) 0.028 9.680 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41/CO[7] net (fo=1, routed) 0.030 9.710 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41_n_0 SLICE_X127Y29 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) 0.028 9.738 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32/CO[7] net (fo=1, routed) 0.043 9.781 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32_n_0 SLICE_X127Y30 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) 0.028 9.809 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23/CO[7] net (fo=1, routed) 0.030 9.839 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23_n_0 SLICE_X127Y31 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) 0.028 9.867 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14/CO[7] net (fo=1, routed) 0.030 9.897 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14_n_0 SLICE_X127Y32 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) 0.028 9.925 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7/CO[7] net (fo=1, routed) 0.030 9.955 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7_n_0 SLICE_X127Y33 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[5]) 0.136 10.091 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_5/CO[5] net (fo=3, routed) 1.027 11.118 i_tcds2_if/prbs_checker/cmp_prbs_gen/CO[0] SLICE_X130Y22 LUT5 (Prop_H6LUT_SLICEL_I1_O) 0.238 11.356 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_2/O net (fo=2, routed) 0.472 11.828 i_tcds2_if/prbs_checker/prbs_lock_state SLICE_X130Y23 FDRE r i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 24.952 24.952 r BUFG_GT_X1Y1 BUFG_GT 0.000 24.952 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 2.819 27.771 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.260 28.031 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 3.654 31.685 i_tcds2_if/prbs_checker/node_ff_reg[22] SLICE_X130Y23 FDRE r i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0]/C clock pessimism 0.649 32.334 clock uncertainty -0.035 32.299 SLICE_X130Y23 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 32.244 i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0] ------------------------------------------------------------------- required time 32.244 arrival time -11.828 ------------------------------------------------------------------- slack 20.416 Slack (MET) : 20.416ns (required time - arrival time) Source: i_tcds2_if/prbs_checker/data_r2_reg[53]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/CE (rising edge-triggered cell FDSE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000ns) Data Path Delay: 4.323ns (logic 1.141ns (26.394%) route 3.182ns (73.606%)) Logic Levels: 10 (CARRY8=8 LUT5=1 LUT6=1) Clock Path Skew: -0.123ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 6.733ns = ( 31.685 - 24.952 ) Source Clock Delay (SCD): 7.505ns Clock Pessimism Removal (CPR): 0.649ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 4.048ns (routing 1.980ns, distribution 2.068ns) Clock Net Delay (Destination): 3.654ns (routing 1.829ns, distribution 1.825ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 3.112 3.112 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.345 3.457 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 4.048 7.505 i_tcds2_if/prbs_checker/node_ff_reg[22] SLICE_X128Y26 FDRE r i_tcds2_if/prbs_checker/data_r2_reg[53]/C ------------------------------------------------------------------- ------------------- SLICE_X128Y26 FDRE (Prop_EFF2_SLICEL_C_Q) 0.138 7.643 r i_tcds2_if/prbs_checker/data_r2_reg[53]/Q net (fo=1, routed) 1.460 9.103 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59_4 SLICE_X127Y26 LUT6 (Prop_B6LUT_SLICEL_I2_O) 0.053 9.156 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_75/O net (fo=1, routed) 0.000 9.156 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_75_n_0 SLICE_X127Y26 CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[7]) 0.408 9.564 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59/CO[7] net (fo=1, routed) 0.030 9.594 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59_n_0 SLICE_X127Y27 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) 0.028 9.622 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50/CO[7] net (fo=1, routed) 0.030 9.652 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50_n_0 SLICE_X127Y28 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) 0.028 9.680 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41/CO[7] net (fo=1, routed) 0.030 9.710 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41_n_0 SLICE_X127Y29 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) 0.028 9.738 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32/CO[7] net (fo=1, routed) 0.043 9.781 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32_n_0 SLICE_X127Y30 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) 0.028 9.809 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23/CO[7] net (fo=1, routed) 0.030 9.839 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23_n_0 SLICE_X127Y31 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) 0.028 9.867 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14/CO[7] net (fo=1, routed) 0.030 9.897 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14_n_0 SLICE_X127Y32 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) 0.028 9.925 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7/CO[7] net (fo=1, routed) 0.030 9.955 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7_n_0 SLICE_X127Y33 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[5]) 0.136 10.091 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_5/CO[5] net (fo=3, routed) 1.027 11.118 i_tcds2_if/prbs_checker/cmp_prbs_gen/CO[0] SLICE_X130Y22 LUT5 (Prop_H6LUT_SLICEL_I1_O) 0.238 11.356 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_2/O net (fo=2, routed) 0.472 11.828 i_tcds2_if/prbs_checker/prbs_lock_state SLICE_X130Y23 FDSE r i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 24.952 24.952 r BUFG_GT_X1Y1 BUFG_GT 0.000 24.952 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 2.819 27.771 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.260 28.031 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 3.654 31.685 i_tcds2_if/prbs_checker/node_ff_reg[22] SLICE_X130Y23 FDSE r i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/C clock pessimism 0.649 32.334 clock uncertainty -0.035 32.299 SLICE_X130Y23 FDSE (Setup_CFF2_SLICEL_C_CE) -0.055 32.244 i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1] ------------------------------------------------------------------- required time 32.244 arrival time -11.828 ------------------------------------------------------------------- slack 20.416 Slack (MET) : 20.523ns (required time - arrival time) Source: i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[210]/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000ns) Data Path Delay: 4.239ns (logic 0.573ns (13.517%) route 3.666ns (86.483%)) Logic Levels: 3 (LUT2=1 LUT6=2) Clock Path Skew: -0.217ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 6.665ns = ( 31.617 - 24.952 ) Source Clock Delay (SCD): 7.532ns Clock Pessimism Removal (CPR): 0.650ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 4.075ns (routing 1.980ns, distribution 2.095ns) Clock Net Delay (Destination): 3.586ns (routing 1.829ns, distribution 1.757ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 3.112 3.112 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.345 3.457 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 4.075 7.532 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X130Y23 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X130Y23 FDRE (Prop_HFF_SLICEL_C_Q) 0.138 7.670 r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/Q net (fo=49, routed) 1.677 9.347 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[16] SLICE_X124Y24 LUT2 (Prop_D6LUT_SLICEL_I0_O) 0.238 9.585 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[231]_i_6/O net (fo=8, routed) 1.876 11.461 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[231]_i_6_n_0 SLICE_X124Y32 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.051 11.512 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[210]_i_2__0/O net (fo=3, routed) 0.076 11.588 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[210]_i_2__0_n_0 SLICE_X124Y32 LUT6 (Prop_C6LUT_SLICEL_I5_O) 0.146 11.734 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[210]_i_1__0/O net (fo=1, routed) 0.037 11.771 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[210]_6[0] SLICE_X124Y32 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[210]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 24.952 24.952 r BUFG_GT_X1Y1 BUFG_GT 0.000 24.952 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 2.819 27.771 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.260 28.031 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 3.586 31.617 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X124Y32 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[210]/C clock pessimism 0.650 32.267 clock uncertainty -0.035 32.231 SLICE_X124Y32 FDRE (Setup_CFF_SLICEL_C_D) 0.063 32.294 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[210] ------------------------------------------------------------------- required time 32.294 arrival time -11.771 ------------------------------------------------------------------- slack 20.523 Slack (MET) : 20.526ns (required time - arrival time) Source: i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[211]/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000ns) Data Path Delay: 4.270ns (logic 0.630ns (14.754%) route 3.640ns (85.246%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.185ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 6.698ns = ( 31.650 - 24.952 ) Source Clock Delay (SCD): 7.532ns Clock Pessimism Removal (CPR): 0.649ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 4.075ns (routing 1.980ns, distribution 2.095ns) Clock Net Delay (Destination): 3.619ns (routing 1.829ns, distribution 1.790ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 3.112 3.112 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.345 3.457 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 4.075 7.532 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X130Y23 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X130Y23 FDRE (Prop_HFF_SLICEL_C_Q) 0.138 7.670 r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/Q net (fo=49, routed) 1.582 9.252 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[16] SLICE_X124Y27 LUT4 (Prop_B5LUT_SLICEL_I3_O) 0.272 9.524 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[230]_i_4/O net (fo=15, routed) 1.283 10.807 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[230]_i_4_n_0 SLICE_X130Y30 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.051 10.858 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[211]_i_2__0/O net (fo=3, routed) 0.081 10.939 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[211]_i_2__0_n_0 SLICE_X130Y30 LUT4 (Prop_C5LUT_SLICEL_I3_O) 0.169 11.108 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[211]_i_1__0/O net (fo=1, routed) 0.694 11.802 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[210]_6[1] SLICE_X129Y30 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[211]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 24.952 24.952 r BUFG_GT_X1Y1 BUFG_GT 0.000 24.952 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 2.819 27.771 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.260 28.031 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 3.619 31.650 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X129Y30 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[211]/C clock pessimism 0.649 32.299 clock uncertainty -0.035 32.264 SLICE_X129Y30 FDRE (Setup_EFF_SLICEL_C_D) 0.064 32.328 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[211] ------------------------------------------------------------------- required time 32.328 arrival time -11.802 ------------------------------------------------------------------- slack 20.526 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.045ns (arrival time - required time) Source: i_tcds2_if/prbs_checker/data_r_reg[104]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/data_r2_reg[104]/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000ns) Data Path Delay: 0.169ns (logic 0.048ns (28.402%) route 0.121ns (71.598%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.302ns Source Clock Delay (SCD): 2.820ns Clock Pessimism Removal (CPR): 0.414ns Clock Net Delay (Source): 1.549ns (routing 0.788ns, distribution 0.761ns) Clock Net Delay (Destination): 1.779ns (routing 0.876ns, distribution 0.903ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.251 1.251 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.020 1.271 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 1.549 2.820 i_tcds2_if/prbs_checker/node_ff_reg[22] SLICE_X131Y31 FDRE r i_tcds2_if/prbs_checker/data_r_reg[104]/C ------------------------------------------------------------------- ------------------- SLICE_X131Y31 FDRE (Prop_GFF_SLICEL_C_Q) 0.048 2.868 r i_tcds2_if/prbs_checker/data_r_reg[104]/Q net (fo=1, routed) 0.121 2.989 i_tcds2_if/prbs_checker/data_r[104] SLICE_X131Y29 FDRE r i_tcds2_if/prbs_checker/data_r2_reg[104]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.402 1.402 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.121 1.523 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 1.779 3.302 i_tcds2_if/prbs_checker/node_ff_reg[22] SLICE_X131Y29 FDRE r i_tcds2_if/prbs_checker/data_r2_reg[104]/C clock pessimism -0.414 2.888 SLICE_X131Y29 FDRE (Hold_EFF_SLICEL_C_D) 0.056 2.944 i_tcds2_if/prbs_checker/data_r2_reg[104] ------------------------------------------------------------------- required time -2.944 arrival time 2.989 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: i_tcds2_if/prbs_checker/data_r_reg[129]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/data_r2_reg[129]/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000ns) Data Path Delay: 0.142ns (logic 0.048ns (33.803%) route 0.094ns (66.197%)) Logic Levels: 0 Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.270ns Source Clock Delay (SCD): 2.785ns Clock Pessimism Removal (CPR): 0.443ns Clock Net Delay (Source): 1.514ns (routing 0.788ns, distribution 0.726ns) Clock Net Delay (Destination): 1.747ns (routing 0.876ns, distribution 0.871ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.251 1.251 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.020 1.271 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 1.514 2.785 i_tcds2_if/prbs_checker/node_ff_reg[22] SLICE_X127Y35 FDRE r i_tcds2_if/prbs_checker/data_r_reg[129]/C ------------------------------------------------------------------- ------------------- SLICE_X127Y35 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 2.833 r i_tcds2_if/prbs_checker/data_r_reg[129]/Q net (fo=1, routed) 0.094 2.927 i_tcds2_if/prbs_checker/data_r[129] SLICE_X127Y34 FDRE r i_tcds2_if/prbs_checker/data_r2_reg[129]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.402 1.402 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.121 1.523 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 1.747 3.270 i_tcds2_if/prbs_checker/node_ff_reg[22] SLICE_X127Y34 FDRE r i_tcds2_if/prbs_checker/data_r2_reg[129]/C clock pessimism -0.443 2.827 SLICE_X127Y34 FDRE (Hold_EFF2_SLICEL_C_D) 0.055 2.882 i_tcds2_if/prbs_checker/data_r2_reg[129] ------------------------------------------------------------------- required time -2.882 arrival time 2.927 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.048ns (arrival time - required time) Source: i_tcds2_if/prbs_checker/data_r_reg[59]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/data_r2_reg[59]/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000ns) Data Path Delay: 0.141ns (logic 0.048ns (34.043%) route 0.093ns (65.957%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.301ns Source Clock Delay (SCD): 2.818ns Clock Pessimism Removal (CPR): 0.446ns Clock Net Delay (Source): 1.547ns (routing 0.788ns, distribution 0.759ns) Clock Net Delay (Destination): 1.778ns (routing 0.876ns, distribution 0.902ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.251 1.251 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.020 1.271 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 1.547 2.818 i_tcds2_if/prbs_checker/node_ff_reg[22] SLICE_X132Y27 FDRE r i_tcds2_if/prbs_checker/data_r_reg[59]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y27 FDRE (Prop_FFF2_SLICEL_C_Q) 0.048 2.866 r i_tcds2_if/prbs_checker/data_r_reg[59]/Q net (fo=1, routed) 0.093 2.959 i_tcds2_if/prbs_checker/data_r[59] SLICE_X132Y26 FDRE r i_tcds2_if/prbs_checker/data_r2_reg[59]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.402 1.402 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.121 1.523 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 1.778 3.301 i_tcds2_if/prbs_checker/node_ff_reg[22] SLICE_X132Y26 FDRE r i_tcds2_if/prbs_checker/data_r2_reg[59]/C clock pessimism -0.446 2.855 SLICE_X132Y26 FDRE (Hold_GFF_SLICEL_C_D) 0.056 2.911 i_tcds2_if/prbs_checker/data_r2_reg[59] ------------------------------------------------------------------- required time -2.911 arrival time 2.959 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.054ns (arrival time - required time) Source: i_tcds2_if/bcnt_reg[6]/C (rising edge-triggered cell FDCE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/bcnt_reg[8]/D (rising edge-triggered cell FDCE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000ns) Data Path Delay: 0.115ns (logic 0.064ns (55.652%) route 0.051ns (44.348%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.226ns Source Clock Delay (SCD): 2.744ns Clock Pessimism Removal (CPR): 0.477ns Clock Net Delay (Source): 1.473ns (routing 0.788ns, distribution 0.685ns) Clock Net Delay (Destination): 1.703ns (routing 0.876ns, distribution 0.827ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.251 1.251 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.020 1.271 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 1.473 2.744 i_tcds2_if/fabric_clk_in SLICE_X97Y247 FDCE r i_tcds2_if/bcnt_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y247 FDCE (Prop_BFF_SLICEM_C_Q) 0.049 2.793 r i_tcds2_if/bcnt_reg[6]/Q net (fo=7, routed) 0.039 2.832 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l0_inst/bcnt_reg[11][6] SLICE_X97Y247 LUT6 (Prop_A6LUT_SLICEM_I2_O) 0.015 2.847 r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l0_inst/bcnt[8]_i_1/O net (fo=1, routed) 0.012 2.859 i_tcds2_if/p_0_in[8] SLICE_X97Y247 FDCE r i_tcds2_if/bcnt_reg[8]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.402 1.402 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.121 1.523 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 1.703 3.226 i_tcds2_if/fabric_clk_in SLICE_X97Y247 FDCE r i_tcds2_if/bcnt_reg[8]/C clock pessimism -0.477 2.749 SLICE_X97Y247 FDCE (Hold_AFF_SLICEM_C_D) 0.056 2.805 i_tcds2_if/bcnt_reg[8] ------------------------------------------------------------------- required time -2.805 arrival time 2.859 ------------------------------------------------------------------- slack 0.054 Slack (MET) : 0.055ns (arrival time - required time) Source: i_tcds2_if/ttc_rx_err_cnt_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/ttc_rx_err_cnt_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000ns) Data Path Delay: 0.115ns (logic 0.063ns (54.782%) route 0.052ns (45.217%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.004ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.308ns Source Clock Delay (SCD): 2.826ns Clock Pessimism Removal (CPR): 0.478ns Clock Net Delay (Source): 1.555ns (routing 0.788ns, distribution 0.767ns) Clock Net Delay (Destination): 1.785ns (routing 0.876ns, distribution 0.909ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.251 1.251 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.020 1.271 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 1.555 2.826 i_tcds2_if/fabric_clk_in SLICE_X137Y41 FDRE r i_tcds2_if/ttc_rx_err_cnt_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y41 FDRE (Prop_HFF_SLICEL_C_Q) 0.048 2.874 r i_tcds2_if/ttc_rx_err_cnt_reg/Q net (fo=2, routed) 0.036 2.910 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/ttc_rx_err_cnt_reg_0[0] SLICE_X137Y41 LUT6 (Prop_H6LUT_SLICEL_I5_O) 0.015 2.925 r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/ttc_rx_err_cnt_i_1/O net (fo=1, routed) 0.016 2.941 i_tcds2_if/cmp_lpgbtfpga_uplink_n_41 SLICE_X137Y41 FDRE r i_tcds2_if/ttc_rx_err_cnt_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.402 1.402 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.121 1.523 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 1.785 3.308 i_tcds2_if/fabric_clk_in SLICE_X137Y41 FDRE r i_tcds2_if/ttc_rx_err_cnt_reg/C clock pessimism -0.478 2.830 SLICE_X137Y41 FDRE (Hold_HFF_SLICEL_C_D) 0.056 2.886 i_tcds2_if/ttc_rx_err_cnt_reg ------------------------------------------------------------------- required time -2.886 arrival time 2.941 ------------------------------------------------------------------- slack 0.055 Slack (MET) : 0.055ns (arrival time - required time) Source: i_tcds2_if/prbs_checker/data_r_reg[41]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/data_r2_reg[41]/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000ns) Data Path Delay: 0.185ns (logic 0.048ns (25.946%) route 0.137ns (74.054%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.304ns Source Clock Delay (SCD): 2.815ns Clock Pessimism Removal (CPR): 0.414ns Clock Net Delay (Source): 1.544ns (routing 0.788ns, distribution 0.756ns) Clock Net Delay (Destination): 1.781ns (routing 0.876ns, distribution 0.905ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.251 1.251 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.020 1.271 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 1.544 2.815 i_tcds2_if/prbs_checker/node_ff_reg[22] SLICE_X131Y23 FDRE r i_tcds2_if/prbs_checker/data_r_reg[41]/C ------------------------------------------------------------------- ------------------- SLICE_X131Y23 FDRE (Prop_GFF2_SLICEL_C_Q) 0.048 2.863 r i_tcds2_if/prbs_checker/data_r_reg[41]/Q net (fo=1, routed) 0.137 3.000 i_tcds2_if/prbs_checker/data_r[41] SLICE_X130Y23 FDRE r i_tcds2_if/prbs_checker/data_r2_reg[41]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.402 1.402 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.121 1.523 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 1.781 3.304 i_tcds2_if/prbs_checker/node_ff_reg[22] SLICE_X130Y23 FDRE r i_tcds2_if/prbs_checker/data_r2_reg[41]/C clock pessimism -0.414 2.890 SLICE_X130Y23 FDRE (Hold_FFF2_SLICEL_C_D) 0.055 2.945 i_tcds2_if/prbs_checker/data_r2_reg[41] ------------------------------------------------------------------- required time -2.945 arrival time 3.000 ------------------------------------------------------------------- slack 0.055 Slack (MET) : 0.056ns (arrival time - required time) Source: i_tcds2_if/bcnt_reg[3]/C (rising edge-triggered cell FDCE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/bcnt_reg[4]/D (rising edge-triggered cell FDCE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000ns) Data Path Delay: 0.117ns (logic 0.064ns (54.701%) route 0.053ns (45.299%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.225ns Source Clock Delay (SCD): 2.745ns Clock Pessimism Removal (CPR): 0.475ns Clock Net Delay (Source): 1.474ns (routing 0.788ns, distribution 0.686ns) Clock Net Delay (Destination): 1.702ns (routing 0.876ns, distribution 0.826ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.251 1.251 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.020 1.271 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 1.474 2.745 i_tcds2_if/fabric_clk_in SLICE_X96Y246 FDCE r i_tcds2_if/bcnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y246 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 2.794 r i_tcds2_if/bcnt_reg[3]/Q net (fo=6, routed) 0.037 2.831 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l0_inst/bcnt_reg[11][3] SLICE_X96Y246 LUT6 (Prop_C6LUT_SLICEL_I4_O) 0.015 2.846 r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l0_inst/bcnt[4]_i_1/O net (fo=1, routed) 0.016 2.862 i_tcds2_if/p_0_in[4] SLICE_X96Y246 FDCE r i_tcds2_if/bcnt_reg[4]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.402 1.402 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.121 1.523 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 1.702 3.225 i_tcds2_if/fabric_clk_in SLICE_X96Y246 FDCE r i_tcds2_if/bcnt_reg[4]/C clock pessimism -0.475 2.750 SLICE_X96Y246 FDCE (Hold_CFF_SLICEL_C_D) 0.056 2.806 i_tcds2_if/bcnt_reg[4] ------------------------------------------------------------------- required time -2.806 arrival time 2.862 ------------------------------------------------------------------- slack 0.056 Slack (MET) : 0.057ns (arrival time - required time) Source: i_tcds2_if/prbs_checker/data_r_reg[128]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/data_r2_reg[128]/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000ns) Data Path Delay: 0.155ns (logic 0.048ns (30.968%) route 0.107ns (69.032%)) Logic Levels: 0 Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.270ns Source Clock Delay (SCD): 2.785ns Clock Pessimism Removal (CPR): 0.443ns Clock Net Delay (Source): 1.514ns (routing 0.788ns, distribution 0.726ns) Clock Net Delay (Destination): 1.747ns (routing 0.876ns, distribution 0.871ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.251 1.251 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.020 1.271 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 1.514 2.785 i_tcds2_if/prbs_checker/node_ff_reg[22] SLICE_X127Y35 FDRE r i_tcds2_if/prbs_checker/data_r_reg[128]/C ------------------------------------------------------------------- ------------------- SLICE_X127Y35 FDRE (Prop_HFF_SLICEL_C_Q) 0.048 2.833 r i_tcds2_if/prbs_checker/data_r_reg[128]/Q net (fo=1, routed) 0.107 2.940 i_tcds2_if/prbs_checker/data_r[128] SLICE_X127Y34 FDRE r i_tcds2_if/prbs_checker/data_r2_reg[128]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.402 1.402 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.121 1.523 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 1.747 3.270 i_tcds2_if/prbs_checker/node_ff_reg[22] SLICE_X127Y34 FDRE r i_tcds2_if/prbs_checker/data_r2_reg[128]/C clock pessimism -0.443 2.827 SLICE_X127Y34 FDRE (Hold_EFF_SLICEL_C_D) 0.056 2.883 i_tcds2_if/prbs_checker/data_r2_reg[128] ------------------------------------------------------------------- required time -2.883 arrival time 2.940 ------------------------------------------------------------------- slack 0.057 Slack (MET) : 0.059ns (arrival time - required time) Source: i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/C (rising edge-triggered cell FDSE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[21]/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000ns) Data Path Delay: 0.200ns (logic 0.063ns (31.500%) route 0.137ns (68.500%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.319ns Source Clock Delay (SCD): 2.820ns Clock Pessimism Removal (CPR): 0.414ns Clock Net Delay (Source): 1.549ns (routing 0.788ns, distribution 0.761ns) Clock Net Delay (Destination): 1.796ns (routing 0.876ns, distribution 0.920ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.251 1.251 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.020 1.271 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 1.549 2.820 i_tcds2_if/prbs_checker/node_ff_reg[22] SLICE_X130Y23 FDSE r i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X130Y23 FDSE (Prop_CFF2_SLICEL_C_Q) 0.048 2.868 r i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/Q net (fo=29, routed) 0.122 2.990 i_tcds2_if/prbs_checker/cmp_prbs_gen/Q[1] SLICE_X131Y25 LUT6 (Prop_B6LUT_SLICEL_I0_O) 0.015 3.005 r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff[21]_i_1__0/O net (fo=1, routed) 0.015 3.020 i_tcds2_if/prbs_checker/cmp_prbs_gen/p_1_in[21] SLICE_X131Y25 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[21]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.402 1.402 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.121 1.523 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 1.796 3.319 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X131Y25 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[21]/C clock pessimism -0.414 2.905 SLICE_X131Y25 FDRE (Hold_BFF_SLICEL_C_D) 0.056 2.961 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[21] ------------------------------------------------------------------- required time -2.961 arrival time 3.020 ------------------------------------------------------------------- slack 0.059 Slack (MET) : 0.060ns (arrival time - required time) Source: i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[12]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[58]/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000ns) Data Path Delay: 0.145ns (logic 0.094ns (64.828%) route 0.051ns (35.172%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.275ns Source Clock Delay (SCD): 2.793ns Clock Pessimism Removal (CPR): 0.453ns Clock Net Delay (Source): 1.522ns (routing 0.788ns, distribution 0.734ns) Clock Net Delay (Destination): 1.752ns (routing 0.876ns, distribution 0.876ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.251 1.251 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.020 1.271 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 1.522 2.793 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X127Y22 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X127Y22 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 2.842 r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[12]/Q net (fo=43, routed) 0.039 2.881 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[11] SLICE_X127Y22 LUT6 (Prop_F6LUT_SLICEL_I1_O) 0.045 2.926 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[58]_i_1__0/O net (fo=1, routed) 0.012 2.938 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[58]_0[0] SLICE_X127Y22 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[58]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.402 1.402 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.121 1.523 r i_tcds2_if/bufgce_clk_40_rx/O X4Y2 (CLOCK_ROOT) net (fo=792, routed) 1.752 3.275 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X127Y22 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[58]/C clock pessimism -0.453 2.822 SLICE_X127Y22 FDRE (Hold_FFF_SLICEL_C_D) 0.056 2.878 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[58] ------------------------------------------------------------------- required time -2.878 arrival time 2.938 ------------------------------------------------------------------- slack 0.060 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: fabric_clk_in Waveform(ns): { 0.000 12.476 } Period(ns): 24.952 Sources: { i_tcds2_if/bufgce_clk_40_rx/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a MMCME3_ADV/CLKIN1 n/a 1.250 24.952 23.702 MMCME3_ADV_X2Y4 fabric_clk_MMCM/CLKIN1 Min Period n/a FDRE/C n/a 0.550 24.952 24.402 SLICE_X88Y214 i_tcds2_if/BC0_early_cnt_reg/C Min Period n/a FDRE/C n/a 0.550 24.952 24.402 SLICE_X88Y213 i_tcds2_if/BC0_late_cnt_reg/C Min Period n/a FDRE/C n/a 0.550 24.952 24.402 SLICE_X88Y214 i_tcds2_if/BC0_onTime_cnt_reg/C Min Period n/a FDRE/C n/a 0.550 24.952 24.402 SLICE_X124Y34 i_tcds2_if/EvCntRes_cnt_reg/C Min Period n/a FDRE/C n/a 0.550 24.952 24.402 SLICE_X88Y213 i_tcds2_if/QIEreset_cnt_reg/C Min Period n/a FDRE/C n/a 0.550 24.952 24.402 SLICE_X129Y78 i_tcds2_if/WTE_cnt_reg/C Min Period n/a FDRE/C n/a 0.550 24.952 24.402 SLICE_X130Y25 i_tcds2_if/WTE_i_reg/C Min Period n/a FDCE/C n/a 0.550 24.952 24.402 SLICE_X96Y246 i_tcds2_if/bcnt_reg[0]/C Min Period n/a FDCE/C n/a 0.550 24.952 24.402 SLICE_X97Y246 i_tcds2_if/bcnt_reg[10]/C Low Pulse Width Slow MMCME3_ADV/CLKIN1 n/a 6.238 12.476 6.238 MMCME3_ADV_X2Y4 fabric_clk_MMCM/CLKIN1 Low Pulse Width Fast MMCME3_ADV/CLKIN1 n/a 6.238 12.476 6.238 MMCME3_ADV_X2Y4 fabric_clk_MMCM/CLKIN1 Low Pulse Width Slow FDRE/C n/a 0.275 12.476 12.201 SLICE_X130Y23 i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0]/C Low Pulse Width Slow FDSE/C n/a 0.275 12.476 12.201 SLICE_X130Y23 i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/C Low Pulse Width Slow FDRE/C n/a 0.275 12.476 12.201 SLICE_X131Y25 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[121]/C Low Pulse Width Slow FDRE/C n/a 0.275 12.476 12.201 SLICE_X129Y29 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[138]/C Low Pulse Width Slow FDRE/C n/a 0.275 12.476 12.201 SLICE_X125Y29 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[139]/C Low Pulse Width Slow FDRE/C n/a 0.275 12.476 12.201 SLICE_X125Y29 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[140]/C Low Pulse Width Slow FDRE/C n/a 0.275 12.476 12.201 SLICE_X128Y29 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[143]/C Low Pulse Width Slow FDRE/C n/a 0.275 12.476 12.201 SLICE_X125Y29 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[145]/C High Pulse Width Slow MMCME3_ADV/CLKIN1 n/a 6.238 12.476 6.238 MMCME3_ADV_X2Y4 fabric_clk_MMCM/CLKIN1 High Pulse Width Fast MMCME3_ADV/CLKIN1 n/a 6.238 12.476 6.238 MMCME3_ADV_X2Y4 fabric_clk_MMCM/CLKIN1 High Pulse Width Fast FDRE/C n/a 0.275 12.476 12.201 SLICE_X88Y213 i_tcds2_if/QIEreset_cnt_reg/C High Pulse Width Fast FDRE/C n/a 0.275 12.476 12.201 SLICE_X128Y24 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[10]/C High Pulse Width Fast FDRE/C n/a 0.275 12.476 12.201 SLICE_X125Y26 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[115]/C High Pulse Width Fast FDRE/C n/a 0.275 12.476 12.201 SLICE_X125Y29 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[124]/C High Pulse Width Fast FDRE/C n/a 0.275 12.476 12.201 SLICE_X128Y24 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[12]/C High Pulse Width Fast FDRE/C n/a 0.275 12.476 12.201 SLICE_X128Y26 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[134]/C High Pulse Width Fast FDRE/C n/a 0.275 12.476 12.201 SLICE_X125Y29 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[135]/C High Pulse Width Fast FDRE/C n/a 0.275 12.476 12.201 SLICE_X125Y28 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[141]/C --------------------------------------------------------------------------------------------------- From Clock: CLKFBOUT To Clock: CLKFBOUT Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 23.365ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: CLKFBOUT Waveform(ns): { 6.238 18.714 } Period(ns): 24.952 Sources: { fabric_clk_MMCM/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFGCE/I n/a 1.587 24.952 23.365 BUFGCE_X2Y111 CLKFBOUT_bufg/I Min Period n/a MMCME3_ADV/CLKFBOUT n/a 1.250 24.952 23.702 MMCME3_ADV_X2Y4 fabric_clk_MMCM/CLKFBOUT Min Period n/a MMCME3_ADV/CLKFBIN n/a 1.250 24.952 23.702 MMCME3_ADV_X2Y4 fabric_clk_MMCM/CLKFBIN --------------------------------------------------------------------------------------------------- From Clock: fabric_clk_dcm To Clock: fabric_clk_dcm Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 23.365ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: fabric_clk_dcm Waveform(ns): { 0.000 12.476 } Period(ns): 24.952 Sources: { fabric_clk_MMCM/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFGCE/I n/a 1.587 24.952 23.365 BUFGCE_X2Y119 fabric_clk_bufg/I Min Period n/a MMCME3_ADV/CLKOUT0 n/a 1.250 24.952 23.702 MMCME3_ADV_X2Y4 fabric_clk_MMCM/CLKOUT0 --------------------------------------------------------------------------------------------------- From Clock: tx_wordclk_dcm To Clock: tx_wordclk_dcm Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 6.730ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: tx_wordclk_dcm Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { fabric_clk_MMCM/CLKOUT1 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFGCE/I n/a 1.587 8.317 6.730 BUFGCE_X2Y118 tx_wordclk_bufg/I Min Period n/a MMCME3_ADV/CLKOUT1 n/a 1.250 8.317 7.067 MMCME3_ADV_X2Y4 fabric_clk_MMCM/CLKOUT1 --------------------------------------------------------------------------------------------------- From Clock: clk125 To Clock: clk125 Setup : 0 Failing Endpoints, Worst Slack 1.074ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.024ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 2.200ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.074ns (required time - arrival time) Source: eth/mac/i_mac/emacclientrxdvld_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[107]_srl2___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_76/CE (rising edge-triggered cell SRL16E clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 6.023ns (logic 0.496ns (8.235%) route 5.527ns (91.765%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.358ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.378ns = ( 11.378 - 8.000 ) Source Clock Delay (SCD): 3.812ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.812ns (routing 0.946ns, distribution 2.866ns) Clock Net Delay (Destination): 3.378ns (routing 0.870ns, distribution 2.508ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.812 3.812 eth/mac/i_mac/CLKFBIN SLICE_X137Y156 FDRE r eth/mac/i_mac/emacclientrxdvld_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y156 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 3.952 f eth/mac/i_mac/emacclientrxdvld_reg/Q net (fo=302, routed) 3.052 7.004 ipb/udp_if/rx_reset_block/mac_rx_valid SLICE_X140Y274 LUT2 (Prop_D5LUT_SLICEL_I1_O) 0.168 7.172 r ipb/udp_if/rx_reset_block/set_addr_i_1__1/O net (fo=682, routed) 1.169 8.341 ipb/udp_if/rx_reset_block/SR[0] SLICE_X132Y263 LUT3 (Prop_C5LUT_SLICEL_I0_O) 0.188 8.529 r ipb/udp_if/rx_reset_block/rarp.pkt_data[125]_i_1/O net (fo=97, routed) 1.306 9.835 ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[125]_0 SLICE_X142Y270 SRL16E r ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[107]_srl2___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_76/CE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y108 BUFGCE 0.000 8.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.378 11.378 ipb/udp_if/rx_packet_parser/CLKFBIN SLICE_X142Y270 SRL16E r ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[107]_srl2___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_76/CLK clock pessimism 0.076 11.454 clock uncertainty -0.053 11.401 SLICE_X142Y270 SRL16E (Setup_A6LUT_SLICEM_CLK_CE) -0.492 10.909 ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[107]_srl2___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_76 ------------------------------------------------------------------- required time 10.909 arrival time -9.835 ------------------------------------------------------------------- slack 1.074 Slack (MET) : 1.074ns (required time - arrival time) Source: eth/mac/i_mac/emacclientrxdvld_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[110]_srl11___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_85/CE (rising edge-triggered cell SRL16E clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 6.023ns (logic 0.496ns (8.235%) route 5.527ns (91.765%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.358ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.378ns = ( 11.378 - 8.000 ) Source Clock Delay (SCD): 3.812ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.812ns (routing 0.946ns, distribution 2.866ns) Clock Net Delay (Destination): 3.378ns (routing 0.870ns, distribution 2.508ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.812 3.812 eth/mac/i_mac/CLKFBIN SLICE_X137Y156 FDRE r eth/mac/i_mac/emacclientrxdvld_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y156 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 3.952 f eth/mac/i_mac/emacclientrxdvld_reg/Q net (fo=302, routed) 3.052 7.004 ipb/udp_if/rx_reset_block/mac_rx_valid SLICE_X140Y274 LUT2 (Prop_D5LUT_SLICEL_I1_O) 0.168 7.172 r ipb/udp_if/rx_reset_block/set_addr_i_1__1/O net (fo=682, routed) 1.169 8.341 ipb/udp_if/rx_reset_block/SR[0] SLICE_X132Y263 LUT3 (Prop_C5LUT_SLICEL_I0_O) 0.188 8.529 r ipb/udp_if/rx_reset_block/rarp.pkt_data[125]_i_1/O net (fo=97, routed) 1.306 9.835 ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[125]_0 SLICE_X142Y270 SRL16E r ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[110]_srl11___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_85/CE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y108 BUFGCE 0.000 8.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.378 11.378 ipb/udp_if/rx_packet_parser/CLKFBIN SLICE_X142Y270 SRL16E r ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[110]_srl11___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_85/CLK clock pessimism 0.076 11.454 clock uncertainty -0.053 11.401 SLICE_X142Y270 SRL16E (Setup_B6LUT_SLICEM_CLK_CE) -0.492 10.909 ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[110]_srl11___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_85 ------------------------------------------------------------------- required time 10.909 arrival time -9.835 ------------------------------------------------------------------- slack 1.074 Slack (MET) : 1.074ns (required time - arrival time) Source: eth/mac/i_mac/emacclientrxdvld_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[67]_srl3___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_77/CE (rising edge-triggered cell SRL16E clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 6.023ns (logic 0.496ns (8.235%) route 5.527ns (91.765%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.358ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.378ns = ( 11.378 - 8.000 ) Source Clock Delay (SCD): 3.812ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.812ns (routing 0.946ns, distribution 2.866ns) Clock Net Delay (Destination): 3.378ns (routing 0.870ns, distribution 2.508ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.812 3.812 eth/mac/i_mac/CLKFBIN SLICE_X137Y156 FDRE r eth/mac/i_mac/emacclientrxdvld_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y156 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 3.952 f eth/mac/i_mac/emacclientrxdvld_reg/Q net (fo=302, routed) 3.052 7.004 ipb/udp_if/rx_reset_block/mac_rx_valid SLICE_X140Y274 LUT2 (Prop_D5LUT_SLICEL_I1_O) 0.168 7.172 r ipb/udp_if/rx_reset_block/set_addr_i_1__1/O net (fo=682, routed) 1.169 8.341 ipb/udp_if/rx_reset_block/SR[0] SLICE_X132Y263 LUT3 (Prop_C5LUT_SLICEL_I0_O) 0.188 8.529 r ipb/udp_if/rx_reset_block/rarp.pkt_data[125]_i_1/O net (fo=97, routed) 1.306 9.835 ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[125]_0 SLICE_X142Y270 SRL16E r ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[67]_srl3___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_77/CE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y108 BUFGCE 0.000 8.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.378 11.378 ipb/udp_if/rx_packet_parser/CLKFBIN SLICE_X142Y270 SRL16E r ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[67]_srl3___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_77/CLK clock pessimism 0.076 11.454 clock uncertainty -0.053 11.401 SLICE_X142Y270 SRL16E (Setup_C6LUT_SLICEM_CLK_CE) -0.492 10.909 ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[67]_srl3___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_77 ------------------------------------------------------------------- required time 10.909 arrival time -9.835 ------------------------------------------------------------------- slack 1.074 Slack (MET) : 1.074ns (required time - arrival time) Source: eth/mac/i_mac/emacclientrxdvld_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[90]_srl2___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_76/CE (rising edge-triggered cell SRL16E clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 6.023ns (logic 0.496ns (8.235%) route 5.527ns (91.765%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.358ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.378ns = ( 11.378 - 8.000 ) Source Clock Delay (SCD): 3.812ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.812ns (routing 0.946ns, distribution 2.866ns) Clock Net Delay (Destination): 3.378ns (routing 0.870ns, distribution 2.508ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.812 3.812 eth/mac/i_mac/CLKFBIN SLICE_X137Y156 FDRE r eth/mac/i_mac/emacclientrxdvld_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y156 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 3.952 f eth/mac/i_mac/emacclientrxdvld_reg/Q net (fo=302, routed) 3.052 7.004 ipb/udp_if/rx_reset_block/mac_rx_valid SLICE_X140Y274 LUT2 (Prop_D5LUT_SLICEL_I1_O) 0.168 7.172 r ipb/udp_if/rx_reset_block/set_addr_i_1__1/O net (fo=682, routed) 1.169 8.341 ipb/udp_if/rx_reset_block/SR[0] SLICE_X132Y263 LUT3 (Prop_C5LUT_SLICEL_I0_O) 0.188 8.529 r ipb/udp_if/rx_reset_block/rarp.pkt_data[125]_i_1/O net (fo=97, routed) 1.306 9.835 ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[125]_0 SLICE_X142Y270 SRL16E r ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[90]_srl2___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_76/CE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y108 BUFGCE 0.000 8.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.378 11.378 ipb/udp_if/rx_packet_parser/CLKFBIN SLICE_X142Y270 SRL16E r ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[90]_srl2___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_76/CLK clock pessimism 0.076 11.454 clock uncertainty -0.053 11.401 SLICE_X142Y270 SRL16E (Setup_D6LUT_SLICEM_CLK_CE) -0.492 10.909 ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[90]_srl2___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_76 ------------------------------------------------------------------- required time 10.909 arrival time -9.835 ------------------------------------------------------------------- slack 1.074 Slack (MET) : 1.098ns (required time - arrival time) Source: eth/mac/i_mac/emacclientrxdvld_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[105]_srl4___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_78/CE (rising edge-triggered cell SRL16E clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 6.004ns (logic 0.496ns (8.261%) route 5.508ns (91.739%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.353ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.383ns = ( 11.383 - 8.000 ) Source Clock Delay (SCD): 3.812ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.812ns (routing 0.946ns, distribution 2.866ns) Clock Net Delay (Destination): 3.383ns (routing 0.870ns, distribution 2.513ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.812 3.812 eth/mac/i_mac/CLKFBIN SLICE_X137Y156 FDRE r eth/mac/i_mac/emacclientrxdvld_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y156 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 3.952 f eth/mac/i_mac/emacclientrxdvld_reg/Q net (fo=302, routed) 3.052 7.004 ipb/udp_if/rx_reset_block/mac_rx_valid SLICE_X140Y274 LUT2 (Prop_D5LUT_SLICEL_I1_O) 0.168 7.172 r ipb/udp_if/rx_reset_block/set_addr_i_1__1/O net (fo=682, routed) 1.169 8.341 ipb/udp_if/rx_reset_block/SR[0] SLICE_X132Y263 LUT3 (Prop_C5LUT_SLICEL_I0_O) 0.188 8.529 r ipb/udp_if/rx_reset_block/rarp.pkt_data[125]_i_1/O net (fo=97, routed) 1.287 9.816 ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[125]_0 SLICE_X142Y273 SRL16E r ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[105]_srl4___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_78/CE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y108 BUFGCE 0.000 8.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.383 11.383 ipb/udp_if/rx_packet_parser/CLKFBIN SLICE_X142Y273 SRL16E r ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[105]_srl4___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_78/CLK clock pessimism 0.076 11.459 clock uncertainty -0.053 11.406 SLICE_X142Y273 SRL16E (Setup_A6LUT_SLICEM_CLK_CE) -0.492 10.914 ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[105]_srl4___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_78 ------------------------------------------------------------------- required time 10.914 arrival time -9.816 ------------------------------------------------------------------- slack 1.098 Slack (MET) : 1.098ns (required time - arrival time) Source: eth/mac/i_mac/emacclientrxdvld_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[72]_srl5___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_79/CE (rising edge-triggered cell SRL16E clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 6.004ns (logic 0.496ns (8.261%) route 5.508ns (91.739%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.353ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.383ns = ( 11.383 - 8.000 ) Source Clock Delay (SCD): 3.812ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.812ns (routing 0.946ns, distribution 2.866ns) Clock Net Delay (Destination): 3.383ns (routing 0.870ns, distribution 2.513ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.812 3.812 eth/mac/i_mac/CLKFBIN SLICE_X137Y156 FDRE r eth/mac/i_mac/emacclientrxdvld_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y156 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 3.952 f eth/mac/i_mac/emacclientrxdvld_reg/Q net (fo=302, routed) 3.052 7.004 ipb/udp_if/rx_reset_block/mac_rx_valid SLICE_X140Y274 LUT2 (Prop_D5LUT_SLICEL_I1_O) 0.168 7.172 r ipb/udp_if/rx_reset_block/set_addr_i_1__1/O net (fo=682, routed) 1.169 8.341 ipb/udp_if/rx_reset_block/SR[0] SLICE_X132Y263 LUT3 (Prop_C5LUT_SLICEL_I0_O) 0.188 8.529 r ipb/udp_if/rx_reset_block/rarp.pkt_data[125]_i_1/O net (fo=97, routed) 1.287 9.816 ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[125]_0 SLICE_X142Y273 SRL16E r ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[72]_srl5___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_79/CE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y108 BUFGCE 0.000 8.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.383 11.383 ipb/udp_if/rx_packet_parser/CLKFBIN SLICE_X142Y273 SRL16E r ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[72]_srl5___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_79/CLK clock pessimism 0.076 11.459 clock uncertainty -0.053 11.406 SLICE_X142Y273 SRL16E (Setup_B6LUT_SLICEM_CLK_CE) -0.492 10.914 ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[72]_srl5___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_79 ------------------------------------------------------------------- required time 10.914 arrival time -9.816 ------------------------------------------------------------------- slack 1.098 Slack (MET) : 1.098ns (required time - arrival time) Source: eth/mac/i_mac/emacclientrxdvld_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[92]_srl6___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_80/CE (rising edge-triggered cell SRL16E clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 6.004ns (logic 0.496ns (8.261%) route 5.508ns (91.739%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.353ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.383ns = ( 11.383 - 8.000 ) Source Clock Delay (SCD): 3.812ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.812ns (routing 0.946ns, distribution 2.866ns) Clock Net Delay (Destination): 3.383ns (routing 0.870ns, distribution 2.513ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.812 3.812 eth/mac/i_mac/CLKFBIN SLICE_X137Y156 FDRE r eth/mac/i_mac/emacclientrxdvld_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y156 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 3.952 f eth/mac/i_mac/emacclientrxdvld_reg/Q net (fo=302, routed) 3.052 7.004 ipb/udp_if/rx_reset_block/mac_rx_valid SLICE_X140Y274 LUT2 (Prop_D5LUT_SLICEL_I1_O) 0.168 7.172 r ipb/udp_if/rx_reset_block/set_addr_i_1__1/O net (fo=682, routed) 1.169 8.341 ipb/udp_if/rx_reset_block/SR[0] SLICE_X132Y263 LUT3 (Prop_C5LUT_SLICEL_I0_O) 0.188 8.529 r ipb/udp_if/rx_reset_block/rarp.pkt_data[125]_i_1/O net (fo=97, routed) 1.287 9.816 ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[125]_0 SLICE_X142Y273 SRL16E r ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[92]_srl6___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_80/CE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y108 BUFGCE 0.000 8.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.383 11.383 ipb/udp_if/rx_packet_parser/CLKFBIN SLICE_X142Y273 SRL16E r ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[92]_srl6___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_80/CLK clock pessimism 0.076 11.459 clock uncertainty -0.053 11.406 SLICE_X142Y273 SRL16E (Setup_C6LUT_SLICEM_CLK_CE) -0.492 10.914 ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[92]_srl6___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_80 ------------------------------------------------------------------- required time 10.914 arrival time -9.816 ------------------------------------------------------------------- slack 1.098 Slack (MET) : 1.098ns (required time - arrival time) Source: eth/mac/i_mac/emacclientrxdvld_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[93]_srl7___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_81/CE (rising edge-triggered cell SRL16E clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 6.004ns (logic 0.496ns (8.261%) route 5.508ns (91.739%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.353ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.383ns = ( 11.383 - 8.000 ) Source Clock Delay (SCD): 3.812ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.812ns (routing 0.946ns, distribution 2.866ns) Clock Net Delay (Destination): 3.383ns (routing 0.870ns, distribution 2.513ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.812 3.812 eth/mac/i_mac/CLKFBIN SLICE_X137Y156 FDRE r eth/mac/i_mac/emacclientrxdvld_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y156 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 3.952 f eth/mac/i_mac/emacclientrxdvld_reg/Q net (fo=302, routed) 3.052 7.004 ipb/udp_if/rx_reset_block/mac_rx_valid SLICE_X140Y274 LUT2 (Prop_D5LUT_SLICEL_I1_O) 0.168 7.172 r ipb/udp_if/rx_reset_block/set_addr_i_1__1/O net (fo=682, routed) 1.169 8.341 ipb/udp_if/rx_reset_block/SR[0] SLICE_X132Y263 LUT3 (Prop_C5LUT_SLICEL_I0_O) 0.188 8.529 r ipb/udp_if/rx_reset_block/rarp.pkt_data[125]_i_1/O net (fo=97, routed) 1.287 9.816 ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[125]_0 SLICE_X142Y273 SRL16E r ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[93]_srl7___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_81/CE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y108 BUFGCE 0.000 8.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.383 11.383 ipb/udp_if/rx_packet_parser/CLKFBIN SLICE_X142Y273 SRL16E r ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[93]_srl7___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_81/CLK clock pessimism 0.076 11.459 clock uncertainty -0.053 11.406 SLICE_X142Y273 SRL16E (Setup_D6LUT_SLICEM_CLK_CE) -0.492 10.914 ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[93]_srl7___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_81 ------------------------------------------------------------------- required time 10.914 arrival time -9.816 ------------------------------------------------------------------- slack 1.098 Slack (MET) : 1.230ns (required time - arrival time) Source: eth/mac/i_mac/emacclientrxdvld_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: ipb/udp_if/rx_packet_parser/arp.pkt_data_reg[100]_ipb_udp_if_rx_packet_parser_arp.pkt_data_reg_r_75/CE (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 6.225ns (logic 0.396ns (6.361%) route 5.829ns (93.639%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.438ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.298ns = ( 11.298 - 8.000 ) Source Clock Delay (SCD): 3.812ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.812ns (routing 0.946ns, distribution 2.866ns) Clock Net Delay (Destination): 3.298ns (routing 0.870ns, distribution 2.428ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.812 3.812 eth/mac/i_mac/CLKFBIN SLICE_X137Y156 FDRE r eth/mac/i_mac/emacclientrxdvld_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y156 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 3.952 f eth/mac/i_mac/emacclientrxdvld_reg/Q net (fo=302, routed) 3.052 7.004 ipb/udp_if/rx_reset_block/mac_rx_valid SLICE_X140Y274 LUT2 (Prop_D5LUT_SLICEL_I1_O) 0.168 7.172 r ipb/udp_if/rx_reset_block/set_addr_i_1__1/O net (fo=682, routed) 0.788 7.960 ipb/udp_if/rx_reset_block/SR[0] SLICE_X134Y260 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 8.048 r ipb/udp_if/rx_reset_block/arp.pkt_data[31]_i_1/O net (fo=87, routed) 1.989 10.037 ipb/udp_if/rx_packet_parser/arp.pkt_data_reg[31]_0 SLICE_X119Y247 FDRE r ipb/udp_if/rx_packet_parser/arp.pkt_data_reg[100]_ipb_udp_if_rx_packet_parser_arp.pkt_data_reg_r_75/CE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y108 BUFGCE 0.000 8.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.298 11.298 ipb/udp_if/rx_packet_parser/CLKFBIN SLICE_X119Y247 FDRE r ipb/udp_if/rx_packet_parser/arp.pkt_data_reg[100]_ipb_udp_if_rx_packet_parser_arp.pkt_data_reg_r_75/C clock pessimism 0.076 11.374 clock uncertainty -0.053 11.321 SLICE_X119Y247 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 11.267 ipb/udp_if/rx_packet_parser/arp.pkt_data_reg[100]_ipb_udp_if_rx_packet_parser_arp.pkt_data_reg_r_75 ------------------------------------------------------------------- required time 11.267 arrival time -10.037 ------------------------------------------------------------------- slack 1.230 Slack (MET) : 1.230ns (required time - arrival time) Source: eth/mac/i_mac/emacclientrxdvld_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: ipb/udp_if/rx_packet_parser/arp.pkt_data_reg[59]_ipb_udp_if_rx_packet_parser_arp.pkt_data_reg_r_70/CE (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 6.225ns (logic 0.396ns (6.361%) route 5.829ns (93.639%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.438ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.298ns = ( 11.298 - 8.000 ) Source Clock Delay (SCD): 3.812ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.812ns (routing 0.946ns, distribution 2.866ns) Clock Net Delay (Destination): 3.298ns (routing 0.870ns, distribution 2.428ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.812 3.812 eth/mac/i_mac/CLKFBIN SLICE_X137Y156 FDRE r eth/mac/i_mac/emacclientrxdvld_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y156 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 3.952 f eth/mac/i_mac/emacclientrxdvld_reg/Q net (fo=302, routed) 3.052 7.004 ipb/udp_if/rx_reset_block/mac_rx_valid SLICE_X140Y274 LUT2 (Prop_D5LUT_SLICEL_I1_O) 0.168 7.172 r ipb/udp_if/rx_reset_block/set_addr_i_1__1/O net (fo=682, routed) 0.788 7.960 ipb/udp_if/rx_reset_block/SR[0] SLICE_X134Y260 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 8.048 r ipb/udp_if/rx_reset_block/arp.pkt_data[31]_i_1/O net (fo=87, routed) 1.989 10.037 ipb/udp_if/rx_packet_parser/arp.pkt_data_reg[31]_0 SLICE_X119Y247 FDRE r ipb/udp_if/rx_packet_parser/arp.pkt_data_reg[59]_ipb_udp_if_rx_packet_parser_arp.pkt_data_reg_r_70/CE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y108 BUFGCE 0.000 8.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.298 11.298 ipb/udp_if/rx_packet_parser/CLKFBIN SLICE_X119Y247 FDRE r ipb/udp_if/rx_packet_parser/arp.pkt_data_reg[59]_ipb_udp_if_rx_packet_parser_arp.pkt_data_reg_r_70/C clock pessimism 0.076 11.374 clock uncertainty -0.053 11.321 SLICE_X119Y247 FDRE (Setup_BFF_SLICEM_C_CE) -0.054 11.267 ipb/udp_if/rx_packet_parser/arp.pkt_data_reg[59]_ipb_udp_if_rx_packet_parser_arp.pkt_data_reg_r_70 ------------------------------------------------------------------- required time 11.267 arrival time -10.037 ------------------------------------------------------------------- slack 1.230 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.024ns (arrival time - required time) Source: ipb/udp_if/rx_packet_parser/ipbus_mask.pkt_mask_reg[39]_srl32____ipb_udp_if_rx_packet_parser_ipbus_mask.pkt_mask_reg_s_30/CLK (rising edge-triggered cell SRLC32E clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: ipb/udp_if/rx_packet_parser/ipbus_mask.pkt_mask_reg[42]_srl3____ipb_udp_if_rx_packet_parser_ipbus_mask.pkt_mask_reg_s_33/D (rising edge-triggered cell SRL16E clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.153ns (logic 0.153ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.009ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.600ns Source Clock Delay (SCD): 1.366ns Clock Pessimism Removal (CPR): 0.225ns Clock Net Delay (Source): 1.366ns (routing 0.352ns, distribution 1.014ns) Clock Net Delay (Destination): 1.600ns (routing 0.390ns, distribution 1.210ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.366 1.366 ipb/udp_if/rx_packet_parser/CLKFBIN SLICE_X142Y264 SRLC32E r ipb/udp_if/rx_packet_parser/ipbus_mask.pkt_mask_reg[39]_srl32____ipb_udp_if_rx_packet_parser_ipbus_mask.pkt_mask_reg_s_30/CLK ------------------------------------------------------------------- ------------------- SLICE_X142Y264 SRLC32E (Prop_B6LUT_SLICEM_CLK_Q31) 0.153 1.519 r ipb/udp_if/rx_packet_parser/ipbus_mask.pkt_mask_reg[39]_srl32____ipb_udp_if_rx_packet_parser_ipbus_mask.pkt_mask_reg_s_30/Q31 net (fo=1, routed) 0.000 1.519 ipb/udp_if/rx_packet_parser/ipbus_mask.pkt_mask_reg[39]_srl32____ipb_udp_if_rx_packet_parser_ipbus_mask.pkt_mask_reg_s_30_n_1 SLICE_X142Y264 SRL16E r ipb/udp_if/rx_packet_parser/ipbus_mask.pkt_mask_reg[42]_srl3____ipb_udp_if_rx_packet_parser_ipbus_mask.pkt_mask_reg_s_33/D ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.600 1.600 ipb/udp_if/rx_packet_parser/CLKFBIN SLICE_X142Y264 SRL16E r ipb/udp_if/rx_packet_parser/ipbus_mask.pkt_mask_reg[42]_srl3____ipb_udp_if_rx_packet_parser_ipbus_mask.pkt_mask_reg_s_33/CLK clock pessimism -0.225 1.375 SLICE_X142Y264 SRL16E (Hold_A6LUT_SLICEM_CLK_D) 0.120 1.495 ipb/udp_if/rx_packet_parser/ipbus_mask.pkt_mask_reg[42]_srl3____ipb_udp_if_rx_packet_parser_ipbus_mask.pkt_mask_reg_s_33 ------------------------------------------------------------------- required time -1.495 arrival time 1.519 ------------------------------------------------------------------- slack 0.024 Slack (MET) : 0.031ns (arrival time - required time) Source: ipb/udp_if/tx_main/udp_build_data.udpram_end_addr_int_reg[7]/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: ipb/udp_if/tx_main/state_machine.end_addr_int_reg[7]/D (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.079ns (45.665%) route 0.094ns (54.335%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.610ns Source Clock Delay (SCD): 1.371ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 1.371ns (routing 0.352ns, distribution 1.019ns) Clock Net Delay (Destination): 1.610ns (routing 0.390ns, distribution 1.220ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.371 1.371 ipb/udp_if/tx_main/CLKFBIN SLICE_X133Y256 FDRE r ipb/udp_if/tx_main/udp_build_data.udpram_end_addr_int_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y256 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.420 r ipb/udp_if/tx_main/udp_build_data.udpram_end_addr_int_reg[7]/Q net (fo=2, routed) 0.079 1.499 ipb/udp_if/tx_main/udp_build_data.udpram_end_addr_int_reg[7] SLICE_X135Y256 LUT5 (Prop_B6LUT_SLICEL_I0_O) 0.030 1.529 r ipb/udp_if/tx_main/state_machine.end_addr_int[7]_i_1/O net (fo=1, routed) 0.015 1.544 ipb/udp_if/tx_main/state_machine.end_addr_int[7]_i_1_n_0 SLICE_X135Y256 FDRE r ipb/udp_if/tx_main/state_machine.end_addr_int_reg[7]/D ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.610 1.610 ipb/udp_if/tx_main/CLKFBIN SLICE_X135Y256 FDRE r ipb/udp_if/tx_main/state_machine.end_addr_int_reg[7]/C clock pessimism -0.153 1.457 SLICE_X135Y256 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.513 ipb/udp_if/tx_main/state_machine.end_addr_int_reg[7] ------------------------------------------------------------------- required time -1.513 arrival time 1.544 ------------------------------------------------------------------- slack 0.031 Slack (MET) : 0.032ns (arrival time - required time) Source: ipb/udp_if/rx_packet_parser/rarp.pkt_mask_reg[37]/C (rising edge-triggered cell FDSE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: ipb/udp_if/rx_packet_parser/rarp.pkt_drop_reg/D (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.079ns (45.665%) route 0.094ns (54.335%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.605ns Source Clock Delay (SCD): 1.367ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 1.367ns (routing 0.352ns, distribution 1.015ns) Clock Net Delay (Destination): 1.605ns (routing 0.390ns, distribution 1.215ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.367 1.367 ipb/udp_if/rx_packet_parser/CLKFBIN SLICE_X141Y263 FDSE r ipb/udp_if/rx_packet_parser/rarp.pkt_mask_reg[37]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y263 FDSE (Prop_DFF2_SLICEL_C_Q) 0.049 1.416 f ipb/udp_if/rx_packet_parser/rarp.pkt_mask_reg[37]/Q net (fo=4, routed) 0.078 1.494 ipb/udp_if/rx_packet_parser/rarp.pkt_mask_reg[37]_0 SLICE_X139Y263 LUT6 (Prop_D6LUT_SLICEL_I2_O) 0.030 1.524 r ipb/udp_if/rx_packet_parser/rarp.pkt_drop_i_1/O net (fo=1, routed) 0.016 1.540 ipb/udp_if/rx_packet_parser/rarp.pkt_drop_i_1_n_0 SLICE_X139Y263 FDRE r ipb/udp_if/rx_packet_parser/rarp.pkt_drop_reg/D ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.605 1.605 ipb/udp_if/rx_packet_parser/CLKFBIN SLICE_X139Y263 FDRE r ipb/udp_if/rx_packet_parser/rarp.pkt_drop_reg/C clock pessimism -0.153 1.452 SLICE_X139Y263 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.508 ipb/udp_if/rx_packet_parser/rarp.pkt_drop_reg ------------------------------------------------------------------- required time -1.508 arrival time 1.540 ------------------------------------------------------------------- slack 0.032 Slack (MET) : 0.033ns (arrival time - required time) Source: eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync5/C (rising edge-triggered cell FDPE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync6/D (rising edge-triggered cell FDPE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.048ns (33.566%) route 0.095ns (66.434%)) Logic Levels: 0 Clock Path Skew: 0.054ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.647ns Source Clock Delay (SCD): 1.421ns Clock Pessimism Removal (CPR): 0.172ns Clock Net Delay (Source): 1.421ns (routing 0.352ns, distribution 1.069ns) Clock Net Delay (Destination): 1.647ns (routing 0.390ns, distribution 1.257ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.421 1.421 eth/phy/U0/transceiver_inst/reclock_encommaalign/userclk2 SLICE_X139Y2 FDPE r eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync5/C ------------------------------------------------------------------- ------------------- SLICE_X139Y2 FDPE (Prop_EFF2_SLICEL_C_Q) 0.048 1.469 r eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync5/Q net (fo=1, routed) 0.095 1.564 eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync_reg5 SLICE_X139Y3 FDPE r eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync6/D ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.647 1.647 eth/phy/U0/transceiver_inst/reclock_encommaalign/userclk2 SLICE_X139Y3 FDPE r eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync6/C clock pessimism -0.172 1.475 SLICE_X139Y3 FDPE (Hold_AFF2_SLICEL_C_D) 0.056 1.531 eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync6 ------------------------------------------------------------------- required time -1.531 arrival time 1.564 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.033ns (arrival time - required time) Source: eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_RX/reset_sync5/C (rising edge-triggered cell FDPE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_RX/reset_sync6/D (rising edge-triggered cell FDPE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.048ns (33.566%) route 0.095ns (66.434%)) Logic Levels: 0 Clock Path Skew: 0.054ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.640ns Source Clock Delay (SCD): 1.415ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 1.415ns (routing 0.352ns, distribution 1.063ns) Clock Net Delay (Destination): 1.640ns (routing 0.390ns, distribution 1.250ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.415 1.415 eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_RX/rxuserclk2 SLICE_X140Y8 FDPE r eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_RX/reset_sync5/C ------------------------------------------------------------------- ------------------- SLICE_X140Y8 FDPE (Prop_EFF2_SLICEL_C_Q) 0.048 1.463 r eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_RX/reset_sync5/Q net (fo=1, routed) 0.095 1.558 eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_RX/reset_sync_reg5 SLICE_X140Y9 FDPE r eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_RX/reset_sync6/D ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.640 1.640 eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_RX/rxuserclk2 SLICE_X140Y9 FDPE r eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_RX/reset_sync6/C clock pessimism -0.171 1.469 SLICE_X140Y9 FDPE (Hold_AFF2_SLICEL_C_D) 0.056 1.525 eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_RX/reset_sync6 ------------------------------------------------------------------- required time -1.525 arrival time 1.558 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.034ns (arrival time - required time) Source: ipb/udp_if/status/write_data.shift_buf_reg[20]/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: ipb/udp_if/status/write_data.shift_buf_reg[28]/D (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.150ns (logic 0.064ns (42.667%) route 0.086ns (57.333%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.616ns Source Clock Delay (SCD): 1.372ns Clock Pessimism Removal (CPR): 0.184ns Clock Net Delay (Source): 1.372ns (routing 0.352ns, distribution 1.020ns) Clock Net Delay (Destination): 1.616ns (routing 0.390ns, distribution 1.226ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.372 1.372 ipb/udp_if/status/CLKFBIN SLICE_X139Y249 FDRE r ipb/udp_if/status/write_data.shift_buf_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X139Y249 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.421 r ipb/udp_if/status/write_data.shift_buf_reg[20]/Q net (fo=2, routed) 0.070 1.491 ipb/udp_if/status_buffer/status_data_reg[7]_0[20] SLICE_X139Y248 LUT5 (Prop_D6LUT_SLICEL_I2_O) 0.015 1.506 r ipb/udp_if/status_buffer/write_data.shift_buf[28]_i_1__0/O net (fo=1, routed) 0.016 1.522 ipb/udp_if/status/D[20] SLICE_X139Y248 FDRE r ipb/udp_if/status/write_data.shift_buf_reg[28]/D ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.616 1.616 ipb/udp_if/status/CLKFBIN SLICE_X139Y248 FDRE r ipb/udp_if/status/write_data.shift_buf_reg[28]/C clock pessimism -0.184 1.432 SLICE_X139Y248 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.488 ipb/udp_if/status/write_data.shift_buf_reg[28] ------------------------------------------------------------------- required time -1.488 arrival time 1.522 ------------------------------------------------------------------- slack 0.034 Slack (MET) : 0.034ns (arrival time - required time) Source: eth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[7]/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: eth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[7]_srl5/D (rising edge-triggered cell SRL16E clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.510ns (logic 0.123ns (24.118%) route 0.387ns (75.882%)) Logic Levels: 0 Clock Path Skew: 0.138ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.798ns Source Clock Delay (SCD): 3.404ns Clock Pessimism Removal (CPR): 0.256ns Clock Net Delay (Source): 3.404ns (routing 0.870ns, distribution 2.534ns) Clock Net Delay (Destination): 3.798ns (routing 0.946ns, distribution 2.852ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.404 3.404 eth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/userclk2 SLICE_X141Y5 FDRE r eth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y5 FDRE (Prop_EFF2_SLICEL_C_Q) 0.123 3.527 r eth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[7]/Q net (fo=8, routed) 0.387 3.914 eth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/Q[7] SLICE_X142Y2 SRL16E r eth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[7]_srl5/D ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.798 3.798 eth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/userclk2 SLICE_X142Y2 SRL16E r eth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[7]_srl5/CLK clock pessimism -0.256 3.542 SLICE_X142Y2 SRL16E (Hold_H6LUT_SLICEM_CLK_D) 0.338 3.880 eth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[7]_srl5 ------------------------------------------------------------------- required time -3.880 arrival time 3.914 ------------------------------------------------------------------- slack 0.034 Slack (MET) : 0.036ns (arrival time - required time) Source: eth/mac/i_mac/i_tx_CRC32D8/crc_i_reg[12]/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: eth/mac/i_mac/i_tx_CRC32D8/crc_i_reg[20]/D (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.181ns (logic 0.094ns (51.934%) route 0.087ns (48.066%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.561ns Source Clock Delay (SCD): 1.326ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 1.326ns (routing 0.352ns, distribution 0.974ns) Clock Net Delay (Destination): 1.561ns (routing 0.390ns, distribution 1.171ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.326 1.326 eth/mac/i_mac/i_tx_CRC32D8/CLKFBIN SLICE_X138Y209 FDRE r eth/mac/i_mac/i_tx_CRC32D8/crc_i_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X138Y209 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.375 r eth/mac/i_mac/i_tx_CRC32D8/crc_i_reg[12]/Q net (fo=2, routed) 0.075 1.450 eth/mac/i_mac/i_tx_CRC32D8/p_19_in SLICE_X137Y209 LUT4 (Prop_H6LUT_SLICEL_I2_O) 0.045 1.495 r eth/mac/i_mac/i_tx_CRC32D8/crc_i[20]_i_1/O net (fo=1, routed) 0.012 1.507 eth/mac/i_mac/i_tx_CRC32D8/p_42_out[20] SLICE_X137Y209 FDRE r eth/mac/i_mac/i_tx_CRC32D8/crc_i_reg[20]/D ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.561 1.561 eth/mac/i_mac/i_tx_CRC32D8/CLKFBIN SLICE_X137Y209 FDRE r eth/mac/i_mac/i_tx_CRC32D8/crc_i_reg[20]/C clock pessimism -0.146 1.415 SLICE_X137Y209 FDRE (Hold_HFF2_SLICEL_C_D) 0.056 1.471 eth/mac/i_mac/i_tx_CRC32D8/crc_i_reg[20] ------------------------------------------------------------------- required time -1.471 arrival time 1.507 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.037ns (arrival time - required time) Source: ipb/udp_if/tx_main/do_ipbus_hdr.ipbus_hdr_int_reg[21]/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: ipb/udp_if/status_buffer/ipbus_out_reg[21]/D (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.182ns (logic 0.049ns (26.923%) route 0.133ns (73.077%)) Logic Levels: 0 Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.615ns Source Clock Delay (SCD): 1.373ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 1.373ns (routing 0.352ns, distribution 1.021ns) Clock Net Delay (Destination): 1.615ns (routing 0.390ns, distribution 1.225ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.373 1.373 ipb/udp_if/tx_main/CLKFBIN SLICE_X137Y241 FDRE r ipb/udp_if/tx_main/do_ipbus_hdr.ipbus_hdr_int_reg[21]/C ------------------------------------------------------------------- ------------------- SLICE_X137Y241 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.422 r ipb/udp_if/tx_main/do_ipbus_hdr.ipbus_hdr_int_reg[21]/Q net (fo=3, routed) 0.133 1.555 ipb/udp_if/status_buffer/Q[21] SLICE_X139Y241 FDRE r ipb/udp_if/status_buffer/ipbus_out_reg[21]/D ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.615 1.615 ipb/udp_if/status_buffer/CLKFBIN SLICE_X139Y241 FDRE r ipb/udp_if/status_buffer/ipbus_out_reg[21]/C clock pessimism -0.153 1.462 SLICE_X139Y241 FDRE (Hold_HFF2_SLICEL_C_D) 0.056 1.518 ipb/udp_if/status_buffer/ipbus_out_reg[21] ------------------------------------------------------------------- required time -1.518 arrival time 1.555 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.037ns (arrival time - required time) Source: ipb/udp_if/RARP_block/data_block.data_buffer_reg[47]/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: ipb/udp_if/RARP_block/data_block.we_buffer_reg[2]/D (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.182ns (logic 0.094ns (51.648%) route 0.088ns (48.352%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.564ns Source Clock Delay (SCD): 1.329ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 1.329ns (routing 0.352ns, distribution 0.977ns) Clock Net Delay (Destination): 1.564ns (routing 0.390ns, distribution 1.174ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.329 1.329 ipb/udp_if/RARP_block/CLKFBIN SLICE_X130Y233 FDRE r ipb/udp_if/RARP_block/data_block.data_buffer_reg[47]/C ------------------------------------------------------------------- ------------------- SLICE_X130Y233 FDRE (Prop_EFF_SLICEL_C_Q) 0.049 1.378 r ipb/udp_if/RARP_block/data_block.data_buffer_reg[47]/Q net (fo=2, routed) 0.074 1.452 ipb/udp_if/RARP_block/data_buffer[47] SLICE_X131Y233 LUT2 (Prop_G6LUT_SLICEL_I1_O) 0.045 1.497 r ipb/udp_if/RARP_block/data_block.we_buffer[2]_i_1/O net (fo=1, routed) 0.014 1.511 ipb/udp_if/RARP_block/data_block.we_buffer[2]_i_1_n_0 SLICE_X131Y233 FDRE r ipb/udp_if/RARP_block/data_block.we_buffer_reg[2]/D ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.564 1.564 ipb/udp_if/RARP_block/CLKFBIN SLICE_X131Y233 FDRE r ipb/udp_if/RARP_block/data_block.we_buffer_reg[2]/C clock pessimism -0.146 1.418 SLICE_X131Y233 FDRE (Hold_GFF_SLICEL_C_D) 0.056 1.474 ipb/udp_if/RARP_block/data_block.we_buffer_reg[2] ------------------------------------------------------------------- required time -1.474 arrival time 1.511 ------------------------------------------------------------------- slack 0.037 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk125 Waveform(ns): { 0.000 4.000 } Period(ns): 8.000 Sources: { i_clk125_bufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/DRPCLK n/a 4.000 8.000 4.000 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 2.174 8.000 5.826 RAMB36_X17Y51 ipb/udp_if/internal_ram/ram_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKBWRCLK n/a 1.905 8.000 6.095 RAMB36_X17Y51 ipb/udp_if/internal_ram/ram_reg_bram_0/CLKBWRCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 1.905 8.000 6.095 RAMB36_X15Y51 ipb/udp_if/ipbus_rx_ram/ram1_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 1.905 8.000 6.095 RAMB36_X15Y52 ipb/udp_if/ipbus_rx_ram/ram1_reg_bram_1/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 1.905 8.000 6.095 RAMB36_X16Y51 ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 1.905 8.000 6.095 RAMB36_X16Y52 ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 1.905 8.000 6.095 RAMB36_X16Y49 ipb/udp_if/ipbus_rx_ram/ram3_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 1.905 8.000 6.095 RAMB36_X16Y50 ipb/udp_if/ipbus_rx_ram/ram3_reg_bram_1/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 1.905 8.000 6.095 RAMB36_X15Y49 ipb/udp_if/ipbus_rx_ram/ram4_reg_bram_0/CLKARDCLK Low Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.000 2.200 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Fast GTHE3_CHANNEL/DRPCLK n/a 1.800 4.000 2.200 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 4.000 2.914 RAMB36_X17Y51 ipb/udp_if/internal_ram/ram_reg_bram_0/CLKARDCLK Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 1.086 4.000 2.914 RAMB36_X17Y51 ipb/udp_if/internal_ram/ram_reg_bram_0/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.952 4.000 3.048 RAMB36_X17Y51 ipb/udp_if/internal_ram/ram_reg_bram_0/CLKBWRCLK Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.952 4.000 3.048 RAMB36_X15Y52 ipb/udp_if/ipbus_rx_ram/ram1_reg_bram_1/CLKARDCLK Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.952 4.000 3.048 RAMB36_X16Y51 ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 4.000 3.048 RAMB36_X16Y52 ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 4.000 3.048 RAMB36_X16Y49 ipb/udp_if/ipbus_rx_ram/ram3_reg_bram_0/CLKARDCLK Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.952 4.000 3.048 RAMB36_X15Y49 ipb/udp_if/ipbus_rx_ram/ram4_reg_bram_0/CLKARDCLK High Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.000 2.200 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Fast GTHE3_CHANNEL/DRPCLK n/a 1.800 4.000 2.200 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 1.086 4.000 2.914 RAMB36_X17Y51 ipb/udp_if/internal_ram/ram_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 4.000 2.914 RAMB36_X17Y51 ipb/udp_if/internal_ram/ram_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 4.000 3.048 RAMB36_X16Y50 ipb/udp_if/ipbus_rx_ram/ram3_reg_bram_1/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 4.000 3.048 RAMB36_X15Y49 ipb/udp_if/ipbus_rx_ram/ram4_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 4.000 3.048 RAMB36_X15Y50 ipb/udp_if/ipbus_rx_ram/ram4_reg_bram_1/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.952 4.000 3.048 RAMB36_X11Y48 ipb/udp_if/ipbus_tx_ram/ram_reg_bram_4/CLKBWRCLK High Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.952 4.000 3.048 RAMB36_X11Y49 ipb/udp_if/ipbus_tx_ram/ram_reg_bram_5/CLKBWRCLK High Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.952 4.000 3.048 RAMB36_X17Y51 ipb/udp_if/internal_ram/ram_reg_bram_0/CLKBWRCLK --------------------------------------------------------------------------------------------------- From Clock: clk250 To Clock: clk250 Setup : 0 Failing Endpoints, Worst Slack 0.158ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.042ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 1.048ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.158ns (required time - arrival time) Source: stat_regs_inst/reset_count_rate_reg_rep/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: stat_regs_inst/g_DSP_rate[50].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/RSTP (rising edge-triggered cell DSP_OUTPUT clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - clk250 rise@0.000ns) Data Path Delay: 3.105ns (logic 0.140ns (4.509%) route 2.965ns (95.491%)) Logic Levels: 0 Clock Path Skew: -0.271ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.143ns = ( 7.143 - 4.000 ) Source Clock Delay (SCD): 3.529ns Clock Pessimism Removal (CPR): 0.115ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.104ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.529ns (routing 1.281ns, distribution 2.248ns) Clock Net Delay (Destination): 3.143ns (routing 1.181ns, distribution 1.962ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.529 3.529 stat_regs_inst/clk250 SLICE_X98Y167 FDRE r stat_regs_inst/reset_count_rate_reg_rep/C ------------------------------------------------------------------- ------------------- SLICE_X98Y167 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 3.669 r stat_regs_inst/reset_count_rate_reg_rep/Q net (fo=32, routed) 2.965 6.634 stat_regs_inst/g_DSP_rate[50].i_DSP_counterX4/DSP48E2_inst/RSTP DSP48E2_X21Y41 DSP_OUTPUT r stat_regs_inst/g_DSP_rate[50].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/RSTP ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y100 BUFGCE 0.000 4.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.143 7.143 stat_regs_inst/g_DSP_rate[50].i_DSP_counterX4/DSP48E2_inst/CLK DSP48E2_X21Y41 DSP_OUTPUT r stat_regs_inst/g_DSP_rate[50].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK clock pessimism 0.115 7.258 clock uncertainty -0.063 7.195 DSP48E2_X21Y41 DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_RSTP) -0.403 6.792 stat_regs_inst/g_DSP_rate[50].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST ------------------------------------------------------------------- required time 6.792 arrival time -6.634 ------------------------------------------------------------------- slack 0.158 Slack (MET) : 0.160ns (required time - arrival time) Source: g_clock_rate_din[23].i_rate_ngccm_status0/q_reg/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[23].i_rate_ngccm_status2/rate_i_reg[5]/CE (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - clk250 rise@0.000ns) Data Path Delay: 3.934ns (logic 0.139ns (3.533%) route 3.795ns (96.467%)) Logic Levels: 0 Clock Path Skew: 0.211ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.201ns = ( 7.201 - 4.000 ) Source Clock Delay (SCD): 3.241ns Clock Pessimism Removal (CPR): 0.251ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.104ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.241ns (routing 1.281ns, distribution 1.960ns) Clock Net Delay (Destination): 3.201ns (routing 1.181ns, distribution 2.020ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.241 3.241 g_clock_rate_din[23].i_rate_ngccm_status0/clk250 SLICE_X84Y280 FDRE r g_clock_rate_din[23].i_rate_ngccm_status0/q_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y280 FDRE (Prop_EFF_SLICEL_C_Q) 0.139 3.380 r g_clock_rate_din[23].i_rate_ngccm_status0/q_reg/Q net (fo=98, routed) 3.795 7.175 g_clock_rate_din[23].i_rate_ngccm_status2/E[0] SLICE_X114Y289 FDRE r g_clock_rate_din[23].i_rate_ngccm_status2/rate_i_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y100 BUFGCE 0.000 4.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.201 7.201 g_clock_rate_din[23].i_rate_ngccm_status2/clk250 SLICE_X114Y289 FDRE r g_clock_rate_din[23].i_rate_ngccm_status2/rate_i_reg[5]/C clock pessimism 0.251 7.452 clock uncertainty -0.063 7.389 SLICE_X114Y289 FDRE (Setup_AFF_SLICEL_C_CE) -0.054 7.335 g_clock_rate_din[23].i_rate_ngccm_status2/rate_i_reg[5] ------------------------------------------------------------------- required time 7.335 arrival time -7.175 ------------------------------------------------------------------- slack 0.160 Slack (MET) : 0.160ns (required time - arrival time) Source: g_clock_rate_din[24].i_rate_ngccm_status0/q_reg/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[21]/CE (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - clk250 rise@0.000ns) Data Path Delay: 3.778ns (logic 0.139ns (3.679%) route 3.639ns (96.321%)) Logic Levels: 0 Clock Path Skew: 0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.183ns = ( 7.183 - 4.000 ) Source Clock Delay (SCD): 3.228ns Clock Pessimism Removal (CPR): 0.100ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.104ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.228ns (routing 1.281ns, distribution 1.947ns) Clock Net Delay (Destination): 3.183ns (routing 1.181ns, distribution 2.002ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.228 3.228 g_clock_rate_din[24].i_rate_ngccm_status0/clk250 SLICE_X89Y239 FDRE r g_clock_rate_din[24].i_rate_ngccm_status0/q_reg/C ------------------------------------------------------------------- ------------------- SLICE_X89Y239 FDRE (Prop_DFF_SLICEM_C_Q) 0.139 3.367 r g_clock_rate_din[24].i_rate_ngccm_status0/q_reg/Q net (fo=98, routed) 3.639 7.006 g_clock_rate_din[24].i_rate_ngccm_status2/E[0] SLICE_X117Y271 FDRE r g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[21]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y100 BUFGCE 0.000 4.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.183 7.183 g_clock_rate_din[24].i_rate_ngccm_status2/clk250 SLICE_X117Y271 FDRE r g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[21]/C clock pessimism 0.100 7.283 clock uncertainty -0.063 7.220 SLICE_X117Y271 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 7.166 g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[21] ------------------------------------------------------------------- required time 7.166 arrival time -7.006 ------------------------------------------------------------------- slack 0.160 Slack (MET) : 0.160ns (required time - arrival time) Source: g_clock_rate_din[24].i_rate_ngccm_status0/q_reg/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[28]/CE (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - clk250 rise@0.000ns) Data Path Delay: 3.778ns (logic 0.139ns (3.679%) route 3.639ns (96.321%)) Logic Levels: 0 Clock Path Skew: 0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.183ns = ( 7.183 - 4.000 ) Source Clock Delay (SCD): 3.228ns Clock Pessimism Removal (CPR): 0.100ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.104ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.228ns (routing 1.281ns, distribution 1.947ns) Clock Net Delay (Destination): 3.183ns (routing 1.181ns, distribution 2.002ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.228 3.228 g_clock_rate_din[24].i_rate_ngccm_status0/clk250 SLICE_X89Y239 FDRE r g_clock_rate_din[24].i_rate_ngccm_status0/q_reg/C ------------------------------------------------------------------- ------------------- SLICE_X89Y239 FDRE (Prop_DFF_SLICEM_C_Q) 0.139 3.367 r g_clock_rate_din[24].i_rate_ngccm_status0/q_reg/Q net (fo=98, routed) 3.639 7.006 g_clock_rate_din[24].i_rate_ngccm_status2/E[0] SLICE_X117Y271 FDRE r g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[28]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y100 BUFGCE 0.000 4.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.183 7.183 g_clock_rate_din[24].i_rate_ngccm_status2/clk250 SLICE_X117Y271 FDRE r g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[28]/C clock pessimism 0.100 7.283 clock uncertainty -0.063 7.220 SLICE_X117Y271 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 7.166 g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[28] ------------------------------------------------------------------- required time 7.166 arrival time -7.006 ------------------------------------------------------------------- slack 0.160 Slack (MET) : 0.160ns (required time - arrival time) Source: g_clock_rate_din[24].i_rate_ngccm_status0/q_reg/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[6]/CE (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - clk250 rise@0.000ns) Data Path Delay: 3.778ns (logic 0.139ns (3.679%) route 3.639ns (96.321%)) Logic Levels: 0 Clock Path Skew: 0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.183ns = ( 7.183 - 4.000 ) Source Clock Delay (SCD): 3.228ns Clock Pessimism Removal (CPR): 0.100ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.104ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.228ns (routing 1.281ns, distribution 1.947ns) Clock Net Delay (Destination): 3.183ns (routing 1.181ns, distribution 2.002ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.228 3.228 g_clock_rate_din[24].i_rate_ngccm_status0/clk250 SLICE_X89Y239 FDRE r g_clock_rate_din[24].i_rate_ngccm_status0/q_reg/C ------------------------------------------------------------------- ------------------- SLICE_X89Y239 FDRE (Prop_DFF_SLICEM_C_Q) 0.139 3.367 r g_clock_rate_din[24].i_rate_ngccm_status0/q_reg/Q net (fo=98, routed) 3.639 7.006 g_clock_rate_din[24].i_rate_ngccm_status2/E[0] SLICE_X117Y271 FDRE r g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y100 BUFGCE 0.000 4.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.183 7.183 g_clock_rate_din[24].i_rate_ngccm_status2/clk250 SLICE_X117Y271 FDRE r g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[6]/C clock pessimism 0.100 7.283 clock uncertainty -0.063 7.220 SLICE_X117Y271 FDRE (Setup_BFF_SLICEL_C_CE) -0.054 7.166 g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[6] ------------------------------------------------------------------- required time 7.166 arrival time -7.006 ------------------------------------------------------------------- slack 0.160 Slack (MET) : 0.160ns (required time - arrival time) Source: g_clock_rate_din[24].i_rate_ngccm_status0/q_reg/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[8]/CE (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - clk250 rise@0.000ns) Data Path Delay: 3.778ns (logic 0.139ns (3.679%) route 3.639ns (96.321%)) Logic Levels: 0 Clock Path Skew: 0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.183ns = ( 7.183 - 4.000 ) Source Clock Delay (SCD): 3.228ns Clock Pessimism Removal (CPR): 0.100ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.104ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.228ns (routing 1.281ns, distribution 1.947ns) Clock Net Delay (Destination): 3.183ns (routing 1.181ns, distribution 2.002ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.228 3.228 g_clock_rate_din[24].i_rate_ngccm_status0/clk250 SLICE_X89Y239 FDRE r g_clock_rate_din[24].i_rate_ngccm_status0/q_reg/C ------------------------------------------------------------------- ------------------- SLICE_X89Y239 FDRE (Prop_DFF_SLICEM_C_Q) 0.139 3.367 r g_clock_rate_din[24].i_rate_ngccm_status0/q_reg/Q net (fo=98, routed) 3.639 7.006 g_clock_rate_din[24].i_rate_ngccm_status2/E[0] SLICE_X117Y271 FDRE r g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[8]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y100 BUFGCE 0.000 4.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.183 7.183 g_clock_rate_din[24].i_rate_ngccm_status2/clk250 SLICE_X117Y271 FDRE r g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[8]/C clock pessimism 0.100 7.283 clock uncertainty -0.063 7.220 SLICE_X117Y271 FDRE (Setup_AFF_SLICEL_C_CE) -0.054 7.166 g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[8] ------------------------------------------------------------------- required time 7.166 arrival time -7.006 ------------------------------------------------------------------- slack 0.160 Slack (MET) : 0.163ns (required time - arrival time) Source: stat_regs_inst/reset_count_rate_reg/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: stat_regs_inst/g_DSP_rate[1].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/RSTP (rising edge-triggered cell DSP_OUTPUT clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - clk250 rise@0.000ns) Data Path Delay: 2.777ns (logic 0.139ns (5.005%) route 2.638ns (94.995%)) Logic Levels: 0 Clock Path Skew: -0.594ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.820ns = ( 6.820 - 4.000 ) Source Clock Delay (SCD): 3.529ns Clock Pessimism Removal (CPR): 0.115ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.104ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.529ns (routing 1.281ns, distribution 2.248ns) Clock Net Delay (Destination): 2.820ns (routing 1.181ns, distribution 1.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.529 3.529 stat_regs_inst/clk250 SLICE_X98Y167 FDRE r stat_regs_inst/reset_count_rate_reg/C ------------------------------------------------------------------- ------------------- SLICE_X98Y167 FDRE (Prop_BFF_SLICEL_C_Q) 0.139 3.668 r stat_regs_inst/reset_count_rate_reg/Q net (fo=32, routed) 2.638 6.306 stat_regs_inst/g_DSP_rate[1].i_DSP_counterX4/DSP48E2_inst/RSTP DSP48E2_X17Y39 DSP_OUTPUT r stat_regs_inst/g_DSP_rate[1].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/RSTP ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y100 BUFGCE 0.000 4.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 2.820 6.820 stat_regs_inst/g_DSP_rate[1].i_DSP_counterX4/DSP48E2_inst/CLK DSP48E2_X17Y39 DSP_OUTPUT r stat_regs_inst/g_DSP_rate[1].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK clock pessimism 0.115 6.935 clock uncertainty -0.063 6.872 DSP48E2_X17Y39 DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_RSTP) -0.403 6.469 stat_regs_inst/g_DSP_rate[1].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST ------------------------------------------------------------------- required time 6.469 arrival time -6.306 ------------------------------------------------------------------- slack 0.163 Slack (MET) : 0.165ns (required time - arrival time) Source: stat_regs_inst/reset_count_rate_reg_rep/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: stat_regs_inst/g_DSP_rate[49].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/RSTP (rising edge-triggered cell DSP_OUTPUT clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - clk250 rise@0.000ns) Data Path Delay: 3.105ns (logic 0.140ns (4.509%) route 2.965ns (95.491%)) Logic Levels: 0 Clock Path Skew: -0.264ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.150ns = ( 7.150 - 4.000 ) Source Clock Delay (SCD): 3.529ns Clock Pessimism Removal (CPR): 0.115ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.104ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.529ns (routing 1.281ns, distribution 2.248ns) Clock Net Delay (Destination): 3.150ns (routing 1.181ns, distribution 1.969ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.529 3.529 stat_regs_inst/clk250 SLICE_X98Y167 FDRE r stat_regs_inst/reset_count_rate_reg_rep/C ------------------------------------------------------------------- ------------------- SLICE_X98Y167 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 3.669 r stat_regs_inst/reset_count_rate_reg_rep/Q net (fo=32, routed) 2.965 6.634 stat_regs_inst/g_DSP_rate[49].i_DSP_counterX4/DSP48E2_inst/RSTP DSP48E2_X21Y40 DSP_OUTPUT r stat_regs_inst/g_DSP_rate[49].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/RSTP ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y100 BUFGCE 0.000 4.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.150 7.150 stat_regs_inst/g_DSP_rate[49].i_DSP_counterX4/DSP48E2_inst/CLK DSP48E2_X21Y40 DSP_OUTPUT r stat_regs_inst/g_DSP_rate[49].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK clock pessimism 0.115 7.265 clock uncertainty -0.063 7.202 DSP48E2_X21Y40 DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_RSTP) -0.403 6.799 stat_regs_inst/g_DSP_rate[49].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST ------------------------------------------------------------------- required time 6.799 arrival time -6.634 ------------------------------------------------------------------- slack 0.165 Slack (MET) : 0.167ns (required time - arrival time) Source: stat_regs_inst/reset_count_rate_reg/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: stat_regs_inst/g_DSP_rate[0].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/RSTP (rising edge-triggered cell DSP_OUTPUT clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - clk250 rise@0.000ns) Data Path Delay: 2.771ns (logic 0.139ns (5.016%) route 2.632ns (94.984%)) Logic Levels: 0 Clock Path Skew: -0.596ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.818ns = ( 6.818 - 4.000 ) Source Clock Delay (SCD): 3.529ns Clock Pessimism Removal (CPR): 0.115ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.104ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.529ns (routing 1.281ns, distribution 2.248ns) Clock Net Delay (Destination): 2.818ns (routing 1.181ns, distribution 1.637ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.529 3.529 stat_regs_inst/clk250 SLICE_X98Y167 FDRE r stat_regs_inst/reset_count_rate_reg/C ------------------------------------------------------------------- ------------------- SLICE_X98Y167 FDRE (Prop_BFF_SLICEL_C_Q) 0.139 3.668 r stat_regs_inst/reset_count_rate_reg/Q net (fo=32, routed) 2.632 6.300 stat_regs_inst/g_DSP_rate[0].i_DSP_counterX4/DSP48E2_inst/RSTP DSP48E2_X17Y38 DSP_OUTPUT r stat_regs_inst/g_DSP_rate[0].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/RSTP ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y100 BUFGCE 0.000 4.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 2.818 6.818 stat_regs_inst/g_DSP_rate[0].i_DSP_counterX4/DSP48E2_inst/CLK DSP48E2_X17Y38 DSP_OUTPUT r stat_regs_inst/g_DSP_rate[0].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK clock pessimism 0.115 6.933 clock uncertainty -0.063 6.870 DSP48E2_X17Y38 DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_RSTP) -0.403 6.467 stat_regs_inst/g_DSP_rate[0].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST ------------------------------------------------------------------- required time 6.467 arrival time -6.300 ------------------------------------------------------------------- slack 0.167 Slack (MET) : 0.168ns (required time - arrival time) Source: g_clock_rate_din[23].i_rate_ngccm_status0/q_reg/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[23].i_rate_ngccm_status2/rate_i_reg[0]/CE (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - clk250 rise@0.000ns) Data Path Delay: 3.921ns (logic 0.139ns (3.545%) route 3.782ns (96.455%)) Logic Levels: 0 Clock Path Skew: 0.206ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.196ns = ( 7.196 - 4.000 ) Source Clock Delay (SCD): 3.241ns Clock Pessimism Removal (CPR): 0.251ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.104ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.241ns (routing 1.281ns, distribution 1.960ns) Clock Net Delay (Destination): 3.196ns (routing 1.181ns, distribution 2.015ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.241 3.241 g_clock_rate_din[23].i_rate_ngccm_status0/clk250 SLICE_X84Y280 FDRE r g_clock_rate_din[23].i_rate_ngccm_status0/q_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y280 FDRE (Prop_EFF_SLICEL_C_Q) 0.139 3.380 r g_clock_rate_din[23].i_rate_ngccm_status0/q_reg/Q net (fo=98, routed) 3.782 7.162 g_clock_rate_din[23].i_rate_ngccm_status2/E[0] SLICE_X110Y295 FDRE r g_clock_rate_din[23].i_rate_ngccm_status2/rate_i_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y100 BUFGCE 0.000 4.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.196 7.196 g_clock_rate_din[23].i_rate_ngccm_status2/clk250 SLICE_X110Y295 FDRE r g_clock_rate_din[23].i_rate_ngccm_status2/rate_i_reg[0]/C clock pessimism 0.251 7.447 clock uncertainty -0.063 7.384 SLICE_X110Y295 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 7.330 g_clock_rate_din[23].i_rate_ngccm_status2/rate_i_reg[0] ------------------------------------------------------------------- required time 7.330 arrival time -7.162 ------------------------------------------------------------------- slack 0.168 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.042ns (arrival time - required time) Source: stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK (rising edge-triggered cell DSP_OUTPUT clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/A[24] (rising edge-triggered cell DSP_A_B_DATA clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.222ns (logic 0.121ns (54.505%) route 0.101ns (45.496%)) Logic Levels: 0 Clock Path Skew: 0.175ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.543ns Source Clock Delay (SCD): 1.317ns Clock Pessimism Removal (CPR): 0.051ns Clock Net Delay (Source): 1.317ns (routing 0.481ns, distribution 0.836ns) Clock Net Delay (Destination): 1.543ns (routing 0.532ns, distribution 1.011ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.317 1.317 stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/CLK DSP48E2_X8Y72 DSP_OUTPUT r stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK ------------------------------------------------------------------- ------------------- DSP48E2_X8Y72 DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[42]) 0.121 1.438 r stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/P[42] net (fo=1, routed) 0.101 1.539 stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/A[24] DSP48E2_X8Y71 DSP_A_B_DATA r stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/A[24] ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.543 1.543 stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/CLK DSP48E2_X8Y71 DSP_A_B_DATA r stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/CLK clock pessimism -0.051 1.492 DSP48E2_X8Y71 DSP_A_B_DATA (Hold_DSP_A_B_DATA_DSP48E2_CLK_A[24]) 0.005 1.497 stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST ------------------------------------------------------------------- required time -1.497 arrival time 1.539 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.046ns (arrival time - required time) Source: stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK (rising edge-triggered cell DSP_OUTPUT clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/A[23] (rising edge-triggered cell DSP_A_B_DATA clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.222ns (logic 0.122ns (54.955%) route 0.100ns (45.045%)) Logic Levels: 0 Clock Path Skew: 0.175ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.543ns Source Clock Delay (SCD): 1.317ns Clock Pessimism Removal (CPR): 0.051ns Clock Net Delay (Source): 1.317ns (routing 0.481ns, distribution 0.836ns) Clock Net Delay (Destination): 1.543ns (routing 0.532ns, distribution 1.011ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.317 1.317 stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/CLK DSP48E2_X8Y72 DSP_OUTPUT r stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK ------------------------------------------------------------------- ------------------- DSP48E2_X8Y72 DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[41]) 0.122 1.439 r stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/P[41] net (fo=1, routed) 0.100 1.539 stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/A[23] DSP48E2_X8Y71 DSP_A_B_DATA r stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/A[23] ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.543 1.543 stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/CLK DSP48E2_X8Y71 DSP_A_B_DATA r stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/CLK clock pessimism -0.051 1.492 DSP48E2_X8Y71 DSP_A_B_DATA (Hold_DSP_A_B_DATA_DSP48E2_CLK_A[23]) 0.001 1.493 stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST ------------------------------------------------------------------- required time -1.493 arrival time 1.539 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK (rising edge-triggered cell DSP_OUTPUT clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/A[29] (rising edge-triggered cell DSP_A_B_DATA clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.228ns (logic 0.123ns (53.947%) route 0.105ns (46.053%)) Logic Levels: 0 Clock Path Skew: 0.175ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.543ns Source Clock Delay (SCD): 1.317ns Clock Pessimism Removal (CPR): 0.051ns Clock Net Delay (Source): 1.317ns (routing 0.481ns, distribution 0.836ns) Clock Net Delay (Destination): 1.543ns (routing 0.532ns, distribution 1.011ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.317 1.317 stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/CLK DSP48E2_X8Y72 DSP_OUTPUT r stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK ------------------------------------------------------------------- ------------------- DSP48E2_X8Y72 DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[47]) 0.123 1.440 r stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/P[47] net (fo=1, routed) 0.105 1.545 stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/A[29] DSP48E2_X8Y71 DSP_A_B_DATA r stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/A[29] ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.543 1.543 stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/CLK DSP48E2_X8Y71 DSP_A_B_DATA r stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/CLK clock pessimism -0.051 1.492 DSP48E2_X8Y71 DSP_A_B_DATA (Hold_DSP_A_B_DATA_DSP48E2_CLK_A[29]) 0.006 1.498 stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST ------------------------------------------------------------------- required time -1.498 arrival time 1.545 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.051ns (arrival time - required time) Source: g_clock_rate_din[40].i_rate_ngccm_status0/P0_q_reg/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[40].i_rate_ngccm_status0/q_reg/D (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.112ns (logic 0.064ns (57.143%) route 0.048ns (42.857%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.340ns Source Clock Delay (SCD): 1.150ns Clock Pessimism Removal (CPR): 0.185ns Clock Net Delay (Source): 1.150ns (routing 0.481ns, distribution 0.669ns) Clock Net Delay (Destination): 1.340ns (routing 0.532ns, distribution 0.808ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.150 1.150 g_clock_rate_din[40].i_rate_ngccm_status0/clk250 SLICE_X84Y266 FDRE r g_clock_rate_din[40].i_rate_ngccm_status0/P0_q_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y266 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.199 r g_clock_rate_din[40].i_rate_ngccm_status0/P0_q_reg/Q net (fo=1, routed) 0.032 1.231 g_clock_rate_din[40].i_rate_ngccm_status0/P0_q SLICE_X84Y266 LUT2 (Prop_C6LUT_SLICEL_I1_O) 0.015 1.246 r g_clock_rate_din[40].i_rate_ngccm_status0/q_i_1__39/O net (fo=33, routed) 0.016 1.262 g_clock_rate_din[40].i_rate_ngccm_status0/q0 SLICE_X84Y266 FDRE r g_clock_rate_din[40].i_rate_ngccm_status0/q_reg/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.340 1.340 g_clock_rate_din[40].i_rate_ngccm_status0/clk250 SLICE_X84Y266 FDRE r g_clock_rate_din[40].i_rate_ngccm_status0/q_reg/C clock pessimism -0.185 1.155 SLICE_X84Y266 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.211 g_clock_rate_din[40].i_rate_ngccm_status0/q_reg ------------------------------------------------------------------- required time -1.211 arrival time 1.262 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.051ns (arrival time - required time) Source: stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK (rising edge-triggered cell DSP_OUTPUT clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/A[22] (rising edge-triggered cell DSP_A_B_DATA clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.220ns (logic 0.120ns (54.545%) route 0.100ns (45.455%)) Logic Levels: 0 Clock Path Skew: 0.175ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.543ns Source Clock Delay (SCD): 1.317ns Clock Pessimism Removal (CPR): 0.051ns Clock Net Delay (Source): 1.317ns (routing 0.481ns, distribution 0.836ns) Clock Net Delay (Destination): 1.543ns (routing 0.532ns, distribution 1.011ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.317 1.317 stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/CLK DSP48E2_X8Y72 DSP_OUTPUT r stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK ------------------------------------------------------------------- ------------------- DSP48E2_X8Y72 DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[40]) 0.120 1.437 r stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/P[40] net (fo=1, routed) 0.100 1.537 stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/A[22] DSP48E2_X8Y71 DSP_A_B_DATA r stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/A[22] ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.543 1.543 stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/CLK DSP48E2_X8Y71 DSP_A_B_DATA r stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/CLK clock pessimism -0.051 1.492 DSP48E2_X8Y71 DSP_A_B_DATA (Hold_DSP_A_B_DATA_DSP48E2_CLK_A[22]) -0.006 1.486 stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST ------------------------------------------------------------------- required time -1.486 arrival time 1.537 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.056ns (arrival time - required time) Source: stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/reset_r_reg[1]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/d_sync_rst_reg[1]/D (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.152ns (logic 0.104ns (68.421%) route 0.048ns (31.579%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.389ns Source Clock Delay (SCD): 1.190ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 1.190ns (routing 0.481ns, distribution 0.709ns) Clock Net Delay (Destination): 1.389ns (routing 0.532ns, distribution 0.857ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.190 1.190 stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/clk250 SLICE_X60Y124 FDRE r stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/reset_r_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y124 FDRE (Prop_FFF_SLICEL_C_Q) 0.049 1.239 r stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/reset_r_reg[1]/Q net (fo=2, routed) 0.037 1.276 stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/p_5_in SLICE_X60Y124 LUT3 (Prop_C5LUT_SLICEL_I1_O) 0.055 1.331 r stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/d_sync_rst[1]_i_1/O net (fo=1, routed) 0.011 1.342 stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/d_sync_rst[1]_i_1_n_0 SLICE_X60Y124 FDRE r stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/d_sync_rst_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.389 1.389 stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/clk250 SLICE_X60Y124 FDRE r stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/d_sync_rst_reg[1]/C clock pessimism -0.159 1.230 SLICE_X60Y124 FDRE (Hold_CFF2_SLICEL_C_D) 0.056 1.286 stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/d_sync_rst_reg[1] ------------------------------------------------------------------- required time -1.286 arrival time 1.342 ------------------------------------------------------------------- slack 0.056 Slack (MET) : 0.059ns (arrival time - required time) Source: stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/g_sync[0].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d_reg[0]/D (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.101ns (65.584%) route 0.053ns (34.416%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.311ns Source Clock Delay (SCD): 1.116ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.116ns (routing 0.481ns, distribution 0.635ns) Clock Net Delay (Destination): 1.311ns (routing 0.532ns, distribution 0.779ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.116 1.116 stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/g_sync[0].g_cdc.xpm_cdc_single_inst/dest_clk SLICE_X78Y208 FDRE r stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/g_sync[0].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y208 FDRE (Prop_CFF2_SLICEL_C_Q) 0.048 1.164 r stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/g_sync[0].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[3]/Q net (fo=2, routed) 0.039 1.203 stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d_sync_0 SLICE_X78Y208 LUT2 (Prop_G6LUT_SLICEL_I1_O) 0.053 1.256 r stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d[0]_i_1/O net (fo=1, routed) 0.014 1.270 stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/p_3_out[0] SLICE_X78Y208 FDRE r stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.311 1.311 stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/clk250 SLICE_X78Y208 FDRE r stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d_reg[0]/C clock pessimism -0.156 1.155 SLICE_X78Y208 FDRE (Hold_GFF_SLICEL_C_D) 0.056 1.211 stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d_reg[0] ------------------------------------------------------------------- required time -1.211 arrival time 1.270 ------------------------------------------------------------------- slack 0.059 Slack (MET) : 0.060ns (arrival time - required time) Source: stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/g_sync[2].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d_reg[2]/D (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.516%) route 0.055ns (35.484%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.315ns Source Clock Delay (SCD): 1.119ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.119ns (routing 0.481ns, distribution 0.638ns) Clock Net Delay (Destination): 1.315ns (routing 0.532ns, distribution 0.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.119 1.119 stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/g_sync[2].g_cdc.xpm_cdc_single_inst/dest_clk SLICE_X78Y206 FDRE r stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/g_sync[2].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y206 FDRE (Prop_CFF2_SLICEL_C_Q) 0.048 1.167 r stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/g_sync[2].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[3]/Q net (fo=2, routed) 0.039 1.206 stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d_sync_2 SLICE_X78Y206 LUT2 (Prop_H6LUT_SLICEL_I1_O) 0.052 1.258 r stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d[2]_i_1/O net (fo=1, routed) 0.016 1.274 stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/p_3_out[2] SLICE_X78Y206 FDRE r stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d_reg[2]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.315 1.315 stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/clk250 SLICE_X78Y206 FDRE r stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d_reg[2]/C clock pessimism -0.157 1.158 SLICE_X78Y206 FDRE (Hold_HFF_SLICEL_C_D) 0.056 1.214 stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d_reg[2] ------------------------------------------------------------------- required time -1.214 arrival time 1.274 ------------------------------------------------------------------- slack 0.060 Slack (MET) : 0.060ns (arrival time - required time) Source: stat_regs_inst/i_cntr_rst_ctrl/SR_reg[1]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst/DSP_A_B_DATA_INST/B[1] (rising edge-triggered cell DSP_A_B_DATA clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.128ns (logic 0.049ns (38.281%) route 0.079ns (61.719%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.382ns Source Clock Delay (SCD): 1.195ns Clock Pessimism Removal (CPR): 0.119ns Clock Net Delay (Source): 1.195ns (routing 0.481ns, distribution 0.714ns) Clock Net Delay (Destination): 1.382ns (routing 0.532ns, distribution 0.850ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.195 1.195 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLICE_X54Y132 FDRE r stat_regs_inst/i_cntr_rst_ctrl/SR_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y132 FDRE (Prop_EFF_SLICEL_C_Q) 0.049 1.244 r stat_regs_inst/i_cntr_rst_ctrl/SR_reg[1]/Q net (fo=12, routed) 0.079 1.323 stat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst/B[1] DSP48E2_X9Y53 DSP_A_B_DATA r stat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst/DSP_A_B_DATA_INST/B[1] ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.382 1.382 stat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst/CLK DSP48E2_X9Y53 DSP_A_B_DATA r stat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst/DSP_A_B_DATA_INST/CLK clock pessimism -0.119 1.263 DSP48E2_X9Y53 DSP_A_B_DATA (Hold_DSP_A_B_DATA_DSP48E2_CLK_B[1]) 0.000 1.263 stat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst/DSP_A_B_DATA_INST ------------------------------------------------------------------- required time -1.263 arrival time 1.323 ------------------------------------------------------------------- slack 0.060 Slack (MET) : 0.060ns (arrival time - required time) Source: stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/reset_r_reg[1]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/d_sync_rst_reg[1]/D (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.153ns (logic 0.104ns (67.974%) route 0.049ns (32.026%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.491ns Source Clock Delay (SCD): 1.282ns Clock Pessimism Removal (CPR): 0.172ns Clock Net Delay (Source): 1.282ns (routing 0.481ns, distribution 0.801ns) Clock Net Delay (Destination): 1.491ns (routing 0.532ns, distribution 0.959ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.282 1.282 stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/clk250 SLICE_X106Y153 FDRE r stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/reset_r_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y153 FDRE (Prop_FFF_SLICEM_C_Q) 0.049 1.331 r stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/reset_r_reg[1]/Q net (fo=2, routed) 0.038 1.369 stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/p_5_in SLICE_X106Y153 LUT3 (Prop_C5LUT_SLICEM_I1_O) 0.055 1.424 r stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/d_sync_rst[1]_i_1/O net (fo=1, routed) 0.011 1.435 stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/d_sync_rst[1]_i_1_n_0 SLICE_X106Y153 FDRE r stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/d_sync_rst_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.491 1.491 stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/clk250 SLICE_X106Y153 FDRE r stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/d_sync_rst_reg[1]/C clock pessimism -0.172 1.319 SLICE_X106Y153 FDRE (Hold_CFF2_SLICEM_C_D) 0.056 1.375 stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/d_sync_rst_reg[1] ------------------------------------------------------------------- required time -1.375 arrival time 1.435 ------------------------------------------------------------------- slack 0.060 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk250 Waveform(ns): { 0.000 2.000 } Period(ns): 4.000 Sources: { i_clk250_bufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB36E2/CLKARDCLK n/a 1.905 4.000 2.095 RAMB36_X9Y45 stat_regs_inst/i_ram_cntr/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 1.905 4.000 2.095 RAMB36_X11Y43 stat_regs_inst/i_ram_rate/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_0/CLKARDCLK Min Period n/a SRL16E/CLK n/a 1.356 4.000 2.644 SLICE_X82Y215 stat_regs_inst/clk_phase_reg[2]_srl3/CLK Min Period n/a SRL16E/CLK n/a 1.356 4.000 2.644 SLICE_X83Y190 stat_regs_inst/clk_phase_reg[5]_srl2/CLK Min Period n/a DSP_OUTPUT/CLK n/a 1.350 4.000 2.650 DSP48E2_X19Y79 g_clock_rate_din[5].i_rate_test_comm/DSP48E2_inst/DSP_OUTPUT_INST/CLK Min Period n/a DSP_OUTPUT/CLK n/a 1.350 4.000 2.650 DSP48E2_X16Y53 stat_regs_inst/g_DSP_rate[13].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK Min Period n/a DSP_OUTPUT/CLK n/a 1.350 4.000 2.650 DSP48E2_X20Y107 g_clock_rate_din[29].i_rate_ngccm_status2/DSP48E2_inst/DSP_OUTPUT_INST/CLK Min Period n/a DSP_OUTPUT/CLK n/a 1.350 4.000 2.650 DSP48E2_X10Y66 stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK Min Period n/a DSP_OUTPUT/CLK n/a 1.350 4.000 2.650 DSP48E2_X9Y48 stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK Min Period n/a DSP_OUTPUT/CLK n/a 1.350 4.000 2.650 DSP48E2_X16Y92 g_clock_rate_din[6].i_rate_ngccm_status0/DSP48E2_inst/DSP_OUTPUT_INST/CLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 2.000 1.048 RAMB36_X11Y43 stat_regs_inst/i_ram_rate/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_0/CLKARDCLK Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.952 2.000 1.048 RAMB36_X11Y43 stat_regs_inst/i_ram_rate/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_0/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 2.000 1.048 RAMB36_X9Y45 stat_regs_inst/i_ram_cntr/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.952 2.000 1.048 RAMB36_X9Y45 stat_regs_inst/i_ram_cntr/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK Low Pulse Width Fast SRL16E/CLK n/a 0.678 2.000 1.322 SLICE_X82Y215 stat_regs_inst/clk_phase_reg[2]_srl3/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.678 2.000 1.322 SLICE_X82Y215 stat_regs_inst/clk_phase_reg[2]_srl3/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.678 2.000 1.322 SLICE_X83Y190 stat_regs_inst/clk_phase_reg[5]_srl2/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.678 2.000 1.322 SLICE_X83Y190 stat_regs_inst/clk_phase_reg[5]_srl2/CLK Low Pulse Width Slow FDRE/C n/a 0.275 2.000 1.725 SLICE_X80Y255 stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/g_sync[3].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[0]/C Low Pulse Width Slow FDRE/C n/a 0.275 2.000 1.725 SLICE_X80Y255 stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/g_sync[3].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[1]/C High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 2.000 1.048 RAMB36_X9Y45 stat_regs_inst/i_ram_cntr/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.952 2.000 1.048 RAMB36_X11Y43 stat_regs_inst/i_ram_rate/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_0/CLKARDCLK High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.952 2.000 1.048 RAMB36_X9Y45 stat_regs_inst/i_ram_cntr/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 2.000 1.048 RAMB36_X11Y43 stat_regs_inst/i_ram_rate/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_0/CLKARDCLK High Pulse Width Slow SRL16E/CLK n/a 0.678 2.000 1.322 SLICE_X82Y215 stat_regs_inst/clk_phase_reg[2]_srl3/CLK High Pulse Width Fast SRL16E/CLK n/a 0.678 2.000 1.322 SLICE_X82Y215 stat_regs_inst/clk_phase_reg[2]_srl3/CLK High Pulse Width Slow SRL16E/CLK n/a 0.678 2.000 1.322 SLICE_X83Y190 stat_regs_inst/clk_phase_reg[5]_srl2/CLK High Pulse Width Fast SRL16E/CLK n/a 0.678 2.000 1.322 SLICE_X83Y190 stat_regs_inst/clk_phase_reg[5]_srl2/CLK High Pulse Width Slow FDRE/C n/a 0.275 2.000 1.725 SLICE_X78Y235 g_clock_rate_din[29].i_rate_ngccm_status1/rate_i_reg[6]/C High Pulse Width Slow FDRE/C n/a 0.275 2.000 1.725 SLICE_X71Y164 stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/d_reg[0]/C --------------------------------------------------------------------------------------------------- From Clock: fabric_clk To Clock: fabric_clk Setup : 0 Failing Endpoints, Worst Slack 11.114ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.030ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 11.390ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 11.114ns (required time - arrival time) Source: i2c_clk_en_reg_rep__17/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[1]/CE (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 13.342ns (logic 0.306ns (2.294%) route 13.036ns (97.706%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.083ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.543ns = ( 28.495 - 24.952 ) Source Clock Delay (SCD): 3.542ns Clock Pessimism Removal (CPR): 0.082ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.396ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.543ns Common Clock Delay (CCD): 0.904ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.542ns (routing 0.986ns, distribution 2.556ns) Clock Net Delay (Destination): 3.543ns (routing 0.904ns, distribution 2.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.542 3.542 fabric_clk SLR Crossing[0->1] SLICE_X88Y373 FDRE r i2c_clk_en_reg_rep__17/C ------------------------------------------------------------------- ------------------- SLICE_X88Y373 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 3.682 r i2c_clk_en_reg_rep__17/Q net (fo=132, routed) 12.566 16.248 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 SLR Crossing[1->0] SLICE_X128Y4 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.166 16.414 r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440/O net (fo=6, routed) 0.470 16.884 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440_n_0 SLICE_X128Y2 FDRE r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y119 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.543 28.495 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLICE_X128Y2 FDRE r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[1]/C clock pessimism 0.082 28.577 inter-SLR compensation -0.396 28.181 clock uncertainty -0.128 28.053 SLICE_X128Y2 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 27.998 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[1] ------------------------------------------------------------------- required time 27.998 arrival time -16.884 ------------------------------------------------------------------- slack 11.114 Slack (MET) : 11.114ns (required time - arrival time) Source: i2c_clk_en_reg_rep__17/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[4]/CE (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 13.342ns (logic 0.306ns (2.294%) route 13.036ns (97.706%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.083ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.543ns = ( 28.495 - 24.952 ) Source Clock Delay (SCD): 3.542ns Clock Pessimism Removal (CPR): 0.082ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.396ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.543ns Common Clock Delay (CCD): 0.904ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.542ns (routing 0.986ns, distribution 2.556ns) Clock Net Delay (Destination): 3.543ns (routing 0.904ns, distribution 2.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.542 3.542 fabric_clk SLR Crossing[0->1] SLICE_X88Y373 FDRE r i2c_clk_en_reg_rep__17/C ------------------------------------------------------------------- ------------------- SLICE_X88Y373 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 3.682 r i2c_clk_en_reg_rep__17/Q net (fo=132, routed) 12.566 16.248 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 SLR Crossing[1->0] SLICE_X128Y4 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.166 16.414 r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440/O net (fo=6, routed) 0.470 16.884 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440_n_0 SLICE_X128Y2 FDRE r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y119 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.543 28.495 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLICE_X128Y2 FDRE r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[4]/C clock pessimism 0.082 28.577 inter-SLR compensation -0.396 28.181 clock uncertainty -0.128 28.053 SLICE_X128Y2 FDRE (Setup_GFF_SLICEL_C_CE) -0.055 27.998 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[4] ------------------------------------------------------------------- required time 27.998 arrival time -16.884 ------------------------------------------------------------------- slack 11.114 Slack (MET) : 11.152ns (required time - arrival time) Source: i2c_clk_en_reg_rep__17/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[0]/CE (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 13.308ns (logic 0.306ns (2.299%) route 13.002ns (97.701%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.546ns = ( 28.498 - 24.952 ) Source Clock Delay (SCD): 3.542ns Clock Pessimism Removal (CPR): 0.082ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.396ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.546ns Common Clock Delay (CCD): 0.904ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.542ns (routing 0.986ns, distribution 2.556ns) Clock Net Delay (Destination): 3.546ns (routing 0.904ns, distribution 2.642ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.542 3.542 fabric_clk SLR Crossing[0->1] SLICE_X88Y373 FDRE r i2c_clk_en_reg_rep__17/C ------------------------------------------------------------------- ------------------- SLICE_X88Y373 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 3.682 r i2c_clk_en_reg_rep__17/Q net (fo=132, routed) 12.566 16.248 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 SLR Crossing[1->0] SLICE_X128Y4 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.166 16.414 r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440/O net (fo=6, routed) 0.436 16.850 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440_n_0 SLICE_X128Y0 FDRE r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y119 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.546 28.498 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLICE_X128Y0 FDRE r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[0]/C clock pessimism 0.082 28.580 inter-SLR compensation -0.396 28.184 clock uncertainty -0.128 28.056 SLICE_X128Y0 FDRE (Setup_BFF_SLICEL_C_CE) -0.054 28.002 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[0] ------------------------------------------------------------------- required time 28.002 arrival time -16.850 ------------------------------------------------------------------- slack 11.152 Slack (MET) : 11.163ns (required time - arrival time) Source: i2c_clk_en_reg_rep__17/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[2]/CE (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 13.297ns (logic 0.306ns (2.301%) route 12.991ns (97.699%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.546ns = ( 28.498 - 24.952 ) Source Clock Delay (SCD): 3.542ns Clock Pessimism Removal (CPR): 0.082ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.396ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.546ns Common Clock Delay (CCD): 0.904ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.542ns (routing 0.986ns, distribution 2.556ns) Clock Net Delay (Destination): 3.546ns (routing 0.904ns, distribution 2.642ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.542 3.542 fabric_clk SLR Crossing[0->1] SLICE_X88Y373 FDRE r i2c_clk_en_reg_rep__17/C ------------------------------------------------------------------- ------------------- SLICE_X88Y373 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 3.682 r i2c_clk_en_reg_rep__17/Q net (fo=132, routed) 12.566 16.248 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 SLR Crossing[1->0] SLICE_X128Y4 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.166 16.414 r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440/O net (fo=6, routed) 0.425 16.839 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440_n_0 SLICE_X128Y1 FDRE r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y119 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.546 28.498 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLICE_X128Y1 FDRE r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[2]/C clock pessimism 0.082 28.580 inter-SLR compensation -0.396 28.184 clock uncertainty -0.128 28.056 SLICE_X128Y1 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 28.002 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[2] ------------------------------------------------------------------- required time 28.002 arrival time -16.839 ------------------------------------------------------------------- slack 11.163 Slack (MET) : 11.163ns (required time - arrival time) Source: i2c_clk_en_reg_rep__17/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[3]/CE (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 13.297ns (logic 0.306ns (2.301%) route 12.991ns (97.699%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.546ns = ( 28.498 - 24.952 ) Source Clock Delay (SCD): 3.542ns Clock Pessimism Removal (CPR): 0.082ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.396ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.546ns Common Clock Delay (CCD): 0.904ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.542ns (routing 0.986ns, distribution 2.556ns) Clock Net Delay (Destination): 3.546ns (routing 0.904ns, distribution 2.642ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.542 3.542 fabric_clk SLR Crossing[0->1] SLICE_X88Y373 FDRE r i2c_clk_en_reg_rep__17/C ------------------------------------------------------------------- ------------------- SLICE_X88Y373 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 3.682 r i2c_clk_en_reg_rep__17/Q net (fo=132, routed) 12.566 16.248 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 SLR Crossing[1->0] SLICE_X128Y4 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.166 16.414 r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440/O net (fo=6, routed) 0.425 16.839 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440_n_0 SLICE_X128Y1 FDRE r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y119 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.546 28.498 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLICE_X128Y1 FDRE r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[3]/C clock pessimism 0.082 28.580 inter-SLR compensation -0.396 28.184 clock uncertainty -0.128 28.056 SLICE_X128Y1 FDRE (Setup_BFF_SLICEL_C_CE) -0.054 28.002 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[3] ------------------------------------------------------------------- required time 28.002 arrival time -16.839 ------------------------------------------------------------------- slack 11.163 Slack (MET) : 11.261ns (required time - arrival time) Source: i2c_clk_en_reg_rep__17/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 13.315ns (logic 0.472ns (3.545%) route 12.843ns (96.455%)) Logic Levels: 2 (LUT3=1 LUT6=1) Clock Path Skew: 0.085ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.545ns = ( 28.497 - 24.952 ) Source Clock Delay (SCD): 3.542ns Clock Pessimism Removal (CPR): 0.082ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.396ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.545ns Common Clock Delay (CCD): 0.904ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.542ns (routing 0.986ns, distribution 2.556ns) Clock Net Delay (Destination): 3.545ns (routing 0.904ns, distribution 2.641ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.542 3.542 fabric_clk SLR Crossing[0->1] SLICE_X88Y373 FDRE r i2c_clk_en_reg_rep__17/C ------------------------------------------------------------------- ------------------- SLICE_X88Y373 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 3.682 r i2c_clk_en_reg_rep__17/Q net (fo=132, routed) 12.566 16.248 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 SLR Crossing[1->0] SLICE_X128Y4 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.166 16.414 r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440/O net (fo=6, routed) 0.242 16.656 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440_n_0 SLICE_X128Y2 LUT3 (Prop_D6LUT_SLICEL_I1_O) 0.166 16.822 r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_i_1__440/O net (fo=1, routed) 0.035 16.857 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_i_1__440_n_0 SLICE_X128Y2 FDRE r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y119 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.545 28.497 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLICE_X128Y2 FDRE r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_reg/C clock pessimism 0.082 28.579 inter-SLR compensation -0.396 28.183 clock uncertainty -0.128 28.055 SLICE_X128Y2 FDRE (Setup_DFF_SLICEL_C_D) 0.063 28.118 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_reg ------------------------------------------------------------------- required time 28.118 arrival time -16.857 ------------------------------------------------------------------- slack 11.261 Slack (MET) : 11.350ns (required time - arrival time) Source: i2c_clk_en_reg_rep__17/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 13.219ns (logic 0.387ns (2.928%) route 12.832ns (97.072%)) Logic Levels: 3 (LUT3=1 LUT6=2) Clock Path Skew: 0.077ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.537ns = ( 28.489 - 24.952 ) Source Clock Delay (SCD): 3.542ns Clock Pessimism Removal (CPR): 0.082ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.395ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.537ns Common Clock Delay (CCD): 0.904ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.542ns (routing 0.986ns, distribution 2.556ns) Clock Net Delay (Destination): 3.537ns (routing 0.904ns, distribution 2.633ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.542 3.542 fabric_clk SLR Crossing[0->1] SLICE_X88Y373 FDRE r i2c_clk_en_reg_rep__17/C ------------------------------------------------------------------- ------------------- SLICE_X88Y373 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 3.682 r i2c_clk_en_reg_rep__17/Q net (fo=132, routed) 12.561 16.243 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 SLR Crossing[1->0] SLICE_X128Y4 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.146 16.389 r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/sda_chk_i_3__440/O net (fo=2, routed) 0.164 16.553 SFP_GEN[8].ngCCM_gbt/Sync_TX_Reset/isda_oen_reg SLICE_X128Y3 LUT3 (Prop_E6LUT_SLICEL_I2_O) 0.050 16.603 r SFP_GEN[8].ngCCM_gbt/Sync_TX_Reset/isda_oen_i_5__440/O net (fo=1, routed) 0.070 16.673 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg_0 SLICE_X128Y3 LUT6 (Prop_C6LUT_SLICEL_I3_O) 0.051 16.724 r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_i_1__440/O net (fo=1, routed) 0.037 16.761 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_i_1__440_n_0 SLICE_X128Y3 FDRE r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y119 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.537 28.489 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLICE_X128Y3 FDRE r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg/C clock pessimism 0.082 28.571 inter-SLR compensation -0.395 28.176 clock uncertainty -0.128 28.048 SLICE_X128Y3 FDRE (Setup_CFF_SLICEL_C_D) 0.063 28.111 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg ------------------------------------------------------------------- required time 28.111 arrival time -16.761 ------------------------------------------------------------------- slack 11.350 Slack (MET) : 11.416ns (required time - arrival time) Source: i2c_clk_en_reg_rep__17/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[6]/CE (rising edge-triggered cell FDSE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 13.038ns (logic 0.375ns (2.876%) route 12.663ns (97.124%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.084ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.544ns = ( 28.496 - 24.952 ) Source Clock Delay (SCD): 3.542ns Clock Pessimism Removal (CPR): 0.082ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.396ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.544ns Common Clock Delay (CCD): 0.904ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.542ns (routing 0.986ns, distribution 2.556ns) Clock Net Delay (Destination): 3.544ns (routing 0.904ns, distribution 2.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.542 3.542 fabric_clk SLR Crossing[0->1] SLICE_X88Y373 FDRE r i2c_clk_en_reg_rep__17/C ------------------------------------------------------------------- ------------------- SLICE_X88Y373 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 3.682 r i2c_clk_en_reg_rep__17/Q net (fo=132, routed) 12.017 15.699 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 SLR Crossing[1->0] SLICE_X124Y1 LUT3 (Prop_F6LUT_SLICEL_I1_O) 0.235 15.934 r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__440/O net (fo=8, routed) 0.646 16.580 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__440_n_0 SLICE_X128Y1 FDSE r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y119 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.544 28.496 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLICE_X128Y1 FDSE r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[6]/C clock pessimism 0.082 28.578 inter-SLR compensation -0.396 28.182 clock uncertainty -0.128 28.054 SLICE_X128Y1 FDSE (Setup_HFF2_SLICEL_C_CE) -0.058 27.996 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[6] ------------------------------------------------------------------- required time 27.996 arrival time -16.580 ------------------------------------------------------------------- slack 11.416 Slack (MET) : 11.423ns (required time - arrival time) Source: i2c_clk_en_reg_rep__17/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[7]/CE (rising edge-triggered cell FDSE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 13.034ns (logic 0.375ns (2.877%) route 12.659ns (97.123%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.084ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.544ns = ( 28.496 - 24.952 ) Source Clock Delay (SCD): 3.542ns Clock Pessimism Removal (CPR): 0.082ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.396ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.544ns Common Clock Delay (CCD): 0.904ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.542ns (routing 0.986ns, distribution 2.556ns) Clock Net Delay (Destination): 3.544ns (routing 0.904ns, distribution 2.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.542 3.542 fabric_clk SLR Crossing[0->1] SLICE_X88Y373 FDRE r i2c_clk_en_reg_rep__17/C ------------------------------------------------------------------- ------------------- SLICE_X88Y373 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 3.682 r i2c_clk_en_reg_rep__17/Q net (fo=132, routed) 12.017 15.699 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 SLR Crossing[1->0] SLICE_X124Y1 LUT3 (Prop_F6LUT_SLICEL_I1_O) 0.235 15.934 r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__440/O net (fo=8, routed) 0.642 16.576 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__440_n_0 SLICE_X128Y1 FDSE r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[7]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y119 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.544 28.496 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLICE_X128Y1 FDSE r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[7]/C clock pessimism 0.082 28.578 inter-SLR compensation -0.396 28.182 clock uncertainty -0.128 28.054 SLICE_X128Y1 FDSE (Setup_EFF_SLICEL_C_CE) -0.055 27.999 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[7] ------------------------------------------------------------------- required time 27.999 arrival time -16.576 ------------------------------------------------------------------- slack 11.423 Slack (MET) : 11.472ns (required time - arrival time) Source: i2c_clk_en_reg_rep__17/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[3]/CE (rising edge-triggered cell FDSE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 12.973ns (logic 0.375ns (2.891%) route 12.598ns (97.109%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.070ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.530ns = ( 28.482 - 24.952 ) Source Clock Delay (SCD): 3.542ns Clock Pessimism Removal (CPR): 0.082ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.394ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.530ns Common Clock Delay (CCD): 0.904ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.542ns (routing 0.986ns, distribution 2.556ns) Clock Net Delay (Destination): 3.530ns (routing 0.904ns, distribution 2.626ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.542 3.542 fabric_clk SLR Crossing[0->1] SLICE_X88Y373 FDRE r i2c_clk_en_reg_rep__17/C ------------------------------------------------------------------- ------------------- SLICE_X88Y373 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 3.682 r i2c_clk_en_reg_rep__17/Q net (fo=132, routed) 12.017 15.699 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 SLR Crossing[1->0] SLICE_X124Y1 LUT3 (Prop_F6LUT_SLICEL_I1_O) 0.235 15.934 r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__440/O net (fo=8, routed) 0.581 16.515 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__440_n_0 SLICE_X127Y2 FDSE r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y119 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.530 28.482 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLICE_X127Y2 FDSE r SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[3]/C clock pessimism 0.082 28.564 inter-SLR compensation -0.394 28.170 clock uncertainty -0.128 28.042 SLICE_X127Y2 FDSE (Setup_CFF2_SLICEL_C_CE) -0.055 27.987 SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[3] ------------------------------------------------------------------- required time 27.987 arrival time -16.515 ------------------------------------------------------------------- slack 11.472 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/DoSleep_reg/C (rising edge-triggered cell FDCE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[4]/D (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.416ns (logic 0.159ns (38.221%) route 0.257ns (61.779%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.259ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.969ns Source Clock Delay (SCD): 3.435ns Clock Pessimism Removal (CPR): 0.275ns Clock Net Delay (Source): 3.435ns (routing 0.904ns, distribution 2.531ns) Clock Net Delay (Destination): 3.969ns (routing 0.986ns, distribution 2.983ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.435 3.435 SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/fabric_clk SLR Crossing[0->1] SLICE_X118Y504 FDCE r SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/DoSleep_reg/C ------------------------------------------------------------------- ------------------- SLICE_X118Y504 FDCE (Prop_DFF_SLICEM_C_Q) 0.123 3.558 r SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/DoSleep_reg/Q net (fo=35, routed) 0.222 3.780 SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/jtag_reg_o[9] SLICE_X119Y505 LUT6 (Prop_C6LUT_SLICEM_I2_O) 0.036 3.816 r SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount[4]_i_1__39/O net (fo=1, routed) 0.035 3.851 SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount[4]_i_1__39_n_0 SLICE_X119Y505 FDPE r SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[4]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.969 3.969 SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/fabric_clk SLR Crossing[0->1] SLICE_X119Y505 FDPE r SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[4]/C clock pessimism -0.275 3.694 SLICE_X119Y505 FDPE (Hold_CFF_SLICEM_C_D) 0.127 3.821 SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[4] ------------------------------------------------------------------- required time -3.821 arrival time 3.851 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDIBits_reg[14]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDIBits_reg[13]/D (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.164ns (logic 0.079ns (48.171%) route 0.085ns (51.829%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.687ns Source Clock Delay (SCD): 1.454ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 1.454ns (routing 0.373ns, distribution 1.081ns) Clock Net Delay (Destination): 1.687ns (routing 0.409ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.454 1.454 SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/fabric_clk SLR Crossing[0->1] SLICE_X3Y410 FDRE r SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDIBits_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X3Y410 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.503 r SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDIBits_reg[14]/Q net (fo=1, routed) 0.073 1.576 SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/TDIBits_reg[13]_0 SLICE_X4Y410 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.030 1.606 r SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/TDIBits[13]_i_1__19/O net (fo=1, routed) 0.012 1.618 SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM_n_50 SLICE_X4Y410 FDRE r SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDIBits_reg[13]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.687 1.687 SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/fabric_clk SLR Crossing[0->1] SLICE_X4Y410 FDRE r SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDIBits_reg[13]/C clock pessimism -0.155 1.532 SLICE_X4Y410 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.588 SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDIBits_reg[13] ------------------------------------------------------------------- required time -1.588 arrival time 1.618 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[0]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[2]/D (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.161ns (logic 0.065ns (40.373%) route 0.096ns (59.627%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.573ns Source Clock Delay (SCD): 1.353ns Clock Pessimism Removal (CPR): 0.145ns Clock Net Delay (Source): 1.353ns (routing 0.373ns, distribution 0.980ns) Clock Net Delay (Destination): 1.573ns (routing 0.409ns, distribution 1.164ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.353 1.353 SFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLICE_X33Y253 FDRE r SFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y253 FDRE (Prop_AFF_SLICEL_C_Q) 0.049 1.402 f SFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[0]/Q net (fo=15, routed) 0.081 1.483 SFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/c_state__0_0[0] SLICE_X34Y253 LUT6 (Prop_B6LUT_SLICEM_I4_O) 0.016 1.499 r SFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[2]_i_1__415/O net (fo=1, routed) 0.015 1.514 SFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[2]_i_1__415_n_0 SLICE_X34Y253 FDRE r SFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[2]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.573 1.573 SFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLICE_X34Y253 FDRE r SFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[2]/C clock pessimism -0.145 1.428 SLICE_X34Y253 FDRE (Hold_BFF_SLICEM_C_D) 0.056 1.484 SFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[2] ------------------------------------------------------------------- required time -1.484 arrival time 1.514 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[6]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[6]/D (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.159ns (logic 0.065ns (40.880%) route 0.094ns (59.119%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.635ns Source Clock Delay (SCD): 1.410ns Clock Pessimism Removal (CPR): 0.152ns Clock Net Delay (Source): 1.410ns (routing 0.373ns, distribution 1.037ns) Clock Net Delay (Destination): 1.635ns (routing 0.409ns, distribution 1.226ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.410 1.410 SFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/fabric_clk SLR Crossing[0->1] SLICE_X117Y341 FDRE r SFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y341 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.459 r SFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[6]/Q net (fo=2, routed) 0.078 1.537 SFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/dout[6] SLICE_X118Y341 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.016 1.553 r SFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/wb_dat_o[6]_i_1__30/O net (fo=1, routed) 0.016 1.569 SFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/wb_dat_o[6] SLICE_X118Y341 FDRE r SFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[6]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.635 1.635 SFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/fabric_clk SLR Crossing[0->1] SLICE_X118Y341 FDRE r SFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[6]/C clock pessimism -0.152 1.483 SLICE_X118Y341 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.539 SFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[6] ------------------------------------------------------------------- required time -1.539 arrival time 1.569 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/cr_reg[5]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/st_irq_block.tip_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.161ns (logic 0.063ns (39.130%) route 0.098ns (60.870%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.586ns Source Clock Delay (SCD): 1.366ns Clock Pessimism Removal (CPR): 0.145ns Clock Net Delay (Source): 1.366ns (routing 0.373ns, distribution 0.993ns) Clock Net Delay (Destination): 1.586ns (routing 0.409ns, distribution 1.177ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.366 1.366 SFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/fabric_clk SLICE_X109Y189 FDRE r SFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/cr_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X109Y189 FDRE (Prop_EFF2_SLICEM_C_Q) 0.048 1.414 r SFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/cr_reg[5]/Q net (fo=7, routed) 0.084 1.498 SFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/read SLICE_X110Y189 LUT4 (Prop_G6LUT_SLICEM_I3_O) 0.015 1.513 r SFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/st_irq_block.tip_i_1__18/O net (fo=1, routed) 0.014 1.527 SFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/st_irq_block.tip_i_1__18_n_0 SLICE_X110Y189 FDRE r SFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/st_irq_block.tip_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.586 1.586 SFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/fabric_clk SLICE_X110Y189 FDRE r SFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/st_irq_block.tip_reg/C clock pessimism -0.145 1.441 SLICE_X110Y189 FDRE (Hold_GFF_SLICEM_C_D) 0.056 1.497 SFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/st_irq_block.tip_reg ------------------------------------------------------------------- required time -1.497 arrival time 1.527 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[17].ngCCM_gbt/IPbus_gen[6].IPbus_local_inst/write_local_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[17].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/cr_reg[3]/D (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.177ns (logic 0.078ns (44.068%) route 0.099ns (55.932%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.642ns Source Clock Delay (SCD): 1.399ns Clock Pessimism Removal (CPR): 0.152ns Clock Net Delay (Source): 1.399ns (routing 0.373ns, distribution 1.026ns) Clock Net Delay (Destination): 1.642ns (routing 0.409ns, distribution 1.233ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.399 1.399 SFP_GEN[17].ngCCM_gbt/IPbus_gen[6].IPbus_local_inst/clk_local SLR Crossing[0->1] SLICE_X112Y338 FDRE r SFP_GEN[17].ngCCM_gbt/IPbus_gen[6].IPbus_local_inst/write_local_reg/C ------------------------------------------------------------------- ------------------- SLICE_X112Y338 FDRE (Prop_CFF_SLICEM_C_Q) 0.048 1.447 r SFP_GEN[17].ngCCM_gbt/IPbus_gen[6].IPbus_local_inst/write_local_reg/Q net (fo=5, routed) 0.084 1.531 SFP_GEN[17].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/write_local SLICE_X111Y338 LUT6 (Prop_B6LUT_SLICEL_I3_O) 0.030 1.561 r SFP_GEN[17].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/cr[3]_i_1__290/O net (fo=1, routed) 0.015 1.576 SFP_GEN[17].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/cr[3]_i_1__290_n_0 SLICE_X111Y338 FDRE r SFP_GEN[17].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/cr_reg[3]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.642 1.642 SFP_GEN[17].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/fabric_clk SLR Crossing[0->1] SLICE_X111Y338 FDRE r SFP_GEN[17].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/cr_reg[3]/C clock pessimism -0.152 1.490 SLICE_X111Y338 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.546 SFP_GEN[17].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/cr_reg[3] ------------------------------------------------------------------- required time -1.546 arrival time 1.576 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[30].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/DataIn_local_reg[11]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[30].ngCCM_gbt/i2c_gen[1].LocalI2CBridge_fe/i2c_master/cr_reg[3]/D (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.146ns (logic 0.064ns (43.836%) route 0.082ns (56.164%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.601ns Source Clock Delay (SCD): 1.365ns Clock Pessimism Removal (CPR): 0.176ns Clock Net Delay (Source): 1.365ns (routing 0.373ns, distribution 0.992ns) Clock Net Delay (Destination): 1.601ns (routing 0.409ns, distribution 1.192ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.365 1.365 SFP_GEN[30].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/clk_local SLICE_X30Y184 FDRE r SFP_GEN[30].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/DataIn_local_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X30Y184 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.414 r SFP_GEN[30].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/DataIn_local_reg[11]/Q net (fo=1, routed) 0.070 1.484 SFP_GEN[30].ngCCM_gbt/i2c_gen[1].LocalI2CBridge_fe/i2c_master/DataIn_local[9] SLICE_X30Y183 LUT6 (Prop_A6LUT_SLICEL_I0_O) 0.015 1.499 r SFP_GEN[30].ngCCM_gbt/i2c_gen[1].LocalI2CBridge_fe/i2c_master/cr[3]_i_1__84/O net (fo=1, routed) 0.012 1.511 SFP_GEN[30].ngCCM_gbt/i2c_gen[1].LocalI2CBridge_fe/i2c_master/cr[3]_i_1__84_n_0 SLICE_X30Y183 FDRE r SFP_GEN[30].ngCCM_gbt/i2c_gen[1].LocalI2CBridge_fe/i2c_master/cr_reg[3]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.601 1.601 SFP_GEN[30].ngCCM_gbt/i2c_gen[1].LocalI2CBridge_fe/i2c_master/fabric_clk SLICE_X30Y183 FDRE r SFP_GEN[30].ngCCM_gbt/i2c_gen[1].LocalI2CBridge_fe/i2c_master/cr_reg[3]/C clock pessimism -0.176 1.425 SLICE_X30Y183 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.481 SFP_GEN[30].ngCCM_gbt/i2c_gen[1].LocalI2CBridge_fe/i2c_master/cr_reg[3] ------------------------------------------------------------------- required time -1.481 arrival time 1.511 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[37].ngCCM_gbt/IPbus_gen[7].IPbus_local_inst/addr_local_reg[0]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[37].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[7]/D (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.172ns (logic 0.078ns (45.349%) route 0.094ns (54.651%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.617ns Source Clock Delay (SCD): 1.383ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 1.383ns (routing 0.373ns, distribution 1.010ns) Clock Net Delay (Destination): 1.617ns (routing 0.409ns, distribution 1.208ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.383 1.383 SFP_GEN[37].ngCCM_gbt/IPbus_gen[7].IPbus_local_inst/clk_local SLR Crossing[0->1] SLICE_X36Y398 FDRE r SFP_GEN[37].ngCCM_gbt/IPbus_gen[7].IPbus_local_inst/addr_local_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y398 FDRE (Prop_CFF2_SLICEL_C_Q) 0.048 1.431 r SFP_GEN[37].ngCCM_gbt/IPbus_gen[7].IPbus_local_inst/addr_local_reg[0]/Q net (fo=17, routed) 0.082 1.513 SFP_GEN[37].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/addr_local[0] SLICE_X37Y398 LUT4 (Prop_A6LUT_SLICEM_I2_O) 0.030 1.543 r SFP_GEN[37].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/wb_dat_o[7]_i_1__246/O net (fo=1, routed) 0.012 1.555 SFP_GEN[37].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/wb_dat_o[7] SLICE_X37Y398 FDRE r SFP_GEN[37].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[7]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.617 1.617 SFP_GEN[37].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/fabric_clk SLR Crossing[0->1] SLICE_X37Y398 FDRE r SFP_GEN[37].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[7]/C clock pessimism -0.148 1.469 SLICE_X37Y398 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.525 SFP_GEN[37].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[7] ------------------------------------------------------------------- required time -1.525 arrival time 1.555 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDOBits_reg[28]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDOBits_reg[27]/D (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.167ns (logic 0.048ns (28.743%) route 0.119ns (71.257%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.629ns Source Clock Delay (SCD): 1.398ns Clock Pessimism Removal (CPR): 0.150ns Clock Net Delay (Source): 1.398ns (routing 0.373ns, distribution 1.025ns) Clock Net Delay (Destination): 1.629ns (routing 0.409ns, distribution 1.220ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.398 1.398 SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/fabric_clk SLR Crossing[0->1] SLICE_X107Y371 FDRE r SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDOBits_reg[28]/C ------------------------------------------------------------------- ------------------- SLICE_X107Y371 FDRE (Prop_HFF2_SLICEM_C_Q) 0.048 1.446 r SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDOBits_reg[28]/Q net (fo=2, routed) 0.119 1.565 SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/p_0_in[27] SLICE_X109Y371 FDRE r SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDOBits_reg[27]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.629 1.629 SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/fabric_clk SLR Crossing[0->1] SLICE_X109Y371 FDRE r SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDOBits_reg[27]/C clock pessimism -0.150 1.479 SLICE_X109Y371 FDRE (Hold_BFF2_SLICEM_C_D) 0.056 1.535 SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDOBits_reg[27] ------------------------------------------------------------------- required time -1.535 arrival time 1.565 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[34].ngCCM_gbt/IPbus_gen[10].IPbus_local_inst/DataIn_local_reg[1]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[34].ngCCM_gbt/i2c_gen[10].LocalI2CBridge_fe/i2c_master/txr_reg[1]/D (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.143ns (logic 0.048ns (33.566%) route 0.095ns (66.434%)) Logic Levels: 0 Clock Path Skew: 0.057ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.585ns Source Clock Delay (SCD): 1.350ns Clock Pessimism Removal (CPR): 0.178ns Clock Net Delay (Source): 1.350ns (routing 0.373ns, distribution 0.977ns) Clock Net Delay (Destination): 1.585ns (routing 0.409ns, distribution 1.176ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.350 1.350 SFP_GEN[34].ngCCM_gbt/IPbus_gen[10].IPbus_local_inst/clk_local SLICE_X36Y285 FDRE r SFP_GEN[34].ngCCM_gbt/IPbus_gen[10].IPbus_local_inst/DataIn_local_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y285 FDRE (Prop_EFF2_SLICEL_C_Q) 0.048 1.398 r SFP_GEN[34].ngCCM_gbt/IPbus_gen[10].IPbus_local_inst/DataIn_local_reg[1]/Q net (fo=1, routed) 0.095 1.493 SFP_GEN[34].ngCCM_gbt/i2c_gen[10].LocalI2CBridge_fe/i2c_master/DataIn_local[1] SLICE_X36Y286 FDRE r SFP_GEN[34].ngCCM_gbt/i2c_gen[10].LocalI2CBridge_fe/i2c_master/txr_reg[1]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.585 1.585 SFP_GEN[34].ngCCM_gbt/i2c_gen[10].LocalI2CBridge_fe/i2c_master/fabric_clk SLICE_X36Y286 FDRE r SFP_GEN[34].ngCCM_gbt/i2c_gen[10].LocalI2CBridge_fe/i2c_master/txr_reg[1]/C clock pessimism -0.178 1.407 SLICE_X36Y286 FDRE (Hold_AFF2_SLICEL_C_D) 0.056 1.463 SFP_GEN[34].ngCCM_gbt/i2c_gen[10].LocalI2CBridge_fe/i2c_master/txr_reg[1] ------------------------------------------------------------------- required time -1.463 arrival time 1.493 ------------------------------------------------------------------- slack 0.030 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: fabric_clk Waveform(ns): { 0.000 12.476 } Period(ns): 24.952 Sources: { fabric_clk_bufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB36E2/CLKARDCLK n/a 2.174 24.952 22.778 RAMB36_X0Y12 SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 2.174 24.952 22.778 RAMB36_X5Y97 SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 2.174 24.952 22.778 RAMB36_X2Y43 SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 2.174 24.952 22.778 RAMB36_X15Y99 SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 2.174 24.952 22.778 RAMB36_X15Y11 SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 2.174 24.952 22.778 RAMB36_X15Y26 SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 2.174 24.952 22.778 RAMB36_X5Y100 SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 2.174 24.952 22.778 RAMB36_X11Y45 SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 2.174 24.952 22.778 RAMB36_X14Y101 SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 2.174 24.952 22.778 RAMB36_X13Y18 SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X2Y43 SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X15Y99 SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X15Y26 SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X5Y100 SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X11Y45 SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X13Y18 SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X15Y87 SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X9Y117 SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X9Y117 SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X5Y50 SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X0Y12 SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X5Y100 SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X14Y101 SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X12Y19 SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X8Y107 SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X2Y50 SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X2Y50 SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X5Y61 SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X15Y43 SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X6Y91 SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK --------------------------------------------------------------------------------------------------- From Clock: ipb_clk To Clock: ipb_clk Setup : 0 Failing Endpoints, Worst Slack 0.199ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.030ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 15.048ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.199ns (required time - arrival time) Source: ipb/trans/sm/rmw_result_reg[8]/C (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[43].ngFEC_module/bram_array[11].buffer_server/input_size_i_reg[8]/D (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 31.001ns (logic 0.193ns (0.623%) route 30.808ns (99.377%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.464ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.636ns = ( 34.636 - 32.000 ) Source Clock Delay (SCD): 3.148ns Clock Pessimism Removal (CPR): 0.048ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.313ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 2.636ns Common Clock Delay (CCD): 0.546ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.148ns (routing 0.594ns, distribution 2.554ns) Clock Net Delay (Destination): 2.636ns (routing 0.546ns, distribution 2.090ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.148 3.148 ipb/trans/sm/CLK SLICE_X80Y244 FDRE r ipb/trans/sm/rmw_result_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y244 FDRE (Prop_HFF_SLICEL_C_Q) 0.138 3.286 r ipb/trans/sm/rmw_result_reg[8]/Q net (fo=688, routed) 30.774 34.060 ipb/trans/iface/regs_reg[126][31][8] SLR Crossing[0->1] SLICE_X64Y555 LUT6 (Prop_B6LUT_SLICEM_I4_O) 0.055 34.115 r ipb/trans/iface/input_size_i[8]_i_1__75/O net (fo=1, routed) 0.034 34.149 SFP_GEN[43].ngFEC_module/bram_array[11].buffer_server/input_size_i_reg[12]_1[6] SLICE_X64Y555 FDCE r SFP_GEN[43].ngFEC_module/bram_array[11].buffer_server/input_size_i_reg[8]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 2.636 34.636 SFP_GEN[43].ngFEC_module/bram_array[11].buffer_server/CLK SLR Crossing[0->1] SLICE_X64Y555 FDCE r SFP_GEN[43].ngFEC_module/bram_array[11].buffer_server/input_size_i_reg[8]/C clock pessimism 0.048 34.684 inter-SLR compensation -0.313 34.371 clock uncertainty -0.085 34.286 SLICE_X64Y555 FDCE (Setup_BFF_SLICEM_C_D) 0.062 34.348 SFP_GEN[43].ngFEC_module/bram_array[11].buffer_server/input_size_i_reg[8] ------------------------------------------------------------------- required time 34.348 arrival time -34.149 ------------------------------------------------------------------- slack 0.199 Slack (MET) : 0.529ns (required time - arrival time) Source: ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[38].ngFEC_module/bram_array[13].buffer_server/input_size_i_reg[8]/D (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 30.337ns (logic 1.995ns (6.576%) route 28.342ns (93.424%)) Logic Levels: 2 (LUT6=1 RAMB36E2=1) Clock Path Skew: -0.746ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.984ns = ( 34.984 - 32.000 ) Source Clock Delay (SCD): 3.778ns Clock Pessimism Removal (CPR): 0.048ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.366ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 2.984ns Common Clock Delay (CCD): 0.546ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.778ns (routing 0.594ns, distribution 3.184ns) Clock Net Delay (Destination): 2.984ns (routing 0.546ns, distribution 2.438ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.778 3.778 ipb/udp_if/ipbus_rx_ram/CLK RAMB36_X16Y51 RAMB36E2 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X16Y51 RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[0]) 1.727 5.505 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CASDOUTB[0] net (fo=1, routed) 0.015 5.520 ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0_n_67 RAMB36_X16Y52 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[0]_DOUTBDOUT[0]) 0.218 5.738 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/DOUTBDOUT[0] net (fo=698, routed) 28.296 34.034 ipb/trans/iface/rx_dob[8] SLR Crossing[0->1] SLICE_X39Y479 LUT6 (Prop_A6LUT_SLICEM_I0_O) 0.050 34.084 r ipb/trans/iface/input_size_i[8]_i_1__147/O net (fo=1, routed) 0.031 34.115 SFP_GEN[38].ngFEC_module/bram_array[13].buffer_server/input_size_i_reg[12]_2[6] SLICE_X39Y479 FDCE r SFP_GEN[38].ngFEC_module/bram_array[13].buffer_server/input_size_i_reg[8]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 2.984 34.984 SFP_GEN[38].ngFEC_module/bram_array[13].buffer_server/CLK SLR Crossing[0->1] SLICE_X39Y479 FDCE r SFP_GEN[38].ngFEC_module/bram_array[13].buffer_server/input_size_i_reg[8]/C clock pessimism 0.048 35.032 inter-SLR compensation -0.366 34.666 clock uncertainty -0.085 34.581 SLICE_X39Y479 FDCE (Setup_AFF_SLICEM_C_D) 0.063 34.644 SFP_GEN[38].ngFEC_module/bram_array[13].buffer_server/input_size_i_reg[8] ------------------------------------------------------------------- required time 34.644 arrival time -34.115 ------------------------------------------------------------------- slack 0.529 Slack (MET) : 0.616ns (required time - arrival time) Source: ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[38].ngFEC_module/bram_array[5].buffer_server/input_size_i_reg[8]/D (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 30.337ns (logic 2.164ns (7.133%) route 28.173ns (92.867%)) Logic Levels: 2 (LUT6=1 RAMB36E2=1) Clock Path Skew: -0.643ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.087ns = ( 35.087 - 32.000 ) Source Clock Delay (SCD): 3.778ns Clock Pessimism Removal (CPR): 0.048ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.381ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.087ns Common Clock Delay (CCD): 0.546ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.778ns (routing 0.594ns, distribution 3.184ns) Clock Net Delay (Destination): 3.087ns (routing 0.546ns, distribution 2.541ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.778 3.778 ipb/udp_if/ipbus_rx_ram/CLK RAMB36_X16Y51 RAMB36E2 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X16Y51 RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[0]) 1.727 5.505 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CASDOUTB[0] net (fo=1, routed) 0.015 5.520 ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0_n_67 RAMB36_X16Y52 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[0]_DOUTBDOUT[0]) 0.218 5.738 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/DOUTBDOUT[0] net (fo=698, routed) 28.125 33.863 ipb/trans/iface/rx_dob[8] SLR Crossing[0->1] SLICE_X20Y468 LUT6 (Prop_B6LUT_SLICEL_I0_O) 0.219 34.082 r ipb/trans/iface/input_size_i[8]_i_1__139/O net (fo=1, routed) 0.033 34.115 SFP_GEN[38].ngFEC_module/bram_array[5].buffer_server/input_size_i_reg[12]_1[6] SLICE_X20Y468 FDCE r SFP_GEN[38].ngFEC_module/bram_array[5].buffer_server/input_size_i_reg[8]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.087 35.087 SFP_GEN[38].ngFEC_module/bram_array[5].buffer_server/CLK SLR Crossing[0->1] SLICE_X20Y468 FDCE r SFP_GEN[38].ngFEC_module/bram_array[5].buffer_server/input_size_i_reg[8]/C clock pessimism 0.048 35.135 inter-SLR compensation -0.381 34.754 clock uncertainty -0.085 34.669 SLICE_X20Y468 FDCE (Setup_BFF_SLICEL_C_D) 0.062 34.731 SFP_GEN[38].ngFEC_module/bram_array[5].buffer_server/input_size_i_reg[8] ------------------------------------------------------------------- required time 34.731 arrival time -34.115 ------------------------------------------------------------------- slack 0.616 Slack (MET) : 0.719ns (required time - arrival time) Source: ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[38].ngFEC_module/bram_array[3].buffer_server/input_size_i_reg[8]/D (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 30.244ns (logic 2.191ns (7.244%) route 28.053ns (92.756%)) Logic Levels: 2 (LUT6=1 RAMB36E2=1) Clock Path Skew: -0.633ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.097ns = ( 35.097 - 32.000 ) Source Clock Delay (SCD): 3.778ns Clock Pessimism Removal (CPR): 0.048ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.383ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.097ns Common Clock Delay (CCD): 0.546ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.778ns (routing 0.594ns, distribution 3.184ns) Clock Net Delay (Destination): 3.097ns (routing 0.546ns, distribution 2.551ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.778 3.778 ipb/udp_if/ipbus_rx_ram/CLK RAMB36_X16Y51 RAMB36E2 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X16Y51 RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[0]) 1.727 5.505 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CASDOUTB[0] net (fo=1, routed) 0.015 5.520 ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0_n_67 RAMB36_X16Y52 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[0]_DOUTBDOUT[0]) 0.218 5.738 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/DOUTBDOUT[0] net (fo=698, routed) 28.004 33.742 ipb/trans/iface/rx_dob[8] SLR Crossing[0->1] SLICE_X14Y472 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.246 33.988 r ipb/trans/iface/input_size_i[8]_i_1__137/O net (fo=1, routed) 0.034 34.022 SFP_GEN[38].ngFEC_module/bram_array[3].buffer_server/input_size_i_reg[12]_1[6] SLICE_X14Y472 FDCE r SFP_GEN[38].ngFEC_module/bram_array[3].buffer_server/input_size_i_reg[8]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.097 35.097 SFP_GEN[38].ngFEC_module/bram_array[3].buffer_server/CLK SLR Crossing[0->1] SLICE_X14Y472 FDCE r SFP_GEN[38].ngFEC_module/bram_array[3].buffer_server/input_size_i_reg[8]/C clock pessimism 0.048 35.145 inter-SLR compensation -0.383 34.762 clock uncertainty -0.085 34.677 SLICE_X14Y472 FDCE (Setup_GFF_SLICEM_C_D) 0.064 34.741 SFP_GEN[38].ngFEC_module/bram_array[3].buffer_server/input_size_i_reg[8] ------------------------------------------------------------------- required time 34.741 arrival time -34.022 ------------------------------------------------------------------- slack 0.719 Slack (MET) : 0.837ns (required time - arrival time) Source: ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[38].ngFEC_module/bram_array[4].buffer_server/input_size_i_reg[8]/D (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 30.134ns (logic 2.188ns (7.261%) route 27.946ns (92.739%)) Logic Levels: 2 (LUT6=1 RAMB36E2=1) Clock Path Skew: -0.622ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.108ns = ( 35.108 - 32.000 ) Source Clock Delay (SCD): 3.778ns Clock Pessimism Removal (CPR): 0.048ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.384ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.108ns Common Clock Delay (CCD): 0.546ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.778ns (routing 0.594ns, distribution 3.184ns) Clock Net Delay (Destination): 3.108ns (routing 0.546ns, distribution 2.562ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.778 3.778 ipb/udp_if/ipbus_rx_ram/CLK RAMB36_X16Y51 RAMB36E2 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X16Y51 RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[0]) 1.727 5.505 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CASDOUTB[0] net (fo=1, routed) 0.015 5.520 ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0_n_67 RAMB36_X16Y52 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[0]_DOUTBDOUT[0]) 0.218 5.738 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/DOUTBDOUT[0] net (fo=698, routed) 27.897 33.635 ipb/trans/iface/rx_dob[8] SLR Crossing[0->1] SLICE_X17Y469 LUT6 (Prop_B6LUT_SLICEM_I0_O) 0.243 33.878 r ipb/trans/iface/input_size_i[8]_i_1__138/O net (fo=1, routed) 0.034 33.912 SFP_GEN[38].ngFEC_module/bram_array[4].buffer_server/input_size_i_reg[12]_1[6] SLICE_X17Y469 FDCE r SFP_GEN[38].ngFEC_module/bram_array[4].buffer_server/input_size_i_reg[8]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.108 35.108 SFP_GEN[38].ngFEC_module/bram_array[4].buffer_server/CLK SLR Crossing[0->1] SLICE_X17Y469 FDCE r SFP_GEN[38].ngFEC_module/bram_array[4].buffer_server/input_size_i_reg[8]/C clock pessimism 0.048 35.156 inter-SLR compensation -0.384 34.772 clock uncertainty -0.085 34.687 SLICE_X17Y469 FDCE (Setup_BFF_SLICEM_C_D) 0.062 34.749 SFP_GEN[38].ngFEC_module/bram_array[4].buffer_server/input_size_i_reg[8] ------------------------------------------------------------------- required time 34.749 arrival time -33.912 ------------------------------------------------------------------- slack 0.837 Slack (MET) : 0.989ns (required time - arrival time) Source: ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[38].ngFEC_module/bram_array[6].buffer_server/input_size_i_reg[8]/D (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 29.904ns (logic 2.037ns (6.812%) route 27.867ns (93.188%)) Logic Levels: 2 (LUT6=1 RAMB36E2=1) Clock Path Skew: -0.715ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.015ns = ( 35.015 - 32.000 ) Source Clock Delay (SCD): 3.778ns Clock Pessimism Removal (CPR): 0.048ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.370ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.015ns Common Clock Delay (CCD): 0.546ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.778ns (routing 0.594ns, distribution 3.184ns) Clock Net Delay (Destination): 3.015ns (routing 0.546ns, distribution 2.469ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.778 3.778 ipb/udp_if/ipbus_rx_ram/CLK RAMB36_X16Y51 RAMB36E2 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X16Y51 RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[0]) 1.727 5.505 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CASDOUTB[0] net (fo=1, routed) 0.015 5.520 ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0_n_67 RAMB36_X16Y52 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[0]_DOUTBDOUT[0]) 0.218 5.738 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/DOUTBDOUT[0] net (fo=698, routed) 27.817 33.555 ipb/trans/iface/rx_dob[8] SLR Crossing[0->1] SLICE_X29Y478 LUT6 (Prop_D6LUT_SLICEM_I0_O) 0.092 33.647 r ipb/trans/iface/input_size_i[8]_i_1__140/O net (fo=1, routed) 0.035 33.682 SFP_GEN[38].ngFEC_module/bram_array[6].buffer_server/input_size_i_reg[12]_1[6] SLICE_X29Y478 FDCE r SFP_GEN[38].ngFEC_module/bram_array[6].buffer_server/input_size_i_reg[8]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.015 35.015 SFP_GEN[38].ngFEC_module/bram_array[6].buffer_server/CLK SLR Crossing[0->1] SLICE_X29Y478 FDCE r SFP_GEN[38].ngFEC_module/bram_array[6].buffer_server/input_size_i_reg[8]/C clock pessimism 0.048 35.063 inter-SLR compensation -0.370 34.693 clock uncertainty -0.085 34.608 SLICE_X29Y478 FDCE (Setup_DFF_SLICEM_C_D) 0.063 34.671 SFP_GEN[38].ngFEC_module/bram_array[6].buffer_server/input_size_i_reg[8] ------------------------------------------------------------------- required time 34.671 arrival time -33.682 ------------------------------------------------------------------- slack 0.989 Slack (MET) : 1.075ns (required time - arrival time) Source: ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[38].ngFEC_module/bram_array[8].buffer_server/input_size_i_reg[8]/D (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 29.802ns (logic 2.000ns (6.711%) route 27.802ns (93.289%)) Logic Levels: 2 (LUT6=1 RAMB36E2=1) Clock Path Skew: -0.733ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.997ns = ( 34.997 - 32.000 ) Source Clock Delay (SCD): 3.778ns Clock Pessimism Removal (CPR): 0.048ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.368ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 2.997ns Common Clock Delay (CCD): 0.546ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.778ns (routing 0.594ns, distribution 3.184ns) Clock Net Delay (Destination): 2.997ns (routing 0.546ns, distribution 2.451ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.778 3.778 ipb/udp_if/ipbus_rx_ram/CLK RAMB36_X16Y51 RAMB36E2 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X16Y51 RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[0]) 1.727 5.505 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CASDOUTB[0] net (fo=1, routed) 0.015 5.520 ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0_n_67 RAMB36_X16Y52 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[0]_DOUTBDOUT[0]) 0.218 5.738 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/DOUTBDOUT[0] net (fo=698, routed) 27.752 33.490 ipb/trans/iface/rx_dob[8] SLR Crossing[0->1] SLICE_X29Y481 LUT6 (Prop_D6LUT_SLICEM_I0_O) 0.055 33.545 r ipb/trans/iface/input_size_i[8]_i_1__142/O net (fo=1, routed) 0.035 33.580 SFP_GEN[38].ngFEC_module/bram_array[8].buffer_server/input_size_i_reg[12]_1[6] SLICE_X29Y481 FDCE r SFP_GEN[38].ngFEC_module/bram_array[8].buffer_server/input_size_i_reg[8]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 2.997 34.997 SFP_GEN[38].ngFEC_module/bram_array[8].buffer_server/CLK SLR Crossing[0->1] SLICE_X29Y481 FDCE r SFP_GEN[38].ngFEC_module/bram_array[8].buffer_server/input_size_i_reg[8]/C clock pessimism 0.048 35.045 inter-SLR compensation -0.368 34.677 clock uncertainty -0.085 34.592 SLICE_X29Y481 FDCE (Setup_DFF_SLICEM_C_D) 0.063 34.655 SFP_GEN[38].ngFEC_module/bram_array[8].buffer_server/input_size_i_reg[8] ------------------------------------------------------------------- required time 34.655 arrival time -33.580 ------------------------------------------------------------------- slack 1.075 Slack (MET) : 1.384ns (required time - arrival time) Source: ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[38].ngFEC_module/bram_array[1].buffer_server/input_size_i_reg[8]/D (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 29.505ns (logic 2.117ns (7.175%) route 27.388ns (92.825%)) Logic Levels: 2 (LUT6=1 RAMB36E2=1) Clock Path Skew: -0.718ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.012ns = ( 35.012 - 32.000 ) Source Clock Delay (SCD): 3.778ns Clock Pessimism Removal (CPR): 0.048ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.370ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.012ns Common Clock Delay (CCD): 0.546ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.778ns (routing 0.594ns, distribution 3.184ns) Clock Net Delay (Destination): 3.012ns (routing 0.546ns, distribution 2.466ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.778 3.778 ipb/udp_if/ipbus_rx_ram/CLK RAMB36_X16Y51 RAMB36E2 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X16Y51 RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[0]) 1.727 5.505 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CASDOUTB[0] net (fo=1, routed) 0.015 5.520 ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0_n_67 RAMB36_X16Y52 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[0]_DOUTBDOUT[0]) 0.218 5.738 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/DOUTBDOUT[0] net (fo=698, routed) 27.339 33.077 ipb/trans/iface/rx_dob[8] SLR Crossing[0->1] SLICE_X23Y481 LUT6 (Prop_B6LUT_SLICEM_I0_O) 0.172 33.249 r ipb/trans/iface/input_size_i[8]_i_1__135/O net (fo=1, routed) 0.034 33.283 SFP_GEN[38].ngFEC_module/bram_array[1].buffer_server/input_size_i_reg[12]_1[6] SLICE_X23Y481 FDCE r SFP_GEN[38].ngFEC_module/bram_array[1].buffer_server/input_size_i_reg[8]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.012 35.012 SFP_GEN[38].ngFEC_module/bram_array[1].buffer_server/CLK SLR Crossing[0->1] SLICE_X23Y481 FDCE r SFP_GEN[38].ngFEC_module/bram_array[1].buffer_server/input_size_i_reg[8]/C clock pessimism 0.048 35.060 inter-SLR compensation -0.370 34.690 clock uncertainty -0.085 34.605 SLICE_X23Y481 FDCE (Setup_BFF_SLICEM_C_D) 0.062 34.667 SFP_GEN[38].ngFEC_module/bram_array[1].buffer_server/input_size_i_reg[8] ------------------------------------------------------------------- required time 34.667 arrival time -33.283 ------------------------------------------------------------------- slack 1.384 Slack (MET) : 1.435ns (required time - arrival time) Source: ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[38].ngFEC_module/bram_array[2].buffer_server/input_size_i_reg[8]/D (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 29.544ns (logic 2.033ns (6.881%) route 27.511ns (93.119%)) Logic Levels: 2 (LUT6=1 RAMB36E2=1) Clock Path Skew: -0.614ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.116ns = ( 35.116 - 32.000 ) Source Clock Delay (SCD): 3.778ns Clock Pessimism Removal (CPR): 0.048ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.385ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.116ns Common Clock Delay (CCD): 0.546ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.778ns (routing 0.594ns, distribution 3.184ns) Clock Net Delay (Destination): 3.116ns (routing 0.546ns, distribution 2.570ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.778 3.778 ipb/udp_if/ipbus_rx_ram/CLK RAMB36_X16Y51 RAMB36E2 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X16Y51 RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[0]) 1.727 5.505 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CASDOUTB[0] net (fo=1, routed) 0.015 5.520 ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0_n_67 RAMB36_X16Y52 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[0]_DOUTBDOUT[0]) 0.218 5.738 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/DOUTBDOUT[0] net (fo=698, routed) 27.459 33.197 ipb/trans/iface/rx_dob[8] SLR Crossing[0->1] SLICE_X18Y481 LUT6 (Prop_C6LUT_SLICEL_I0_O) 0.088 33.285 r ipb/trans/iface/input_size_i[8]_i_1__136/O net (fo=1, routed) 0.037 33.322 SFP_GEN[38].ngFEC_module/bram_array[2].buffer_server/input_size_i_reg[12]_1[6] SLICE_X18Y481 FDCE r SFP_GEN[38].ngFEC_module/bram_array[2].buffer_server/input_size_i_reg[8]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.116 35.116 SFP_GEN[38].ngFEC_module/bram_array[2].buffer_server/CLK SLR Crossing[0->1] SLICE_X18Y481 FDCE r SFP_GEN[38].ngFEC_module/bram_array[2].buffer_server/input_size_i_reg[8]/C clock pessimism 0.048 35.164 inter-SLR compensation -0.385 34.779 clock uncertainty -0.085 34.694 SLICE_X18Y481 FDCE (Setup_CFF_SLICEL_C_D) 0.063 34.757 SFP_GEN[38].ngFEC_module/bram_array[2].buffer_server/input_size_i_reg[8] ------------------------------------------------------------------- required time 34.757 arrival time -33.322 ------------------------------------------------------------------- slack 1.435 Slack (MET) : 1.550ns (required time - arrival time) Source: ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[38].ngFEC_module/bram_array[9].buffer_server/input_size_i_reg[8]/D (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 29.412ns (logic 2.188ns (7.439%) route 27.224ns (92.561%)) Logic Levels: 2 (LUT6=1 RAMB36E2=1) Clock Path Skew: -0.632ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.098ns = ( 35.098 - 32.000 ) Source Clock Delay (SCD): 3.778ns Clock Pessimism Removal (CPR): 0.048ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.383ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.098ns Common Clock Delay (CCD): 0.546ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.778ns (routing 0.594ns, distribution 3.184ns) Clock Net Delay (Destination): 3.098ns (routing 0.546ns, distribution 2.552ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.778 3.778 ipb/udp_if/ipbus_rx_ram/CLK RAMB36_X16Y51 RAMB36E2 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X16Y51 RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[0]) 1.727 5.505 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CASDOUTB[0] net (fo=1, routed) 0.015 5.520 ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0_n_67 RAMB36_X16Y52 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[0]_DOUTBDOUT[0]) 0.218 5.738 r ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/DOUTBDOUT[0] net (fo=698, routed) 27.175 32.913 ipb/trans/iface/rx_dob[8] SLR Crossing[0->1] SLICE_X22Y486 LUT6 (Prop_B6LUT_SLICEM_I0_O) 0.243 33.156 r ipb/trans/iface/input_size_i[8]_i_1__143/O net (fo=1, routed) 0.034 33.190 SFP_GEN[38].ngFEC_module/bram_array[9].buffer_server/input_size_i_reg[12]_1[6] SLICE_X22Y486 FDCE r SFP_GEN[38].ngFEC_module/bram_array[9].buffer_server/input_size_i_reg[8]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.098 35.098 SFP_GEN[38].ngFEC_module/bram_array[9].buffer_server/CLK SLR Crossing[0->1] SLICE_X22Y486 FDCE r SFP_GEN[38].ngFEC_module/bram_array[9].buffer_server/input_size_i_reg[8]/C clock pessimism 0.048 35.146 inter-SLR compensation -0.383 34.763 clock uncertainty -0.085 34.678 SLICE_X22Y486 FDCE (Setup_BFF_SLICEM_C_D) 0.062 34.740 SFP_GEN[38].ngFEC_module/bram_array[9].buffer_server/input_size_i_reg[8] ------------------------------------------------------------------- required time 34.740 arrival time -33.190 ------------------------------------------------------------------- slack 1.550 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[21].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/ngccm_din_reg[1]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[21].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[1] (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.179ns (logic 0.048ns (26.816%) route 0.131ns (73.184%)) Logic Levels: 0 Clock Path Skew: 0.120ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.413ns Source Clock Delay (SCD): 1.175ns Clock Pessimism Removal (CPR): 0.118ns Clock Net Delay (Source): 1.175ns (routing 0.203ns, distribution 0.972ns) Clock Net Delay (Destination): 1.413ns (routing 0.225ns, distribution 1.188ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.175 1.175 SFP_GEN[21].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/CLK SLR Crossing[0->1] SLICE_X93Y534 FDCE r SFP_GEN[21].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/ngccm_din_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y534 FDCE (Prop_GFF2_SLICEL_C_Q) 0.048 1.223 r SFP_GEN[21].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/ngccm_din_reg[1]/Q net (fo=2, routed) 0.131 1.354 SFP_GEN[21].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/dinb[1] RAMB36_X11Y106 RAMB36E2 r SFP_GEN[21].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[1] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.413 1.413 SFP_GEN[21].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/clka SLR Crossing[0->1] RAMB36_X11Y106 RAMB36E2 r SFP_GEN[21].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK clock pessimism -0.118 1.295 RAMB36_X11Y106 RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[1]) 0.029 1.324 SFP_GEN[21].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 ------------------------------------------------------------------- required time -1.324 arrival time 1.354 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[31].ngFEC_module/buffer_ngccm_jtag/ngccm_din_reg[16]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[31].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINPBDINP[0] (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.181ns (logic 0.048ns (26.519%) route 0.133ns (73.481%)) Logic Levels: 0 Clock Path Skew: 0.122ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.345ns Source Clock Delay (SCD): 1.103ns Clock Pessimism Removal (CPR): 0.120ns Clock Net Delay (Source): 1.103ns (routing 0.203ns, distribution 0.900ns) Clock Net Delay (Destination): 1.345ns (routing 0.225ns, distribution 1.120ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.103 1.103 SFP_GEN[31].ngFEC_module/buffer_ngccm_jtag/CLK SLICE_X93Y230 FDCE r SFP_GEN[31].ngFEC_module/buffer_ngccm_jtag/ngccm_din_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y230 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.151 r SFP_GEN[31].ngFEC_module/buffer_ngccm_jtag/ngccm_din_reg[16]/Q net (fo=2, routed) 0.133 1.284 SFP_GEN[31].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/dinb[16] RAMB36_X11Y46 RAMB36E2 r SFP_GEN[31].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINPBDINP[0] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.345 1.345 SFP_GEN[31].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/clka RAMB36_X11Y46 RAMB36E2 r SFP_GEN[31].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK clock pessimism -0.120 1.225 RAMB36_X11Y46 RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINPBDINP[0]) 0.029 1.254 SFP_GEN[31].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 ------------------------------------------------------------------- required time -1.254 arrival time 1.284 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[31].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ngccm_din_reg[9]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[31].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/DINADIN[9] (rising edge-triggered cell RAMB18E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.182ns (logic 0.048ns (26.374%) route 0.134ns (73.626%)) Logic Levels: 0 Clock Path Skew: 0.123ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.470ns Source Clock Delay (SCD): 1.213ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 1.213ns (routing 0.203ns, distribution 1.010ns) Clock Net Delay (Destination): 1.470ns (routing 0.225ns, distribution 1.245ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.213 1.213 SFP_GEN[31].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/CLK SLICE_X115Y214 FDCE r SFP_GEN[31].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ngccm_din_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X115Y214 FDCE (Prop_CFF2_SLICEM_C_Q) 0.048 1.261 r SFP_GEN[31].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ngccm_din_reg[9]/Q net (fo=2, routed) 0.134 1.395 SFP_GEN[31].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/dina[9] RAMB18_X14Y85 RAMB18E2 r SFP_GEN[31].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/DINADIN[9] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.470 1.470 SFP_GEN[31].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/clka RAMB18_X14Y85 RAMB18E2 r SFP_GEN[31].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK clock pessimism -0.134 1.336 RAMB18_X14Y85 RAMB18E2 (Hold_RAMB18E2_U_RAMB181_CLKBWRCLK_DINADIN[9]) 0.029 1.365 SFP_GEN[31].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg ------------------------------------------------------------------- required time -1.365 arrival time 1.395 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[27].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/ngccm_din_reg[26]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[27].ngFEC_module/bram_array[8].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[8] (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.153ns (logic 0.048ns (31.373%) route 0.105ns (68.627%)) Logic Levels: 0 Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.324ns Source Clock Delay (SCD): 1.082ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 1.082ns (routing 0.203ns, distribution 0.879ns) Clock Net Delay (Destination): 1.324ns (routing 0.225ns, distribution 1.099ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.082 1.082 SFP_GEN[27].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/CLK SLICE_X81Y190 FDCE r SFP_GEN[27].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/ngccm_din_reg[26]/C ------------------------------------------------------------------- ------------------- SLICE_X81Y190 FDCE (Prop_EFF2_SLICEL_C_Q) 0.048 1.130 r SFP_GEN[27].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/ngccm_din_reg[26]/Q net (fo=2, routed) 0.105 1.235 SFP_GEN[27].ngFEC_module/bram_array[8].RAM/BRAM_l/xpm_memory_base_inst/dinb[26] RAMB36_X10Y38 RAMB36E2 r SFP_GEN[27].ngFEC_module/bram_array[8].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[8] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.324 1.324 SFP_GEN[27].ngFEC_module/bram_array[8].RAM/BRAM_l/xpm_memory_base_inst/clka RAMB36_X10Y38 RAMB36E2 r SFP_GEN[27].ngFEC_module/bram_array[8].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK clock pessimism -0.148 1.176 RAMB36_X10Y38 RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[8]) 0.029 1.205 SFP_GEN[27].ngFEC_module/bram_array[8].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 ------------------------------------------------------------------- required time -1.205 arrival time 1.235 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[32].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/ngccm_din_reg[14]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[32].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[14] (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.178ns (logic 0.049ns (27.528%) route 0.129ns (72.472%)) Logic Levels: 0 Clock Path Skew: 0.119ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.471ns Source Clock Delay (SCD): 1.218ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 1.218ns (routing 0.203ns, distribution 1.015ns) Clock Net Delay (Destination): 1.471ns (routing 0.225ns, distribution 1.246ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.218 1.218 SFP_GEN[32].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/CLK SLICE_X8Y222 FDCE r SFP_GEN[32].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/ngccm_din_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X8Y222 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 1.267 r SFP_GEN[32].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/ngccm_din_reg[14]/Q net (fo=2, routed) 0.129 1.396 SFP_GEN[32].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/dinb[14] RAMB36_X1Y44 RAMB36E2 r SFP_GEN[32].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[14] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.471 1.471 SFP_GEN[32].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/clka RAMB36_X1Y44 RAMB36E2 r SFP_GEN[32].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK clock pessimism -0.134 1.337 RAMB36_X1Y44 RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[14]) 0.029 1.366 SFP_GEN[32].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 ------------------------------------------------------------------- required time -1.366 arrival time 1.396 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[9].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/ngccm_din_reg[24]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[9].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[6] (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.193ns (logic 0.049ns (25.389%) route 0.144ns (74.611%)) Logic Levels: 0 Clock Path Skew: 0.134ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.504ns Source Clock Delay (SCD): 1.245ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 1.245ns (routing 0.203ns, distribution 1.042ns) Clock Net Delay (Destination): 1.504ns (routing 0.225ns, distribution 1.279ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.245 1.245 SFP_GEN[9].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/CLK SLICE_X106Y53 FDCE r SFP_GEN[9].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/ngccm_din_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y53 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.294 r SFP_GEN[9].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/ngccm_din_reg[24]/Q net (fo=2, routed) 0.144 1.438 SFP_GEN[9].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/dinb[24] RAMB36_X13Y10 RAMB36E2 r SFP_GEN[9].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[6] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.504 1.504 SFP_GEN[9].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/clka RAMB36_X13Y10 RAMB36E2 r SFP_GEN[9].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK clock pessimism -0.125 1.379 RAMB36_X13Y10 RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[6]) 0.029 1.408 SFP_GEN[9].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 ------------------------------------------------------------------- required time -1.408 arrival time 1.438 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[1].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/ngccm_din_reg[12]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[1].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/DINADIN[12] (rising edge-triggered cell RAMB18E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.156ns (logic 0.049ns (31.410%) route 0.107ns (68.590%)) Logic Levels: 0 Clock Path Skew: 0.097ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.459ns Source Clock Delay (SCD): 1.242ns Clock Pessimism Removal (CPR): 0.120ns Clock Net Delay (Source): 1.242ns (routing 0.203ns, distribution 1.039ns) Clock Net Delay (Destination): 1.459ns (routing 0.225ns, distribution 1.234ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.242 1.242 SFP_GEN[1].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/CLK SLICE_X25Y6 FDCE r SFP_GEN[1].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/ngccm_din_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X25Y6 FDCE (Prop_DFF_SLICEM_C_Q) 0.049 1.291 r SFP_GEN[1].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/ngccm_din_reg[12]/Q net (fo=2, routed) 0.107 1.398 SFP_GEN[1].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/dina[12] RAMB18_X3Y2 RAMB18E2 r SFP_GEN[1].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/DINADIN[12] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.459 1.459 SFP_GEN[1].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/clka RAMB18_X3Y2 RAMB18E2 r SFP_GEN[1].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK clock pessimism -0.120 1.339 RAMB18_X3Y2 RAMB18E2 (Hold_RAMB18E2_L_RAMB180_CLKBWRCLK_DINADIN[12]) 0.029 1.368 SFP_GEN[1].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg ------------------------------------------------------------------- required time -1.368 arrival time 1.398 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[47].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/ngccm_din_reg[26]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[47].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[8] (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.152ns (logic 0.048ns (31.579%) route 0.104ns (68.421%)) Logic Levels: 0 Clock Path Skew: 0.093ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.278ns Source Clock Delay (SCD): 1.041ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 1.041ns (routing 0.203ns, distribution 0.838ns) Clock Net Delay (Destination): 1.278ns (routing 0.225ns, distribution 1.053ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.041 1.041 SFP_GEN[47].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/CLK SLR Crossing[0->1] SLICE_X69Y401 FDCE r SFP_GEN[47].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/ngccm_din_reg[26]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y401 FDCE (Prop_GFF2_SLICEL_C_Q) 0.048 1.089 r SFP_GEN[47].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/ngccm_din_reg[26]/Q net (fo=2, routed) 0.104 1.193 SFP_GEN[47].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/dinb[26] RAMB36_X8Y80 RAMB36E2 r SFP_GEN[47].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[8] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.278 1.278 SFP_GEN[47].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/clka SLR Crossing[0->1] RAMB36_X8Y80 RAMB36E2 r SFP_GEN[47].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK clock pessimism -0.144 1.134 RAMB36_X8Y80 RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[8]) 0.029 1.163 SFP_GEN[47].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 ------------------------------------------------------------------- required time -1.163 arrival time 1.193 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[18].ngFEC_module/bkp_buffer_ngccm/ngccm_din_reg[2]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[18].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[2] (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.193ns (logic 0.048ns (24.870%) route 0.145ns (75.130%)) Logic Levels: 0 Clock Path Skew: 0.134ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.403ns Source Clock Delay (SCD): 1.147ns Clock Pessimism Removal (CPR): 0.122ns Clock Net Delay (Source): 1.147ns (routing 0.203ns, distribution 0.944ns) Clock Net Delay (Destination): 1.403ns (routing 0.225ns, distribution 1.178ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.147 1.147 SFP_GEN[18].ngFEC_module/bkp_buffer_ngccm/CLK SLR Crossing[0->1] SLICE_X95Y440 FDCE r SFP_GEN[18].ngFEC_module/bkp_buffer_ngccm/ngccm_din_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y440 FDCE (Prop_FFF2_SLICEM_C_Q) 0.048 1.195 r SFP_GEN[18].ngFEC_module/bkp_buffer_ngccm/ngccm_din_reg[2]/Q net (fo=2, routed) 0.145 1.340 SFP_GEN[18].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/dinb[2] RAMB36_X11Y88 RAMB36E2 r SFP_GEN[18].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[2] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.403 1.403 SFP_GEN[18].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/clka SLR Crossing[0->1] RAMB36_X11Y88 RAMB36E2 r SFP_GEN[18].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK clock pessimism -0.122 1.281 RAMB36_X11Y88 RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[2]) 0.029 1.310 SFP_GEN[18].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 ------------------------------------------------------------------- required time -1.310 arrival time 1.340 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[26].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ngccm_din_reg[29]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[26].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[11] (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.184ns (logic 0.049ns (26.630%) route 0.135ns (73.370%)) Logic Levels: 0 Clock Path Skew: 0.125ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.480ns Source Clock Delay (SCD): 1.224ns Clock Pessimism Removal (CPR): 0.131ns Clock Net Delay (Source): 1.224ns (routing 0.203ns, distribution 1.021ns) Clock Net Delay (Destination): 1.480ns (routing 0.225ns, distribution 1.255ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.224 1.224 SFP_GEN[26].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/CLK SLICE_X7Y157 FDCE r SFP_GEN[26].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ngccm_din_reg[29]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y157 FDCE (Prop_BFF_SLICEM_C_Q) 0.049 1.273 r SFP_GEN[26].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ngccm_din_reg[29]/Q net (fo=2, routed) 0.135 1.408 SFP_GEN[26].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/dinb[29] RAMB36_X1Y31 RAMB36E2 r SFP_GEN[26].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[11] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.480 1.480 SFP_GEN[26].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/clka RAMB36_X1Y31 RAMB36E2 r SFP_GEN[26].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK clock pessimism -0.131 1.349 RAMB36_X1Y31 RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[11]) 0.029 1.378 SFP_GEN[26].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 ------------------------------------------------------------------- required time -1.378 arrival time 1.408 ------------------------------------------------------------------- slack 0.030 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ipb_clk Waveform(ns): { 0.000 16.000 } Period(ns): 32.000 Sources: { i_ipb_clk_bufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB36E2/CLKARDCLK n/a 1.905 32.000 30.095 RAMB36_X3Y7 SFP_GEN[1].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK Min Period n/a RAMB36E2/CLKBWRCLK n/a 1.905 32.000 30.095 RAMB36_X3Y7 SFP_GEN[1].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK Min Period n/a RAMB18E2/CLKARDCLK n/a 1.905 32.000 30.095 RAMB18_X4Y15 SFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK Min Period n/a RAMB18E2/CLKBWRCLK n/a 1.905 32.000 30.095 RAMB18_X4Y15 SFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK Min Period n/a RAMB18E2/CLKARDCLK n/a 1.905 32.000 30.095 RAMB18_X7Y55 SFP_GEN[7].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK Min Period n/a RAMB18E2/CLKBWRCLK n/a 1.905 32.000 30.095 RAMB18_X7Y55 SFP_GEN[7].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 1.905 32.000 30.095 RAMB36_X4Y8 SFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKBWRCLK n/a 1.905 32.000 30.095 RAMB36_X4Y8 SFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 1.905 32.000 30.095 RAMB36_X7Y26 SFP_GEN[7].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKBWRCLK n/a 1.905 32.000 30.095 RAMB36_X7Y26 SFP_GEN[7].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 16.000 15.048 RAMB36_X3Y7 SFP_GEN[1].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK Low Pulse Width Slow RAMB18E2/CLKBWRCLK n/a 0.952 16.000 15.048 RAMB18_X7Y55 SFP_GEN[7].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 16.000 15.048 RAMB36_X4Y8 SFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.952 16.000 15.048 RAMB36_X4Y8 SFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.952 16.000 15.048 RAMB36_X4Y8 SFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK Low Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.952 16.000 15.048 RAMB36_X7Y26 SFP_GEN[7].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK Low Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.952 16.000 15.048 RAMB36_X4Y9 SFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK Low Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.952 16.000 15.048 RAMB36_X7Y28 SFP_GEN[7].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK Low Pulse Width Fast RAMB18E2/CLKARDCLK n/a 0.952 16.000 15.048 RAMB18_X6Y51 SFP_GEN[7].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK Low Pulse Width Fast RAMB18E2/CLKBWRCLK n/a 0.952 16.000 15.048 RAMB18_X6Y51 SFP_GEN[7].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK High Pulse Width Slow RAMB18E2/CLKBWRCLK n/a 0.952 16.000 15.048 RAMB18_X4Y15 SFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 16.000 15.048 RAMB36_X4Y8 SFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 16.000 15.048 RAMB36_X7Y28 SFP_GEN[7].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.952 16.000 15.048 RAMB36_X5Y26 SFP_GEN[7].ngFEC_module/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 16.000 15.048 RAMB36_X5Y4 SFP_GEN[1].ngFEC_module/bram_array[4].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 16.000 15.048 RAMB36_X5Y22 SFP_GEN[7].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK High Pulse Width Slow RAMB18E2/CLKARDCLK n/a 0.952 16.000 15.048 RAMB18_X1Y26 SFP_GEN[0].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK High Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.952 16.000 15.048 RAMB36_X1Y11 SFP_GEN[0].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK High Pulse Width Slow RAMB18E2/CLKBWRCLK n/a 0.952 16.000 15.048 RAMB18_X1Y13 SFP_GEN[0].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK High Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.952 16.000 15.048 RAMB36_X1Y0 SFP_GEN[0].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK --------------------------------------------------------------------------------------------------- From Clock: refclk125 To Clock: refclk125 Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 1.600ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: refclk125 Waveform(ns): { 0.000 4.000 } Period(ns): 8.000 Sources: { refclk125_p } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG_GT/I n/a 1.587 8.000 6.413 BUFG_GT_X1Y0 i_refclk125_bufg/I Min Period n/a MMCME3_ADV/CLKIN1 n/a 1.250 8.000 6.750 MMCME3_ADV_X1Y4 i_clk125_MMCM/CLKIN1 Low Pulse Width Fast MMCME3_ADV/CLKIN1 n/a 2.400 4.000 1.600 MMCME3_ADV_X1Y4 i_clk125_MMCM/CLKIN1 Low Pulse Width Slow MMCME3_ADV/CLKIN1 n/a 2.400 4.000 1.600 MMCME3_ADV_X1Y4 i_clk125_MMCM/CLKIN1 High Pulse Width Slow MMCME3_ADV/CLKIN1 n/a 2.400 4.000 1.600 MMCME3_ADV_X1Y4 i_clk125_MMCM/CLKIN1 High Pulse Width Fast MMCME3_ADV/CLKIN1 n/a 2.400 4.000 1.600 MMCME3_ADV_X1Y4 i_clk125_MMCM/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: DRPclk_dcm To Clock: DRPclk_dcm Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 18.413ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: DRPclk_dcm Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { i_clk125_MMCM/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFGCE/I n/a 1.587 20.000 18.413 BUFGCE_X1Y114 i_DRPclk_bufg/I Min Period n/a MMCME3_ADV/CLKOUT0 n/a 1.250 20.000 18.750 MMCME3_ADV_X1Y4 i_clk125_MMCM/CLKOUT0 --------------------------------------------------------------------------------------------------- From Clock: clk125_dcm To Clock: clk125_dcm Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 6.413ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk125_dcm Waveform(ns): { 0.000 4.000 } Period(ns): 8.000 Sources: { i_clk125_MMCM/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFGCE/I n/a 1.587 8.000 6.413 BUFGCE_X1Y108 i_clk125_bufg/I Min Period n/a MMCME3_ADV/CLKFBOUT n/a 1.250 8.000 6.750 MMCME3_ADV_X1Y4 i_clk125_MMCM/CLKFBOUT --------------------------------------------------------------------------------------------------- From Clock: clk250_dcm To Clock: clk250_dcm Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 2.413ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk250_dcm Waveform(ns): { 0.000 2.000 } Period(ns): 4.000 Sources: { i_clk125_MMCM/CLKOUT3 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFGCE/I n/a 1.587 4.000 2.413 BUFGCE_X1Y100 i_clk250_bufg/I Min Period n/a MMCME3_ADV/CLKOUT3 n/a 1.250 4.000 2.750 MMCME3_ADV_X1Y4 i_clk125_MMCM/CLKOUT3 --------------------------------------------------------------------------------------------------- From Clock: clk62_5_dcm To Clock: clk62_5_dcm Setup : 0 Failing Endpoints, Worst Slack 14.025ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.033ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 14.025ns (required time - arrival time) Source: eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: eth/phy/U0/transceiver_inst/rxbufstatus_reg_reg[2]/D (rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_dcm Path Type: Setup (Max at Slow Process Corner) Requirement: 16.000ns (clk62_5_dcm rise@16.000ns - clk62_5_dcm rise@0.000ns) Data Path Delay: 1.917ns (logic 1.267ns (66.093%) route 0.650ns (33.907%)) Logic Levels: 0 Clock Path Skew: -0.045ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.041ns = ( 20.041 - 16.000 ) Source Clock Delay (SCD): 4.999ns Clock Pessimism Removal (CPR): 0.912ns Clock Uncertainty: 0.076ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.135ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.947ns (routing 2.551ns, distribution 1.396ns) Clock Net Delay (Destination): 3.616ns (routing 2.351ns, distribution 1.265ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.391 0.391 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.091 0.482 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.866 r i_refclk125_bufg/O net (fo=1, routed) 3.742 4.608 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -4.158 0.450 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.501 0.951 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.101 1.052 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 3.947 4.999 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXBUFSTATUS[2]) 1.267 6.266 r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXBUFSTATUS[2] net (fo=1, routed) 0.650 6.916 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i_n_58 SLICE_X141Y8 FDRE r eth/phy/U0/transceiver_inst/rxbufstatus_reg_reg[2]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 16.000 16.000 r GTHE3_COMMON_X1Y0 0.000 16.000 r refclk125_p (IN) net (fo=0) 0.000 16.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.209 16.209 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.052 16.261 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 16.607 r i_refclk125_bufg/O net (fo=1, routed) 3.370 19.977 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -4.065 15.912 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.422 16.334 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.091 16.425 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 3.616 20.041 eth/phy/U0/transceiver_inst/userclk SLICE_X141Y8 FDRE r eth/phy/U0/transceiver_inst/rxbufstatus_reg_reg[2]/C clock pessimism 0.912 20.954 clock uncertainty -0.076 20.878 SLICE_X141Y8 FDRE (Setup_EFF_SLICEL_C_D) 0.064 20.942 eth/phy/U0/transceiver_inst/rxbufstatus_reg_reg[2] ------------------------------------------------------------------- required time 20.942 arrival time -6.916 ------------------------------------------------------------------- slack 14.025 Slack (MET) : 14.109ns (required time - arrival time) Source: eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: eth/phy/U0/transceiver_inst/txbufstatus_reg_reg[1]/D (rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_dcm Path Type: Setup (Max at Slow Process Corner) Requirement: 16.000ns (clk62_5_dcm rise@16.000ns - clk62_5_dcm rise@0.000ns) Data Path Delay: 1.828ns (logic 1.299ns (71.061%) route 0.529ns (28.939%)) Logic Levels: 0 Clock Path Skew: -0.050ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.054ns = ( 20.054 - 16.000 ) Source Clock Delay (SCD): 5.016ns Clock Pessimism Removal (CPR): 0.912ns Clock Uncertainty: 0.076ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.135ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.964ns (routing 2.551ns, distribution 1.413ns) Clock Net Delay (Destination): 3.629ns (routing 2.351ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.391 0.391 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.091 0.482 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.866 r i_refclk125_bufg/O net (fo=1, routed) 3.742 4.608 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -4.158 0.450 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.501 0.951 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.101 1.052 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 3.964 5.016 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_TXUSRCLK2_TXBUFSTATUS[1]) 1.299 6.315 r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXBUFSTATUS[1] net (fo=1, routed) 0.529 6.844 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i_n_118 SLICE_X140Y2 FDRE r eth/phy/U0/transceiver_inst/txbufstatus_reg_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 16.000 16.000 r GTHE3_COMMON_X1Y0 0.000 16.000 r refclk125_p (IN) net (fo=0) 0.000 16.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.209 16.209 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.052 16.261 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 16.607 r i_refclk125_bufg/O net (fo=1, routed) 3.370 19.977 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -4.065 15.912 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.422 16.334 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.091 16.425 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 3.629 20.054 eth/phy/U0/transceiver_inst/userclk SLICE_X140Y2 FDRE r eth/phy/U0/transceiver_inst/txbufstatus_reg_reg[1]/C clock pessimism 0.912 20.966 clock uncertainty -0.076 20.890 SLICE_X140Y2 FDRE (Setup_AFF_SLICEL_C_D) 0.063 20.953 eth/phy/U0/transceiver_inst/txbufstatus_reg_reg[1] ------------------------------------------------------------------- required time 20.953 arrival time -6.844 ------------------------------------------------------------------- slack 14.109 Slack (MET) : 14.166ns (required time - arrival time) Source: eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: eth/phy/U0/transceiver_inst/rxdata_reg_reg[0]/D (rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_dcm Path Type: Setup (Max at Slow Process Corner) Requirement: 16.000ns (clk62_5_dcm rise@16.000ns - clk62_5_dcm rise@0.000ns) Data Path Delay: 1.866ns (logic 1.104ns (59.164%) route 0.762ns (40.836%)) Logic Levels: 0 Clock Path Skew: 0.046ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.060ns = ( 20.060 - 16.000 ) Source Clock Delay (SCD): 4.999ns Clock Pessimism Removal (CPR): 0.984ns Clock Uncertainty: 0.076ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.135ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.947ns (routing 2.551ns, distribution 1.396ns) Clock Net Delay (Destination): 3.635ns (routing 2.351ns, distribution 1.284ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.391 0.391 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.091 0.482 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.866 r i_refclk125_bufg/O net (fo=1, routed) 3.742 4.608 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -4.158 0.450 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.501 0.951 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.101 1.052 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 3.947 4.999 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 6.103 r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=1, routed) 0.762 6.865 eth/phy/U0/transceiver_inst/rxdata_int[0] SLICE_X142Y6 FDRE r eth/phy/U0/transceiver_inst/rxdata_reg_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 16.000 16.000 r GTHE3_COMMON_X1Y0 0.000 16.000 r refclk125_p (IN) net (fo=0) 0.000 16.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.209 16.209 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.052 16.261 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 16.607 r i_refclk125_bufg/O net (fo=1, routed) 3.370 19.977 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -4.065 15.912 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.422 16.334 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.091 16.425 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 3.635 20.060 eth/phy/U0/transceiver_inst/userclk SLICE_X142Y6 FDRE r eth/phy/U0/transceiver_inst/rxdata_reg_reg[0]/C clock pessimism 0.984 21.045 clock uncertainty -0.076 20.969 SLICE_X142Y6 FDRE (Setup_AFF_SLICEM_C_D) 0.063 21.032 eth/phy/U0/transceiver_inst/rxdata_reg_reg[0] ------------------------------------------------------------------- required time 21.032 arrival time -6.865 ------------------------------------------------------------------- slack 14.166 Slack (MET) : 14.183ns (required time - arrival time) Source: eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: eth/phy/U0/transceiver_inst/rxdata_reg_reg[15]/D (rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_dcm Path Type: Setup (Max at Slow Process Corner) Requirement: 16.000ns (clk62_5_dcm rise@16.000ns - clk62_5_dcm rise@0.000ns) Data Path Delay: 1.857ns (logic 1.123ns (60.474%) route 0.734ns (39.526%)) Logic Levels: 0 Clock Path Skew: 0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.066ns = ( 20.066 - 16.000 ) Source Clock Delay (SCD): 4.999ns Clock Pessimism Removal (CPR): 0.984ns Clock Uncertainty: 0.076ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.135ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.947ns (routing 2.551ns, distribution 1.396ns) Clock Net Delay (Destination): 3.641ns (routing 2.351ns, distribution 1.290ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.391 0.391 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.091 0.482 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.866 r i_refclk125_bufg/O net (fo=1, routed) 3.742 4.608 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -4.158 0.450 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.501 0.951 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.101 1.052 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 3.947 4.999 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[15]) 1.123 6.122 r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[15] net (fo=1, routed) 0.734 6.856 eth/phy/U0/transceiver_inst/rxdata_int[15] SLICE_X142Y5 FDRE r eth/phy/U0/transceiver_inst/rxdata_reg_reg[15]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 16.000 16.000 r GTHE3_COMMON_X1Y0 0.000 16.000 r refclk125_p (IN) net (fo=0) 0.000 16.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.209 16.209 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.052 16.261 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 16.607 r i_refclk125_bufg/O net (fo=1, routed) 3.370 19.977 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -4.065 15.912 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.422 16.334 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.091 16.425 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 3.641 20.066 eth/phy/U0/transceiver_inst/userclk SLICE_X142Y5 FDRE r eth/phy/U0/transceiver_inst/rxdata_reg_reg[15]/C clock pessimism 0.984 21.051 clock uncertainty -0.076 20.974 SLICE_X142Y5 FDRE (Setup_EFF2_SLICEM_C_D) 0.065 21.039 eth/phy/U0/transceiver_inst/rxdata_reg_reg[15] ------------------------------------------------------------------- required time 21.039 arrival time -6.856 ------------------------------------------------------------------- slack 14.183 Slack (MET) : 14.200ns (required time - arrival time) Source: eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: eth/phy/U0/transceiver_inst/rxdata_reg_reg[11]/D (rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_dcm Path Type: Setup (Max at Slow Process Corner) Requirement: 16.000ns (clk62_5_dcm rise@16.000ns - clk62_5_dcm rise@0.000ns) Data Path Delay: 1.830ns (logic 1.084ns (59.235%) route 0.746ns (40.765%)) Logic Levels: 0 Clock Path Skew: 0.044ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.058ns = ( 20.058 - 16.000 ) Source Clock Delay (SCD): 4.999ns Clock Pessimism Removal (CPR): 0.984ns Clock Uncertainty: 0.076ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.135ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.947ns (routing 2.551ns, distribution 1.396ns) Clock Net Delay (Destination): 3.633ns (routing 2.351ns, distribution 1.282ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.391 0.391 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.091 0.482 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.866 r i_refclk125_bufg/O net (fo=1, routed) 3.742 4.608 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -4.158 0.450 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.501 0.951 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.101 1.052 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 3.947 4.999 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[11]) 1.084 6.083 r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[11] net (fo=1, routed) 0.746 6.829 eth/phy/U0/transceiver_inst/rxdata_int[11] SLICE_X142Y6 FDRE r eth/phy/U0/transceiver_inst/rxdata_reg_reg[11]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 16.000 16.000 r GTHE3_COMMON_X1Y0 0.000 16.000 r refclk125_p (IN) net (fo=0) 0.000 16.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.209 16.209 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.052 16.261 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 16.607 r i_refclk125_bufg/O net (fo=1, routed) 3.370 19.977 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -4.065 15.912 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.422 16.334 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.091 16.425 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 3.633 20.058 eth/phy/U0/transceiver_inst/userclk SLICE_X142Y6 FDRE r eth/phy/U0/transceiver_inst/rxdata_reg_reg[11]/C clock pessimism 0.984 21.043 clock uncertainty -0.076 20.967 SLICE_X142Y6 FDRE (Setup_FFF_SLICEM_C_D) 0.063 21.030 eth/phy/U0/transceiver_inst/rxdata_reg_reg[11] ------------------------------------------------------------------- required time 21.030 arrival time -6.829 ------------------------------------------------------------------- slack 14.200 Slack (MET) : 14.208ns (required time - arrival time) Source: eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: eth/phy/U0/transceiver_inst/rxdata_reg_reg[7]/D (rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_dcm Path Type: Setup (Max at Slow Process Corner) Requirement: 16.000ns (clk62_5_dcm rise@16.000ns - clk62_5_dcm rise@0.000ns) Data Path Delay: 1.831ns (logic 1.119ns (61.114%) route 0.712ns (38.886%)) Logic Levels: 0 Clock Path Skew: 0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.066ns = ( 20.066 - 16.000 ) Source Clock Delay (SCD): 4.999ns Clock Pessimism Removal (CPR): 0.984ns Clock Uncertainty: 0.076ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.135ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.947ns (routing 2.551ns, distribution 1.396ns) Clock Net Delay (Destination): 3.641ns (routing 2.351ns, distribution 1.290ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.391 0.391 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.091 0.482 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.866 r i_refclk125_bufg/O net (fo=1, routed) 3.742 4.608 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -4.158 0.450 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.501 0.951 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.101 1.052 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 3.947 4.999 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[7]) 1.119 6.118 r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[7] net (fo=1, routed) 0.712 6.830 eth/phy/U0/transceiver_inst/rxdata_int[7] SLICE_X142Y5 FDRE r eth/phy/U0/transceiver_inst/rxdata_reg_reg[7]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 16.000 16.000 r GTHE3_COMMON_X1Y0 0.000 16.000 r refclk125_p (IN) net (fo=0) 0.000 16.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.209 16.209 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.052 16.261 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 16.607 r i_refclk125_bufg/O net (fo=1, routed) 3.370 19.977 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -4.065 15.912 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.422 16.334 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.091 16.425 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 3.641 20.066 eth/phy/U0/transceiver_inst/userclk SLICE_X142Y5 FDRE r eth/phy/U0/transceiver_inst/rxdata_reg_reg[7]/C clock pessimism 0.984 21.051 clock uncertainty -0.076 20.974 SLICE_X142Y5 FDRE (Setup_HFF2_SLICEM_C_D) 0.064 21.038 eth/phy/U0/transceiver_inst/rxdata_reg_reg[7] ------------------------------------------------------------------- required time 21.038 arrival time -6.830 ------------------------------------------------------------------- slack 14.208 Slack (MET) : 14.226ns (required time - arrival time) Source: eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: eth/phy/U0/transceiver_inst/rxdata_reg_reg[5]/D (rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_dcm Path Type: Setup (Max at Slow Process Corner) Requirement: 16.000ns (clk62_5_dcm rise@16.000ns - clk62_5_dcm rise@0.000ns) Data Path Delay: 1.814ns (logic 1.097ns (60.474%) route 0.717ns (39.526%)) Logic Levels: 0 Clock Path Skew: 0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.066ns = ( 20.066 - 16.000 ) Source Clock Delay (SCD): 4.999ns Clock Pessimism Removal (CPR): 0.984ns Clock Uncertainty: 0.076ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.135ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.947ns (routing 2.551ns, distribution 1.396ns) Clock Net Delay (Destination): 3.641ns (routing 2.351ns, distribution 1.290ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.391 0.391 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.091 0.482 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.866 r i_refclk125_bufg/O net (fo=1, routed) 3.742 4.608 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -4.158 0.450 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.501 0.951 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.101 1.052 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 3.947 4.999 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[5]) 1.097 6.096 r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[5] net (fo=1, routed) 0.717 6.813 eth/phy/U0/transceiver_inst/rxdata_int[5] SLICE_X142Y5 FDRE r eth/phy/U0/transceiver_inst/rxdata_reg_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 16.000 16.000 r GTHE3_COMMON_X1Y0 0.000 16.000 r refclk125_p (IN) net (fo=0) 0.000 16.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.209 16.209 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.052 16.261 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 16.607 r i_refclk125_bufg/O net (fo=1, routed) 3.370 19.977 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -4.065 15.912 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.422 16.334 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.091 16.425 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 3.641 20.066 eth/phy/U0/transceiver_inst/userclk SLICE_X142Y5 FDRE r eth/phy/U0/transceiver_inst/rxdata_reg_reg[5]/C clock pessimism 0.984 21.051 clock uncertainty -0.076 20.974 SLICE_X142Y5 FDRE (Setup_GFF2_SLICEM_C_D) 0.065 21.039 eth/phy/U0/transceiver_inst/rxdata_reg_reg[5] ------------------------------------------------------------------- required time 21.039 arrival time -6.813 ------------------------------------------------------------------- slack 14.226 Slack (MET) : 14.292ns (required time - arrival time) Source: eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: eth/phy/U0/transceiver_inst/rxchariscomma_reg_reg[1]/D (rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_dcm Path Type: Setup (Max at Slow Process Corner) Requirement: 16.000ns (clk62_5_dcm rise@16.000ns - clk62_5_dcm rise@0.000ns) Data Path Delay: 1.739ns (logic 0.935ns (53.767%) route 0.804ns (46.233%)) Logic Levels: 0 Clock Path Skew: 0.044ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.058ns = ( 20.058 - 16.000 ) Source Clock Delay (SCD): 4.999ns Clock Pessimism Removal (CPR): 0.984ns Clock Uncertainty: 0.076ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.135ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.947ns (routing 2.551ns, distribution 1.396ns) Clock Net Delay (Destination): 3.633ns (routing 2.351ns, distribution 1.282ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.391 0.391 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.091 0.482 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.866 r i_refclk125_bufg/O net (fo=1, routed) 3.742 4.608 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -4.158 0.450 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.501 0.951 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.101 1.052 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 3.947 4.999 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXCTRL2[1]) 0.935 5.934 r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXCTRL2[1] net (fo=1, routed) 0.804 6.738 eth/phy/U0/transceiver_inst/rxctrl2_out[1] SLICE_X142Y6 FDRE r eth/phy/U0/transceiver_inst/rxchariscomma_reg_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 16.000 16.000 r GTHE3_COMMON_X1Y0 0.000 16.000 r refclk125_p (IN) net (fo=0) 0.000 16.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.209 16.209 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.052 16.261 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 16.607 r i_refclk125_bufg/O net (fo=1, routed) 3.370 19.977 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -4.065 15.912 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.422 16.334 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.091 16.425 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 3.633 20.058 eth/phy/U0/transceiver_inst/userclk SLICE_X142Y6 FDRE r eth/phy/U0/transceiver_inst/rxchariscomma_reg_reg[1]/C clock pessimism 0.984 21.043 clock uncertainty -0.076 20.967 SLICE_X142Y6 FDRE (Setup_EFF_SLICEM_C_D) 0.064 21.031 eth/phy/U0/transceiver_inst/rxchariscomma_reg_reg[1] ------------------------------------------------------------------- required time 21.031 arrival time -6.738 ------------------------------------------------------------------- slack 14.292 Slack (MET) : 14.339ns (required time - arrival time) Source: eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: eth/phy/U0/transceiver_inst/rxdata_reg_reg[14]/D (rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_dcm Path Type: Setup (Max at Slow Process Corner) Requirement: 16.000ns (clk62_5_dcm rise@16.000ns - clk62_5_dcm rise@0.000ns) Data Path Delay: 1.700ns (logic 1.087ns (63.941%) route 0.613ns (36.059%)) Logic Levels: 0 Clock Path Skew: 0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.066ns = ( 20.066 - 16.000 ) Source Clock Delay (SCD): 4.999ns Clock Pessimism Removal (CPR): 0.984ns Clock Uncertainty: 0.076ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.135ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.947ns (routing 2.551ns, distribution 1.396ns) Clock Net Delay (Destination): 3.641ns (routing 2.351ns, distribution 1.290ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.391 0.391 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.091 0.482 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.866 r i_refclk125_bufg/O net (fo=1, routed) 3.742 4.608 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -4.158 0.450 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.501 0.951 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.101 1.052 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 3.947 4.999 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[14]) 1.087 6.086 r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[14] net (fo=1, routed) 0.613 6.699 eth/phy/U0/transceiver_inst/rxdata_int[14] SLICE_X142Y5 FDRE r eth/phy/U0/transceiver_inst/rxdata_reg_reg[14]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 16.000 16.000 r GTHE3_COMMON_X1Y0 0.000 16.000 r refclk125_p (IN) net (fo=0) 0.000 16.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.209 16.209 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.052 16.261 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 16.607 r i_refclk125_bufg/O net (fo=1, routed) 3.370 19.977 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -4.065 15.912 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.422 16.334 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.091 16.425 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 3.641 20.066 eth/phy/U0/transceiver_inst/userclk SLICE_X142Y5 FDRE r eth/phy/U0/transceiver_inst/rxdata_reg_reg[14]/C clock pessimism 0.984 21.051 clock uncertainty -0.076 20.974 SLICE_X142Y5 FDRE (Setup_EFF_SLICEM_C_D) 0.064 21.038 eth/phy/U0/transceiver_inst/rxdata_reg_reg[14] ------------------------------------------------------------------- required time 21.038 arrival time -6.699 ------------------------------------------------------------------- slack 14.339 Slack (MET) : 14.340ns (required time - arrival time) Source: eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: eth/phy/U0/transceiver_inst/rxcharisk_reg_reg[1]/D (rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_dcm Path Type: Setup (Max at Slow Process Corner) Requirement: 16.000ns (clk62_5_dcm rise@16.000ns - clk62_5_dcm rise@0.000ns) Data Path Delay: 1.685ns (logic 0.956ns (56.736%) route 0.729ns (43.264%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.050ns = ( 20.050 - 16.000 ) Source Clock Delay (SCD): 4.999ns Clock Pessimism Removal (CPR): 0.985ns Clock Uncertainty: 0.076ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.135ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.947ns (routing 2.551ns, distribution 1.396ns) Clock Net Delay (Destination): 3.625ns (routing 2.351ns, distribution 1.274ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.391 0.391 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.091 0.482 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.866 r i_refclk125_bufg/O net (fo=1, routed) 3.742 4.608 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -4.158 0.450 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.501 0.951 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.101 1.052 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 3.947 4.999 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXCTRL0[1]) 0.956 5.955 r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXCTRL0[1] net (fo=1, routed) 0.729 6.684 eth/phy/U0/transceiver_inst/rxctrl0_out[1] SLICE_X142Y3 FDRE r eth/phy/U0/transceiver_inst/rxcharisk_reg_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 16.000 16.000 r GTHE3_COMMON_X1Y0 0.000 16.000 r refclk125_p (IN) net (fo=0) 0.000 16.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.209 16.209 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.052 16.261 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 16.607 r i_refclk125_bufg/O net (fo=1, routed) 3.370 19.977 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -4.065 15.912 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.422 16.334 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.091 16.425 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 3.625 20.050 eth/phy/U0/transceiver_inst/userclk SLICE_X142Y3 FDRE r eth/phy/U0/transceiver_inst/rxcharisk_reg_reg[1]/C clock pessimism 0.985 21.035 clock uncertainty -0.076 20.959 SLICE_X142Y3 FDRE (Setup_EFF2_SLICEM_C_D) 0.065 21.024 eth/phy/U0/transceiver_inst/rxcharisk_reg_reg[1] ------------------------------------------------------------------- required time 21.024 arrival time -6.684 ------------------------------------------------------------------- slack 14.340 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.033ns (arrival time - required time) Source: eth/phy/U0/transceiver_inst/txdata_int_reg[4]/C (rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[4] (rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_dcm Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_dcm rise@0.000ns - clk62_5_dcm rise@0.000ns) Data Path Delay: 0.221ns (logic 0.048ns (21.719%) route 0.173ns (78.281%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.301ns Source Clock Delay (SCD): 1.812ns Clock Pessimism Removal (CPR): 0.473ns Clock Net Delay (Source): 1.516ns (routing 1.004ns, distribution 0.512ns) Clock Net Delay (Destination): 1.689ns (routing 1.112ns, distribution 0.577ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.160 0.160 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.018 0.178 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.278 r i_refclk125_bufg/O net (fo=1, routed) 1.452 1.730 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -1.628 0.102 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.167 0.269 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.027 0.296 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 1.516 1.812 eth/phy/U0/transceiver_inst/userclk SLICE_X141Y3 FDRE r eth/phy/U0/transceiver_inst/txdata_int_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y3 FDRE (Prop_GFF_SLICEL_C_Q) 0.048 1.860 r eth/phy/U0/transceiver_inst/txdata_int_reg[4]/Q net (fo=1, routed) 0.173 2.033 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[4] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[4] ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.248 0.248 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.035 0.283 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.413 r i_refclk125_bufg/O net (fo=1, routed) 1.653 2.066 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -1.694 0.372 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.209 0.581 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.031 0.612 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 1.689 2.301 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 clock pessimism -0.473 1.828 GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[4]) 0.172 2.000 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST ------------------------------------------------------------------- required time -2.000 arrival time 2.033 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.037ns (arrival time - required time) Source: eth/phy/U0/transceiver_inst/txdata_int_reg[9]/C (rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[9] (rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_dcm Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_dcm rise@0.000ns - clk62_5_dcm rise@0.000ns) Data Path Delay: 0.169ns (logic 0.048ns (28.402%) route 0.121ns (71.598%)) Logic Levels: 0 Clock Path Skew: -0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.301ns Source Clock Delay (SCD): 1.817ns Clock Pessimism Removal (CPR): 0.499ns Clock Net Delay (Source): 1.521ns (routing 1.004ns, distribution 0.517ns) Clock Net Delay (Destination): 1.689ns (routing 1.112ns, distribution 0.577ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.160 0.160 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.018 0.178 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.278 r i_refclk125_bufg/O net (fo=1, routed) 1.452 1.730 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -1.628 0.102 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.167 0.269 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.027 0.296 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 1.521 1.817 eth/phy/U0/transceiver_inst/userclk SLICE_X142Y1 FDRE r eth/phy/U0/transceiver_inst/txdata_int_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X142Y1 FDRE (Prop_FFF2_SLICEM_C_Q) 0.048 1.865 r eth/phy/U0/transceiver_inst/txdata_int_reg[9]/Q net (fo=1, routed) 0.121 1.986 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[9] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[9] ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.248 0.248 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.035 0.283 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.413 r i_refclk125_bufg/O net (fo=1, routed) 1.653 2.066 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -1.694 0.372 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.209 0.581 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.031 0.612 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 1.689 2.301 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 clock pessimism -0.499 1.803 GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[9]) 0.147 1.950 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST ------------------------------------------------------------------- required time -1.950 arrival time 1.986 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.045ns (arrival time - required time) Source: eth/phy/U0/transceiver_inst/txchardispmode_int_reg[0]/C (rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXCTRL1[0] (rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_dcm Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_dcm rise@0.000ns - clk62_5_dcm rise@0.000ns) Data Path Delay: 0.220ns (logic 0.049ns (22.273%) route 0.171ns (77.727%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.301ns Source Clock Delay (SCD): 1.816ns Clock Pessimism Removal (CPR): 0.473ns Clock Net Delay (Source): 1.520ns (routing 1.004ns, distribution 0.516ns) Clock Net Delay (Destination): 1.689ns (routing 1.112ns, distribution 0.577ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.160 0.160 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.018 0.178 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.278 r i_refclk125_bufg/O net (fo=1, routed) 1.452 1.730 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -1.628 0.102 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.167 0.269 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.027 0.296 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 1.520 1.816 eth/phy/U0/transceiver_inst/userclk SLICE_X141Y2 FDRE r eth/phy/U0/transceiver_inst/txchardispmode_int_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y2 FDRE (Prop_EFF_SLICEL_C_Q) 0.049 1.865 r eth/phy/U0/transceiver_inst/txchardispmode_int_reg[0]/Q net (fo=1, routed) 0.171 2.036 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txctrl1_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXCTRL1[0] ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.248 0.248 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.035 0.283 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.413 r i_refclk125_bufg/O net (fo=1, routed) 1.653 2.066 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -1.694 0.372 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.209 0.581 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.031 0.612 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 1.689 2.301 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 clock pessimism -0.473 1.828 GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Hold_GTHE3_CHANNEL_TXUSRCLK2_TXCTRL1[0]) 0.163 1.991 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST ------------------------------------------------------------------- required time -1.991 arrival time 2.036 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.047ns (arrival time - required time) Source: eth/phy/U0/transceiver_inst/txcharisk_int_reg[1]/C (rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXCTRL2[1] (rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_dcm Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_dcm rise@0.000ns - clk62_5_dcm rise@0.000ns) Data Path Delay: 0.206ns (logic 0.048ns (23.301%) route 0.158ns (76.699%)) Logic Levels: 0 Clock Path Skew: -0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.301ns Source Clock Delay (SCD): 1.817ns Clock Pessimism Removal (CPR): 0.499ns Clock Net Delay (Source): 1.521ns (routing 1.004ns, distribution 0.517ns) Clock Net Delay (Destination): 1.689ns (routing 1.112ns, distribution 0.577ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.160 0.160 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.018 0.178 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.278 r i_refclk125_bufg/O net (fo=1, routed) 1.452 1.730 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -1.628 0.102 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.167 0.269 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.027 0.296 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 1.521 1.817 eth/phy/U0/transceiver_inst/userclk SLICE_X142Y1 FDRE r eth/phy/U0/transceiver_inst/txcharisk_int_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X142Y1 FDRE (Prop_EFF2_SLICEM_C_Q) 0.048 1.865 r eth/phy/U0/transceiver_inst/txcharisk_int_reg[1]/Q net (fo=1, routed) 0.158 2.023 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txctrl2_in[1] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXCTRL2[1] ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.248 0.248 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.035 0.283 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.413 r i_refclk125_bufg/O net (fo=1, routed) 1.653 2.066 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -1.694 0.372 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.209 0.581 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.031 0.612 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 1.689 2.301 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 clock pessimism -0.499 1.803 GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Hold_GTHE3_CHANNEL_TXUSRCLK2_TXCTRL2[1]) 0.174 1.977 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST ------------------------------------------------------------------- required time -1.977 arrival time 2.023 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.047ns (arrival time - required time) Source: eth/phy/U0/transceiver_inst/txdata_int_reg[5]/C (rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[5] (rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_dcm Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_dcm rise@0.000ns - clk62_5_dcm rise@0.000ns) Data Path Delay: 0.168ns (logic 0.048ns (28.571%) route 0.120ns (71.429%)) Logic Levels: 0 Clock Path Skew: -0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.301ns Source Clock Delay (SCD): 1.816ns Clock Pessimism Removal (CPR): 0.499ns Clock Net Delay (Source): 1.520ns (routing 1.004ns, distribution 0.516ns) Clock Net Delay (Destination): 1.689ns (routing 1.112ns, distribution 0.577ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.160 0.160 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.018 0.178 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.278 r i_refclk125_bufg/O net (fo=1, routed) 1.452 1.730 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -1.628 0.102 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.167 0.269 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.027 0.296 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 1.520 1.816 eth/phy/U0/transceiver_inst/userclk SLICE_X142Y3 FDRE r eth/phy/U0/transceiver_inst/txdata_int_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X142Y3 FDRE (Prop_GFF2_SLICEM_C_Q) 0.048 1.864 r eth/phy/U0/transceiver_inst/txdata_int_reg[5]/Q net (fo=1, routed) 0.120 1.984 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[5] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[5] ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.248 0.248 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.035 0.283 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.413 r i_refclk125_bufg/O net (fo=1, routed) 1.653 2.066 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -1.694 0.372 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.209 0.581 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.031 0.612 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 1.689 2.301 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 clock pessimism -0.499 1.803 GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[5]) 0.135 1.938 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST ------------------------------------------------------------------- required time -1.938 arrival time 1.984 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.049ns (arrival time - required time) Source: eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync5/C (rising edge-triggered cell FDPE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync6/D (rising edge-triggered cell FDPE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_dcm Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_dcm rise@0.000ns - clk62_5_dcm rise@0.000ns) Data Path Delay: 0.143ns (logic 0.048ns (33.566%) route 0.095ns (66.434%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.353ns Source Clock Delay (SCD): 1.817ns Clock Pessimism Removal (CPR): 0.498ns Clock Net Delay (Source): 1.521ns (routing 1.004ns, distribution 0.517ns) Clock Net Delay (Destination): 1.741ns (routing 1.112ns, distribution 0.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.160 0.160 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.018 0.178 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.278 r i_refclk125_bufg/O net (fo=1, routed) 1.452 1.730 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -1.628 0.102 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.167 0.269 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.027 0.296 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 1.521 1.817 eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/userclk SLICE_X137Y8 FDPE r eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync5/C ------------------------------------------------------------------- ------------------- SLICE_X137Y8 FDPE (Prop_EFF2_SLICEL_C_Q) 0.048 1.865 r eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync5/Q net (fo=1, routed) 0.095 1.960 eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync_reg5 SLICE_X137Y9 FDPE r eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync6/D ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.248 0.248 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.035 0.283 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.413 r i_refclk125_bufg/O net (fo=1, routed) 1.653 2.066 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -1.694 0.372 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.209 0.581 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.031 0.612 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 1.741 2.353 eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/userclk SLICE_X137Y9 FDPE r eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync6/C clock pessimism -0.498 1.855 SLICE_X137Y9 FDPE (Hold_AFF2_SLICEL_C_D) 0.056 1.911 eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync6 ------------------------------------------------------------------- required time -1.911 arrival time 1.960 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: eth/phy/U0/transceiver_inst/txdata_int_reg[0]/C (rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[0] (rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_dcm Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_dcm rise@0.000ns - clk62_5_dcm rise@0.000ns) Data Path Delay: 0.175ns (logic 0.049ns (28.000%) route 0.126ns (72.000%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.301ns Source Clock Delay (SCD): 1.816ns Clock Pessimism Removal (CPR): 0.473ns Clock Net Delay (Source): 1.520ns (routing 1.004ns, distribution 0.516ns) Clock Net Delay (Destination): 1.689ns (routing 1.112ns, distribution 0.577ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.160 0.160 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.018 0.178 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.278 r i_refclk125_bufg/O net (fo=1, routed) 1.452 1.730 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -1.628 0.102 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.167 0.269 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.027 0.296 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 1.520 1.816 eth/phy/U0/transceiver_inst/userclk SLICE_X141Y2 FDRE r eth/phy/U0/transceiver_inst/txdata_int_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y2 FDRE (Prop_FFF_SLICEL_C_Q) 0.049 1.865 r eth/phy/U0/transceiver_inst/txdata_int_reg[0]/Q net (fo=1, routed) 0.126 1.991 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[0] ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.248 0.248 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.035 0.283 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.413 r i_refclk125_bufg/O net (fo=1, routed) 1.653 2.066 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -1.694 0.372 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.209 0.581 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.031 0.612 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 1.689 2.301 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 clock pessimism -0.473 1.828 GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[0]) 0.113 1.941 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST ------------------------------------------------------------------- required time -1.941 arrival time 1.991 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.055ns (arrival time - required time) Source: eth/phy/U0/transceiver_inst/txchardispval_int_reg[0]/C (rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXCTRL0[0] (rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_dcm Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_dcm rise@0.000ns - clk62_5_dcm rise@0.000ns) Data Path Delay: 0.222ns (logic 0.048ns (21.622%) route 0.174ns (78.378%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.301ns Source Clock Delay (SCD): 1.812ns Clock Pessimism Removal (CPR): 0.473ns Clock Net Delay (Source): 1.516ns (routing 1.004ns, distribution 0.512ns) Clock Net Delay (Destination): 1.689ns (routing 1.112ns, distribution 0.577ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.160 0.160 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.018 0.178 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.278 r i_refclk125_bufg/O net (fo=1, routed) 1.452 1.730 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -1.628 0.102 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.167 0.269 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.027 0.296 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 1.516 1.812 eth/phy/U0/transceiver_inst/userclk SLICE_X141Y3 FDRE r eth/phy/U0/transceiver_inst/txchardispval_int_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y3 FDRE (Prop_EFF2_SLICEL_C_Q) 0.048 1.860 r eth/phy/U0/transceiver_inst/txchardispval_int_reg[0]/Q net (fo=1, routed) 0.174 2.034 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txctrl0_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXCTRL0[0] ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.248 0.248 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.035 0.283 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.413 r i_refclk125_bufg/O net (fo=1, routed) 1.653 2.066 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -1.694 0.372 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.209 0.581 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.031 0.612 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 1.689 2.301 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 clock pessimism -0.473 1.828 GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Hold_GTHE3_CHANNEL_TXUSRCLK2_TXCTRL0[0]) 0.151 1.979 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST ------------------------------------------------------------------- required time -1.979 arrival time 2.034 ------------------------------------------------------------------- slack 0.055 Slack (MET) : 0.057ns (arrival time - required time) Source: eth/phy/U0/transceiver_inst/txdata_int_reg[2]/C (rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[2] (rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_dcm Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_dcm rise@0.000ns - clk62_5_dcm rise@0.000ns) Data Path Delay: 0.216ns (logic 0.048ns (22.222%) route 0.168ns (77.778%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.301ns Source Clock Delay (SCD): 1.816ns Clock Pessimism Removal (CPR): 0.473ns Clock Net Delay (Source): 1.520ns (routing 1.004ns, distribution 0.516ns) Clock Net Delay (Destination): 1.689ns (routing 1.112ns, distribution 0.577ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.160 0.160 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.018 0.178 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.278 r i_refclk125_bufg/O net (fo=1, routed) 1.452 1.730 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -1.628 0.102 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.167 0.269 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.027 0.296 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 1.520 1.816 eth/phy/U0/transceiver_inst/userclk SLICE_X141Y2 FDRE r eth/phy/U0/transceiver_inst/txdata_int_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y2 FDRE (Prop_HFF_SLICEL_C_Q) 0.048 1.864 r eth/phy/U0/transceiver_inst/txdata_int_reg[2]/Q net (fo=1, routed) 0.168 2.032 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[2] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[2] ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.248 0.248 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.035 0.283 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.413 r i_refclk125_bufg/O net (fo=1, routed) 1.653 2.066 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -1.694 0.372 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.209 0.581 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.031 0.612 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 1.689 2.301 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 clock pessimism -0.473 1.828 GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[2]) 0.147 1.975 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST ------------------------------------------------------------------- required time -1.975 arrival time 2.032 ------------------------------------------------------------------- slack 0.057 Slack (MET) : 0.058ns (arrival time - required time) Source: eth/phy/U0/transceiver_inst/txdata_int_reg[10]/C (rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[10] (rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_dcm Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_dcm rise@0.000ns - clk62_5_dcm rise@0.000ns) Data Path Delay: 0.213ns (logic 0.048ns (22.535%) route 0.165ns (77.465%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.301ns Source Clock Delay (SCD): 1.812ns Clock Pessimism Removal (CPR): 0.473ns Clock Net Delay (Source): 1.516ns (routing 1.004ns, distribution 0.512ns) Clock Net Delay (Destination): 1.689ns (routing 1.112ns, distribution 0.577ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.160 0.160 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.018 0.178 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.278 r i_refclk125_bufg/O net (fo=1, routed) 1.452 1.730 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -1.628 0.102 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.167 0.269 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.027 0.296 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 1.516 1.812 eth/phy/U0/transceiver_inst/userclk SLICE_X141Y3 FDRE r eth/phy/U0/transceiver_inst/txdata_int_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y3 FDRE (Prop_FFF2_SLICEL_C_Q) 0.048 1.860 r eth/phy/U0/transceiver_inst/txdata_int_reg[10]/Q net (fo=1, routed) 0.165 2.025 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[10] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[10] ------------------------------------------------------------------- ------------------- (clock clk62_5_dcm rise edge) 0.000 0.000 r GTHE3_COMMON_X1Y0 0.000 0.000 r refclk125_p (IN) net (fo=0) 0.000 0.000 refclk125_p GTHE3_COMMON_X1Y0 IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2) 0.248 0.248 r i_refclk125_ibuf/ODIV2 net (fo=2, routed) 0.035 0.283 refclk125_o BUFG_GT_X1Y0 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.413 r i_refclk125_bufg/O net (fo=1, routed) 1.653 2.066 CLKIN1 MMCME3_ADV_X1Y4 MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1) -1.694 0.372 r i_clk125_MMCM/CLKOUT1 net (fo=1, routed) 0.209 0.581 clk62_5_dcm BUFGCE_X1Y98 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.031 0.612 r i_clk62_5_bufg/O X5Y0 (CLOCK_ROOT) net (fo=69, routed) 1.689 2.301 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 clock pessimism -0.473 1.828 GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[10]) 0.139 1.967 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST ------------------------------------------------------------------- required time -1.967 arrival time 2.025 ------------------------------------------------------------------- slack 0.058 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk62_5_dcm Waveform(ns): { 0.000 8.000 } Period(ns): 16.000 Sources: { i_clk125_MMCM/CLKOUT1 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 16.000 12.800 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 16.000 12.800 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a GTHE3_CHANNEL/TXUSRCLK n/a 3.200 16.000 12.800 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Min Period n/a GTHE3_CHANNEL/TXUSRCLK2 n/a 3.200 16.000 12.800 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 Min Period n/a BUFGCE/I n/a 1.587 16.000 14.413 BUFGCE_X1Y98 i_clk62_5_bufg/I Min Period n/a MMCME3_ADV/CLKOUT1 n/a 1.250 16.000 14.750 MMCME3_ADV_X1Y4 i_clk125_MMCM/CLKOUT1 Min Period n/a FDPE/C n/a 0.550 16.000 15.450 SLICE_X137Y8 eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync1/C Min Period n/a FDPE/C n/a 0.550 16.000 15.450 SLICE_X137Y8 eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync2/C Min Period n/a FDPE/C n/a 0.550 16.000 15.450 SLICE_X137Y8 eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync3/C Min Period n/a FDPE/C n/a 0.550 16.000 15.450 SLICE_X137Y8 eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync4/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 8.000 6.560 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 8.000 6.560 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/TXUSRCLK n/a 1.440 8.000 6.560 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/TXUSRCLK2 n/a 1.440 8.000 6.560 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/TXUSRCLK n/a 1.440 8.000 6.560 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/TXUSRCLK2 n/a 1.440 8.000 6.560 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 8.000 6.560 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 8.000 6.560 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDPE/C n/a 0.275 8.000 7.725 SLICE_X137Y8 eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync1/C Low Pulse Width Slow FDPE/C n/a 0.275 8.000 7.725 SLICE_X137Y8 eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync2/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 8.000 6.560 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 8.000 6.560 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 8.000 6.560 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 8.000 6.560 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow GTHE3_CHANNEL/TXUSRCLK n/a 1.440 8.000 6.560 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/TXUSRCLK n/a 1.440 8.000 6.560 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/TXUSRCLK2 n/a 1.440 8.000 6.560 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/TXUSRCLK2 n/a 1.440 8.000 6.560 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 High Pulse Width Slow FDPE/C n/a 0.275 8.000 7.725 SLICE_X137Y9 eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync6/C High Pulse Width Slow FDCE/C n/a 0.275 8.000 7.725 SLICE_X140Y10 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.021 0.499 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.613 0.045 0.568 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Slow GTHE3_CHANNEL/TXUSRCLK2 GTHE3_CHANNEL/TXUSRCLK 0.864 0.045 0.819 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Fast GTHE3_CHANNEL/TXUSRCLK2 GTHE3_CHANNEL/TXUSRCLK 0.914 0.021 0.893 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y0 eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: ipb_clk_dcm To Clock: ipb_clk_dcm Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 30.413ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ipb_clk_dcm Waveform(ns): { 0.000 16.000 } Period(ns): 32.000 Sources: { i_clk125_MMCM/CLKOUT2 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFGCE/I n/a 1.587 32.000 30.413 BUFGCE_X1Y106 i_ipb_clk_bufg/I Min Period n/a MMCME3_ADV/CLKOUT2 n/a 1.250 32.000 30.750 MMCME3_ADV_X1Y4 i_clk125_MMCM/CLKOUT2 --------------------------------------------------------------------------------------------------- From Clock: tx_wordclk To Clock: tx_wordclk Setup : 0 Failing Endpoints, Worst Slack 0.181ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.030ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.495ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.181ns (required time - arrival time) Source: fabric_clk_div2_q_reg[3]__0/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: TX_CLKEN_reg_replica_2/D (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 7.904ns (logic 0.365ns (4.618%) route 7.539ns (95.382%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.199ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.482ns = ( 11.799 - 8.317 ) Source Clock Delay (SCD): 3.366ns Clock Pessimism Removal (CPR): 0.083ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.387ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.482ns Common Clock Delay (CCD): 0.903ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.366ns (routing 0.986ns, distribution 2.380ns) Clock Net Delay (Destination): 3.482ns (routing 0.903ns, distribution 2.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.366 3.366 tx_wordclk SLICE_X62Y242 FDRE r fabric_clk_div2_q_reg[3]__0/C ------------------------------------------------------------------- ------------------- SLICE_X62Y242 FDRE (Prop_AFF_SLICEM_C_Q) 0.140 3.506 r fabric_clk_div2_q_reg[3]__0/Q net (fo=64, routed) 7.504 11.010 fabric_clk_div2_q[3] SLR Crossing[0->1] SLICE_X10Y420 LUT2 (Prop_D6LUT_SLICEM_I0_O) 0.225 11.235 r TX_CLKEN_i_1_replica_2/O net (fo=1, routed) 0.035 11.270 TX_CLKEN_i_1_n_0_repN_2 SLICE_X10Y420 FDRE r TX_CLKEN_reg_replica_2/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.482 11.799 tx_wordclk SLR Crossing[0->1] SLICE_X10Y420 FDRE r TX_CLKEN_reg_replica_2/C clock pessimism 0.083 11.882 inter-SLR compensation -0.387 11.495 clock uncertainty -0.107 11.388 SLICE_X10Y420 FDRE (Setup_DFF_SLICEM_C_D) 0.063 11.451 TX_CLKEN_reg_replica_2 ------------------------------------------------------------------- required time 11.451 arrival time -11.270 ------------------------------------------------------------------- slack 0.181 Slack (MET) : 0.184ns (required time - arrival time) Source: fabric_clk_div2_q_reg[3]__0/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: TX_CLKEN_reg_replica_3/D (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 7.901ns (logic 0.364ns (4.607%) route 7.537ns (95.393%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.199ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.482ns = ( 11.799 - 8.317 ) Source Clock Delay (SCD): 3.366ns Clock Pessimism Removal (CPR): 0.083ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.387ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.482ns Common Clock Delay (CCD): 0.903ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.366ns (routing 0.986ns, distribution 2.380ns) Clock Net Delay (Destination): 3.482ns (routing 0.903ns, distribution 2.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.366 3.366 tx_wordclk SLICE_X62Y242 FDRE r fabric_clk_div2_q_reg[3]__0/C ------------------------------------------------------------------- ------------------- SLICE_X62Y242 FDRE (Prop_AFF_SLICEM_C_Q) 0.140 3.506 r fabric_clk_div2_q_reg[3]__0/Q net (fo=64, routed) 7.499 11.005 fabric_clk_div2_q[3] SLR Crossing[0->1] SLICE_X10Y420 LUT2 (Prop_C6LUT_SLICEM_I0_O) 0.224 11.229 r TX_CLKEN_i_1_replica_3/O net (fo=1, routed) 0.038 11.267 TX_CLKEN_i_1_n_0_repN_3 SLICE_X10Y420 FDRE r TX_CLKEN_reg_replica_3/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.482 11.799 tx_wordclk SLR Crossing[0->1] SLICE_X10Y420 FDRE r TX_CLKEN_reg_replica_3/C clock pessimism 0.083 11.882 inter-SLR compensation -0.387 11.495 clock uncertainty -0.107 11.388 SLICE_X10Y420 FDRE (Setup_CFF_SLICEM_C_D) 0.063 11.451 TX_CLKEN_reg_replica_3 ------------------------------------------------------------------- required time 11.451 arrival time -11.267 ------------------------------------------------------------------- slack 0.184 Slack (MET) : 0.217ns (required time - arrival time) Source: fabric_clk_div2_q_reg[3]__0/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: TX_CLKEN_reg_replica_7/D (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 7.867ns (logic 0.232ns (2.949%) route 7.635ns (97.051%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.199ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.482ns = ( 11.799 - 8.317 ) Source Clock Delay (SCD): 3.366ns Clock Pessimism Removal (CPR): 0.083ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.387ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.482ns Common Clock Delay (CCD): 0.903ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.366ns (routing 0.986ns, distribution 2.380ns) Clock Net Delay (Destination): 3.482ns (routing 0.903ns, distribution 2.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.366 3.366 tx_wordclk SLICE_X62Y242 FDRE r fabric_clk_div2_q_reg[3]__0/C ------------------------------------------------------------------- ------------------- SLICE_X62Y242 FDRE (Prop_AFF_SLICEM_C_Q) 0.140 3.506 r fabric_clk_div2_q_reg[3]__0/Q net (fo=64, routed) 7.601 11.107 fabric_clk_div2_q[3] SLR Crossing[0->1] SLICE_X10Y420 LUT2 (Prop_B6LUT_SLICEM_I0_O) 0.092 11.199 r TX_CLKEN_i_1_replica_7/O net (fo=1, routed) 0.034 11.233 TX_CLKEN_i_1_n_0_repN_7 SLICE_X10Y420 FDRE r TX_CLKEN_reg_replica_7/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.482 11.799 tx_wordclk SLR Crossing[0->1] SLICE_X10Y420 FDRE r TX_CLKEN_reg_replica_7/C clock pessimism 0.083 11.882 inter-SLR compensation -0.387 11.495 clock uncertainty -0.107 11.388 SLICE_X10Y420 FDRE (Setup_BFF_SLICEM_C_D) 0.062 11.450 TX_CLKEN_reg_replica_7 ------------------------------------------------------------------- required time 11.450 arrival time -11.233 ------------------------------------------------------------------- slack 0.217 Slack (MET) : 0.295ns (required time - arrival time) Source: fabric_clk_div2_q_reg[4]/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: TX_CLKEN_reg_replica_41/D (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 7.474ns (logic 0.358ns (4.790%) route 7.116ns (95.210%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.504ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.893ns = ( 11.210 - 8.317 ) Source Clock Delay (SCD): 3.480ns Clock Pessimism Removal (CPR): 0.083ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.480ns (routing 0.986ns, distribution 2.494ns) Clock Net Delay (Destination): 2.893ns (routing 0.903ns, distribution 1.990ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.480 3.480 tx_wordclk SLICE_X78Y249 FDRE r fabric_clk_div2_q_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y249 FDRE (Prop_EFF_SLICEL_C_Q) 0.139 3.619 r fabric_clk_div2_q_reg[4]/Q net (fo=63, routed) 7.079 10.698 fabric_clk_div2_q[4] SLICE_X63Y129 LUT2 (Prop_C6LUT_SLICEL_I1_O) 0.219 10.917 r TX_CLKEN_i_1_replica_41/O net (fo=1, routed) 0.037 10.954 TX_CLKEN_i_1_n_0_repN_41 SLICE_X63Y129 FDRE r TX_CLKEN_reg_replica_41/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 2.893 11.210 tx_wordclk SLICE_X63Y129 FDRE r TX_CLKEN_reg_replica_41/C clock pessimism 0.083 11.293 clock uncertainty -0.107 11.186 SLICE_X63Y129 FDRE (Setup_CFF_SLICEL_C_D) 0.063 11.249 TX_CLKEN_reg_replica_41 ------------------------------------------------------------------- required time 11.249 arrival time -10.954 ------------------------------------------------------------------- slack 0.295 Slack (MET) : 0.373ns (required time - arrival time) Source: fabric_clk_div2_q_reg[3]__0/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: TX_CLKEN_reg_replica_18/D (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 7.960ns (logic 0.286ns (3.593%) route 7.674ns (96.407%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.342ns = ( 11.659 - 8.317 ) Source Clock Delay (SCD): 3.366ns Clock Pessimism Removal (CPR): 0.083ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.366ns (routing 0.986ns, distribution 2.380ns) Clock Net Delay (Destination): 3.342ns (routing 0.903ns, distribution 2.439ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.366 3.366 tx_wordclk SLICE_X62Y242 FDRE r fabric_clk_div2_q_reg[3]__0/C ------------------------------------------------------------------- ------------------- SLICE_X62Y242 FDRE (Prop_AFF_SLICEM_C_Q) 0.140 3.506 r fabric_clk_div2_q_reg[3]__0/Q net (fo=64, routed) 7.640 11.146 fabric_clk_div2_q[3] SLICE_X101Y36 LUT2 (Prop_G6LUT_SLICEM_I0_O) 0.146 11.292 r TX_CLKEN_i_1_replica_18/O net (fo=1, routed) 0.034 11.326 TX_CLKEN_i_1_n_0_repN_18 SLICE_X101Y36 FDRE r TX_CLKEN_reg_replica_18/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.342 11.659 tx_wordclk SLICE_X101Y36 FDRE r TX_CLKEN_reg_replica_18/C clock pessimism 0.083 11.742 clock uncertainty -0.107 11.635 SLICE_X101Y36 FDRE (Setup_GFF_SLICEM_C_D) 0.064 11.699 TX_CLKEN_reg_replica_18 ------------------------------------------------------------------- required time 11.699 arrival time -11.326 ------------------------------------------------------------------- slack 0.373 Slack (MET) : 0.382ns (required time - arrival time) Source: fabric_clk_div2_q_reg[4]/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: TX_CLKEN_reg_replica_22/D (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 7.389ns (logic 0.231ns (3.126%) route 7.158ns (96.874%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.502ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.895ns = ( 11.212 - 8.317 ) Source Clock Delay (SCD): 3.480ns Clock Pessimism Removal (CPR): 0.083ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.480ns (routing 0.986ns, distribution 2.494ns) Clock Net Delay (Destination): 2.895ns (routing 0.903ns, distribution 1.992ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.480 3.480 tx_wordclk SLICE_X78Y249 FDRE r fabric_clk_div2_q_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y249 FDRE (Prop_EFF_SLICEL_C_Q) 0.139 3.619 r fabric_clk_div2_q_reg[4]/Q net (fo=63, routed) 7.123 10.742 fabric_clk_div2_q[4] SLICE_X64Y36 LUT2 (Prop_D6LUT_SLICEM_I1_O) 0.092 10.834 r TX_CLKEN_i_1_replica_22/O net (fo=1, routed) 0.035 10.869 TX_CLKEN_i_1_n_0_repN_22 SLICE_X64Y36 FDRE r TX_CLKEN_reg_replica_22/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 2.895 11.212 tx_wordclk SLICE_X64Y36 FDRE r TX_CLKEN_reg_replica_22/C clock pessimism 0.083 11.295 clock uncertainty -0.107 11.188 SLICE_X64Y36 FDRE (Setup_DFF_SLICEM_C_D) 0.063 11.251 TX_CLKEN_reg_replica_22 ------------------------------------------------------------------- required time 11.251 arrival time -10.869 ------------------------------------------------------------------- slack 0.382 Slack (MET) : 0.401ns (required time - arrival time) Source: fabric_clk_div2_q_reg[4]/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: TX_CLKEN_reg_replica_24/D (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 7.420ns (logic 0.192ns (2.588%) route 7.228ns (97.412%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.452ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.945ns = ( 11.262 - 8.317 ) Source Clock Delay (SCD): 3.480ns Clock Pessimism Removal (CPR): 0.083ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.480ns (routing 0.986ns, distribution 2.494ns) Clock Net Delay (Destination): 2.945ns (routing 0.903ns, distribution 2.042ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.480 3.480 tx_wordclk SLICE_X78Y249 FDRE r fabric_clk_div2_q_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y249 FDRE (Prop_EFF_SLICEL_C_Q) 0.139 3.619 r fabric_clk_div2_q_reg[4]/Q net (fo=63, routed) 7.193 10.812 fabric_clk_div2_q[4] SLICE_X60Y60 LUT2 (Prop_D6LUT_SLICEL_I1_O) 0.053 10.865 r TX_CLKEN_i_1_replica_24/O net (fo=1, routed) 0.035 10.900 TX_CLKEN_i_1_n_0_repN_24 SLICE_X60Y60 FDRE r TX_CLKEN_reg_replica_24/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 2.945 11.262 tx_wordclk SLICE_X60Y60 FDRE r TX_CLKEN_reg_replica_24/C clock pessimism 0.083 11.345 clock uncertainty -0.107 11.238 SLICE_X60Y60 FDRE (Setup_DFF_SLICEL_C_D) 0.063 11.301 TX_CLKEN_reg_replica_24 ------------------------------------------------------------------- required time 11.301 arrival time -10.900 ------------------------------------------------------------------- slack 0.401 Slack (MET) : 0.406ns (required time - arrival time) Source: fabric_clk_div2_q_reg[3]__0/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: TX_CLKEN_reg_replica_16/D (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 8.178ns (logic 0.311ns (3.803%) route 7.867ns (96.197%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.311ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.594ns = ( 11.911 - 8.317 ) Source Clock Delay (SCD): 3.366ns Clock Pessimism Removal (CPR): 0.083ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.366ns (routing 0.986ns, distribution 2.380ns) Clock Net Delay (Destination): 3.594ns (routing 0.903ns, distribution 2.691ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.366 3.366 tx_wordclk SLICE_X62Y242 FDRE r fabric_clk_div2_q_reg[3]__0/C ------------------------------------------------------------------- ------------------- SLICE_X62Y242 FDRE (Prop_AFF_SLICEM_C_Q) 0.140 3.506 r fabric_clk_div2_q_reg[3]__0/Q net (fo=64, routed) 7.832 11.338 fabric_clk_div2_q[3] SLICE_X136Y121 LUT2 (Prop_D6LUT_SLICEM_I0_O) 0.171 11.509 r TX_CLKEN_i_1_replica_16/O net (fo=1, routed) 0.035 11.544 TX_CLKEN_i_1_n_0_repN_16 SLICE_X136Y121 FDRE r TX_CLKEN_reg_replica_16/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.594 11.911 tx_wordclk SLICE_X136Y121 FDRE r TX_CLKEN_reg_replica_16/C clock pessimism 0.083 11.994 clock uncertainty -0.107 11.887 SLICE_X136Y121 FDRE (Setup_DFF_SLICEM_C_D) 0.063 11.950 TX_CLKEN_reg_replica_16 ------------------------------------------------------------------- required time 11.950 arrival time -11.544 ------------------------------------------------------------------- slack 0.406 Slack (MET) : 0.453ns (required time - arrival time) Source: fabric_clk_div2_q_reg[4]/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: TX_CLKEN_reg_replica/D (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 7.403ns (logic 0.376ns (5.079%) route 7.027ns (94.921%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.049ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.348ns = ( 11.665 - 8.317 ) Source Clock Delay (SCD): 3.480ns Clock Pessimism Removal (CPR): 0.083ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.367ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.348ns Common Clock Delay (CCD): 0.903ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.480ns (routing 0.986ns, distribution 2.494ns) Clock Net Delay (Destination): 3.348ns (routing 0.903ns, distribution 2.445ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.480 3.480 tx_wordclk SLICE_X78Y249 FDRE r fabric_clk_div2_q_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y249 FDRE (Prop_EFF_SLICEL_C_Q) 0.139 3.619 r fabric_clk_div2_q_reg[4]/Q net (fo=63, routed) 6.994 10.613 fabric_clk_div2_q[4] SLR Crossing[0->1] SLICE_X24Y452 LUT2 (Prop_B6LUT_SLICEL_I1_O) 0.237 10.850 r TX_CLKEN_i_1_replica/O net (fo=1, routed) 0.033 10.883 TX_CLKEN_i_1_n_0_repN SLICE_X24Y452 FDRE r TX_CLKEN_reg_replica/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.348 11.665 tx_wordclk SLR Crossing[0->1] SLICE_X24Y452 FDRE r TX_CLKEN_reg_replica/C clock pessimism 0.083 11.748 inter-SLR compensation -0.367 11.381 clock uncertainty -0.107 11.274 SLICE_X24Y452 FDRE (Setup_BFF_SLICEL_C_D) 0.062 11.336 TX_CLKEN_reg_replica ------------------------------------------------------------------- required time 11.336 arrival time -10.883 ------------------------------------------------------------------- slack 0.453 Slack (MET) : 0.528ns (required time - arrival time) Source: fabric_clk_div2_q_reg[3]__0/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: TX_CLKEN_reg_replica_21/D (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 7.858ns (logic 0.313ns (3.983%) route 7.545ns (96.017%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.396ns = ( 11.713 - 8.317 ) Source Clock Delay (SCD): 3.366ns Clock Pessimism Removal (CPR): 0.083ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.366ns (routing 0.986ns, distribution 2.380ns) Clock Net Delay (Destination): 3.396ns (routing 0.903ns, distribution 2.493ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.366 3.366 tx_wordclk SLICE_X62Y242 FDRE r fabric_clk_div2_q_reg[3]__0/C ------------------------------------------------------------------- ------------------- SLICE_X62Y242 FDRE (Prop_AFF_SLICEM_C_Q) 0.140 3.506 r fabric_clk_div2_q_reg[3]__0/Q net (fo=64, routed) 7.510 11.016 fabric_clk_div2_q[3] SLICE_X107Y66 LUT2 (Prop_H6LUT_SLICEM_I0_O) 0.173 11.189 r TX_CLKEN_i_1_replica_21/O net (fo=1, routed) 0.035 11.224 TX_CLKEN_i_1_n_0_repN_21 SLICE_X107Y66 FDRE r TX_CLKEN_reg_replica_21/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.396 11.713 tx_wordclk SLICE_X107Y66 FDRE r TX_CLKEN_reg_replica_21/C clock pessimism 0.083 11.796 clock uncertainty -0.107 11.689 SLICE_X107Y66 FDRE (Setup_HFF_SLICEM_C_D) 0.063 11.752 TX_CLKEN_reg_replica_21 ------------------------------------------------------------------- required time 11.752 arrival time -11.224 ------------------------------------------------------------------- slack 0.528 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.030ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[9]/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[7]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.171ns (logic 0.079ns (46.199%) route 0.092ns (53.801%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.655ns Source Clock Delay (SCD): 1.416ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 1.416ns (routing 0.373ns, distribution 1.043ns) Clock Net Delay (Destination): 1.655ns (routing 0.411ns, distribution 1.244ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.416 1.416 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk SLICE_X133Y221 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y221 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.465 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[9]/Q net (fo=11, routed) 0.080 1.545 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/Q[9] SLICE_X135Y221 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.030 1.575 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister[7]_i_1__186/O net (fo=1, routed) 0.012 1.587 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/p_41_out[7] SLICE_X135Y221 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[7]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.655 1.655 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk SLICE_X135Y221 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[7]/C clock pessimism -0.154 1.501 SLICE_X135Y221 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.557 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[7] ------------------------------------------------------------------- required time -1.557 arrival time 1.587 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[0]/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[16]/D (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.256ns (logic 0.210ns (82.031%) route 0.046ns (17.969%)) Logic Levels: 4 (CARRY8=3 LUT1=1) Clock Path Skew: 0.170ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.722ns Source Clock Delay (SCD): 1.486ns Clock Pessimism Removal (CPR): 0.066ns Clock Net Delay (Source): 1.486ns (routing 0.373ns, distribution 1.113ns) Clock Net Delay (Destination): 1.722ns (routing 0.411ns, distribution 1.311ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.486 1.486 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/tx_wordclk SLR Crossing[0->1] SLICE_X8Y538 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X8Y538 FDRE (Prop_AFF_SLICEL_C_Q) 0.049 1.535 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[0]/Q net (fo=2, routed) 0.035 1.570 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[0] SLICE_X8Y538 LUT1 (Prop_A6LUT_SLICEL_I0_O) 0.015 1.585 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc[0]_i_3__43/O net (fo=1, routed) 0.001 1.586 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc[0]_i_3__43_n_0 SLICE_X8Y538 CARRY8 (Prop_CARRY8_SLICEL_S[0]_CO[7]) 0.096 1.682 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[0]_i_2__43/CO[7] net (fo=1, routed) 0.000 1.682 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[0]_i_2__43_n_0 SLICE_X8Y539 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) 0.016 1.698 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[8]_i_1__43/CO[7] net (fo=1, routed) 0.000 1.698 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[8]_i_1__43_n_0 SLICE_X8Y540 CARRY8 (Prop_CARRY8_SLICEL_CI_O[0]) 0.034 1.732 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[16]_i_1__43/O[0] net (fo=1, routed) 0.010 1.742 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[16]_i_1__43_n_15 SLICE_X8Y540 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[16]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.722 1.722 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/tx_wordclk SLR Crossing[0->1] SLICE_X8Y540 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[16]/C clock pessimism -0.066 1.656 SLICE_X8Y540 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.712 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[16] ------------------------------------------------------------------- required time -1.712 arrival time 1.742 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[9]/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[24]/D (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.247ns (logic 0.189ns (76.518%) route 0.058ns (23.482%)) Logic Levels: 3 (CARRY8=3) Clock Path Skew: 0.161ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.738ns Source Clock Delay (SCD): 1.520ns Clock Pessimism Removal (CPR): 0.057ns Clock Net Delay (Source): 1.520ns (routing 0.373ns, distribution 1.147ns) Clock Net Delay (Destination): 1.738ns (routing 0.411ns, distribution 1.327ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.520 1.520 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/tx_wordclk SLR Crossing[0->1] SLICE_X138Y478 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X138Y478 FDRE (Prop_BFF_SLICEL_C_Q) 0.049 1.569 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[9]/Q net (fo=1, routed) 0.048 1.617 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg_n_0_[9] SLICE_X138Y478 CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[7]) 0.090 1.707 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[8]_i_1__15/CO[7] net (fo=1, routed) 0.000 1.707 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[8]_i_1__15_n_0 SLICE_X138Y479 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) 0.016 1.723 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[16]_i_1__15/CO[7] net (fo=1, routed) 0.000 1.723 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[16]_i_1__15_n_0 SLICE_X138Y480 CARRY8 (Prop_CARRY8_SLICEL_CI_O[0]) 0.034 1.757 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[24]_i_1__15/O[0] net (fo=1, routed) 0.010 1.767 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[24]_i_1__15_n_15 SLICE_X138Y480 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[24]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.738 1.738 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/tx_wordclk SLR Crossing[0->1] SLICE_X138Y480 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[24]/C clock pessimism -0.057 1.681 SLICE_X138Y480 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.737 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[24] ------------------------------------------------------------------- required time -1.737 arrival time 1.767 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[0]/C (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[19]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.160ns (logic 0.064ns (40.000%) route 0.096ns (60.000%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.742ns Source Clock Delay (SCD): 1.502ns Clock Pessimism Removal (CPR): 0.166ns Clock Net Delay (Source): 1.502ns (routing 0.373ns, distribution 1.129ns) Clock Net Delay (Destination): 1.742ns (routing 0.411ns, distribution 1.331ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.502 1.502 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X134Y366 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X134Y366 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 1.551 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[0]/Q net (fo=14, routed) 0.080 1.631 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/Q[0] SLICE_X136Y366 LUT5 (Prop_C6LUT_SLICEM_I3_O) 0.015 1.646 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[19]_i_1__149/O net (fo=1, routed) 0.016 1.662 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/p_41_out[19] SLICE_X136Y366 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[19]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.742 1.742 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X136Y366 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[19]/C clock pessimism -0.166 1.576 SLICE_X136Y366 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.632 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[19] ------------------------------------------------------------------- required time -1.632 arrival time 1.662 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[28]/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_o_reg[28]/D (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.154ns (logic 0.049ns (31.818%) route 0.105ns (68.182%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.701ns Source Clock Delay (SCD): 1.476ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.476ns (routing 0.373ns, distribution 1.103ns) Clock Net Delay (Destination): 1.701ns (routing 0.411ns, distribution 1.290ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.476 1.476 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/tx_wordclk SLICE_X141Y143 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[28]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y143 FDRE (Prop_EFF_SLICEL_C_Q) 0.049 1.525 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[28]/Q net (fo=2, routed) 0.105 1.630 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[28] SLICE_X142Y143 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_o_reg[28]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.701 1.701 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/tx_wordclk SLICE_X142Y143 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_o_reg[28]/C clock pessimism -0.157 1.544 SLICE_X142Y143 FDRE (Hold_GFF_SLICEM_C_D) 0.056 1.600 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_o_reg[28] ------------------------------------------------------------------- required time -1.600 arrival time 1.630 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.031ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[18]/D (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.215ns (logic 0.119ns (55.349%) route 0.096ns (44.651%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.128ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.420ns Source Clock Delay (SCD): 1.229ns Clock Pessimism Removal (CPR): 0.063ns Clock Net Delay (Source): 1.229ns (routing 0.373ns, distribution 0.856ns) Clock Net Delay (Destination): 1.420ns (routing 0.411ns, distribution 1.009ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.229 1.229 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk SLICE_X54Y59 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y59 FDCE (Prop_CFF2_SLICEL_C_Q) 0.048 1.277 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]/Q net (fo=13, routed) 0.084 1.361 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/Q[20] SLICE_X54Y61 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.071 1.432 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[18]_i_1__76/O net (fo=1, routed) 0.012 1.444 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[18] SLICE_X54Y61 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[18]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.420 1.420 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk SLICE_X54Y61 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.063 1.357 SLICE_X54Y61 FDPE (Hold_AFF_SLICEL_C_D) 0.056 1.413 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -1.413 arrival time 1.444 ------------------------------------------------------------------- slack 0.031 Slack (MET) : 0.031ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[1]/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[8]/D (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.235ns (logic 0.177ns (75.319%) route 0.058ns (24.681%)) Logic Levels: 2 (CARRY8=2) Clock Path Skew: 0.148ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.713ns Source Clock Delay (SCD): 1.502ns Clock Pessimism Removal (CPR): 0.063ns Clock Net Delay (Source): 1.502ns (routing 0.373ns, distribution 1.129ns) Clock Net Delay (Destination): 1.713ns (routing 0.411ns, distribution 1.302ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.502 1.502 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/tx_wordclk SLICE_X138Y59 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X138Y59 FDRE (Prop_BFF_SLICEL_C_Q) 0.049 1.551 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[1]/Q net (fo=1, routed) 0.048 1.599 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg_n_0_[1] SLICE_X138Y59 CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[7]) 0.094 1.693 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[0]_i_1/CO[7] net (fo=1, routed) 0.000 1.693 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[0]_i_1_n_0 SLICE_X138Y60 CARRY8 (Prop_CARRY8_SLICEL_CI_O[0]) 0.034 1.727 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[8]_i_1/O[0] net (fo=1, routed) 0.010 1.737 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[8]_i_1_n_15 SLICE_X138Y60 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[8]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.713 1.713 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/tx_wordclk SLICE_X138Y60 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[8]/C clock pessimism -0.063 1.650 SLICE_X138Y60 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.706 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[8] ------------------------------------------------------------------- required time -1.706 arrival time 1.737 ------------------------------------------------------------------- slack 0.031 Slack (MET) : 0.031ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/gen_drp_interface.phase_acc_reg[1]/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPDI[1] (rising edge-triggered cell GTHE3_CHANNEL clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.214ns (logic 0.049ns (22.897%) route 0.165ns (77.103%)) Logic Levels: 0 Clock Path Skew: 0.148ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.717ns Source Clock Delay (SCD): 1.503ns Clock Pessimism Removal (CPR): 0.066ns Clock Net Delay (Source): 1.503ns (routing 0.373ns, distribution 1.130ns) Clock Net Delay (Destination): 1.717ns (routing 0.411ns, distribution 1.306ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.503 1.503 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/tx_wordclk SLR Crossing[0->1] SLICE_X141Y539 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/gen_drp_interface.phase_acc_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y539 FDRE (Prop_BFF_SLICEL_C_Q) 0.049 1.552 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/gen_drp_interface.phase_acc_reg[1]/Q net (fo=9, routed) 0.165 1.717 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/drpdi_in[1] GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPDI[1] ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.717 1.717 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/drpclk_in[0] SLR Crossing[0->1] GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK clock pessimism -0.066 1.651 GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL (Hold_GTHE3_CHANNEL_DRPCLK_DRPDI[1]) 0.035 1.686 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST ------------------------------------------------------------------- required time -1.686 arrival time 1.717 ------------------------------------------------------------------- slack 0.031 Slack (MET) : 0.031ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[89]/C (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[9]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.279ns (logic 0.142ns (50.896%) route 0.137ns (49.104%)) Logic Levels: 2 (LUT4=1 MUXF7=1) Clock Path Skew: 0.192ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.681ns Source Clock Delay (SCD): 1.441ns Clock Pessimism Removal (CPR): 0.048ns Clock Net Delay (Source): 1.441ns (routing 0.373ns, distribution 1.068ns) Clock Net Delay (Destination): 1.681ns (routing 0.411ns, distribution 1.270ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.441 1.441 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/tx_wordclk SLR Crossing[0->1] SLICE_X12Y419 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[89]/C ------------------------------------------------------------------- ------------------- SLICE_X12Y419 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 1.490 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[89]/Q net (fo=1, routed) 0.124 1.614 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/data4[9] SLICE_X13Y421 LUT4 (Prop_C6LUT_SLICEM_I0_O) 0.070 1.684 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O[9]_i_3__42/O net (fo=1, routed) 0.000 1.684 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O[9]_i_3__42_n_0 SLICE_X13Y421 MUXF7 (Prop_F7MUX_CD_SLICEM_I1_O) 0.023 1.707 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[9]_i_1__42/O net (fo=1, routed) 0.013 1.720 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[9]_i_1__42_n_0 SLICE_X13Y421 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[9]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.681 1.681 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/tx_wordclk SLR Crossing[0->1] SLICE_X13Y421 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[9]/C clock pessimism -0.048 1.633 SLICE_X13Y421 FDCE (Hold_DFF_SLICEM_C_D) 0.056 1.689 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[9] ------------------------------------------------------------------- required time -1.689 arrival time 1.720 ------------------------------------------------------------------- slack 0.031 Slack (MET) : 0.031ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/FSM_sequential_phase_aligner_state_reg[1]/C (rising edge-triggered cell FDSE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/ui_align_cntr_reg[1]/D (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.171ns (logic 0.064ns (37.427%) route 0.107ns (62.573%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.765ns Source Clock Delay (SCD): 1.519ns Clock Pessimism Removal (CPR): 0.162ns Clock Net Delay (Source): 1.519ns (routing 0.373ns, distribution 1.146ns) Clock Net Delay (Destination): 1.765ns (routing 0.411ns, distribution 1.354ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.519 1.519 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/tx_wordclk SLR Crossing[0->1] SLICE_X142Y438 FDSE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/FSM_sequential_phase_aligner_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X142Y438 FDSE (Prop_DFF2_SLICEM_C_Q) 0.049 1.568 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/FSM_sequential_phase_aligner_state_reg[1]/Q net (fo=24, routed) 0.093 1.661 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/ui_align_cntr_reg[4][0] SLICE_X140Y437 LUT6 (Prop_G6LUT_SLICEL_I3_O) 0.015 1.676 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/ui_align_cntr[1]_i_1__12/O net (fo=1, routed) 0.014 1.690 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/D[0] SLICE_X140Y437 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/ui_align_cntr_reg[1]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.765 1.765 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/tx_wordclk SLR Crossing[0->1] SLICE_X140Y437 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/ui_align_cntr_reg[1]/C clock pessimism -0.162 1.603 SLICE_X140Y437 FDRE (Hold_GFF_SLICEL_C_D) 0.056 1.659 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/ui_align_cntr_reg[1] ------------------------------------------------------------------- required time -1.659 arrival time 1.690 ------------------------------------------------------------------- slack 0.031 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: tx_wordclk Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { tx_wordclk_bufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/DRPCLK n/a 4.000 8.317 4.317 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Min Period n/a GTHE3_CHANNEL/DRPCLK n/a 4.000 8.317 4.317 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Min Period n/a GTHE3_CHANNEL/DRPCLK n/a 4.000 8.317 4.317 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Min Period n/a GTHE3_CHANNEL/DRPCLK n/a 4.000 8.317 4.317 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Min Period n/a GTHE3_CHANNEL/DRPCLK n/a 4.000 8.317 4.317 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Min Period n/a GTHE3_CHANNEL/DRPCLK n/a 4.000 8.317 4.317 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Min Period n/a GTHE3_CHANNEL/DRPCLK n/a 4.000 8.317 4.317 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Min Period n/a GTHE3_CHANNEL/DRPCLK n/a 4.000 8.317 4.317 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Min Period n/a GTHE3_CHANNEL/DRPCLK n/a 4.000 8.317 4.317 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Min Period n/a GTHE3_CHANNEL/DRPCLK n/a 4.000 8.317 4.317 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Fast GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Fast GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Fast GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Fast GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Fast GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.025 0.495 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.025 0.495 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.025 0.495 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.025 0.495 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.025 0.495 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.025 0.495 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.025 0.495 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.025 0.495 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.025 0.495 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.025 0.495 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK --------------------------------------------------------------------------------------------------- From Clock: ipb_clk To Clock: clk250 Setup : 0 Failing Endpoints, Worst Slack 0.900ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.055ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.900ns (required time - arrival time) Source: ctrl_regs_inst/regs_reg[7][31]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[5]/CE (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - ipb_clk rise@0.000ns) Data Path Delay: 2.837ns (logic 0.305ns (10.751%) route 2.532ns (89.249%)) Logic Levels: 1 (LUT3=1) Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 2.903ns (routing 0.594ns, distribution 2.309ns) Clock Net Delay (Destination): 2.903ns (routing 1.181ns, distribution 1.722ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 2.903 2.903 ctrl_regs_inst/CLK SLICE_X65Y207 FDCE r ctrl_regs_inst/regs_reg[7][31]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y207 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.042 r ctrl_regs_inst/regs_reg[7][31]/Q net (fo=3, routed) 0.879 3.921 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] SLICE_X68Y184 LUT3 (Prop_B6LUT_SLICEL_I1_O) 0.166 4.087 r stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/O net (fo=20, routed) 1.653 5.740 stat_regs_inst/i_cntr_rst_ctrl/reset_type SLICE_X63Y155 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y100 BUFGCE 0.000 4.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 2.903 6.903 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLICE_X63Y155 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[5]/C clock pessimism 0.000 6.903 clock uncertainty -0.205 6.698 SLICE_X63Y155 FDCE (Setup_EFF2_SLICEL_C_CE) -0.058 6.640 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[5] ------------------------------------------------------------------- required time 6.640 arrival time -5.740 ------------------------------------------------------------------- slack 0.900 Slack (MET) : 0.900ns (required time - arrival time) Source: ctrl_regs_inst/regs_reg[7][31]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]/CE (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - ipb_clk rise@0.000ns) Data Path Delay: 2.837ns (logic 0.305ns (10.751%) route 2.532ns (89.249%)) Logic Levels: 1 (LUT3=1) Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 2.903ns (routing 0.594ns, distribution 2.309ns) Clock Net Delay (Destination): 2.903ns (routing 1.181ns, distribution 1.722ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 2.903 2.903 ctrl_regs_inst/CLK SLICE_X65Y207 FDCE r ctrl_regs_inst/regs_reg[7][31]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y207 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.042 r ctrl_regs_inst/regs_reg[7][31]/Q net (fo=3, routed) 0.879 3.921 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] SLICE_X68Y184 LUT3 (Prop_B6LUT_SLICEL_I1_O) 0.166 4.087 r stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/O net (fo=20, routed) 1.653 5.740 stat_regs_inst/i_cntr_rst_ctrl/reset_type SLICE_X63Y155 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y100 BUFGCE 0.000 4.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 2.903 6.903 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLICE_X63Y155 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]/C clock pessimism 0.000 6.903 clock uncertainty -0.205 6.698 SLICE_X63Y155 FDCE (Setup_FFF2_SLICEL_C_CE) -0.058 6.640 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7] ------------------------------------------------------------------- required time 6.640 arrival time -5.740 ------------------------------------------------------------------- slack 0.900 Slack (MET) : 0.906ns (required time - arrival time) Source: ctrl_regs_inst/regs_reg[7][31]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[4]/CE (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - ipb_clk rise@0.000ns) Data Path Delay: 2.834ns (logic 0.305ns (10.762%) route 2.529ns (89.238%)) Logic Levels: 1 (LUT3=1) Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 2.903ns (routing 0.594ns, distribution 2.309ns) Clock Net Delay (Destination): 2.903ns (routing 1.181ns, distribution 1.722ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 2.903 2.903 ctrl_regs_inst/CLK SLICE_X65Y207 FDCE r ctrl_regs_inst/regs_reg[7][31]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y207 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.042 r ctrl_regs_inst/regs_reg[7][31]/Q net (fo=3, routed) 0.879 3.921 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] SLICE_X68Y184 LUT3 (Prop_B6LUT_SLICEL_I1_O) 0.166 4.087 r stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/O net (fo=20, routed) 1.650 5.737 stat_regs_inst/i_cntr_rst_ctrl/reset_type SLICE_X63Y155 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y100 BUFGCE 0.000 4.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 2.903 6.903 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLICE_X63Y155 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[4]/C clock pessimism 0.000 6.903 clock uncertainty -0.205 6.698 SLICE_X63Y155 FDCE (Setup_EFF_SLICEL_C_CE) -0.055 6.643 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[4] ------------------------------------------------------------------- required time 6.643 arrival time -5.737 ------------------------------------------------------------------- slack 0.906 Slack (MET) : 0.906ns (required time - arrival time) Source: ctrl_regs_inst/regs_reg[7][31]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]/CE (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - ipb_clk rise@0.000ns) Data Path Delay: 2.834ns (logic 0.305ns (10.762%) route 2.529ns (89.238%)) Logic Levels: 1 (LUT3=1) Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 2.903ns (routing 0.594ns, distribution 2.309ns) Clock Net Delay (Destination): 2.903ns (routing 1.181ns, distribution 1.722ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 2.903 2.903 ctrl_regs_inst/CLK SLICE_X65Y207 FDCE r ctrl_regs_inst/regs_reg[7][31]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y207 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.042 r ctrl_regs_inst/regs_reg[7][31]/Q net (fo=3, routed) 0.879 3.921 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] SLICE_X68Y184 LUT3 (Prop_B6LUT_SLICEL_I1_O) 0.166 4.087 r stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/O net (fo=20, routed) 1.650 5.737 stat_regs_inst/i_cntr_rst_ctrl/reset_type SLICE_X63Y155 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y100 BUFGCE 0.000 4.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 2.903 6.903 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLICE_X63Y155 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]/C clock pessimism 0.000 6.903 clock uncertainty -0.205 6.698 SLICE_X63Y155 FDCE (Setup_FFF_SLICEL_C_CE) -0.055 6.643 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6] ------------------------------------------------------------------- required time 6.643 arrival time -5.737 ------------------------------------------------------------------- slack 0.906 Slack (MET) : 0.906ns (required time - arrival time) Source: ctrl_regs_inst/regs_reg[7][31]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[8]/CE (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - ipb_clk rise@0.000ns) Data Path Delay: 2.834ns (logic 0.305ns (10.762%) route 2.529ns (89.238%)) Logic Levels: 1 (LUT3=1) Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 2.903ns (routing 0.594ns, distribution 2.309ns) Clock Net Delay (Destination): 2.903ns (routing 1.181ns, distribution 1.722ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 2.903 2.903 ctrl_regs_inst/CLK SLICE_X65Y207 FDCE r ctrl_regs_inst/regs_reg[7][31]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y207 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.042 r ctrl_regs_inst/regs_reg[7][31]/Q net (fo=3, routed) 0.879 3.921 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] SLICE_X68Y184 LUT3 (Prop_B6LUT_SLICEL_I1_O) 0.166 4.087 r stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/O net (fo=20, routed) 1.650 5.737 stat_regs_inst/i_cntr_rst_ctrl/reset_type SLICE_X63Y155 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[8]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y100 BUFGCE 0.000 4.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 2.903 6.903 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLICE_X63Y155 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[8]/C clock pessimism 0.000 6.903 clock uncertainty -0.205 6.698 SLICE_X63Y155 FDCE (Setup_GFF_SLICEL_C_CE) -0.055 6.643 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[8] ------------------------------------------------------------------- required time 6.643 arrival time -5.737 ------------------------------------------------------------------- slack 0.906 Slack (MET) : 1.079ns (required time - arrival time) Source: ctrl_regs_inst/regs_reg[7][31]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[0]/CE (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - ipb_clk rise@0.000ns) Data Path Delay: 2.671ns (logic 0.305ns (11.419%) route 2.366ns (88.581%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.013ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.916ns = ( 6.916 - 4.000 ) Source Clock Delay (SCD): 2.903ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 2.903ns (routing 0.594ns, distribution 2.309ns) Clock Net Delay (Destination): 2.916ns (routing 1.181ns, distribution 1.735ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 2.903 2.903 ctrl_regs_inst/CLK SLICE_X65Y207 FDCE r ctrl_regs_inst/regs_reg[7][31]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y207 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.042 r ctrl_regs_inst/regs_reg[7][31]/Q net (fo=3, routed) 0.879 3.921 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] SLICE_X68Y184 LUT3 (Prop_B6LUT_SLICEL_I1_O) 0.166 4.087 r stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/O net (fo=20, routed) 1.487 5.574 stat_regs_inst/i_cntr_rst_ctrl/reset_type SLICE_X64Y157 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y100 BUFGCE 0.000 4.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 2.916 6.916 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLICE_X64Y157 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[0]/C clock pessimism 0.000 6.916 clock uncertainty -0.205 6.711 SLICE_X64Y157 FDCE (Setup_EFF2_SLICEM_C_CE) -0.058 6.653 stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[0] ------------------------------------------------------------------- required time 6.653 arrival time -5.574 ------------------------------------------------------------------- slack 1.079 Slack (MET) : 1.085ns (required time - arrival time) Source: ctrl_regs_inst/regs_reg[7][31]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]/CE (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - ipb_clk rise@0.000ns) Data Path Delay: 2.668ns (logic 0.305ns (11.432%) route 2.363ns (88.568%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.013ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.916ns = ( 6.916 - 4.000 ) Source Clock Delay (SCD): 2.903ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 2.903ns (routing 0.594ns, distribution 2.309ns) Clock Net Delay (Destination): 2.916ns (routing 1.181ns, distribution 1.735ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 2.903 2.903 ctrl_regs_inst/CLK SLICE_X65Y207 FDCE r ctrl_regs_inst/regs_reg[7][31]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y207 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.042 r ctrl_regs_inst/regs_reg[7][31]/Q net (fo=3, routed) 0.879 3.921 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] SLICE_X68Y184 LUT3 (Prop_B6LUT_SLICEL_I1_O) 0.166 4.087 r stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/O net (fo=20, routed) 1.484 5.571 stat_regs_inst/i_cntr_rst_ctrl/reset_type SLICE_X64Y157 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y100 BUFGCE 0.000 4.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 2.916 6.916 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLICE_X64Y157 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]/C clock pessimism 0.000 6.916 clock uncertainty -0.205 6.711 SLICE_X64Y157 FDCE (Setup_EFF_SLICEM_C_CE) -0.055 6.656 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3] ------------------------------------------------------------------- required time 6.656 arrival time -5.571 ------------------------------------------------------------------- slack 1.085 Slack (MET) : 1.085ns (required time - arrival time) Source: ctrl_regs_inst/regs_reg[7][31]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[1]/CE (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - ipb_clk rise@0.000ns) Data Path Delay: 2.668ns (logic 0.305ns (11.432%) route 2.363ns (88.568%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.013ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.916ns = ( 6.916 - 4.000 ) Source Clock Delay (SCD): 2.903ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 2.903ns (routing 0.594ns, distribution 2.309ns) Clock Net Delay (Destination): 2.916ns (routing 1.181ns, distribution 1.735ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 2.903 2.903 ctrl_regs_inst/CLK SLICE_X65Y207 FDCE r ctrl_regs_inst/regs_reg[7][31]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y207 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.042 r ctrl_regs_inst/regs_reg[7][31]/Q net (fo=3, routed) 0.879 3.921 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] SLICE_X68Y184 LUT3 (Prop_B6LUT_SLICEL_I1_O) 0.166 4.087 r stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/O net (fo=20, routed) 1.484 5.571 stat_regs_inst/i_cntr_rst_ctrl/reset_type SLICE_X64Y157 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y100 BUFGCE 0.000 4.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 2.916 6.916 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLICE_X64Y157 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[1]/C clock pessimism 0.000 6.916 clock uncertainty -0.205 6.711 SLICE_X64Y157 FDCE (Setup_FFF_SLICEM_C_CE) -0.055 6.656 stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[1] ------------------------------------------------------------------- required time 6.656 arrival time -5.571 ------------------------------------------------------------------- slack 1.085 Slack (MET) : 1.286ns (required time - arrival time) Source: ctrl_regs_inst/regs_reg[7][31]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[1]/CE (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - ipb_clk rise@0.000ns) Data Path Delay: 2.452ns (logic 0.305ns (12.439%) route 2.147ns (87.561%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.002ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.901ns = ( 6.901 - 4.000 ) Source Clock Delay (SCD): 2.903ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 2.903ns (routing 0.594ns, distribution 2.309ns) Clock Net Delay (Destination): 2.901ns (routing 1.181ns, distribution 1.720ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 2.903 2.903 ctrl_regs_inst/CLK SLICE_X65Y207 FDCE r ctrl_regs_inst/regs_reg[7][31]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y207 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.042 r ctrl_regs_inst/regs_reg[7][31]/Q net (fo=3, routed) 0.879 3.921 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] SLICE_X68Y184 LUT3 (Prop_B6LUT_SLICEL_I1_O) 0.166 4.087 r stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/O net (fo=20, routed) 1.268 5.355 stat_regs_inst/i_cntr_rst_ctrl/reset_type SLICE_X68Y157 FDCE r stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y100 BUFGCE 0.000 4.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 2.901 6.901 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLICE_X68Y157 FDCE r stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[1]/C clock pessimism 0.000 6.901 clock uncertainty -0.205 6.696 SLICE_X68Y157 FDCE (Setup_AFF2_SLICEL_C_CE) -0.055 6.641 stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[1] ------------------------------------------------------------------- required time 6.641 arrival time -5.355 ------------------------------------------------------------------- slack 1.286 Slack (MET) : 1.286ns (required time - arrival time) Source: ctrl_regs_inst/regs_reg[7][31]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[7]/CE (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - ipb_clk rise@0.000ns) Data Path Delay: 2.452ns (logic 0.305ns (12.439%) route 2.147ns (87.561%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.002ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.901ns = ( 6.901 - 4.000 ) Source Clock Delay (SCD): 2.903ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 2.903ns (routing 0.594ns, distribution 2.309ns) Clock Net Delay (Destination): 2.901ns (routing 1.181ns, distribution 1.720ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 2.903 2.903 ctrl_regs_inst/CLK SLICE_X65Y207 FDCE r ctrl_regs_inst/regs_reg[7][31]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y207 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.042 r ctrl_regs_inst/regs_reg[7][31]/Q net (fo=3, routed) 0.879 3.921 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] SLICE_X68Y184 LUT3 (Prop_B6LUT_SLICEL_I1_O) 0.166 4.087 r stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/O net (fo=20, routed) 1.268 5.355 stat_regs_inst/i_cntr_rst_ctrl/reset_type SLICE_X68Y157 FDCE r stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[7]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y100 BUFGCE 0.000 4.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 2.901 6.901 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLICE_X68Y157 FDCE r stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[7]/C clock pessimism 0.000 6.901 clock uncertainty -0.205 6.696 SLICE_X68Y157 FDCE (Setup_BFF2_SLICEL_C_CE) -0.055 6.641 stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[7] ------------------------------------------------------------------- required time 6.641 arrival time -5.355 ------------------------------------------------------------------- slack 1.286 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.055ns (arrival time - required time) Source: ctrl_regs_inst/regs_reg[7][5]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[5]/D (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.687ns (logic 0.048ns (6.987%) route 0.639ns (93.013%)) Logic Levels: 0 Clock Path Skew: 0.372ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.354ns Source Clock Delay (SCD): 0.982ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 0.982ns (routing 0.203ns, distribution 0.779ns) Clock Net Delay (Destination): 1.354ns (routing 0.532ns, distribution 0.822ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 0.982 0.982 ctrl_regs_inst/CLK SLICE_X64Y205 FDCE r ctrl_regs_inst/regs_reg[7][5]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y205 FDCE (Prop_GFF2_SLICEM_C_Q) 0.048 1.030 r ctrl_regs_inst/regs_reg[7][5]/Q net (fo=2, routed) 0.639 1.669 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[5] SLICE_X63Y155 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.354 1.354 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLICE_X63Y155 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[5]/C clock pessimism 0.000 1.354 clock uncertainty 0.205 1.559 SLICE_X63Y155 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.614 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[5] ------------------------------------------------------------------- required time -1.614 arrival time 1.669 ------------------------------------------------------------------- slack 0.055 Slack (MET) : 0.114ns (arrival time - required time) Source: ctrl_regs_inst/regs_reg[7][31]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg/D (rising edge-triggered cell FDPE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.756ns (logic 0.125ns (16.534%) route 0.631ns (83.466%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.381ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.363ns Source Clock Delay (SCD): 0.982ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 0.982ns (routing 0.203ns, distribution 0.779ns) Clock Net Delay (Destination): 1.363ns (routing 0.532ns, distribution 0.831ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 0.982 0.982 ctrl_regs_inst/CLK SLICE_X65Y207 FDCE r ctrl_regs_inst/regs_reg[7][31]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y207 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.031 r ctrl_regs_inst/regs_reg[7][31]/Q net (fo=3, routed) 0.620 1.651 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] SLICE_X68Y166 LUT5 (Prop_D5LUT_SLICEL_I2_O) 0.076 1.727 r stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_i_1/O net (fo=1, routed) 0.011 1.738 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_i_1_n_0 SLICE_X68Y166 FDPE r stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.363 1.363 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLICE_X68Y166 FDPE r stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg/C clock pessimism 0.000 1.363 clock uncertainty 0.205 1.568 SLICE_X68Y166 FDPE (Hold_DFF2_SLICEL_C_D) 0.056 1.624 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg ------------------------------------------------------------------- required time -1.624 arrival time 1.738 ------------------------------------------------------------------- slack 0.114 Slack (MET) : 0.122ns (arrival time - required time) Source: ctrl_regs_inst/regs_reg[7][2]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[2]/D (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.763ns (logic 0.049ns (6.422%) route 0.714ns (93.578%)) Logic Levels: 0 Clock Path Skew: 0.380ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.361ns Source Clock Delay (SCD): 0.981ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 0.981ns (routing 0.203ns, distribution 0.778ns) Clock Net Delay (Destination): 1.361ns (routing 0.532ns, distribution 0.829ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 0.981 0.981 ctrl_regs_inst/CLK SLICE_X64Y206 FDCE r ctrl_regs_inst/regs_reg[7][2]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y206 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.030 r ctrl_regs_inst/regs_reg[7][2]/Q net (fo=2, routed) 0.714 1.744 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[2] SLICE_X64Y193 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[2]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.361 1.361 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLICE_X64Y193 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[2]/C clock pessimism 0.000 1.361 clock uncertainty 0.205 1.566 SLICE_X64Y193 FDCE (Hold_FFF_SLICEM_C_D) 0.056 1.622 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[2] ------------------------------------------------------------------- required time -1.622 arrival time 1.744 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.161ns (arrival time - required time) Source: ctrl_regs_inst/regs_reg[7][6]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]/D (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.797ns (logic 0.048ns (6.023%) route 0.749ns (93.977%)) Logic Levels: 0 Clock Path Skew: 0.375ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.354ns Source Clock Delay (SCD): 0.979ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 0.979ns (routing 0.203ns, distribution 0.776ns) Clock Net Delay (Destination): 1.354ns (routing 0.532ns, distribution 0.822ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 0.979 0.979 ctrl_regs_inst/CLK SLICE_X64Y210 FDCE r ctrl_regs_inst/regs_reg[7][6]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y210 FDCE (Prop_GFF_SLICEM_C_Q) 0.048 1.027 r ctrl_regs_inst/regs_reg[7][6]/Q net (fo=2, routed) 0.749 1.776 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[6] SLICE_X63Y155 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.354 1.354 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLICE_X63Y155 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]/C clock pessimism 0.000 1.354 clock uncertainty 0.205 1.559 SLICE_X63Y155 FDCE (Hold_FFF_SLICEL_C_D) 0.056 1.615 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6] ------------------------------------------------------------------- required time -1.615 arrival time 1.776 ------------------------------------------------------------------- slack 0.161 Slack (MET) : 0.184ns (arrival time - required time) Source: ctrl_regs_inst/regs_reg[7][3]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]/D (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.827ns (logic 0.048ns (5.804%) route 0.779ns (94.196%)) Logic Levels: 0 Clock Path Skew: 0.382ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.364ns Source Clock Delay (SCD): 0.982ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 0.982ns (routing 0.203ns, distribution 0.779ns) Clock Net Delay (Destination): 1.364ns (routing 0.532ns, distribution 0.832ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 0.982 0.982 ctrl_regs_inst/CLK SLICE_X64Y205 FDCE r ctrl_regs_inst/regs_reg[7][3]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y205 FDCE (Prop_FFF2_SLICEM_C_Q) 0.048 1.030 r ctrl_regs_inst/regs_reg[7][3]/Q net (fo=2, routed) 0.779 1.809 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[3] SLICE_X64Y157 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.364 1.364 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLICE_X64Y157 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]/C clock pessimism 0.000 1.364 clock uncertainty 0.205 1.569 SLICE_X64Y157 FDCE (Hold_EFF_SLICEM_C_D) 0.056 1.625 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3] ------------------------------------------------------------------- required time -1.625 arrival time 1.809 ------------------------------------------------------------------- slack 0.184 Slack (MET) : 0.190ns (arrival time - required time) Source: stat_regs_inst/ipb_clk_div2_reg/C (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/ipb_clk_div2_r_reg/D (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.693ns (logic 0.048ns (6.926%) route 0.645ns (93.074%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.315ns Source Clock Delay (SCD): 1.073ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.073ns (routing 0.203ns, distribution 0.870ns) Clock Net Delay (Destination): 1.315ns (routing 0.532ns, distribution 0.783ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.073 1.073 stat_regs_inst/CLK SLICE_X82Y216 FDRE r stat_regs_inst/ipb_clk_div2_reg/C ------------------------------------------------------------------- ------------------- SLICE_X82Y216 FDRE (Prop_GFF_SLICEM_C_Q) 0.048 1.121 r stat_regs_inst/ipb_clk_div2_reg/Q net (fo=3, routed) 0.645 1.766 stat_regs_inst/ipb_clk_div2 SLICE_X82Y216 FDRE r stat_regs_inst/ipb_clk_div2_r_reg/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.315 1.315 stat_regs_inst/clk250 SLICE_X82Y216 FDRE r stat_regs_inst/ipb_clk_div2_r_reg/C clock pessimism 0.000 1.315 clock uncertainty 0.205 1.520 SLICE_X82Y216 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.576 stat_regs_inst/ipb_clk_div2_r_reg ------------------------------------------------------------------- required time -1.576 arrival time 1.766 ------------------------------------------------------------------- slack 0.190 Slack (MET) : 0.222ns (arrival time - required time) Source: ctrl_regs_inst/regs_reg[7][0]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[0]/D (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.865ns (logic 0.048ns (5.549%) route 0.817ns (94.451%)) Logic Levels: 0 Clock Path Skew: 0.382ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.361ns Source Clock Delay (SCD): 0.979ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 0.979ns (routing 0.203ns, distribution 0.776ns) Clock Net Delay (Destination): 1.361ns (routing 0.532ns, distribution 0.829ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 0.979 0.979 ctrl_regs_inst/CLK SLICE_X64Y210 FDCE r ctrl_regs_inst/regs_reg[7][0]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y210 FDCE (Prop_HFF_SLICEM_C_Q) 0.048 1.027 r ctrl_regs_inst/regs_reg[7][0]/Q net (fo=2, routed) 0.817 1.844 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[0] SLICE_X64Y193 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.361 1.361 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLICE_X64Y193 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[0]/C clock pessimism 0.000 1.361 clock uncertainty 0.205 1.566 SLICE_X64Y193 FDCE (Hold_EFF_SLICEM_C_D) 0.056 1.622 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[0] ------------------------------------------------------------------- required time -1.622 arrival time 1.844 ------------------------------------------------------------------- slack 0.222 Slack (MET) : 0.258ns (arrival time - required time) Source: ctrl_regs_inst/regs_reg[7][31]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[2]/CE (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.835ns (logic 0.102ns (12.216%) route 0.733ns (87.784%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.372ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.354ns Source Clock Delay (SCD): 0.982ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 0.982ns (routing 0.203ns, distribution 0.779ns) Clock Net Delay (Destination): 1.354ns (routing 0.532ns, distribution 0.822ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 0.982 0.982 ctrl_regs_inst/CLK SLICE_X65Y207 FDCE r ctrl_regs_inst/regs_reg[7][31]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y207 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.031 r ctrl_regs_inst/regs_reg[7][31]/Q net (fo=3, routed) 0.395 1.426 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] SLICE_X68Y184 LUT3 (Prop_B6LUT_SLICEL_I1_O) 0.053 1.479 r stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/O net (fo=20, routed) 0.338 1.817 stat_regs_inst/i_cntr_rst_ctrl/reset_type SLICE_X66Y185 FDCE r stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.354 1.354 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLICE_X66Y185 FDCE r stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[2]/C clock pessimism 0.000 1.354 clock uncertainty 0.205 1.559 SLICE_X66Y185 FDCE (Hold_EFF_SLICEL_C_CE) 0.000 1.559 stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[2] ------------------------------------------------------------------- required time -1.559 arrival time 1.817 ------------------------------------------------------------------- slack 0.258 Slack (MET) : 0.258ns (arrival time - required time) Source: ctrl_regs_inst/regs_reg[7][31]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[4]/CE (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.835ns (logic 0.102ns (12.216%) route 0.733ns (87.784%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.372ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.354ns Source Clock Delay (SCD): 0.982ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 0.982ns (routing 0.203ns, distribution 0.779ns) Clock Net Delay (Destination): 1.354ns (routing 0.532ns, distribution 0.822ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 0.982 0.982 ctrl_regs_inst/CLK SLICE_X65Y207 FDCE r ctrl_regs_inst/regs_reg[7][31]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y207 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.031 r ctrl_regs_inst/regs_reg[7][31]/Q net (fo=3, routed) 0.395 1.426 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] SLICE_X68Y184 LUT3 (Prop_B6LUT_SLICEL_I1_O) 0.053 1.479 r stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/O net (fo=20, routed) 0.338 1.817 stat_regs_inst/i_cntr_rst_ctrl/reset_type SLICE_X66Y185 FDCE r stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.354 1.354 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLICE_X66Y185 FDCE r stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[4]/C clock pessimism 0.000 1.354 clock uncertainty 0.205 1.559 SLICE_X66Y185 FDCE (Hold_FFF_SLICEL_C_CE) 0.000 1.559 stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[4] ------------------------------------------------------------------- required time -1.559 arrival time 1.817 ------------------------------------------------------------------- slack 0.258 Slack (MET) : 0.260ns (arrival time - required time) Source: ctrl_regs_inst/regs_reg[7][7]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]/D (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.892ns (logic 0.048ns (5.381%) route 0.844ns (94.619%)) Logic Levels: 0 Clock Path Skew: 0.372ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.354ns Source Clock Delay (SCD): 0.982ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 0.982ns (routing 0.203ns, distribution 0.779ns) Clock Net Delay (Destination): 1.354ns (routing 0.532ns, distribution 0.822ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 0.982 0.982 ctrl_regs_inst/CLK SLICE_X64Y205 FDCE r ctrl_regs_inst/regs_reg[7][7]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y205 FDCE (Prop_HFF_SLICEM_C_Q) 0.048 1.030 r ctrl_regs_inst/regs_reg[7][7]/Q net (fo=2, routed) 0.844 1.874 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[7] SLICE_X63Y155 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.354 1.354 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLICE_X63Y155 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]/C clock pessimism 0.000 1.354 clock uncertainty 0.205 1.559 SLICE_X63Y155 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.614 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7] ------------------------------------------------------------------- required time -1.614 arrival time 1.874 ------------------------------------------------------------------- slack 0.260 --------------------------------------------------------------------------------------------------- From Clock: clk250 To Clock: ipb_clk Setup : 0 Failing Endpoints, Worst Slack 0.586ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.030ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.586ns (required time - arrival time) Source: g_clock_rate_din[27].i_rate_ngccm_status1/rate_i_reg[17]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[27].i_rate_ngccm_status1/rate_reg[17]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (ipb_clk rise@32.000ns - clk250 rise@28.000ns) Data Path Delay: 2.749ns (logic 0.138ns (5.020%) route 2.611ns (94.980%)) Logic Levels: 0 Clock Path Skew: -0.527ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.707ns = ( 34.707 - 32.000 ) Source Clock Delay (SCD): 3.234ns = ( 31.234 - 28.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.234ns (routing 1.281ns, distribution 1.953ns) Clock Net Delay (Destination): 2.707ns (routing 0.546ns, distribution 2.161ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 28.000 28.000 r BUFGCE_X1Y100 BUFGCE 0.000 28.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.234 31.234 g_clock_rate_din[27].i_rate_ngccm_status1/clk250 SLICE_X88Y237 FDRE r g_clock_rate_din[27].i_rate_ngccm_status1/rate_i_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y237 FDRE (Prop_EFF2_SLICEL_C_Q) 0.138 31.372 r g_clock_rate_din[27].i_rate_ngccm_status1/rate_i_reg[17]/Q net (fo=1, routed) 2.611 33.983 g_clock_rate_din[27].i_rate_ngccm_status1/rate_i_reg_n_0_[17] SLICE_X81Y227 FDRE r g_clock_rate_din[27].i_rate_ngccm_status1/rate_reg[17]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 2.707 34.707 g_clock_rate_din[27].i_rate_ngccm_status1/CLK SLICE_X81Y227 FDRE r g_clock_rate_din[27].i_rate_ngccm_status1/rate_reg[17]/C clock pessimism 0.000 34.707 clock uncertainty -0.205 34.502 SLICE_X81Y227 FDRE (Setup_DFF2_SLICEL_C_D) 0.067 34.569 g_clock_rate_din[27].i_rate_ngccm_status1/rate_reg[17] ------------------------------------------------------------------- required time 34.569 arrival time -33.983 ------------------------------------------------------------------- slack 0.586 Slack (MET) : 0.614ns (required time - arrival time) Source: g_clock_rate_din[34].i_rate_ngccm_status1/rate_i_reg[19]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[34].i_rate_ngccm_status1/rate_reg[19]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (ipb_clk rise@32.000ns - clk250 rise@28.000ns) Data Path Delay: 2.059ns (logic 0.140ns (6.799%) route 1.919ns (93.201%)) Logic Levels: 0 Clock Path Skew: -1.186ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.527ns = ( 34.527 - 32.000 ) Source Clock Delay (SCD): 3.713ns = ( 31.713 - 28.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.713ns (routing 1.281ns, distribution 2.432ns) Clock Net Delay (Destination): 2.527ns (routing 0.546ns, distribution 1.981ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 28.000 28.000 r BUFGCE_X1Y100 BUFGCE 0.000 28.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.713 31.713 g_clock_rate_din[34].i_rate_ngccm_status1/clk250 SLICE_X42Y269 FDRE r g_clock_rate_din[34].i_rate_ngccm_status1/rate_i_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y269 FDRE (Prop_AFF_SLICEM_C_Q) 0.140 31.853 r g_clock_rate_din[34].i_rate_ngccm_status1/rate_i_reg[19]/Q net (fo=1, routed) 1.919 33.772 g_clock_rate_din[34].i_rate_ngccm_status1/rate_i_reg_n_0_[19] SLICE_X58Y275 FDRE r g_clock_rate_din[34].i_rate_ngccm_status1/rate_reg[19]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 2.527 34.527 g_clock_rate_din[34].i_rate_ngccm_status1/CLK SLICE_X58Y275 FDRE r g_clock_rate_din[34].i_rate_ngccm_status1/rate_reg[19]/C clock pessimism 0.000 34.527 clock uncertainty -0.205 34.322 SLICE_X58Y275 FDRE (Setup_EFF_SLICEM_C_D) 0.064 34.386 g_clock_rate_din[34].i_rate_ngccm_status1/rate_reg[19] ------------------------------------------------------------------- required time 34.386 arrival time -33.772 ------------------------------------------------------------------- slack 0.614 Slack (MET) : 0.619ns (required time - arrival time) Source: g_clock_rate_din[3].i_rate_ngccm_status1/rate_i_reg[12]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[3].i_rate_ngccm_status1/rate_reg[12]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (ipb_clk rise@32.000ns - clk250 rise@28.000ns) Data Path Delay: 2.735ns (logic 0.139ns (5.082%) route 2.596ns (94.918%)) Logic Levels: 0 Clock Path Skew: -0.505ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.700ns = ( 34.700 - 32.000 ) Source Clock Delay (SCD): 3.205ns = ( 31.205 - 28.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.205ns (routing 1.281ns, distribution 1.924ns) Clock Net Delay (Destination): 2.700ns (routing 0.546ns, distribution 2.154ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 28.000 28.000 r BUFGCE_X1Y100 BUFGCE 0.000 28.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.205 31.205 g_clock_rate_din[3].i_rate_ngccm_status1/clk250 SLICE_X82Y218 FDRE r g_clock_rate_din[3].i_rate_ngccm_status1/rate_i_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X82Y218 FDRE (Prop_BFF_SLICEM_C_Q) 0.139 31.344 r g_clock_rate_din[3].i_rate_ngccm_status1/rate_i_reg[12]/Q net (fo=1, routed) 2.596 33.940 g_clock_rate_din[3].i_rate_ngccm_status1/rate_i_reg_n_0_[12] SLICE_X82Y218 FDRE r g_clock_rate_din[3].i_rate_ngccm_status1/rate_reg[12]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 2.700 34.700 g_clock_rate_din[3].i_rate_ngccm_status1/CLK SLICE_X82Y218 FDRE r g_clock_rate_din[3].i_rate_ngccm_status1/rate_reg[12]/C clock pessimism 0.000 34.700 clock uncertainty -0.205 34.495 SLICE_X82Y218 FDRE (Setup_EFF_SLICEM_C_D) 0.064 34.559 g_clock_rate_din[3].i_rate_ngccm_status1/rate_reg[12] ------------------------------------------------------------------- required time 34.559 arrival time -33.940 ------------------------------------------------------------------- slack 0.619 Slack (MET) : 0.637ns (required time - arrival time) Source: g_clock_rate_din[24].i_rate_ngccm_status1/rate_i_reg[23]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[24].i_rate_ngccm_status1/rate_reg[23]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (ipb_clk rise@32.000ns - clk250 rise@28.000ns) Data Path Delay: 2.724ns (logic 0.139ns (5.103%) route 2.585ns (94.897%)) Logic Levels: 0 Clock Path Skew: -0.496ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.707ns = ( 34.707 - 32.000 ) Source Clock Delay (SCD): 3.203ns = ( 31.203 - 28.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.203ns (routing 1.281ns, distribution 1.922ns) Clock Net Delay (Destination): 2.707ns (routing 0.546ns, distribution 2.161ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 28.000 28.000 r BUFGCE_X1Y100 BUFGCE 0.000 28.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.203 31.203 g_clock_rate_din[24].i_rate_ngccm_status1/clk250 SLICE_X81Y227 FDRE r g_clock_rate_din[24].i_rate_ngccm_status1/rate_i_reg[23]/C ------------------------------------------------------------------- ------------------- SLICE_X81Y227 FDRE (Prop_FFF_SLICEL_C_Q) 0.139 31.342 r g_clock_rate_din[24].i_rate_ngccm_status1/rate_i_reg[23]/Q net (fo=1, routed) 2.585 33.927 g_clock_rate_din[24].i_rate_ngccm_status1/rate_i_reg_n_0_[23] SLICE_X81Y227 FDRE r g_clock_rate_din[24].i_rate_ngccm_status1/rate_reg[23]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 2.707 34.707 g_clock_rate_din[24].i_rate_ngccm_status1/CLK SLICE_X81Y227 FDRE r g_clock_rate_din[24].i_rate_ngccm_status1/rate_reg[23]/C clock pessimism 0.000 34.707 clock uncertainty -0.205 34.502 SLICE_X81Y227 FDRE (Setup_BFF_SLICEL_C_D) 0.062 34.564 g_clock_rate_din[24].i_rate_ngccm_status1/rate_reg[23] ------------------------------------------------------------------- required time 34.564 arrival time -33.927 ------------------------------------------------------------------- slack 0.637 Slack (MET) : 0.645ns (required time - arrival time) Source: g_clock_rate_din[21].i_rate_ngccm_status1/rate_i_reg[23]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[21].i_rate_ngccm_status1/rate_reg[23]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (ipb_clk rise@32.000ns - clk250 rise@28.000ns) Data Path Delay: 2.675ns (logic 0.139ns (5.196%) route 2.536ns (94.804%)) Logic Levels: 0 Clock Path Skew: -0.538ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.731ns = ( 34.731 - 32.000 ) Source Clock Delay (SCD): 3.269ns = ( 31.269 - 28.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.269ns (routing 1.281ns, distribution 1.988ns) Clock Net Delay (Destination): 2.731ns (routing 0.546ns, distribution 2.185ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 28.000 28.000 r BUFGCE_X1Y100 BUFGCE 0.000 28.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.269 31.269 g_clock_rate_din[21].i_rate_ngccm_status1/clk250 SLICE_X84Y297 FDRE r g_clock_rate_din[21].i_rate_ngccm_status1/rate_i_reg[23]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y297 FDRE (Prop_BFF_SLICEL_C_Q) 0.139 31.408 r g_clock_rate_din[21].i_rate_ngccm_status1/rate_i_reg[23]/Q net (fo=1, routed) 2.536 33.944 g_clock_rate_din[21].i_rate_ngccm_status1/rate_i_reg_n_0_[23] SLICE_X84Y297 FDRE r g_clock_rate_din[21].i_rate_ngccm_status1/rate_reg[23]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 2.731 34.731 g_clock_rate_din[21].i_rate_ngccm_status1/CLK SLICE_X84Y297 FDRE r g_clock_rate_din[21].i_rate_ngccm_status1/rate_reg[23]/C clock pessimism 0.000 34.731 clock uncertainty -0.205 34.526 SLICE_X84Y297 FDRE (Setup_FFF_SLICEL_C_D) 0.063 34.589 g_clock_rate_din[21].i_rate_ngccm_status1/rate_reg[23] ------------------------------------------------------------------- required time 34.589 arrival time -33.944 ------------------------------------------------------------------- slack 0.645 Slack (MET) : 0.664ns (required time - arrival time) Source: g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[0]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[10].i_rate_ngccm_status2/rate_reg[0]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (ipb_clk rise@32.000ns - clk250 rise@28.000ns) Data Path Delay: 2.629ns (logic 0.140ns (5.325%) route 2.489ns (94.675%)) Logic Levels: 0 Clock Path Skew: -0.566ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.010ns = ( 35.010 - 32.000 ) Source Clock Delay (SCD): 3.576ns = ( 31.576 - 28.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.576ns (routing 1.281ns, distribution 2.295ns) Clock Net Delay (Destination): 3.010ns (routing 0.546ns, distribution 2.464ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 28.000 28.000 r BUFGCE_X1Y100 BUFGCE 0.000 28.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.576 31.576 g_clock_rate_din[10].i_rate_ngccm_status2/clk250 SLICE_X102Y270 FDRE r g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X102Y270 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 31.716 r g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[0]/Q net (fo=1, routed) 2.489 34.205 g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg_n_0_[0] SLICE_X102Y270 FDRE r g_clock_rate_din[10].i_rate_ngccm_status2/rate_reg[0]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.010 35.010 g_clock_rate_din[10].i_rate_ngccm_status2/CLK SLICE_X102Y270 FDRE r g_clock_rate_din[10].i_rate_ngccm_status2/rate_reg[0]/C clock pessimism 0.000 35.010 clock uncertainty -0.205 34.805 SLICE_X102Y270 FDRE (Setup_EFF_SLICEL_C_D) 0.064 34.869 g_clock_rate_din[10].i_rate_ngccm_status2/rate_reg[0] ------------------------------------------------------------------- required time 34.869 arrival time -34.205 ------------------------------------------------------------------- slack 0.664 Slack (MET) : 0.693ns (required time - arrival time) Source: g_clock_rate_din[8].i_rate_ngccm_status0/rate_i_reg[10]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[8].i_rate_ngccm_status0/rate_reg[10]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (ipb_clk rise@32.000ns - clk250 rise@28.000ns) Data Path Delay: 2.631ns (logic 0.137ns (5.207%) route 2.494ns (94.793%)) Logic Levels: 0 Clock Path Skew: -0.536ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.011ns = ( 35.011 - 32.000 ) Source Clock Delay (SCD): 3.547ns = ( 31.547 - 28.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.547ns (routing 1.281ns, distribution 2.266ns) Clock Net Delay (Destination): 3.011ns (routing 0.546ns, distribution 2.465ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 28.000 28.000 r BUFGCE_X1Y100 BUFGCE 0.000 28.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.547 31.547 g_clock_rate_din[8].i_rate_ngccm_status0/clk250 SLICE_X106Y235 FDRE r g_clock_rate_din[8].i_rate_ngccm_status0/rate_i_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y235 FDRE (Prop_DFF2_SLICEM_C_Q) 0.137 31.684 r g_clock_rate_din[8].i_rate_ngccm_status0/rate_i_reg[10]/Q net (fo=1, routed) 2.494 34.178 g_clock_rate_din[8].i_rate_ngccm_status0/rate_i_reg_n_0_[10] SLICE_X100Y235 FDRE r g_clock_rate_din[8].i_rate_ngccm_status0/rate_reg[10]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.011 35.011 g_clock_rate_din[8].i_rate_ngccm_status0/CLK SLICE_X100Y235 FDRE r g_clock_rate_din[8].i_rate_ngccm_status0/rate_reg[10]/C clock pessimism 0.000 35.011 clock uncertainty -0.205 34.806 SLICE_X100Y235 FDRE (Setup_EFF2_SLICEM_C_D) 0.065 34.871 g_clock_rate_din[8].i_rate_ngccm_status0/rate_reg[10] ------------------------------------------------------------------- required time 34.871 arrival time -34.178 ------------------------------------------------------------------- slack 0.693 Slack (MET) : 0.724ns (required time - arrival time) Source: g_clock_rate_din[21].i_rate_ngccm_status1/rate_i_reg[22]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[21].i_rate_ngccm_status1/rate_reg[22]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (ipb_clk rise@32.000ns - clk250 rise@28.000ns) Data Path Delay: 2.598ns (logic 0.138ns (5.312%) route 2.460ns (94.688%)) Logic Levels: 0 Clock Path Skew: -0.538ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.731ns = ( 34.731 - 32.000 ) Source Clock Delay (SCD): 3.269ns = ( 31.269 - 28.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.269ns (routing 1.281ns, distribution 1.988ns) Clock Net Delay (Destination): 2.731ns (routing 0.546ns, distribution 2.185ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 28.000 28.000 r BUFGCE_X1Y100 BUFGCE 0.000 28.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.269 31.269 g_clock_rate_din[21].i_rate_ngccm_status1/clk250 SLICE_X84Y297 FDRE r g_clock_rate_din[21].i_rate_ngccm_status1/rate_i_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y297 FDRE (Prop_CFF_SLICEL_C_Q) 0.138 31.407 r g_clock_rate_din[21].i_rate_ngccm_status1/rate_i_reg[22]/Q net (fo=1, routed) 2.460 33.867 g_clock_rate_din[21].i_rate_ngccm_status1/rate_i_reg_n_0_[22] SLICE_X84Y297 FDRE r g_clock_rate_din[21].i_rate_ngccm_status1/rate_reg[22]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 2.731 34.731 g_clock_rate_din[21].i_rate_ngccm_status1/CLK SLICE_X84Y297 FDRE r g_clock_rate_din[21].i_rate_ngccm_status1/rate_reg[22]/C clock pessimism 0.000 34.731 clock uncertainty -0.205 34.526 SLICE_X84Y297 FDRE (Setup_EFF2_SLICEL_C_D) 0.065 34.591 g_clock_rate_din[21].i_rate_ngccm_status1/rate_reg[22] ------------------------------------------------------------------- required time 34.591 arrival time -33.867 ------------------------------------------------------------------- slack 0.724 Slack (MET) : 0.732ns (required time - arrival time) Source: g_clock_rate_din[23].i_rate_ngccm_status0/rate_i_reg[29]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[23].i_rate_ngccm_status0/rate_reg[29]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (ipb_clk rise@32.000ns - clk250 rise@28.000ns) Data Path Delay: 2.592ns (logic 0.138ns (5.324%) route 2.454ns (94.676%)) Logic Levels: 0 Clock Path Skew: -0.535ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.721ns = ( 34.721 - 32.000 ) Source Clock Delay (SCD): 3.256ns = ( 31.256 - 28.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.256ns (routing 1.281ns, distribution 1.975ns) Clock Net Delay (Destination): 2.721ns (routing 0.546ns, distribution 2.175ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 28.000 28.000 r BUFGCE_X1Y100 BUFGCE 0.000 28.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.256 31.256 g_clock_rate_din[23].i_rate_ngccm_status0/clk250 SLICE_X87Y268 FDRE r g_clock_rate_din[23].i_rate_ngccm_status0/rate_i_reg[29]/C ------------------------------------------------------------------- ------------------- SLICE_X87Y268 FDRE (Prop_CFF_SLICEM_C_Q) 0.138 31.394 r g_clock_rate_din[23].i_rate_ngccm_status0/rate_i_reg[29]/Q net (fo=1, routed) 2.454 33.848 g_clock_rate_din[23].i_rate_ngccm_status0/rate_i_reg_n_0_[29] SLICE_X87Y268 FDRE r g_clock_rate_din[23].i_rate_ngccm_status0/rate_reg[29]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 2.721 34.721 g_clock_rate_din[23].i_rate_ngccm_status0/CLK SLICE_X87Y268 FDRE r g_clock_rate_din[23].i_rate_ngccm_status0/rate_reg[29]/C clock pessimism 0.000 34.721 clock uncertainty -0.205 34.516 SLICE_X87Y268 FDRE (Setup_GFF_SLICEM_C_D) 0.064 34.580 g_clock_rate_din[23].i_rate_ngccm_status0/rate_reg[29] ------------------------------------------------------------------- required time 34.580 arrival time -33.848 ------------------------------------------------------------------- slack 0.732 Slack (MET) : 0.737ns (required time - arrival time) Source: g_clock_rate_din[22].i_rate_ngccm_status1/rate_i_reg[20]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[22].i_rate_ngccm_status1/rate_reg[20]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (ipb_clk rise@32.000ns - clk250 rise@28.000ns) Data Path Delay: 2.590ns (logic 0.137ns (5.290%) route 2.453ns (94.710%)) Logic Levels: 0 Clock Path Skew: -0.532ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.727ns = ( 34.727 - 32.000 ) Source Clock Delay (SCD): 3.259ns = ( 31.259 - 28.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.259ns (routing 1.281ns, distribution 1.978ns) Clock Net Delay (Destination): 2.727ns (routing 0.546ns, distribution 2.181ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 28.000 28.000 r BUFGCE_X1Y100 BUFGCE 0.000 28.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 3.259 31.259 g_clock_rate_din[22].i_rate_ngccm_status1/clk250 SLICE_X88Y298 FDRE r g_clock_rate_din[22].i_rate_ngccm_status1/rate_i_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y298 FDRE (Prop_DFF2_SLICEL_C_Q) 0.137 31.396 r g_clock_rate_din[22].i_rate_ngccm_status1/rate_i_reg[20]/Q net (fo=1, routed) 2.453 33.849 g_clock_rate_din[22].i_rate_ngccm_status1/rate_i_reg_n_0_[20] SLICE_X88Y298 FDRE r g_clock_rate_din[22].i_rate_ngccm_status1/rate_reg[20]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 2.727 34.727 g_clock_rate_din[22].i_rate_ngccm_status1/CLK SLICE_X88Y298 FDRE r g_clock_rate_din[22].i_rate_ngccm_status1/rate_reg[20]/C clock pessimism 0.000 34.727 clock uncertainty -0.205 34.522 SLICE_X88Y298 FDRE (Setup_GFF_SLICEL_C_D) 0.064 34.586 g_clock_rate_din[22].i_rate_ngccm_status1/rate_reg[20] ------------------------------------------------------------------- required time 34.586 arrival time -33.849 ------------------------------------------------------------------- slack 0.737 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.030ns (arrival time - required time) Source: g_clock_rate_din[18].i_rate_ngccm_status2/rate_i_reg[1]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[18].i_rate_ngccm_status2/rate_reg[1]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.398ns (logic 0.049ns (12.312%) route 0.349ns (87.688%)) Logic Levels: 0 Clock Path Skew: 0.107ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.422ns Source Clock Delay (SCD): 1.315ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.315ns (routing 0.481ns, distribution 0.834ns) Clock Net Delay (Destination): 1.422ns (routing 0.225ns, distribution 1.197ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.315 1.315 g_clock_rate_din[18].i_rate_ngccm_status2/clk250 SLICE_X118Y274 FDRE r g_clock_rate_din[18].i_rate_ngccm_status2/rate_i_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y274 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 1.364 r g_clock_rate_din[18].i_rate_ngccm_status2/rate_i_reg[1]/Q net (fo=1, routed) 0.349 1.713 g_clock_rate_din[18].i_rate_ngccm_status2/rate_i_reg_n_0_[1] SLICE_X118Y274 FDRE r g_clock_rate_din[18].i_rate_ngccm_status2/rate_reg[1]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.422 1.422 g_clock_rate_din[18].i_rate_ngccm_status2/CLK SLICE_X118Y274 FDRE r g_clock_rate_din[18].i_rate_ngccm_status2/rate_reg[1]/C clock pessimism 0.000 1.422 clock uncertainty 0.205 1.627 SLICE_X118Y274 FDRE (Hold_EFF_SLICEM_C_D) 0.056 1.683 g_clock_rate_din[18].i_rate_ngccm_status2/rate_reg[1] ------------------------------------------------------------------- required time -1.683 arrival time 1.713 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_clock_rate_din[43].i_rate_ngccm_status2/rate_i_reg[47]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[43].i_rate_ngccm_status2/rate_reg[47]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.397ns (logic 0.048ns (12.091%) route 0.349ns (87.909%)) Logic Levels: 0 Clock Path Skew: 0.106ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.422ns Source Clock Delay (SCD): 1.316ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.316ns (routing 0.481ns, distribution 0.835ns) Clock Net Delay (Destination): 1.422ns (routing 0.225ns, distribution 1.197ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.316 1.316 g_clock_rate_din[43].i_rate_ngccm_status2/clk250 SLICE_X117Y278 FDRE r g_clock_rate_din[43].i_rate_ngccm_status2/rate_i_reg[47]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y278 FDRE (Prop_CFF2_SLICEL_C_Q) 0.048 1.364 r g_clock_rate_din[43].i_rate_ngccm_status2/rate_i_reg[47]/Q net (fo=1, routed) 0.349 1.713 g_clock_rate_din[43].i_rate_ngccm_status2/rate_i_reg_n_0_[47] SLICE_X117Y278 FDRE r g_clock_rate_din[43].i_rate_ngccm_status2/rate_reg[47]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.422 1.422 g_clock_rate_din[43].i_rate_ngccm_status2/CLK SLICE_X117Y278 FDRE r g_clock_rate_din[43].i_rate_ngccm_status2/rate_reg[47]/C clock pessimism 0.000 1.422 clock uncertainty 0.205 1.627 SLICE_X117Y278 FDRE (Hold_GFF2_SLICEL_C_D) 0.056 1.683 g_clock_rate_din[43].i_rate_ngccm_status2/rate_reg[47] ------------------------------------------------------------------- required time -1.683 arrival time 1.713 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_clock_rate_din[45].i_rate_ngccm_status1/rate_i_reg[21]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[45].i_rate_ngccm_status1/rate_reg[21]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.277ns (logic 0.049ns (17.690%) route 0.228ns (82.310%)) Logic Levels: 0 Clock Path Skew: -0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.175ns Source Clock Delay (SCD): 1.189ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.189ns (routing 0.481ns, distribution 0.708ns) Clock Net Delay (Destination): 1.175ns (routing 0.225ns, distribution 0.950ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.189 1.189 g_clock_rate_din[45].i_rate_ngccm_status1/clk250 SLICE_X64Y292 FDRE r g_clock_rate_din[45].i_rate_ngccm_status1/rate_i_reg[21]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y292 FDRE (Prop_AFF_SLICEM_C_Q) 0.049 1.238 r g_clock_rate_din[45].i_rate_ngccm_status1/rate_i_reg[21]/Q net (fo=1, routed) 0.228 1.466 g_clock_rate_din[45].i_rate_ngccm_status1/rate_i_reg_n_0_[21] SLICE_X64Y299 FDRE r g_clock_rate_din[45].i_rate_ngccm_status1/rate_reg[21]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.175 1.175 g_clock_rate_din[45].i_rate_ngccm_status1/CLK SLICE_X64Y299 FDRE r g_clock_rate_din[45].i_rate_ngccm_status1/rate_reg[21]/C clock pessimism 0.000 1.175 clock uncertainty 0.205 1.380 SLICE_X64Y299 FDRE (Hold_EFF_SLICEM_C_D) 0.056 1.436 g_clock_rate_din[45].i_rate_ngccm_status1/rate_reg[21] ------------------------------------------------------------------- required time -1.436 arrival time 1.466 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_clock_rate_din[4].i_rate_test_comm/rate_i_reg[0]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[4].i_rate_test_comm/rate_reg[0]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.413ns (logic 0.049ns (11.864%) route 0.364ns (88.136%)) Logic Levels: 0 Clock Path Skew: 0.122ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.412ns Source Clock Delay (SCD): 1.290ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.290ns (routing 0.481ns, distribution 0.809ns) Clock Net Delay (Destination): 1.412ns (routing 0.225ns, distribution 1.187ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.290 1.290 g_clock_rate_din[4].i_rate_test_comm/clk250 SLICE_X112Y225 FDRE r g_clock_rate_din[4].i_rate_test_comm/rate_i_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y225 FDRE (Prop_DFF2_SLICEM_C_Q) 0.049 1.339 r g_clock_rate_din[4].i_rate_test_comm/rate_i_reg[0]/Q net (fo=1, routed) 0.364 1.703 g_clock_rate_din[4].i_rate_test_comm/rate_i_reg_n_0_[0] SLICE_X112Y225 FDRE r g_clock_rate_din[4].i_rate_test_comm/rate_reg[0]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.412 1.412 g_clock_rate_din[4].i_rate_test_comm/CLK SLICE_X112Y225 FDRE r g_clock_rate_din[4].i_rate_test_comm/rate_reg[0]/C clock pessimism 0.000 1.412 clock uncertainty 0.205 1.617 SLICE_X112Y225 FDRE (Hold_EFF_SLICEM_C_D) 0.056 1.673 g_clock_rate_din[4].i_rate_test_comm/rate_reg[0] ------------------------------------------------------------------- required time -1.673 arrival time 1.703 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_clock_rate_din[13].i_rate_ngccm_status2/rate_i_reg[19]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[13].i_rate_ngccm_status2/rate_reg[19]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.389ns (logic 0.049ns (12.596%) route 0.340ns (87.404%)) Logic Levels: 0 Clock Path Skew: 0.098ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.387ns Source Clock Delay (SCD): 1.289ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.289ns (routing 0.481ns, distribution 0.808ns) Clock Net Delay (Destination): 1.387ns (routing 0.225ns, distribution 1.162ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.289 1.289 g_clock_rate_din[13].i_rate_ngccm_status2/clk250 SLICE_X100Y280 FDRE r g_clock_rate_din[13].i_rate_ngccm_status2/rate_i_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X100Y280 FDRE (Prop_DFF2_SLICEM_C_Q) 0.049 1.338 r g_clock_rate_din[13].i_rate_ngccm_status2/rate_i_reg[19]/Q net (fo=1, routed) 0.340 1.678 g_clock_rate_din[13].i_rate_ngccm_status2/rate_i_reg_n_0_[19] SLICE_X100Y280 FDRE r g_clock_rate_din[13].i_rate_ngccm_status2/rate_reg[19]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.387 1.387 g_clock_rate_din[13].i_rate_ngccm_status2/CLK SLICE_X100Y280 FDRE r g_clock_rate_din[13].i_rate_ngccm_status2/rate_reg[19]/C clock pessimism 0.000 1.387 clock uncertainty 0.205 1.592 SLICE_X100Y280 FDRE (Hold_EFF_SLICEM_C_D) 0.056 1.648 g_clock_rate_din[13].i_rate_ngccm_status2/rate_reg[19] ------------------------------------------------------------------- required time -1.648 arrival time 1.678 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_clock_rate_din[28].i_rate_ngccm_status1/rate_i_reg[33]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[28].i_rate_ngccm_status1/rate_reg[33]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.400ns (logic 0.049ns (12.250%) route 0.351ns (87.750%)) Logic Levels: 0 Clock Path Skew: 0.110ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.272ns Source Clock Delay (SCD): 1.162ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.162ns (routing 0.481ns, distribution 0.681ns) Clock Net Delay (Destination): 1.272ns (routing 0.225ns, distribution 1.047ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.162 1.162 g_clock_rate_din[28].i_rate_ngccm_status1/clk250 SLICE_X82Y242 FDRE r g_clock_rate_din[28].i_rate_ngccm_status1/rate_i_reg[33]/C ------------------------------------------------------------------- ------------------- SLICE_X82Y242 FDRE (Prop_AFF2_SLICEM_C_Q) 0.049 1.211 r g_clock_rate_din[28].i_rate_ngccm_status1/rate_i_reg[33]/Q net (fo=1, routed) 0.351 1.562 g_clock_rate_din[28].i_rate_ngccm_status1/rate_i_reg_n_0_[33] SLICE_X82Y242 FDRE r g_clock_rate_din[28].i_rate_ngccm_status1/rate_reg[33]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.272 1.272 g_clock_rate_din[28].i_rate_ngccm_status1/CLK SLICE_X82Y242 FDRE r g_clock_rate_din[28].i_rate_ngccm_status1/rate_reg[33]/C clock pessimism 0.000 1.272 clock uncertainty 0.205 1.477 SLICE_X82Y242 FDRE (Hold_EFF2_SLICEM_C_D) 0.055 1.532 g_clock_rate_din[28].i_rate_ngccm_status1/rate_reg[33] ------------------------------------------------------------------- required time -1.532 arrival time 1.562 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_clock_rate_din[31].i_rate_ngccm_status1/rate_i_reg[20]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[31].i_rate_ngccm_status1/rate_reg[20]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.398ns (logic 0.049ns (12.312%) route 0.349ns (87.688%)) Logic Levels: 0 Clock Path Skew: 0.108ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.256ns Source Clock Delay (SCD): 1.148ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.148ns (routing 0.481ns, distribution 0.667ns) Clock Net Delay (Destination): 1.256ns (routing 0.225ns, distribution 1.031ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.148 1.148 g_clock_rate_din[31].i_rate_ngccm_status1/clk250 SLICE_X80Y247 FDRE r g_clock_rate_din[31].i_rate_ngccm_status1/rate_i_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y247 FDRE (Prop_EFF_SLICEL_C_Q) 0.049 1.197 r g_clock_rate_din[31].i_rate_ngccm_status1/rate_i_reg[20]/Q net (fo=1, routed) 0.349 1.546 g_clock_rate_din[31].i_rate_ngccm_status1/rate_i_reg_n_0_[20] SLICE_X80Y232 FDRE r g_clock_rate_din[31].i_rate_ngccm_status1/rate_reg[20]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.256 1.256 g_clock_rate_din[31].i_rate_ngccm_status1/CLK SLICE_X80Y232 FDRE r g_clock_rate_din[31].i_rate_ngccm_status1/rate_reg[20]/C clock pessimism 0.000 1.256 clock uncertainty 0.205 1.461 SLICE_X80Y232 FDRE (Hold_FFF2_SLICEL_C_D) 0.055 1.516 g_clock_rate_din[31].i_rate_ngccm_status1/rate_reg[20] ------------------------------------------------------------------- required time -1.516 arrival time 1.546 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_clock_rate_din[38].i_rate_ngccm_status2/rate_i_reg[30]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[38].i_rate_ngccm_status2/rate_reg[30]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.390ns (logic 0.048ns (12.308%) route 0.342ns (87.692%)) Logic Levels: 0 Clock Path Skew: 0.100ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.416ns Source Clock Delay (SCD): 1.316ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.316ns (routing 0.481ns, distribution 0.835ns) Clock Net Delay (Destination): 1.416ns (routing 0.225ns, distribution 1.191ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.316 1.316 g_clock_rate_din[38].i_rate_ngccm_status2/clk250 SLICE_X112Y292 FDRE r g_clock_rate_din[38].i_rate_ngccm_status2/rate_i_reg[30]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y292 FDRE (Prop_CFF_SLICEM_C_Q) 0.048 1.364 r g_clock_rate_din[38].i_rate_ngccm_status2/rate_i_reg[30]/Q net (fo=1, routed) 0.342 1.706 g_clock_rate_din[38].i_rate_ngccm_status2/rate_i_reg_n_0_[30] SLICE_X112Y292 FDRE r g_clock_rate_din[38].i_rate_ngccm_status2/rate_reg[30]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.416 1.416 g_clock_rate_din[38].i_rate_ngccm_status2/CLK SLICE_X112Y292 FDRE r g_clock_rate_din[38].i_rate_ngccm_status2/rate_reg[30]/C clock pessimism 0.000 1.416 clock uncertainty 0.205 1.621 SLICE_X112Y292 FDRE (Hold_FFF2_SLICEM_C_D) 0.055 1.676 g_clock_rate_din[38].i_rate_ngccm_status2/rate_reg[30] ------------------------------------------------------------------- required time -1.676 arrival time 1.706 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_clock_rate_din[43].i_rate_ngccm_status1/rate_i_reg[34]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[43].i_rate_ngccm_status1/rate_reg[34]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.396ns (logic 0.049ns (12.374%) route 0.347ns (87.626%)) Logic Levels: 0 Clock Path Skew: 0.106ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.254ns Source Clock Delay (SCD): 1.148ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.148ns (routing 0.481ns, distribution 0.667ns) Clock Net Delay (Destination): 1.254ns (routing 0.225ns, distribution 1.029ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.148 1.148 g_clock_rate_din[43].i_rate_ngccm_status1/clk250 SLICE_X80Y286 FDRE r g_clock_rate_din[43].i_rate_ngccm_status1/rate_i_reg[34]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y286 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.197 r g_clock_rate_din[43].i_rate_ngccm_status1/rate_i_reg[34]/Q net (fo=1, routed) 0.347 1.544 g_clock_rate_din[43].i_rate_ngccm_status1/rate_i_reg_n_0_[34] SLICE_X80Y286 FDRE r g_clock_rate_din[43].i_rate_ngccm_status1/rate_reg[34]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.254 1.254 g_clock_rate_din[43].i_rate_ngccm_status1/CLK SLICE_X80Y286 FDRE r g_clock_rate_din[43].i_rate_ngccm_status1/rate_reg[34]/C clock pessimism 0.000 1.254 clock uncertainty 0.205 1.459 SLICE_X80Y286 FDRE (Hold_EFF2_SLICEL_C_D) 0.055 1.514 g_clock_rate_din[43].i_rate_ngccm_status1/rate_reg[34] ------------------------------------------------------------------- required time -1.514 arrival time 1.544 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_clock_rate_din[45].i_rate_ngccm_status2/rate_i_reg[15]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[45].i_rate_ngccm_status2/rate_reg[15]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.396ns (logic 0.049ns (12.374%) route 0.347ns (87.626%)) Logic Levels: 0 Clock Path Skew: 0.106ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.426ns Source Clock Delay (SCD): 1.320ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.320ns (routing 0.481ns, distribution 0.839ns) Clock Net Delay (Destination): 1.426ns (routing 0.225ns, distribution 1.201ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y100 BUFGCE 0.000 0.000 r i_clk250_bufg/O X3Y3 (CLOCK_ROOT) net (fo=17714, routed) 1.320 1.320 g_clock_rate_din[45].i_rate_ngccm_status2/clk250 SLICE_X117Y282 FDRE r g_clock_rate_din[45].i_rate_ngccm_status2/rate_i_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y282 FDRE (Prop_AFF2_SLICEL_C_Q) 0.049 1.369 r g_clock_rate_din[45].i_rate_ngccm_status2/rate_i_reg[15]/Q net (fo=1, routed) 0.347 1.716 g_clock_rate_din[45].i_rate_ngccm_status2/rate_i_reg_n_0_[15] SLICE_X117Y282 FDRE r g_clock_rate_din[45].i_rate_ngccm_status2/rate_reg[15]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.426 1.426 g_clock_rate_din[45].i_rate_ngccm_status2/CLK SLICE_X117Y282 FDRE r g_clock_rate_din[45].i_rate_ngccm_status2/rate_reg[15]/C clock pessimism 0.000 1.426 clock uncertainty 0.205 1.631 SLICE_X117Y282 FDRE (Hold_EFF2_SLICEL_C_D) 0.055 1.686 g_clock_rate_din[45].i_rate_ngccm_status2/rate_reg[15] ------------------------------------------------------------------- required time -1.686 arrival time 1.716 ------------------------------------------------------------------- slack 0.030 --------------------------------------------------------------------------------------------------- From Clock: fabric_clk To Clock: tx_wordclk Setup : 0 Failing Endpoints, Worst Slack 1.461ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.030ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.461ns (required time - arrival time) Source: fabric_clk_div2_reg_replica/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: fabric_clk_div2_q_reg[2]_srl3/D (rising edge-triggered cell SRL16E clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - fabric_clk rise@0.000ns) Data Path Delay: 5.511ns (logic 0.139ns (2.522%) route 5.372ns (97.478%)) Logic Levels: 0 Clock Path Skew: -0.605ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.911ns = ( 11.228 - 8.317 ) Source Clock Delay (SCD): 3.516ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Inter-SLR Compensation: 0.437ns (DCD * PF) Destination Clock Delay (DCD): 2.911ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.516ns (routing 0.986ns, distribution 2.530ns) Clock Net Delay (Destination): 2.911ns (routing 0.903ns, distribution 2.008ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.516 3.516 fabric_clk SLR Crossing[0->1] SLICE_X76Y325 FDRE r fabric_clk_div2_reg_replica/C ------------------------------------------------------------------- ------------------- SLICE_X76Y325 FDRE (Prop_EFF_SLICEM_C_Q) 0.139 3.655 r fabric_clk_div2_reg_replica/Q net (fo=51, routed) 5.372 9.027 fabric_clk_div2_bufg_place_replica SLR Crossing[1->0] SLICE_X62Y242 SRL16E r fabric_clk_div2_q_reg[2]_srl3/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 2.911 11.228 tx_wordclk SLICE_X62Y242 SRL16E r fabric_clk_div2_q_reg[2]_srl3/CLK clock pessimism 0.000 11.228 inter-SLR compensation -0.437 10.791 clock uncertainty -0.248 10.543 SLICE_X62Y242 SRL16E (Setup_A6LUT_SLICEM_CLK_D) -0.055 10.488 fabric_clk_div2_q_reg[2]_srl3 ------------------------------------------------------------------- required time 10.488 arrival time -9.027 ------------------------------------------------------------------- slack 1.461 Slack (MET) : 4.122ns (required time - arrival time) Source: SFP_GEN[4].ngCCM_gbt/TX_Word_o_reg[22]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - fabric_clk rise@0.000ns) Data Path Delay: 3.592ns (logic 0.321ns (8.937%) route 3.271ns (91.063%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.421ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.356ns = ( 11.673 - 8.317 ) Source Clock Delay (SCD): 3.777ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.777ns (routing 0.986ns, distribution 2.791ns) Clock Net Delay (Destination): 3.356ns (routing 0.903ns, distribution 2.453ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.777 3.777 SFP_GEN[4].ngCCM_gbt/fabric_clk SLICE_X100Y135 FDRE r SFP_GEN[4].ngCCM_gbt/TX_Word_o_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X100Y135 FDRE (Prop_EFF_SLICEM_C_Q) 0.139 3.916 r SFP_GEN[4].ngCCM_gbt/TX_Word_o_reg[22]/Q net (fo=2, routed) 3.213 7.129 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[1] SLICE_X98Y36 LUT5 (Prop_B5LUT_SLICEL_I1_O) 0.182 7.311 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[20]_i_1__72/O net (fo=1, routed) 0.058 7.369 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[20] SLICE_X98Y36 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.356 11.673 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk SLICE_X98Y36 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]/C clock pessimism 0.000 11.673 clock uncertainty -0.248 11.425 SLICE_X98Y36 FDCE (Setup_BFF2_SLICEL_C_D) 0.066 11.491 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20] ------------------------------------------------------------------- required time 11.491 arrival time -7.369 ------------------------------------------------------------------- slack 4.122 Slack (MET) : 4.178ns (required time - arrival time) Source: SFP_GEN[4].ngCCM_gbt/TX_Word_o_reg[22]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[1]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - fabric_clk rise@0.000ns) Data Path Delay: 3.532ns (logic 0.286ns (8.097%) route 3.246ns (91.903%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.421ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.356ns = ( 11.673 - 8.317 ) Source Clock Delay (SCD): 3.777ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.777ns (routing 0.986ns, distribution 2.791ns) Clock Net Delay (Destination): 3.356ns (routing 0.903ns, distribution 2.453ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.777 3.777 SFP_GEN[4].ngCCM_gbt/fabric_clk SLICE_X100Y135 FDRE r SFP_GEN[4].ngCCM_gbt/TX_Word_o_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X100Y135 FDRE (Prop_EFF_SLICEM_C_Q) 0.139 3.916 r SFP_GEN[4].ngCCM_gbt/TX_Word_o_reg[22]/Q net (fo=2, routed) 3.213 7.129 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[1] SLICE_X98Y36 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.147 7.276 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[1]_i_1__60/O net (fo=1, routed) 0.033 7.309 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[1] SLICE_X98Y36 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[1]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.356 11.673 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk SLICE_X98Y36 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[1]/C clock pessimism 0.000 11.673 clock uncertainty -0.248 11.425 SLICE_X98Y36 FDCE (Setup_BFF_SLICEL_C_D) 0.062 11.487 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time 11.487 arrival time -7.309 ------------------------------------------------------------------- slack 4.178 Slack (MET) : 4.466ns (required time - arrival time) Source: SFP_GEN[6].ngCCM_gbt/TX_Word_o_reg[27]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[6]/D (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - fabric_clk rise@0.000ns) Data Path Delay: 3.290ns (logic 0.384ns (11.672%) route 2.906ns (88.328%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.376ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.359ns = ( 11.676 - 8.317 ) Source Clock Delay (SCD): 3.735ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.735ns (routing 0.986ns, distribution 2.749ns) Clock Net Delay (Destination): 3.359ns (routing 0.903ns, distribution 2.456ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.735 3.735 SFP_GEN[6].ngCCM_gbt/fabric_clk SLICE_X97Y147 FDRE r SFP_GEN[6].ngCCM_gbt/TX_Word_o_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y147 FDRE (Prop_EFF_SLICEM_C_Q) 0.139 3.874 r SFP_GEN[6].ngCCM_gbt/TX_Word_o_reg[27]/Q net (fo=1, routed) 2.875 6.749 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[6] SLICE_X106Y65 LUT3 (Prop_F6LUT_SLICEM_I1_O) 0.245 6.994 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[6]_i_1__36/O net (fo=1, routed) 0.031 7.025 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[6] SLICE_X106Y65 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[6]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.359 11.676 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk SLICE_X106Y65 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[6]/C clock pessimism 0.000 11.676 clock uncertainty -0.248 11.428 SLICE_X106Y65 FDPE (Setup_FFF_SLICEM_C_D) 0.063 11.491 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[6] ------------------------------------------------------------------- required time 11.491 arrival time -7.025 ------------------------------------------------------------------- slack 4.466 Slack (MET) : 4.495ns (required time - arrival time) Source: SFP_GEN[4].ngCCM_gbt/TX_Word_o_reg[19]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[19]/D (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - fabric_clk rise@0.000ns) Data Path Delay: 3.230ns (logic 0.398ns (12.322%) route 2.832ns (87.678%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.409ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.335ns = ( 11.652 - 8.317 ) Source Clock Delay (SCD): 3.744ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.744ns (routing 0.986ns, distribution 2.758ns) Clock Net Delay (Destination): 3.335ns (routing 0.903ns, distribution 2.432ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.744 3.744 SFP_GEN[4].ngCCM_gbt/fabric_clk SLICE_X96Y144 FDRE r SFP_GEN[4].ngCCM_gbt/TX_Word_o_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y144 FDRE (Prop_HFF2_SLICEL_C_Q) 0.137 3.881 r SFP_GEN[4].ngCCM_gbt/TX_Word_o_reg[19]/Q net (fo=1, routed) 2.779 6.660 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[19] SLICE_X96Y34 LUT5 (Prop_A5LUT_SLICEL_I4_O) 0.261 6.921 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[19]_i_1__59/O net (fo=1, routed) 0.053 6.974 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/p_41_out[19] SLICE_X96Y34 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[19]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.335 11.652 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/tx_wordclk SLICE_X96Y34 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[19]/C clock pessimism 0.000 11.652 clock uncertainty -0.248 11.404 SLICE_X96Y34 FDPE (Setup_AFF2_SLICEL_C_D) 0.065 11.469 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[19] ------------------------------------------------------------------- required time 11.469 arrival time -6.974 ------------------------------------------------------------------- slack 4.495 Slack (MET) : 4.695ns (required time - arrival time) Source: SFP_GEN[6].ngCCM_gbt/TX_Word_o_reg[5]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[5]/D (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - fabric_clk rise@0.000ns) Data Path Delay: 3.003ns (logic 0.364ns (12.121%) route 2.639ns (87.879%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.434ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.352ns = ( 11.669 - 8.317 ) Source Clock Delay (SCD): 3.786ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.786ns (routing 0.986ns, distribution 2.800ns) Clock Net Delay (Destination): 3.352ns (routing 0.903ns, distribution 2.449ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.786 3.786 SFP_GEN[6].ngCCM_gbt/fabric_clk SLICE_X103Y62 FDRE r SFP_GEN[6].ngCCM_gbt/TX_Word_o_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X103Y62 FDRE (Prop_GFF_SLICEM_C_Q) 0.139 3.925 r SFP_GEN[6].ngCCM_gbt/TX_Word_o_reg[5]/Q net (fo=1, routed) 2.604 6.529 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]_1[5] SLICE_X106Y62 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.225 6.754 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[5]_i_1__35/O net (fo=1, routed) 0.035 6.789 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/p_41_out[5] SLICE_X106Y62 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[5]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.352 11.669 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/tx_wordclk SLICE_X106Y62 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[5]/C clock pessimism 0.000 11.669 clock uncertainty -0.248 11.421 SLICE_X106Y62 FDPE (Setup_DFF_SLICEM_C_D) 0.063 11.484 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[5] ------------------------------------------------------------------- required time 11.484 arrival time -6.789 ------------------------------------------------------------------- slack 4.695 Slack (MET) : 4.716ns (required time - arrival time) Source: SFP_GEN[35].ngCCM_gbt/TX_Word_o_reg[40]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[19]/D (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - fabric_clk rise@0.000ns) Data Path Delay: 2.936ns (logic 0.373ns (12.704%) route 2.563ns (87.296%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.480ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.299ns = ( 11.616 - 8.317 ) Source Clock Delay (SCD): 3.779ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.779ns (routing 0.986ns, distribution 2.793ns) Clock Net Delay (Destination): 3.299ns (routing 0.903ns, distribution 2.396ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.779 3.779 SFP_GEN[35].ngCCM_gbt/fabric_clk SLICE_X32Y293 FDRE r SFP_GEN[35].ngCCM_gbt/TX_Word_o_reg[40]/C ------------------------------------------------------------------- ------------------- SLICE_X32Y293 FDRE (Prop_FFF2_SLICEL_C_Q) 0.138 3.917 r SFP_GEN[35].ngCCM_gbt/TX_Word_o_reg[40]/Q net (fo=1, routed) 2.526 6.443 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[19] SLICE_X32Y293 LUT5 (Prop_C6LUT_SLICEL_I4_O) 0.235 6.678 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[19]_i_1__240/O net (fo=1, routed) 0.037 6.715 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[19] SLICE_X32Y293 FDPE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[19]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.299 11.616 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk SLICE_X32Y293 FDPE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[19]/C clock pessimism 0.000 11.616 clock uncertainty -0.248 11.368 SLICE_X32Y293 FDPE (Setup_CFF_SLICEL_C_D) 0.063 11.431 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[19] ------------------------------------------------------------------- required time 11.431 arrival time -6.715 ------------------------------------------------------------------- slack 4.716 Slack (MET) : 4.751ns (required time - arrival time) Source: SFP_GEN[18].ngCCM_gbt/TX_Word_o_reg[12]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[12]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - fabric_clk rise@0.000ns) Data Path Delay: 2.926ns (logic 0.373ns (12.748%) route 2.553ns (87.252%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.455ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.085ns = ( 11.402 - 8.317 ) Source Clock Delay (SCD): 3.540ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.540ns (routing 0.986ns, distribution 2.554ns) Clock Net Delay (Destination): 3.085ns (routing 0.903ns, distribution 2.182ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.540 3.540 SFP_GEN[18].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X81Y326 FDRE r SFP_GEN[18].ngCCM_gbt/TX_Word_o_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X81Y326 FDRE (Prop_FFF2_SLICEL_C_Q) 0.138 3.678 r SFP_GEN[18].ngCCM_gbt/TX_Word_o_reg[12]/Q net (fo=1, routed) 2.516 6.194 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]_1[12] SLICE_X81Y326 LUT3 (Prop_C6LUT_SLICEL_I1_O) 0.235 6.429 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[12]_i_1__95/O net (fo=1, routed) 0.037 6.466 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/p_41_out[12] SLICE_X81Y326 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[12]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.085 11.402 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X81Y326 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[12]/C clock pessimism 0.000 11.402 clock uncertainty -0.248 11.154 SLICE_X81Y326 FDCE (Setup_CFF_SLICEL_C_D) 0.063 11.217 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[12] ------------------------------------------------------------------- required time 11.217 arrival time -6.466 ------------------------------------------------------------------- slack 4.751 Slack (MET) : 4.792ns (required time - arrival time) Source: SFP_GEN[12].ngCCM_gbt/TX_Word_o_reg[56]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[14]/D (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - fabric_clk rise@0.000ns) Data Path Delay: 2.938ns (logic 0.383ns (13.036%) route 2.555ns (86.964%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.402ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.362ns = ( 11.679 - 8.317 ) Source Clock Delay (SCD): 3.764ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.764ns (routing 0.986ns, distribution 2.778ns) Clock Net Delay (Destination): 3.362ns (routing 0.903ns, distribution 2.459ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.764 3.764 SFP_GEN[12].ngCCM_gbt/fabric_clk SLICE_X106Y123 FDRE r SFP_GEN[12].ngCCM_gbt/TX_Word_o_reg[56]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y123 FDRE (Prop_EFF_SLICEM_C_Q) 0.139 3.903 r SFP_GEN[12].ngCCM_gbt/TX_Word_o_reg[56]/Q net (fo=1, routed) 2.520 6.423 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[12] SLICE_X106Y123 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.667 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[14]_i_1__165/O net (fo=1, routed) 0.035 6.702 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/p_41_out[14] SLICE_X106Y123 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[14]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.362 11.679 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk SLICE_X106Y123 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[14]/C clock pessimism 0.000 11.679 clock uncertainty -0.248 11.431 SLICE_X106Y123 FDPE (Setup_DFF_SLICEM_C_D) 0.063 11.494 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[14] ------------------------------------------------------------------- required time 11.494 arrival time -6.702 ------------------------------------------------------------------- slack 4.792 Slack (MET) : 4.824ns (required time - arrival time) Source: SFP_GEN[11].ngCCM_gbt/TX_Word_o_reg[59]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[17]/D (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - fabric_clk rise@0.000ns) Data Path Delay: 2.883ns (logic 0.364ns (12.626%) route 2.519ns (87.374%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.424ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.344ns = ( 11.661 - 8.317 ) Source Clock Delay (SCD): 3.768ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.768ns (routing 0.986ns, distribution 2.782ns) Clock Net Delay (Destination): 3.344ns (routing 0.903ns, distribution 2.441ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.768 3.768 SFP_GEN[11].ngCCM_gbt/fabric_clk SLICE_X105Y145 FDRE r SFP_GEN[11].ngCCM_gbt/TX_Word_o_reg[59]/C ------------------------------------------------------------------- ------------------- SLICE_X105Y145 FDRE (Prop_FFF_SLICEL_C_Q) 0.139 3.907 r SFP_GEN[11].ngCCM_gbt/TX_Word_o_reg[59]/Q net (fo=1, routed) 2.485 6.392 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[15] SLICE_X106Y148 LUT3 (Prop_B6LUT_SLICEM_I1_O) 0.225 6.617 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[17]_i_1__73/O net (fo=1, routed) 0.034 6.651 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/p_41_out[17] SLICE_X106Y148 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[17]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.344 11.661 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk SLICE_X106Y148 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[17]/C clock pessimism 0.000 11.661 clock uncertainty -0.248 11.413 SLICE_X106Y148 FDPE (Setup_BFF_SLICEM_C_D) 0.062 11.475 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time 11.475 arrival time -6.651 ------------------------------------------------------------------- slack 4.824 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[22].ngCCM_gbt/TX_Word_o_reg[40]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[19]/D (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.579ns (logic 0.112ns (19.344%) route 0.467ns (80.656%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.245ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.738ns Source Clock Delay (SCD): 1.493ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.493ns (routing 0.373ns, distribution 1.120ns) Clock Net Delay (Destination): 1.738ns (routing 0.411ns, distribution 1.327ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.493 1.493 SFP_GEN[22].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X130Y438 FDRE r SFP_GEN[22].ngCCM_gbt/TX_Word_o_reg[40]/C ------------------------------------------------------------------- ------------------- SLICE_X130Y438 FDRE (Prop_GFF_SLICEL_C_Q) 0.048 1.541 r SFP_GEN[22].ngCCM_gbt/TX_Word_o_reg[40]/Q net (fo=1, routed) 0.451 1.992 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/TX_DATA_I[19] SLICE_X130Y438 LUT5 (Prop_C6LUT_SLICEL_I4_O) 0.064 2.056 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[19]_i_1__124/O net (fo=1, routed) 0.016 2.072 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[19] SLICE_X130Y438 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[19]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.738 1.738 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X130Y438 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[19]/C clock pessimism 0.000 1.738 clock uncertainty 0.248 1.986 SLICE_X130Y438 FDPE (Hold_CFF_SLICEL_C_D) 0.056 2.042 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[19] ------------------------------------------------------------------- required time -2.042 arrival time 2.072 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[23].ngCCM_gbt/TX_Word_o_reg[35]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[14]/D (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.578ns (logic 0.101ns (17.474%) route 0.477ns (82.526%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.244ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.669ns Source Clock Delay (SCD): 1.425ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.425ns (routing 0.373ns, distribution 1.052ns) Clock Net Delay (Destination): 1.669ns (routing 0.411ns, distribution 1.258ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.425 1.425 SFP_GEN[23].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X120Y391 FDRE r SFP_GEN[23].ngCCM_gbt/TX_Word_o_reg[35]/C ------------------------------------------------------------------- ------------------- SLICE_X120Y391 FDRE (Prop_FFF2_SLICEL_C_Q) 0.048 1.473 r SFP_GEN[23].ngCCM_gbt/TX_Word_o_reg[35]/Q net (fo=1, routed) 0.465 1.938 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[14] SLICE_X120Y392 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.053 1.991 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[14]_i_1__156/O net (fo=1, routed) 0.012 2.003 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[14] SLICE_X120Y392 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[14]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.669 1.669 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X120Y392 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[14]/C clock pessimism 0.000 1.669 clock uncertainty 0.248 1.917 SLICE_X120Y392 FDPE (Hold_AFF_SLICEL_C_D) 0.056 1.973 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[14] ------------------------------------------------------------------- required time -1.973 arrival time 2.003 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[13].ngCCM_gbt/TX_Word_o_reg[2]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[2]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.579ns (logic 0.118ns (20.380%) route 0.461ns (79.620%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.245ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.653ns Source Clock Delay (SCD): 1.408ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.408ns (routing 0.373ns, distribution 1.035ns) Clock Net Delay (Destination): 1.653ns (routing 0.411ns, distribution 1.242ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.408 1.408 SFP_GEN[13].ngCCM_gbt/fabric_clk SLICE_X127Y227 FDRE r SFP_GEN[13].ngCCM_gbt/TX_Word_o_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X127Y227 FDRE (Prop_HFF_SLICEL_C_Q) 0.048 1.456 r SFP_GEN[13].ngCCM_gbt/TX_Word_o_reg[2]/Q net (fo=1, routed) 0.445 1.901 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[2] SLICE_X133Y227 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.070 1.971 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[2]_i_1__159/O net (fo=1, routed) 0.016 1.987 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/p_41_out[2] SLICE_X133Y227 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[2]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.653 1.653 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/tx_wordclk SLICE_X133Y227 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[2]/C clock pessimism 0.000 1.653 clock uncertainty 0.248 1.901 SLICE_X133Y227 FDCE (Hold_HFF_SLICEL_C_D) 0.056 1.957 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time -1.957 arrival time 1.987 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[13].ngCCM_gbt/TX_Word_o_reg[60]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[18]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.101ns (17.908%) route 0.463ns (82.092%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.230ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.635ns Source Clock Delay (SCD): 1.405ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.405ns (routing 0.373ns, distribution 1.032ns) Clock Net Delay (Destination): 1.635ns (routing 0.411ns, distribution 1.224ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.405 1.405 SFP_GEN[13].ngCCM_gbt/fabric_clk SLICE_X131Y223 FDRE r SFP_GEN[13].ngCCM_gbt/TX_Word_o_reg[60]/C ------------------------------------------------------------------- ------------------- SLICE_X131Y223 FDRE (Prop_GFF2_SLICEL_C_Q) 0.048 1.453 r SFP_GEN[13].ngCCM_gbt/TX_Word_o_reg[60]/Q net (fo=1, routed) 0.448 1.901 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[16] SLICE_X131Y223 LUT3 (Prop_B6LUT_SLICEL_I2_O) 0.053 1.954 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[18]_i_1__161/O net (fo=1, routed) 0.015 1.969 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/p_41_out[18] SLICE_X131Y223 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[18]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.635 1.635 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk SLICE_X131Y223 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[18]/C clock pessimism 0.000 1.635 clock uncertainty 0.248 1.883 SLICE_X131Y223 FDCE (Hold_BFF_SLICEL_C_D) 0.056 1.939 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -1.939 arrival time 1.969 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[14].ngCCM_gbt/TX_Word_o_reg[37]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[16]/D (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.562ns (logic 0.119ns (21.174%) route 0.443ns (78.826%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.228ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.648ns Source Clock Delay (SCD): 1.420ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.420ns (routing 0.373ns, distribution 1.047ns) Clock Net Delay (Destination): 1.648ns (routing 0.411ns, distribution 1.237ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.420 1.420 SFP_GEN[14].ngCCM_gbt/fabric_clk SLICE_X135Y230 FDRE r SFP_GEN[14].ngCCM_gbt/TX_Word_o_reg[37]/C ------------------------------------------------------------------- ------------------- SLICE_X135Y230 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 1.468 r SFP_GEN[14].ngCCM_gbt/TX_Word_o_reg[37]/Q net (fo=1, routed) 0.428 1.896 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[16] SLICE_X138Y227 LUT3 (Prop_B6LUT_SLICEL_I2_O) 0.071 1.967 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[16]_i_1__152/O net (fo=1, routed) 0.015 1.982 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[16] SLICE_X138Y227 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[16]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.648 1.648 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk SLICE_X138Y227 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[16]/C clock pessimism 0.000 1.648 clock uncertainty 0.248 1.896 SLICE_X138Y227 FDPE (Hold_BFF_SLICEL_C_D) 0.056 1.952 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time -1.952 arrival time 1.982 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[16].ngCCM_gbt/TX_Word_o_reg[12]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[12]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.582ns (logic 0.093ns (15.979%) route 0.489ns (84.021%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.248ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.728ns Source Clock Delay (SCD): 1.480ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.480ns (routing 0.373ns, distribution 1.107ns) Clock Net Delay (Destination): 1.728ns (routing 0.411ns, distribution 1.317ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.480 1.480 SFP_GEN[16].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X130Y379 FDRE r SFP_GEN[16].ngCCM_gbt/TX_Word_o_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X130Y379 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 1.528 r SFP_GEN[16].ngCCM_gbt/TX_Word_o_reg[12]/Q net (fo=1, routed) 0.473 2.001 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[12] SLICE_X133Y379 LUT3 (Prop_C6LUT_SLICEL_I1_O) 0.045 2.046 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[12]_i_1__119/O net (fo=1, routed) 0.016 2.062 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/p_41_out[12] SLICE_X133Y379 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[12]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.728 1.728 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X133Y379 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[12]/C clock pessimism 0.000 1.728 clock uncertainty 0.248 1.976 SLICE_X133Y379 FDCE (Hold_CFF_SLICEL_C_D) 0.056 2.032 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[12] ------------------------------------------------------------------- required time -2.032 arrival time 2.062 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[24].ngCCM_gbt/TX_Word_o_reg[8]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[8]/D (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.579ns (logic 0.101ns (17.444%) route 0.478ns (82.556%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.245ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.687ns Source Clock Delay (SCD): 1.442ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.442ns (routing 0.373ns, distribution 1.069ns) Clock Net Delay (Destination): 1.687ns (routing 0.411ns, distribution 1.276ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.442 1.442 SFP_GEN[24].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X11Y307 FDRE r SFP_GEN[24].ngCCM_gbt/TX_Word_o_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X11Y307 FDRE (Prop_HFF_SLICEM_C_Q) 0.048 1.490 r SFP_GEN[24].ngCCM_gbt/TX_Word_o_reg[8]/Q net (fo=1, routed) 0.464 1.954 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[8] SLICE_X8Y307 LUT3 (Prop_G6LUT_SLICEL_I2_O) 0.053 2.007 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[8]_i_1__283/O net (fo=1, routed) 0.014 2.021 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/p_41_out[8] SLICE_X8Y307 FDPE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[8]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.687 1.687 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X8Y307 FDPE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[8]/C clock pessimism 0.000 1.687 clock uncertainty 0.248 1.935 SLICE_X8Y307 FDPE (Hold_GFF_SLICEL_C_D) 0.056 1.991 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[8] ------------------------------------------------------------------- required time -1.991 arrival time 2.021 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[24].ngCCM_gbt/TX_Word_o_reg[36]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[15]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.592ns (logic 0.119ns (20.101%) route 0.473ns (79.899%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.258ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.690ns Source Clock Delay (SCD): 1.432ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.432ns (routing 0.373ns, distribution 1.059ns) Clock Net Delay (Destination): 1.690ns (routing 0.411ns, distribution 1.279ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.432 1.432 SFP_GEN[24].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X9Y309 FDRE r SFP_GEN[24].ngCCM_gbt/TX_Word_o_reg[36]/C ------------------------------------------------------------------- ------------------- SLICE_X9Y309 FDRE (Prop_HFF_SLICEL_C_Q) 0.048 1.480 r SFP_GEN[24].ngCCM_gbt/TX_Word_o_reg[36]/Q net (fo=1, routed) 0.461 1.941 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[15] SLICE_X8Y307 LUT3 (Prop_A6LUT_SLICEL_I1_O) 0.071 2.012 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[15]_i_1__248/O net (fo=1, routed) 0.012 2.024 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[15] SLICE_X8Y307 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[15]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.690 1.690 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X8Y307 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[15]/C clock pessimism 0.000 1.690 clock uncertainty 0.248 1.938 SLICE_X8Y307 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.994 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[15] ------------------------------------------------------------------- required time -1.994 arrival time 2.024 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[37].ngCCM_gbt/TX_Word_o_reg[80]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[17]/D (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.641ns (logic 0.113ns (17.629%) route 0.528ns (82.371%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.307ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.709ns Source Clock Delay (SCD): 1.402ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.402ns (routing 0.373ns, distribution 1.029ns) Clock Net Delay (Destination): 1.709ns (routing 0.411ns, distribution 1.298ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.402 1.402 SFP_GEN[37].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X26Y404 FDRE r SFP_GEN[37].ngCCM_gbt/TX_Word_o_reg[80]/C ------------------------------------------------------------------- ------------------- SLICE_X26Y404 FDRE (Prop_EFF_SLICEL_C_Q) 0.049 1.451 r SFP_GEN[37].ngCCM_gbt/TX_Word_o_reg[80]/Q net (fo=1, routed) 0.512 1.963 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20]_2[13] SLICE_X8Y421 LUT3 (Prop_C6LUT_SLICEL_I1_O) 0.064 2.027 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister[17]_i_1__330/O net (fo=1, routed) 0.016 2.043 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/p_41_out[17] SLICE_X8Y421 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[17]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.709 1.709 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X8Y421 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[17]/C clock pessimism 0.000 1.709 clock uncertainty 0.248 1.957 SLICE_X8Y421 FDPE (Hold_CFF_SLICEL_C_D) 0.056 2.013 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time -2.013 arrival time 2.043 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[39].ngCCM_gbt/TX_Word_o_reg[80]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[17]/D (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.570ns (logic 0.063ns (11.053%) route 0.507ns (88.947%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.236ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.645ns Source Clock Delay (SCD): 1.409ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.409ns (routing 0.373ns, distribution 1.036ns) Clock Net Delay (Destination): 1.645ns (routing 0.411ns, distribution 1.234ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.409 1.409 SFP_GEN[39].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X37Y432 FDRE r SFP_GEN[39].ngCCM_gbt/TX_Word_o_reg[80]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y432 FDRE (Prop_CFF2_SLICEM_C_Q) 0.048 1.457 r SFP_GEN[39].ngCCM_gbt/TX_Word_o_reg[80]/Q net (fo=1, routed) 0.491 1.948 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20]_2[13] SLICE_X21Y451 LUT3 (Prop_C6LUT_SLICEL_I1_O) 0.015 1.963 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister[17]_i_1__318/O net (fo=1, routed) 0.016 1.979 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/p_41_out[17] SLICE_X21Y451 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[17]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.645 1.645 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X21Y451 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[17]/C clock pessimism 0.000 1.645 clock uncertainty 0.248 1.893 SLICE_X21Y451 FDPE (Hold_CFF_SLICEL_C_D) 0.056 1.949 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time -1.949 arrival time 1.979 ------------------------------------------------------------------- slack 0.030 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: DRPclk To Clock: DRPclk Setup : 0 Failing Endpoints, Worst Slack 15.473ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.222ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 15.473ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE (recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 4.198ns (logic 0.362ns (8.623%) route 3.836ns (91.377%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.157ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.954ns = ( 22.954 - 20.000 ) Source Clock Delay (SCD): 3.391ns Clock Pessimism Removal (CPR): 0.280ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.391ns (routing 0.987ns, distribution 2.404ns) Clock Net Delay (Destination): 2.954ns (routing 0.904ns, distribution 2.050ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.391 3.391 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/DRPclk SLR Crossing[0->1] SLICE_X79Y419 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X79Y419 FDRE (Prop_HFF_SLICEM_C_Q) 0.138 3.529 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/Q net (fo=2, routed) 1.835 5.364 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_out SLICE_X106Y439 LUT2 (Prop_A6LUT_SLICEM_I1_O) 0.224 5.588 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__11/O net (fo=10, routed) 2.001 7.589 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X81Y419 FDPE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y114 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 2.954 22.954 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X81Y419 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C clock pessimism 0.280 23.234 clock uncertainty -0.079 23.155 SLICE_X81Y419 FDPE (Recov_AFF_SLICEL_C_PRE) -0.093 23.062 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg ------------------------------------------------------------------- required time 23.062 arrival time -7.589 ------------------------------------------------------------------- slack 15.473 Slack (MET) : 15.481ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE (recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 4.188ns (logic 0.362ns (8.644%) route 3.826ns (91.356%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.952ns = ( 22.952 - 20.000 ) Source Clock Delay (SCD): 3.391ns Clock Pessimism Removal (CPR): 0.280ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.391ns (routing 0.987ns, distribution 2.404ns) Clock Net Delay (Destination): 2.952ns (routing 0.904ns, distribution 2.048ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.391 3.391 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/DRPclk SLR Crossing[0->1] SLICE_X79Y419 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X79Y419 FDRE (Prop_HFF_SLICEM_C_Q) 0.138 3.529 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/Q net (fo=2, routed) 1.835 5.364 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_out SLICE_X106Y439 LUT2 (Prop_A6LUT_SLICEM_I1_O) 0.224 5.588 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__11/O net (fo=10, routed) 1.991 7.579 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X81Y419 FDPE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y114 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 2.952 22.952 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X81Y419 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/C clock pessimism 0.280 23.232 clock uncertainty -0.079 23.153 SLICE_X81Y419 FDPE (Recov_HFF2_SLICEL_C_PRE) -0.093 23.060 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg ------------------------------------------------------------------- required time 23.060 arrival time -7.579 ------------------------------------------------------------------- slack 15.481 Slack (MET) : 15.481ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE (recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 4.188ns (logic 0.362ns (8.644%) route 3.826ns (91.356%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.952ns = ( 22.952 - 20.000 ) Source Clock Delay (SCD): 3.391ns Clock Pessimism Removal (CPR): 0.280ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.391ns (routing 0.987ns, distribution 2.404ns) Clock Net Delay (Destination): 2.952ns (routing 0.904ns, distribution 2.048ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.391 3.391 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/DRPclk SLR Crossing[0->1] SLICE_X79Y419 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X79Y419 FDRE (Prop_HFF_SLICEM_C_Q) 0.138 3.529 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/Q net (fo=2, routed) 1.835 5.364 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_out SLICE_X106Y439 LUT2 (Prop_A6LUT_SLICEM_I1_O) 0.224 5.588 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__11/O net (fo=10, routed) 1.991 7.579 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X81Y419 FDPE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y114 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 2.952 22.952 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X81Y419 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/C clock pessimism 0.280 23.232 clock uncertainty -0.079 23.153 SLICE_X81Y419 FDPE (Recov_EFF2_SLICEL_C_PRE) -0.093 23.060 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg ------------------------------------------------------------------- required time 23.060 arrival time -7.579 ------------------------------------------------------------------- slack 15.481 Slack (MET) : 15.481ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE (recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 4.188ns (logic 0.362ns (8.644%) route 3.826ns (91.356%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.952ns = ( 22.952 - 20.000 ) Source Clock Delay (SCD): 3.391ns Clock Pessimism Removal (CPR): 0.280ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.391ns (routing 0.987ns, distribution 2.404ns) Clock Net Delay (Destination): 2.952ns (routing 0.904ns, distribution 2.048ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.391 3.391 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/DRPclk SLR Crossing[0->1] SLICE_X79Y419 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X79Y419 FDRE (Prop_HFF_SLICEM_C_Q) 0.138 3.529 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/Q net (fo=2, routed) 1.835 5.364 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_out SLICE_X106Y439 LUT2 (Prop_A6LUT_SLICEM_I1_O) 0.224 5.588 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__11/O net (fo=10, routed) 1.991 7.579 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X81Y419 FDPE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y114 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 2.952 22.952 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X81Y419 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/C clock pessimism 0.280 23.232 clock uncertainty -0.079 23.153 SLICE_X81Y419 FDPE (Recov_FFF2_SLICEL_C_PRE) -0.093 23.060 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg ------------------------------------------------------------------- required time 23.060 arrival time -7.579 ------------------------------------------------------------------- slack 15.481 Slack (MET) : 15.481ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE (recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 4.188ns (logic 0.362ns (8.644%) route 3.826ns (91.356%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.952ns = ( 22.952 - 20.000 ) Source Clock Delay (SCD): 3.391ns Clock Pessimism Removal (CPR): 0.280ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.391ns (routing 0.987ns, distribution 2.404ns) Clock Net Delay (Destination): 2.952ns (routing 0.904ns, distribution 2.048ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.391 3.391 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/DRPclk SLR Crossing[0->1] SLICE_X79Y419 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X79Y419 FDRE (Prop_HFF_SLICEM_C_Q) 0.138 3.529 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/Q net (fo=2, routed) 1.835 5.364 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_out SLICE_X106Y439 LUT2 (Prop_A6LUT_SLICEM_I1_O) 0.224 5.588 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__11/O net (fo=10, routed) 1.991 7.579 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X81Y419 FDPE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y114 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 2.952 22.952 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X81Y419 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C clock pessimism 0.280 23.232 clock uncertainty -0.079 23.153 SLICE_X81Y419 FDPE (Recov_GFF2_SLICEL_C_PRE) -0.093 23.060 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg ------------------------------------------------------------------- required time 23.060 arrival time -7.579 ------------------------------------------------------------------- slack 15.481 Slack (MET) : 16.528ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE (recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 3.188ns (logic 0.310ns (9.724%) route 2.878ns (90.276%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.112ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.341ns = ( 23.341 - 20.000 ) Source Clock Delay (SCD): 3.850ns Clock Pessimism Removal (CPR): 0.397ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.850ns (routing 0.987ns, distribution 2.863ns) Clock Net Delay (Destination): 3.341ns (routing 0.904ns, distribution 2.437ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.850 3.850 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/DRPclk SLICE_X132Y237 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y237 FDRE (Prop_DFF_SLICEL_C_Q) 0.139 3.989 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/Q net (fo=2, routed) 1.198 5.187 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_11 SLICE_X115Y218 LUT2 (Prop_D5LUT_SLICEM_I1_O) 0.171 5.358 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3/O net (fo=10, routed) 1.680 7.038 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X132Y232 FDPE f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y114 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.341 23.341 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X132Y232 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/C clock pessimism 0.397 23.738 clock uncertainty -0.079 23.659 SLICE_X132Y232 FDPE (Recov_DFF2_SLICEL_C_PRE) -0.093 23.566 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg ------------------------------------------------------------------- required time 23.566 arrival time -7.038 ------------------------------------------------------------------- slack 16.528 Slack (MET) : 16.528ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE (recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 3.188ns (logic 0.310ns (9.724%) route 2.878ns (90.276%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.112ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.341ns = ( 23.341 - 20.000 ) Source Clock Delay (SCD): 3.850ns Clock Pessimism Removal (CPR): 0.397ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.850ns (routing 0.987ns, distribution 2.863ns) Clock Net Delay (Destination): 3.341ns (routing 0.904ns, distribution 2.437ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.850 3.850 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/DRPclk SLICE_X132Y237 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y237 FDRE (Prop_DFF_SLICEL_C_Q) 0.139 3.989 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/Q net (fo=2, routed) 1.198 5.187 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_11 SLICE_X115Y218 LUT2 (Prop_D5LUT_SLICEM_I1_O) 0.171 5.358 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3/O net (fo=10, routed) 1.680 7.038 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X132Y232 FDPE f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y114 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.341 23.341 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X132Y232 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/C clock pessimism 0.397 23.738 clock uncertainty -0.079 23.659 SLICE_X132Y232 FDPE (Recov_AFF2_SLICEL_C_PRE) -0.093 23.566 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg ------------------------------------------------------------------- required time 23.566 arrival time -7.038 ------------------------------------------------------------------- slack 16.528 Slack (MET) : 16.528ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE (recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 3.188ns (logic 0.310ns (9.724%) route 2.878ns (90.276%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.112ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.341ns = ( 23.341 - 20.000 ) Source Clock Delay (SCD): 3.850ns Clock Pessimism Removal (CPR): 0.397ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.850ns (routing 0.987ns, distribution 2.863ns) Clock Net Delay (Destination): 3.341ns (routing 0.904ns, distribution 2.437ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.850 3.850 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/DRPclk SLICE_X132Y237 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y237 FDRE (Prop_DFF_SLICEL_C_Q) 0.139 3.989 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/Q net (fo=2, routed) 1.198 5.187 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_11 SLICE_X115Y218 LUT2 (Prop_D5LUT_SLICEM_I1_O) 0.171 5.358 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3/O net (fo=10, routed) 1.680 7.038 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X132Y232 FDPE f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y114 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.341 23.341 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X132Y232 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/C clock pessimism 0.397 23.738 clock uncertainty -0.079 23.659 SLICE_X132Y232 FDPE (Recov_BFF2_SLICEL_C_PRE) -0.093 23.566 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg ------------------------------------------------------------------- required time 23.566 arrival time -7.038 ------------------------------------------------------------------- slack 16.528 Slack (MET) : 16.528ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE (recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 3.188ns (logic 0.310ns (9.724%) route 2.878ns (90.276%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.112ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.341ns = ( 23.341 - 20.000 ) Source Clock Delay (SCD): 3.850ns Clock Pessimism Removal (CPR): 0.397ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.850ns (routing 0.987ns, distribution 2.863ns) Clock Net Delay (Destination): 3.341ns (routing 0.904ns, distribution 2.437ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.850 3.850 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/DRPclk SLICE_X132Y237 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y237 FDRE (Prop_DFF_SLICEL_C_Q) 0.139 3.989 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/Q net (fo=2, routed) 1.198 5.187 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_11 SLICE_X115Y218 LUT2 (Prop_D5LUT_SLICEM_I1_O) 0.171 5.358 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3/O net (fo=10, routed) 1.680 7.038 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X132Y232 FDPE f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y114 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.341 23.341 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X132Y232 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C clock pessimism 0.397 23.738 clock uncertainty -0.079 23.659 SLICE_X132Y232 FDPE (Recov_CFF2_SLICEL_C_PRE) -0.093 23.566 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg ------------------------------------------------------------------- required time 23.566 arrival time -7.038 ------------------------------------------------------------------- slack 16.528 Slack (MET) : 16.536ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE (recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 3.178ns (logic 0.310ns (9.755%) route 2.868ns (90.245%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.339ns = ( 23.339 - 20.000 ) Source Clock Delay (SCD): 3.850ns Clock Pessimism Removal (CPR): 0.397ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.850ns (routing 0.987ns, distribution 2.863ns) Clock Net Delay (Destination): 3.339ns (routing 0.904ns, distribution 2.435ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.850 3.850 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/DRPclk SLICE_X132Y237 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y237 FDRE (Prop_DFF_SLICEL_C_Q) 0.139 3.989 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/Q net (fo=2, routed) 1.198 5.187 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_11 SLICE_X115Y218 LUT2 (Prop_D5LUT_SLICEM_I1_O) 0.171 5.358 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3/O net (fo=10, routed) 1.670 7.028 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X132Y232 FDPE f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y114 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 3.339 23.339 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X132Y232 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C clock pessimism 0.397 23.736 clock uncertainty -0.079 23.657 SLICE_X132Y232 FDPE (Recov_EFF_SLICEL_C_PRE) -0.093 23.564 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg ------------------------------------------------------------------- required time 23.564 arrival time -7.028 ------------------------------------------------------------------- slack 16.536 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.222ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE (removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.277ns (logic 0.079ns (28.520%) route 0.198ns (71.480%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.626ns Source Clock Delay (SCD): 1.395ns Clock Pessimism Removal (CPR): 0.181ns Clock Net Delay (Source): 1.395ns (routing 0.371ns, distribution 1.024ns) Clock Net Delay (Destination): 1.626ns (routing 0.412ns, distribution 1.214ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.395 1.395 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/DRPclk SLICE_X36Y177 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X36Y177 FDRE (Prop_BFF_SLICEL_C_Q) 0.049 1.444 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/Q net (fo=2, routed) 0.070 1.514 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_4 SLICE_X36Y178 LUT2 (Prop_D6LUT_SLICEL_I1_O) 0.030 1.544 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__27/O net (fo=10, routed) 0.128 1.672 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X35Y178 FDPE f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.626 1.626 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X35Y178 FDPE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/C clock pessimism -0.181 1.445 SLICE_X35Y178 FDPE (Remov_HFF2_SLICEM_C_PRE) 0.005 1.450 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg ------------------------------------------------------------------- required time -1.450 arrival time 1.672 ------------------------------------------------------------------- slack 0.222 Slack (MET) : 0.222ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE (removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.277ns (logic 0.079ns (28.520%) route 0.198ns (71.480%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.626ns Source Clock Delay (SCD): 1.395ns Clock Pessimism Removal (CPR): 0.181ns Clock Net Delay (Source): 1.395ns (routing 0.371ns, distribution 1.024ns) Clock Net Delay (Destination): 1.626ns (routing 0.412ns, distribution 1.214ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.395 1.395 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/DRPclk SLICE_X36Y177 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X36Y177 FDRE (Prop_BFF_SLICEL_C_Q) 0.049 1.444 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/Q net (fo=2, routed) 0.070 1.514 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_4 SLICE_X36Y178 LUT2 (Prop_D6LUT_SLICEL_I1_O) 0.030 1.544 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__27/O net (fo=10, routed) 0.128 1.672 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X35Y178 FDPE f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.626 1.626 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X35Y178 FDPE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C clock pessimism -0.181 1.445 SLICE_X35Y178 FDPE (Remov_EFF_SLICEM_C_PRE) 0.005 1.450 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg ------------------------------------------------------------------- required time -1.450 arrival time 1.672 ------------------------------------------------------------------- slack 0.222 Slack (MET) : 0.222ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE (removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.277ns (logic 0.079ns (28.520%) route 0.198ns (71.480%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.626ns Source Clock Delay (SCD): 1.395ns Clock Pessimism Removal (CPR): 0.181ns Clock Net Delay (Source): 1.395ns (routing 0.371ns, distribution 1.024ns) Clock Net Delay (Destination): 1.626ns (routing 0.412ns, distribution 1.214ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.395 1.395 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/DRPclk SLICE_X36Y177 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X36Y177 FDRE (Prop_BFF_SLICEL_C_Q) 0.049 1.444 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/Q net (fo=2, routed) 0.070 1.514 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_4 SLICE_X36Y178 LUT2 (Prop_D6LUT_SLICEL_I1_O) 0.030 1.544 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__27/O net (fo=10, routed) 0.128 1.672 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X35Y178 FDPE f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.626 1.626 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X35Y178 FDPE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/C clock pessimism -0.181 1.445 SLICE_X35Y178 FDPE (Remov_EFF2_SLICEM_C_PRE) 0.005 1.450 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg ------------------------------------------------------------------- required time -1.450 arrival time 1.672 ------------------------------------------------------------------- slack 0.222 Slack (MET) : 0.222ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE (removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.277ns (logic 0.079ns (28.520%) route 0.198ns (71.480%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.626ns Source Clock Delay (SCD): 1.395ns Clock Pessimism Removal (CPR): 0.181ns Clock Net Delay (Source): 1.395ns (routing 0.371ns, distribution 1.024ns) Clock Net Delay (Destination): 1.626ns (routing 0.412ns, distribution 1.214ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.395 1.395 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/DRPclk SLICE_X36Y177 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X36Y177 FDRE (Prop_BFF_SLICEL_C_Q) 0.049 1.444 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/Q net (fo=2, routed) 0.070 1.514 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_4 SLICE_X36Y178 LUT2 (Prop_D6LUT_SLICEL_I1_O) 0.030 1.544 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__27/O net (fo=10, routed) 0.128 1.672 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X35Y178 FDPE f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.626 1.626 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X35Y178 FDPE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/C clock pessimism -0.181 1.445 SLICE_X35Y178 FDPE (Remov_FFF2_SLICEM_C_PRE) 0.005 1.450 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg ------------------------------------------------------------------- required time -1.450 arrival time 1.672 ------------------------------------------------------------------- slack 0.222 Slack (MET) : 0.222ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE (removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.277ns (logic 0.079ns (28.520%) route 0.198ns (71.480%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.626ns Source Clock Delay (SCD): 1.395ns Clock Pessimism Removal (CPR): 0.181ns Clock Net Delay (Source): 1.395ns (routing 0.371ns, distribution 1.024ns) Clock Net Delay (Destination): 1.626ns (routing 0.412ns, distribution 1.214ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.395 1.395 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/DRPclk SLICE_X36Y177 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X36Y177 FDRE (Prop_BFF_SLICEL_C_Q) 0.049 1.444 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/Q net (fo=2, routed) 0.070 1.514 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_4 SLICE_X36Y178 LUT2 (Prop_D6LUT_SLICEL_I1_O) 0.030 1.544 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__27/O net (fo=10, routed) 0.128 1.672 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X35Y178 FDPE f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.626 1.626 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X35Y178 FDPE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C clock pessimism -0.181 1.445 SLICE_X35Y178 FDPE (Remov_GFF2_SLICEM_C_PRE) 0.005 1.450 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg ------------------------------------------------------------------- required time -1.450 arrival time 1.672 ------------------------------------------------------------------- slack 0.222 Slack (MET) : 0.241ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE (removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.337ns (logic 0.089ns (26.409%) route 0.248ns (73.590%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.676ns Source Clock Delay (SCD): 1.430ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 1.430ns (routing 0.371ns, distribution 1.059ns) Clock Net Delay (Destination): 1.676ns (routing 0.412ns, distribution 1.264ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.430 1.430 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/DRPclk SLR Crossing[0->1] SLICE_X44Y438 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X44Y438 FDRE (Prop_BFF_SLICEM_C_Q) 0.049 1.479 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/Q net (fo=2, routed) 0.080 1.559 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_1 SLICE_X42Y438 LUT2 (Prop_D5LUT_SLICEM_I1_O) 0.040 1.599 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__36/O net (fo=10, routed) 0.168 1.767 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X42Y438 FDPE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.676 1.676 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X42Y438 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/C clock pessimism -0.155 1.521 SLICE_X42Y438 FDPE (Remov_DFF2_SLICEM_C_PRE) 0.005 1.526 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg ------------------------------------------------------------------- required time -1.526 arrival time 1.767 ------------------------------------------------------------------- slack 0.241 Slack (MET) : 0.241ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE (removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.337ns (logic 0.089ns (26.409%) route 0.248ns (73.590%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.676ns Source Clock Delay (SCD): 1.430ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 1.430ns (routing 0.371ns, distribution 1.059ns) Clock Net Delay (Destination): 1.676ns (routing 0.412ns, distribution 1.264ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.430 1.430 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/DRPclk SLR Crossing[0->1] SLICE_X44Y438 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X44Y438 FDRE (Prop_BFF_SLICEM_C_Q) 0.049 1.479 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/Q net (fo=2, routed) 0.080 1.559 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_1 SLICE_X42Y438 LUT2 (Prop_D5LUT_SLICEM_I1_O) 0.040 1.599 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__36/O net (fo=10, routed) 0.168 1.767 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X42Y438 FDPE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.676 1.676 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X42Y438 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/C clock pessimism -0.155 1.521 SLICE_X42Y438 FDPE (Remov_AFF2_SLICEM_C_PRE) 0.005 1.526 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg ------------------------------------------------------------------- required time -1.526 arrival time 1.767 ------------------------------------------------------------------- slack 0.241 Slack (MET) : 0.241ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE (removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.337ns (logic 0.089ns (26.409%) route 0.248ns (73.590%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.676ns Source Clock Delay (SCD): 1.430ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 1.430ns (routing 0.371ns, distribution 1.059ns) Clock Net Delay (Destination): 1.676ns (routing 0.412ns, distribution 1.264ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.430 1.430 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/DRPclk SLR Crossing[0->1] SLICE_X44Y438 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X44Y438 FDRE (Prop_BFF_SLICEM_C_Q) 0.049 1.479 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/Q net (fo=2, routed) 0.080 1.559 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_1 SLICE_X42Y438 LUT2 (Prop_D5LUT_SLICEM_I1_O) 0.040 1.599 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__36/O net (fo=10, routed) 0.168 1.767 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X42Y438 FDPE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.676 1.676 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X42Y438 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/C clock pessimism -0.155 1.521 SLICE_X42Y438 FDPE (Remov_BFF2_SLICEM_C_PRE) 0.005 1.526 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg ------------------------------------------------------------------- required time -1.526 arrival time 1.767 ------------------------------------------------------------------- slack 0.241 Slack (MET) : 0.241ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE (removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.337ns (logic 0.089ns (26.409%) route 0.248ns (73.590%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.676ns Source Clock Delay (SCD): 1.430ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 1.430ns (routing 0.371ns, distribution 1.059ns) Clock Net Delay (Destination): 1.676ns (routing 0.412ns, distribution 1.264ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.430 1.430 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/DRPclk SLR Crossing[0->1] SLICE_X44Y438 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X44Y438 FDRE (Prop_BFF_SLICEM_C_Q) 0.049 1.479 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/Q net (fo=2, routed) 0.080 1.559 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_1 SLICE_X42Y438 LUT2 (Prop_D5LUT_SLICEM_I1_O) 0.040 1.599 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__36/O net (fo=10, routed) 0.168 1.767 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X42Y438 FDPE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.676 1.676 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X42Y438 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C clock pessimism -0.155 1.521 SLICE_X42Y438 FDPE (Remov_CFF2_SLICEM_C_PRE) 0.005 1.526 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg ------------------------------------------------------------------- required time -1.526 arrival time 1.767 ------------------------------------------------------------------- slack 0.241 Slack (MET) : 0.242ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE (removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.339ns (logic 0.089ns (26.254%) route 0.250ns (73.746%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.092ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.677ns Source Clock Delay (SCD): 1.430ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 1.430ns (routing 0.371ns, distribution 1.059ns) Clock Net Delay (Destination): 1.677ns (routing 0.412ns, distribution 1.265ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.430 1.430 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/DRPclk SLR Crossing[0->1] SLICE_X44Y438 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X44Y438 FDRE (Prop_BFF_SLICEM_C_Q) 0.049 1.479 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/Q net (fo=2, routed) 0.080 1.559 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_1 SLICE_X42Y438 LUT2 (Prop_D5LUT_SLICEM_I1_O) 0.040 1.599 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__36/O net (fo=10, routed) 0.170 1.769 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X43Y438 FDPE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y114 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3888, routed) 1.677 1.677 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X43Y438 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C clock pessimism -0.155 1.522 SLICE_X43Y438 FDPE (Remov_AFF_SLICEL_C_PRE) 0.005 1.527 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg ------------------------------------------------------------------- required time -1.527 arrival time 1.769 ------------------------------------------------------------------- slack 0.242 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: TTC_rxusrclk To Clock: TTC_rxusrclk Setup : 0 Failing Endpoints, Worst Slack 0.150ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.132ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.150ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[186]/CLR (recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.807ns (logic 0.140ns (4.988%) route 2.667ns (95.012%)) Logic Levels: 0 Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.692ns = ( 6.811 - 3.119 ) Source Clock Delay (SCD): 3.883ns Clock Pessimism Removal (CPR): 0.157ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.883ns (routing 1.620ns, distribution 2.263ns) Clock Net Delay (Destination): 3.692ns (routing 1.478ns, distribution 2.214ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.883 3.883 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X101Y80 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X101Y80 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 4.023 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.667 6.690 i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i SLICE_X137Y42 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[186]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y1 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.692 6.811 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X137Y42 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[186]/C clock pessimism 0.157 6.968 clock uncertainty -0.035 6.933 SLICE_X137Y42 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 6.840 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[186] ------------------------------------------------------------------- required time 6.840 arrival time -6.690 ------------------------------------------------------------------- slack 0.150 Slack (MET) : 0.150ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[188]/CLR (recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.807ns (logic 0.140ns (4.988%) route 2.667ns (95.012%)) Logic Levels: 0 Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.692ns = ( 6.811 - 3.119 ) Source Clock Delay (SCD): 3.883ns Clock Pessimism Removal (CPR): 0.157ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.883ns (routing 1.620ns, distribution 2.263ns) Clock Net Delay (Destination): 3.692ns (routing 1.478ns, distribution 2.214ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.883 3.883 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X101Y80 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X101Y80 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 4.023 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.667 6.690 i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i SLICE_X137Y42 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[188]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y1 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.692 6.811 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X137Y42 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[188]/C clock pessimism 0.157 6.968 clock uncertainty -0.035 6.933 SLICE_X137Y42 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 6.840 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[188] ------------------------------------------------------------------- required time 6.840 arrival time -6.690 ------------------------------------------------------------------- slack 0.150 Slack (MET) : 0.150ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[37]/CLR (recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.807ns (logic 0.140ns (4.988%) route 2.667ns (95.012%)) Logic Levels: 0 Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.692ns = ( 6.811 - 3.119 ) Source Clock Delay (SCD): 3.883ns Clock Pessimism Removal (CPR): 0.157ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.883ns (routing 1.620ns, distribution 2.263ns) Clock Net Delay (Destination): 3.692ns (routing 1.478ns, distribution 2.214ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.883 3.883 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X101Y80 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X101Y80 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 4.023 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.667 6.690 i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i SLICE_X137Y42 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[37]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y1 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.692 6.811 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X137Y42 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[37]/C clock pessimism 0.157 6.968 clock uncertainty -0.035 6.933 SLICE_X137Y42 FDCE (Recov_FFF_SLICEL_C_CLR) -0.093 6.840 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[37] ------------------------------------------------------------------- required time 6.840 arrival time -6.690 ------------------------------------------------------------------- slack 0.150 Slack (MET) : 0.150ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[79]/CLR (recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.807ns (logic 0.140ns (4.988%) route 2.667ns (95.012%)) Logic Levels: 0 Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.692ns = ( 6.811 - 3.119 ) Source Clock Delay (SCD): 3.883ns Clock Pessimism Removal (CPR): 0.157ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.883ns (routing 1.620ns, distribution 2.263ns) Clock Net Delay (Destination): 3.692ns (routing 1.478ns, distribution 2.214ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.883 3.883 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X101Y80 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X101Y80 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 4.023 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.667 6.690 i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i SLICE_X137Y42 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[79]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y1 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.692 6.811 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X137Y42 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[79]/C clock pessimism 0.157 6.968 clock uncertainty -0.035 6.933 SLICE_X137Y42 FDCE (Recov_FFF2_SLICEL_C_CLR) -0.093 6.840 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[79] ------------------------------------------------------------------- required time 6.840 arrival time -6.690 ------------------------------------------------------------------- slack 0.150 Slack (MET) : 0.152ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[121]/CLR (recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.823ns (logic 0.140ns (4.959%) route 2.683ns (95.041%)) Logic Levels: 0 Clock Path Skew: -0.016ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.710ns = ( 6.829 - 3.119 ) Source Clock Delay (SCD): 3.883ns Clock Pessimism Removal (CPR): 0.157ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.883ns (routing 1.620ns, distribution 2.263ns) Clock Net Delay (Destination): 3.710ns (routing 1.478ns, distribution 2.232ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.883 3.883 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X101Y80 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X101Y80 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 4.023 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.683 6.706 i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i SLICE_X138Y33 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[121]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y1 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.710 6.829 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X138Y33 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[121]/C clock pessimism 0.157 6.986 clock uncertainty -0.035 6.951 SLICE_X138Y33 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 6.858 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[121] ------------------------------------------------------------------- required time 6.858 arrival time -6.706 ------------------------------------------------------------------- slack 0.152 Slack (MET) : 0.154ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[111]/CLR (recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.826ns (logic 0.140ns (4.954%) route 2.686ns (95.046%)) Logic Levels: 0 Clock Path Skew: -0.011ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.715ns = ( 6.834 - 3.119 ) Source Clock Delay (SCD): 3.883ns Clock Pessimism Removal (CPR): 0.157ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.883ns (routing 1.620ns, distribution 2.263ns) Clock Net Delay (Destination): 3.715ns (routing 1.478ns, distribution 2.237ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.883 3.883 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X101Y80 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X101Y80 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 4.023 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.686 6.709 i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i SLICE_X139Y33 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[111]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y1 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.715 6.834 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X139Y33 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[111]/C clock pessimism 0.157 6.991 clock uncertainty -0.035 6.956 SLICE_X139Y33 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 6.863 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[111] ------------------------------------------------------------------- required time 6.863 arrival time -6.709 ------------------------------------------------------------------- slack 0.154 Slack (MET) : 0.154ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[153]/CLR (recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.826ns (logic 0.140ns (4.954%) route 2.686ns (95.046%)) Logic Levels: 0 Clock Path Skew: -0.011ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.715ns = ( 6.834 - 3.119 ) Source Clock Delay (SCD): 3.883ns Clock Pessimism Removal (CPR): 0.157ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.883ns (routing 1.620ns, distribution 2.263ns) Clock Net Delay (Destination): 3.715ns (routing 1.478ns, distribution 2.237ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.883 3.883 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X101Y80 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X101Y80 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 4.023 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.686 6.709 i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i SLICE_X139Y33 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[153]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y1 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.715 6.834 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X139Y33 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[153]/C clock pessimism 0.157 6.991 clock uncertainty -0.035 6.956 SLICE_X139Y33 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 6.863 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[153] ------------------------------------------------------------------- required time 6.863 arrival time -6.709 ------------------------------------------------------------------- slack 0.154 Slack (MET) : 0.154ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[154]/CLR (recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.826ns (logic 0.140ns (4.954%) route 2.686ns (95.046%)) Logic Levels: 0 Clock Path Skew: -0.011ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.715ns = ( 6.834 - 3.119 ) Source Clock Delay (SCD): 3.883ns Clock Pessimism Removal (CPR): 0.157ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.883ns (routing 1.620ns, distribution 2.263ns) Clock Net Delay (Destination): 3.715ns (routing 1.478ns, distribution 2.237ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.883 3.883 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X101Y80 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X101Y80 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 4.023 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.686 6.709 i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i SLICE_X139Y33 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[154]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y1 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.715 6.834 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X139Y33 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[154]/C clock pessimism 0.157 6.991 clock uncertainty -0.035 6.956 SLICE_X139Y33 FDCE (Recov_FFF_SLICEL_C_CLR) -0.093 6.863 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[154] ------------------------------------------------------------------- required time 6.863 arrival time -6.709 ------------------------------------------------------------------- slack 0.154 Slack (MET) : 0.154ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[91]/CLR (recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.826ns (logic 0.140ns (4.954%) route 2.686ns (95.046%)) Logic Levels: 0 Clock Path Skew: -0.011ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.715ns = ( 6.834 - 3.119 ) Source Clock Delay (SCD): 3.883ns Clock Pessimism Removal (CPR): 0.157ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.883ns (routing 1.620ns, distribution 2.263ns) Clock Net Delay (Destination): 3.715ns (routing 1.478ns, distribution 2.237ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.883 3.883 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X101Y80 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X101Y80 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 4.023 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.686 6.709 i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i SLICE_X139Y33 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[91]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y1 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.715 6.834 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X139Y33 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[91]/C clock pessimism 0.157 6.991 clock uncertainty -0.035 6.956 SLICE_X139Y33 FDCE (Recov_FFF2_SLICEL_C_CLR) -0.093 6.863 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[91] ------------------------------------------------------------------- required time 6.863 arrival time -6.709 ------------------------------------------------------------------- slack 0.154 Slack (MET) : 0.161ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[160]/CLR (recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.787ns (logic 0.140ns (5.023%) route 2.647ns (94.977%)) Logic Levels: 0 Clock Path Skew: -0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.683ns = ( 6.802 - 3.119 ) Source Clock Delay (SCD): 3.883ns Clock Pessimism Removal (CPR): 0.157ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.883ns (routing 1.620ns, distribution 2.263ns) Clock Net Delay (Destination): 3.683ns (routing 1.478ns, distribution 2.205ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.883 3.883 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X101Y80 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X101Y80 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 4.023 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.647 6.670 i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i SLICE_X133Y24 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[160]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y1 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.683 6.802 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X133Y24 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[160]/C clock pessimism 0.157 6.959 clock uncertainty -0.035 6.924 SLICE_X133Y24 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 6.831 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[160] ------------------------------------------------------------------- required time 6.831 arrival time -6.670 ------------------------------------------------------------------- slack 0.161 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.132ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg/PRE (removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.222ns (logic 0.048ns (21.622%) route 0.174ns (78.378%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.878ns Source Clock Delay (SCD): 1.626ns Clock Pessimism Removal (CPR): 0.167ns Clock Net Delay (Source): 1.626ns (routing 0.691ns, distribution 0.935ns) Clock Net Delay (Destination): 1.878ns (routing 0.772ns, distribution 1.106ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.626 1.626 i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] SLICE_X140Y15 FDCE r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C ------------------------------------------------------------------- ------------------- SLICE_X140Y15 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.674 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/Q net (fo=6, routed) 0.174 1.848 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rx_active_n SLICE_X142Y15 FDPE f i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg/PRE (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.878 1.878 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg_0 SLICE_X142Y15 FDPE r i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg/C clock pessimism -0.167 1.711 SLICE_X142Y15 FDPE (Remov_EFF_SLICEM_C_PRE) 0.005 1.716 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg ------------------------------------------------------------------- required time -1.716 arrival time 1.848 ------------------------------------------------------------------- slack 0.132 Slack (MET) : 0.135ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_meta_reg/PRE (removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.227ns (logic 0.048ns (21.145%) route 0.179ns (78.855%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.880ns Source Clock Delay (SCD): 1.626ns Clock Pessimism Removal (CPR): 0.167ns Clock Net Delay (Source): 1.626ns (routing 0.691ns, distribution 0.935ns) Clock Net Delay (Destination): 1.880ns (routing 0.772ns, distribution 1.108ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.626 1.626 i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] SLICE_X140Y15 FDCE r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C ------------------------------------------------------------------- ------------------- SLICE_X140Y15 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.674 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/Q net (fo=6, routed) 0.179 1.853 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rx_active_n SLICE_X142Y15 FDPE f i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_meta_reg/PRE (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.880 1.880 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg_0 SLICE_X142Y15 FDPE r i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_meta_reg/C clock pessimism -0.167 1.713 SLICE_X142Y15 FDPE (Remov_DFF2_SLICEM_C_PRE) 0.005 1.718 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_meta_reg ------------------------------------------------------------------- required time -1.718 arrival time 1.853 ------------------------------------------------------------------- slack 0.135 Slack (MET) : 0.135ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync1_reg/PRE (removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.227ns (logic 0.048ns (21.145%) route 0.179ns (78.855%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.880ns Source Clock Delay (SCD): 1.626ns Clock Pessimism Removal (CPR): 0.167ns Clock Net Delay (Source): 1.626ns (routing 0.691ns, distribution 0.935ns) Clock Net Delay (Destination): 1.880ns (routing 0.772ns, distribution 1.108ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.626 1.626 i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] SLICE_X140Y15 FDCE r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C ------------------------------------------------------------------- ------------------- SLICE_X140Y15 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.674 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/Q net (fo=6, routed) 0.179 1.853 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rx_active_n SLICE_X142Y15 FDPE f i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync1_reg/PRE (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.880 1.880 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg_0 SLICE_X142Y15 FDPE r i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync1_reg/C clock pessimism -0.167 1.713 SLICE_X142Y15 FDPE (Remov_AFF2_SLICEM_C_PRE) 0.005 1.718 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync1_reg ------------------------------------------------------------------- required time -1.718 arrival time 1.853 ------------------------------------------------------------------- slack 0.135 Slack (MET) : 0.135ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync2_reg/PRE (removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.227ns (logic 0.048ns (21.145%) route 0.179ns (78.855%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.880ns Source Clock Delay (SCD): 1.626ns Clock Pessimism Removal (CPR): 0.167ns Clock Net Delay (Source): 1.626ns (routing 0.691ns, distribution 0.935ns) Clock Net Delay (Destination): 1.880ns (routing 0.772ns, distribution 1.108ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.626 1.626 i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] SLICE_X140Y15 FDCE r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C ------------------------------------------------------------------- ------------------- SLICE_X140Y15 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.674 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/Q net (fo=6, routed) 0.179 1.853 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rx_active_n SLICE_X142Y15 FDPE f i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync2_reg/PRE (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.880 1.880 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg_0 SLICE_X142Y15 FDPE r i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync2_reg/C clock pessimism -0.167 1.713 SLICE_X142Y15 FDPE (Remov_BFF2_SLICEM_C_PRE) 0.005 1.718 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync2_reg ------------------------------------------------------------------- required time -1.718 arrival time 1.853 ------------------------------------------------------------------- slack 0.135 Slack (MET) : 0.135ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync3_reg/PRE (removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.227ns (logic 0.048ns (21.145%) route 0.179ns (78.855%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.880ns Source Clock Delay (SCD): 1.626ns Clock Pessimism Removal (CPR): 0.167ns Clock Net Delay (Source): 1.626ns (routing 0.691ns, distribution 0.935ns) Clock Net Delay (Destination): 1.880ns (routing 0.772ns, distribution 1.108ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.626 1.626 i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] SLICE_X140Y15 FDCE r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C ------------------------------------------------------------------- ------------------- SLICE_X140Y15 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.674 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/Q net (fo=6, routed) 0.179 1.853 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rx_active_n SLICE_X142Y15 FDPE f i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync3_reg/PRE (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.880 1.880 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg_0 SLICE_X142Y15 FDPE r i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync3_reg/C clock pessimism -0.167 1.713 SLICE_X142Y15 FDPE (Remov_CFF2_SLICEM_C_PRE) 0.005 1.718 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync3_reg ------------------------------------------------------------------- required time -1.718 arrival time 1.853 ------------------------------------------------------------------- slack 0.135 Slack (MET) : 0.145ns (arrival time - required time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/C (rising edge-triggered cell FDPE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[41]/CLR (removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.219ns (logic 0.048ns (21.918%) route 0.171ns (78.082%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.868ns Source Clock Delay (SCD): 1.632ns Clock Pessimism Removal (CPR): 0.167ns Clock Net Delay (Source): 1.632ns (routing 0.691ns, distribution 0.941ns) Clock Net Delay (Destination): 1.868ns (routing 0.772ns, distribution 1.096ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.632 1.632 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X138Y21 FDPE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y21 FDPE (Prop_HFF2_SLICEL_C_Q) 0.048 1.680 f i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/Q net (fo=549, routed) 0.171 1.851 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s SLICE_X137Y21 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[41]/CLR ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.868 1.868 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X137Y21 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[41]/C clock pessimism -0.167 1.701 SLICE_X137Y21 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.706 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[41] ------------------------------------------------------------------- required time -1.706 arrival time 1.851 ------------------------------------------------------------------- slack 0.145 Slack (MET) : 0.145ns (arrival time - required time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/C (rising edge-triggered cell FDPE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[53]/CLR (removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.219ns (logic 0.048ns (21.918%) route 0.171ns (78.082%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.868ns Source Clock Delay (SCD): 1.632ns Clock Pessimism Removal (CPR): 0.167ns Clock Net Delay (Source): 1.632ns (routing 0.691ns, distribution 0.941ns) Clock Net Delay (Destination): 1.868ns (routing 0.772ns, distribution 1.096ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.632 1.632 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X138Y21 FDPE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y21 FDPE (Prop_HFF2_SLICEL_C_Q) 0.048 1.680 f i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/Q net (fo=549, routed) 0.171 1.851 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s SLICE_X137Y21 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[53]/CLR ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.868 1.868 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X137Y21 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[53]/C clock pessimism -0.167 1.701 SLICE_X137Y21 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 1.706 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[53] ------------------------------------------------------------------- required time -1.706 arrival time 1.851 ------------------------------------------------------------------- slack 0.145 Slack (MET) : 0.145ns (arrival time - required time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/C (rising edge-triggered cell FDPE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[61]/CLR (removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.219ns (logic 0.048ns (21.918%) route 0.171ns (78.082%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.868ns Source Clock Delay (SCD): 1.632ns Clock Pessimism Removal (CPR): 0.167ns Clock Net Delay (Source): 1.632ns (routing 0.691ns, distribution 0.941ns) Clock Net Delay (Destination): 1.868ns (routing 0.772ns, distribution 1.096ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.632 1.632 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X138Y21 FDPE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y21 FDPE (Prop_HFF2_SLICEL_C_Q) 0.048 1.680 f i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/Q net (fo=549, routed) 0.171 1.851 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s SLICE_X137Y21 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[61]/CLR ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.868 1.868 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X137Y21 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[61]/C clock pessimism -0.167 1.701 SLICE_X137Y21 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.706 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[61] ------------------------------------------------------------------- required time -1.706 arrival time 1.851 ------------------------------------------------------------------- slack 0.145 Slack (MET) : 0.145ns (arrival time - required time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/C (rising edge-triggered cell FDPE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[63]/CLR (removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.219ns (logic 0.048ns (21.918%) route 0.171ns (78.082%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.868ns Source Clock Delay (SCD): 1.632ns Clock Pessimism Removal (CPR): 0.167ns Clock Net Delay (Source): 1.632ns (routing 0.691ns, distribution 0.941ns) Clock Net Delay (Destination): 1.868ns (routing 0.772ns, distribution 1.096ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.632 1.632 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X138Y21 FDPE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y21 FDPE (Prop_HFF2_SLICEL_C_Q) 0.048 1.680 f i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/Q net (fo=549, routed) 0.171 1.851 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s SLICE_X137Y21 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[63]/CLR ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.868 1.868 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X137Y21 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[63]/C clock pessimism -0.167 1.701 SLICE_X137Y21 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.706 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[63] ------------------------------------------------------------------- required time -1.706 arrival time 1.851 ------------------------------------------------------------------- slack 0.145 Slack (MET) : 0.145ns (arrival time - required time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/C (rising edge-triggered cell FDPE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg1_reg[41]/CLR (removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.219ns (logic 0.048ns (21.918%) route 0.171ns (78.082%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.868ns Source Clock Delay (SCD): 1.632ns Clock Pessimism Removal (CPR): 0.167ns Clock Net Delay (Source): 1.632ns (routing 0.691ns, distribution 0.941ns) Clock Net Delay (Destination): 1.868ns (routing 0.772ns, distribution 1.096ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.632 1.632 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X138Y21 FDPE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y21 FDPE (Prop_HFF2_SLICEL_C_Q) 0.048 1.680 f i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/Q net (fo=549, routed) 0.171 1.851 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s SLICE_X137Y21 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg1_reg[41]/CLR ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y1 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.868 1.868 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X137Y21 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg1_reg[41]/C clock pessimism -0.167 1.701 SLICE_X137Y21 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 1.706 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg1_reg[41] ------------------------------------------------------------------- required time -1.706 arrival time 1.851 ------------------------------------------------------------------- slack 0.145 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: clk125 To Clock: clk125 Setup : 0 Failing Endpoints, Worst Slack 2.606ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.199ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.606ns (required time - arrival time) Source: ipb_rst_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE (recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 5.202ns (logic 0.400ns (7.689%) route 4.802ns (92.311%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.046ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.389ns = ( 11.389 - 8.000 ) Source Clock Delay (SCD): 3.557ns Clock Pessimism Removal (CPR): 0.122ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.557ns (routing 0.946ns, distribution 2.611ns) Clock Net Delay (Destination): 3.389ns (routing 0.870ns, distribution 2.519ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.557 3.557 CLKFBIN SLICE_X106Y107 FDRE r ipb_rst_reg/C ------------------------------------------------------------------- ------------------- SLICE_X106Y107 FDRE (Prop_EFF_SLICEM_C_Q) 0.139 3.696 f ipb_rst_reg/Q net (fo=1953, routed) 3.974 7.670 ctrl_regs_inst/lopt SLICE_X131Y19 LUT3 (Prop_H5LUT_SLICEL_I1_O) 0.261 7.931 f ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/O net (fo=10, routed) 0.828 8.759 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in SLICE_X133Y16 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y108 BUFGCE 0.000 8.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.389 11.389 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/clk_in SLICE_X133Y16 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/C clock pessimism 0.122 11.511 clock uncertainty -0.053 11.458 SLICE_X133Y16 FDPE (Recov_DFF2_SLICEL_C_PRE) -0.093 11.365 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg ------------------------------------------------------------------- required time 11.365 arrival time -8.759 ------------------------------------------------------------------- slack 2.606 Slack (MET) : 2.606ns (required time - arrival time) Source: ipb_rst_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE (recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 5.202ns (logic 0.400ns (7.689%) route 4.802ns (92.311%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.046ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.389ns = ( 11.389 - 8.000 ) Source Clock Delay (SCD): 3.557ns Clock Pessimism Removal (CPR): 0.122ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.557ns (routing 0.946ns, distribution 2.611ns) Clock Net Delay (Destination): 3.389ns (routing 0.870ns, distribution 2.519ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.557 3.557 CLKFBIN SLICE_X106Y107 FDRE r ipb_rst_reg/C ------------------------------------------------------------------- ------------------- SLICE_X106Y107 FDRE (Prop_EFF_SLICEM_C_Q) 0.139 3.696 f ipb_rst_reg/Q net (fo=1953, routed) 3.974 7.670 ctrl_regs_inst/lopt SLICE_X131Y19 LUT3 (Prop_H5LUT_SLICEL_I1_O) 0.261 7.931 f ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/O net (fo=10, routed) 0.828 8.759 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in SLICE_X133Y16 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y108 BUFGCE 0.000 8.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.389 11.389 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/clk_in SLICE_X133Y16 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/C clock pessimism 0.122 11.511 clock uncertainty -0.053 11.458 SLICE_X133Y16 FDPE (Recov_AFF2_SLICEL_C_PRE) -0.093 11.365 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg ------------------------------------------------------------------- required time 11.365 arrival time -8.759 ------------------------------------------------------------------- slack 2.606 Slack (MET) : 2.606ns (required time - arrival time) Source: ipb_rst_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE (recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 5.202ns (logic 0.400ns (7.689%) route 4.802ns (92.311%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.046ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.389ns = ( 11.389 - 8.000 ) Source Clock Delay (SCD): 3.557ns Clock Pessimism Removal (CPR): 0.122ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.557ns (routing 0.946ns, distribution 2.611ns) Clock Net Delay (Destination): 3.389ns (routing 0.870ns, distribution 2.519ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.557 3.557 CLKFBIN SLICE_X106Y107 FDRE r ipb_rst_reg/C ------------------------------------------------------------------- ------------------- SLICE_X106Y107 FDRE (Prop_EFF_SLICEM_C_Q) 0.139 3.696 f ipb_rst_reg/Q net (fo=1953, routed) 3.974 7.670 ctrl_regs_inst/lopt SLICE_X131Y19 LUT3 (Prop_H5LUT_SLICEL_I1_O) 0.261 7.931 f ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/O net (fo=10, routed) 0.828 8.759 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in SLICE_X133Y16 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y108 BUFGCE 0.000 8.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.389 11.389 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/clk_in SLICE_X133Y16 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/C clock pessimism 0.122 11.511 clock uncertainty -0.053 11.458 SLICE_X133Y16 FDPE (Recov_BFF2_SLICEL_C_PRE) -0.093 11.365 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg ------------------------------------------------------------------- required time 11.365 arrival time -8.759 ------------------------------------------------------------------- slack 2.606 Slack (MET) : 2.606ns (required time - arrival time) Source: ipb_rst_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE (recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 5.202ns (logic 0.400ns (7.689%) route 4.802ns (92.311%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.046ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.389ns = ( 11.389 - 8.000 ) Source Clock Delay (SCD): 3.557ns Clock Pessimism Removal (CPR): 0.122ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.557ns (routing 0.946ns, distribution 2.611ns) Clock Net Delay (Destination): 3.389ns (routing 0.870ns, distribution 2.519ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.557 3.557 CLKFBIN SLICE_X106Y107 FDRE r ipb_rst_reg/C ------------------------------------------------------------------- ------------------- SLICE_X106Y107 FDRE (Prop_EFF_SLICEM_C_Q) 0.139 3.696 f ipb_rst_reg/Q net (fo=1953, routed) 3.974 7.670 ctrl_regs_inst/lopt SLICE_X131Y19 LUT3 (Prop_H5LUT_SLICEL_I1_O) 0.261 7.931 f ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/O net (fo=10, routed) 0.828 8.759 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in SLICE_X133Y16 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y108 BUFGCE 0.000 8.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.389 11.389 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/clk_in SLICE_X133Y16 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/C clock pessimism 0.122 11.511 clock uncertainty -0.053 11.458 SLICE_X133Y16 FDPE (Recov_CFF2_SLICEL_C_PRE) -0.093 11.365 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg ------------------------------------------------------------------- required time 11.365 arrival time -8.759 ------------------------------------------------------------------- slack 2.606 Slack (MET) : 2.614ns (required time - arrival time) Source: ipb_rst_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE (recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 5.192ns (logic 0.400ns (7.704%) route 4.792ns (92.296%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.048ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.387ns = ( 11.387 - 8.000 ) Source Clock Delay (SCD): 3.557ns Clock Pessimism Removal (CPR): 0.122ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.557ns (routing 0.946ns, distribution 2.611ns) Clock Net Delay (Destination): 3.387ns (routing 0.870ns, distribution 2.517ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.557 3.557 CLKFBIN SLICE_X106Y107 FDRE r ipb_rst_reg/C ------------------------------------------------------------------- ------------------- SLICE_X106Y107 FDRE (Prop_EFF_SLICEM_C_Q) 0.139 3.696 f ipb_rst_reg/Q net (fo=1953, routed) 3.974 7.670 ctrl_regs_inst/lopt SLICE_X131Y19 LUT3 (Prop_H5LUT_SLICEL_I1_O) 0.261 7.931 f ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/O net (fo=10, routed) 0.818 8.749 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in SLICE_X133Y16 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y108 BUFGCE 0.000 8.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.387 11.387 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/clk_in SLICE_X133Y16 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/C clock pessimism 0.122 11.509 clock uncertainty -0.053 11.456 SLICE_X133Y16 FDPE (Recov_EFF_SLICEL_C_PRE) -0.093 11.363 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg ------------------------------------------------------------------- required time 11.363 arrival time -8.749 ------------------------------------------------------------------- slack 2.614 Slack (MET) : 2.756ns (required time - arrival time) Source: ipb_rst_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE (recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 5.038ns (logic 0.400ns (7.940%) route 4.638ns (92.060%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.375ns = ( 11.375 - 8.000 ) Source Clock Delay (SCD): 3.557ns Clock Pessimism Removal (CPR): 0.122ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.557ns (routing 0.946ns, distribution 2.611ns) Clock Net Delay (Destination): 3.375ns (routing 0.870ns, distribution 2.505ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.557 3.557 CLKFBIN SLICE_X106Y107 FDRE r ipb_rst_reg/C ------------------------------------------------------------------- ------------------- SLICE_X106Y107 FDRE (Prop_EFF_SLICEM_C_Q) 0.139 3.696 f ipb_rst_reg/Q net (fo=1953, routed) 3.974 7.670 ctrl_regs_inst/lopt SLICE_X131Y19 LUT3 (Prop_H5LUT_SLICEL_I1_O) 0.261 7.931 f ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/O net (fo=10, routed) 0.664 8.595 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X131Y16 FDPE f i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y108 BUFGCE 0.000 8.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.375 11.375 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X131Y16 FDPE r i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C clock pessimism 0.122 11.497 clock uncertainty -0.053 11.444 SLICE_X131Y16 FDPE (Recov_EFF_SLICEL_C_PRE) -0.093 11.351 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_reg ------------------------------------------------------------------- required time 11.351 arrival time -8.595 ------------------------------------------------------------------- slack 2.756 Slack (MET) : 2.857ns (required time - arrival time) Source: ipb_rst_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE (recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 4.937ns (logic 0.400ns (8.102%) route 4.537ns (91.898%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.375ns = ( 11.375 - 8.000 ) Source Clock Delay (SCD): 3.557ns Clock Pessimism Removal (CPR): 0.122ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.557ns (routing 0.946ns, distribution 2.611ns) Clock Net Delay (Destination): 3.375ns (routing 0.870ns, distribution 2.505ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.557 3.557 CLKFBIN SLICE_X106Y107 FDRE r ipb_rst_reg/C ------------------------------------------------------------------- ------------------- SLICE_X106Y107 FDRE (Prop_EFF_SLICEM_C_Q) 0.139 3.696 f ipb_rst_reg/Q net (fo=1953, routed) 3.974 7.670 ctrl_regs_inst/lopt SLICE_X131Y19 LUT3 (Prop_H5LUT_SLICEL_I1_O) 0.261 7.931 f ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/O net (fo=10, routed) 0.563 8.494 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X130Y17 FDPE f i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y108 BUFGCE 0.000 8.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.375 11.375 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X130Y17 FDPE r i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/C clock pessimism 0.122 11.497 clock uncertainty -0.053 11.444 SLICE_X130Y17 FDPE (Recov_HFF2_SLICEL_C_PRE) -0.093 11.351 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg ------------------------------------------------------------------- required time 11.351 arrival time -8.494 ------------------------------------------------------------------- slack 2.857 Slack (MET) : 2.857ns (required time - arrival time) Source: ipb_rst_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE (recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 4.937ns (logic 0.400ns (8.102%) route 4.537ns (91.898%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.375ns = ( 11.375 - 8.000 ) Source Clock Delay (SCD): 3.557ns Clock Pessimism Removal (CPR): 0.122ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.557ns (routing 0.946ns, distribution 2.611ns) Clock Net Delay (Destination): 3.375ns (routing 0.870ns, distribution 2.505ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.557 3.557 CLKFBIN SLICE_X106Y107 FDRE r ipb_rst_reg/C ------------------------------------------------------------------- ------------------- SLICE_X106Y107 FDRE (Prop_EFF_SLICEM_C_Q) 0.139 3.696 f ipb_rst_reg/Q net (fo=1953, routed) 3.974 7.670 ctrl_regs_inst/lopt SLICE_X131Y19 LUT3 (Prop_H5LUT_SLICEL_I1_O) 0.261 7.931 f ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/O net (fo=10, routed) 0.563 8.494 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X130Y17 FDPE f i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y108 BUFGCE 0.000 8.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.375 11.375 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X130Y17 FDPE r i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/C clock pessimism 0.122 11.497 clock uncertainty -0.053 11.444 SLICE_X130Y17 FDPE (Recov_EFF2_SLICEL_C_PRE) -0.093 11.351 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg ------------------------------------------------------------------- required time 11.351 arrival time -8.494 ------------------------------------------------------------------- slack 2.857 Slack (MET) : 2.857ns (required time - arrival time) Source: ipb_rst_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE (recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 4.937ns (logic 0.400ns (8.102%) route 4.537ns (91.898%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.375ns = ( 11.375 - 8.000 ) Source Clock Delay (SCD): 3.557ns Clock Pessimism Removal (CPR): 0.122ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.557ns (routing 0.946ns, distribution 2.611ns) Clock Net Delay (Destination): 3.375ns (routing 0.870ns, distribution 2.505ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.557 3.557 CLKFBIN SLICE_X106Y107 FDRE r ipb_rst_reg/C ------------------------------------------------------------------- ------------------- SLICE_X106Y107 FDRE (Prop_EFF_SLICEM_C_Q) 0.139 3.696 f ipb_rst_reg/Q net (fo=1953, routed) 3.974 7.670 ctrl_regs_inst/lopt SLICE_X131Y19 LUT3 (Prop_H5LUT_SLICEL_I1_O) 0.261 7.931 f ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/O net (fo=10, routed) 0.563 8.494 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X130Y17 FDPE f i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y108 BUFGCE 0.000 8.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.375 11.375 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X130Y17 FDPE r i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/C clock pessimism 0.122 11.497 clock uncertainty -0.053 11.444 SLICE_X130Y17 FDPE (Recov_FFF2_SLICEL_C_PRE) -0.093 11.351 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg ------------------------------------------------------------------- required time 11.351 arrival time -8.494 ------------------------------------------------------------------- slack 2.857 Slack (MET) : 2.857ns (required time - arrival time) Source: ipb_rst_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE (recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 4.937ns (logic 0.400ns (8.102%) route 4.537ns (91.898%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.375ns = ( 11.375 - 8.000 ) Source Clock Delay (SCD): 3.557ns Clock Pessimism Removal (CPR): 0.122ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.557ns (routing 0.946ns, distribution 2.611ns) Clock Net Delay (Destination): 3.375ns (routing 0.870ns, distribution 2.505ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.557 3.557 CLKFBIN SLICE_X106Y107 FDRE r ipb_rst_reg/C ------------------------------------------------------------------- ------------------- SLICE_X106Y107 FDRE (Prop_EFF_SLICEM_C_Q) 0.139 3.696 f ipb_rst_reg/Q net (fo=1953, routed) 3.974 7.670 ctrl_regs_inst/lopt SLICE_X131Y19 LUT3 (Prop_H5LUT_SLICEL_I1_O) 0.261 7.931 f ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/O net (fo=10, routed) 0.563 8.494 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X130Y17 FDPE f i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y108 BUFGCE 0.000 8.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 3.375 11.375 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X130Y17 FDPE r i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C clock pessimism 0.122 11.497 clock uncertainty -0.053 11.444 SLICE_X130Y17 FDPE (Recov_GFF2_SLICEL_C_PRE) -0.093 11.351 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg ------------------------------------------------------------------- required time 11.351 arrival time -8.494 ------------------------------------------------------------------- slack 2.857 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.199ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE (removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.243ns (logic 0.048ns (19.753%) route 0.195ns (80.247%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.620ns Source Clock Delay (SCD): 1.411ns Clock Pessimism Removal (CPR): 0.170ns Clock Net Delay (Source): 1.411ns (routing 0.352ns, distribution 1.059ns) Clock Net Delay (Destination): 1.620ns (routing 0.390ns, distribution 1.230ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.411 1.411 i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN SLICE_X134Y16 FDRE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y16 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 1.459 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Q net (fo=7, routed) 0.195 1.654 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in SLICE_X135Y15 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.620 1.620 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/clk_in SLICE_X135Y15 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/C clock pessimism -0.170 1.450 SLICE_X135Y15 FDPE (Remov_HFF2_SLICEL_C_PRE) 0.005 1.455 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg ------------------------------------------------------------------- required time -1.455 arrival time 1.654 ------------------------------------------------------------------- slack 0.199 Slack (MET) : 0.199ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE (removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.243ns (logic 0.048ns (19.753%) route 0.195ns (80.247%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.620ns Source Clock Delay (SCD): 1.411ns Clock Pessimism Removal (CPR): 0.170ns Clock Net Delay (Source): 1.411ns (routing 0.352ns, distribution 1.059ns) Clock Net Delay (Destination): 1.620ns (routing 0.390ns, distribution 1.230ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.411 1.411 i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN SLICE_X134Y16 FDRE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y16 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 1.459 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Q net (fo=7, routed) 0.195 1.654 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in SLICE_X135Y15 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.620 1.620 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/clk_in SLICE_X135Y15 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/C clock pessimism -0.170 1.450 SLICE_X135Y15 FDPE (Remov_EFF_SLICEL_C_PRE) 0.005 1.455 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg ------------------------------------------------------------------- required time -1.455 arrival time 1.654 ------------------------------------------------------------------- slack 0.199 Slack (MET) : 0.199ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE (removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.243ns (logic 0.048ns (19.753%) route 0.195ns (80.247%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.620ns Source Clock Delay (SCD): 1.411ns Clock Pessimism Removal (CPR): 0.170ns Clock Net Delay (Source): 1.411ns (routing 0.352ns, distribution 1.059ns) Clock Net Delay (Destination): 1.620ns (routing 0.390ns, distribution 1.230ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.411 1.411 i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN SLICE_X134Y16 FDRE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y16 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 1.459 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Q net (fo=7, routed) 0.195 1.654 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in SLICE_X135Y15 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.620 1.620 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/clk_in SLICE_X135Y15 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/C clock pessimism -0.170 1.450 SLICE_X135Y15 FDPE (Remov_EFF2_SLICEL_C_PRE) 0.005 1.455 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg ------------------------------------------------------------------- required time -1.455 arrival time 1.654 ------------------------------------------------------------------- slack 0.199 Slack (MET) : 0.199ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE (removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.243ns (logic 0.048ns (19.753%) route 0.195ns (80.247%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.620ns Source Clock Delay (SCD): 1.411ns Clock Pessimism Removal (CPR): 0.170ns Clock Net Delay (Source): 1.411ns (routing 0.352ns, distribution 1.059ns) Clock Net Delay (Destination): 1.620ns (routing 0.390ns, distribution 1.230ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.411 1.411 i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN SLICE_X134Y16 FDRE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y16 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 1.459 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Q net (fo=7, routed) 0.195 1.654 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in SLICE_X135Y15 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.620 1.620 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/clk_in SLICE_X135Y15 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/C clock pessimism -0.170 1.450 SLICE_X135Y15 FDPE (Remov_FFF2_SLICEL_C_PRE) 0.005 1.455 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg ------------------------------------------------------------------- required time -1.455 arrival time 1.654 ------------------------------------------------------------------- slack 0.199 Slack (MET) : 0.199ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE (removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.243ns (logic 0.048ns (19.753%) route 0.195ns (80.247%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.620ns Source Clock Delay (SCD): 1.411ns Clock Pessimism Removal (CPR): 0.170ns Clock Net Delay (Source): 1.411ns (routing 0.352ns, distribution 1.059ns) Clock Net Delay (Destination): 1.620ns (routing 0.390ns, distribution 1.230ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.411 1.411 i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN SLICE_X134Y16 FDRE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y16 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 1.459 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Q net (fo=7, routed) 0.195 1.654 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in SLICE_X135Y15 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.620 1.620 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/clk_in SLICE_X135Y15 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/C clock pessimism -0.170 1.450 SLICE_X135Y15 FDPE (Remov_GFF2_SLICEL_C_PRE) 0.005 1.455 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg ------------------------------------------------------------------- required time -1.455 arrival time 1.654 ------------------------------------------------------------------- slack 0.199 Slack (MET) : 0.299ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE (removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.372ns (logic 0.093ns (25.000%) route 0.279ns (75.000%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.620ns Source Clock Delay (SCD): 1.411ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 1.411ns (routing 0.352ns, distribution 1.059ns) Clock Net Delay (Destination): 1.620ns (routing 0.390ns, distribution 1.230ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.411 1.411 i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN SLICE_X134Y16 FDRE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y16 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 1.459 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Q net (fo=7, routed) 0.072 1.531 i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg_n_0 SLICE_X134Y17 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.045 1.576 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst_i_1/O net (fo=5, routed) 0.207 1.783 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in SLICE_X137Y18 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.620 1.620 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/clk_in SLICE_X137Y18 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/C clock pessimism -0.141 1.479 SLICE_X137Y18 FDPE (Remov_EFF_SLICEL_C_PRE) 0.005 1.484 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg ------------------------------------------------------------------- required time -1.484 arrival time 1.783 ------------------------------------------------------------------- slack 0.299 Slack (MET) : 0.301ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_meta_reg/PRE (removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.388ns (logic 0.078ns (20.103%) route 0.310ns (79.897%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.634ns Source Clock Delay (SCD): 1.411ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 1.411ns (routing 0.352ns, distribution 1.059ns) Clock Net Delay (Destination): 1.634ns (routing 0.390ns, distribution 1.244ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.411 1.411 i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN SLICE_X134Y16 FDRE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y16 FDRE (Prop_GFF2_SLICEL_C_Q) 0.048 1.459 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg/Q net (fo=2, routed) 0.118 1.577 i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg_n_0 SLICE_X134Y16 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.030 1.607 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst_i_1/O net (fo=10, routed) 0.192 1.799 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in SLICE_X140Y16 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_meta_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.634 1.634 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/clk_in SLICE_X140Y16 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_meta_reg/C clock pessimism -0.141 1.493 SLICE_X140Y16 FDPE (Remov_HFF2_SLICEL_C_PRE) 0.005 1.498 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_meta_reg ------------------------------------------------------------------- required time -1.498 arrival time 1.799 ------------------------------------------------------------------- slack 0.301 Slack (MET) : 0.301ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_out_reg/PRE (removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.388ns (logic 0.078ns (20.103%) route 0.310ns (79.897%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.634ns Source Clock Delay (SCD): 1.411ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 1.411ns (routing 0.352ns, distribution 1.059ns) Clock Net Delay (Destination): 1.634ns (routing 0.390ns, distribution 1.244ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.411 1.411 i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN SLICE_X134Y16 FDRE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y16 FDRE (Prop_GFF2_SLICEL_C_Q) 0.048 1.459 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg/Q net (fo=2, routed) 0.118 1.577 i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg_n_0 SLICE_X134Y16 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.030 1.607 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst_i_1/O net (fo=10, routed) 0.192 1.799 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in SLICE_X140Y16 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_out_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.634 1.634 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/clk_in SLICE_X140Y16 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_out_reg/C clock pessimism -0.141 1.493 SLICE_X140Y16 FDPE (Remov_EFF_SLICEL_C_PRE) 0.005 1.498 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_out_reg ------------------------------------------------------------------- required time -1.498 arrival time 1.799 ------------------------------------------------------------------- slack 0.301 Slack (MET) : 0.301ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync1_reg/PRE (removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.388ns (logic 0.078ns (20.103%) route 0.310ns (79.897%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.634ns Source Clock Delay (SCD): 1.411ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 1.411ns (routing 0.352ns, distribution 1.059ns) Clock Net Delay (Destination): 1.634ns (routing 0.390ns, distribution 1.244ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.411 1.411 i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN SLICE_X134Y16 FDRE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y16 FDRE (Prop_GFF2_SLICEL_C_Q) 0.048 1.459 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg/Q net (fo=2, routed) 0.118 1.577 i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg_n_0 SLICE_X134Y16 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.030 1.607 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst_i_1/O net (fo=10, routed) 0.192 1.799 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in SLICE_X140Y16 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync1_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.634 1.634 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/clk_in SLICE_X140Y16 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync1_reg/C clock pessimism -0.141 1.493 SLICE_X140Y16 FDPE (Remov_EFF2_SLICEL_C_PRE) 0.005 1.498 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync1_reg ------------------------------------------------------------------- required time -1.498 arrival time 1.799 ------------------------------------------------------------------- slack 0.301 Slack (MET) : 0.301ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync2_reg/PRE (removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.388ns (logic 0.078ns (20.103%) route 0.310ns (79.897%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.634ns Source Clock Delay (SCD): 1.411ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 1.411ns (routing 0.352ns, distribution 1.059ns) Clock Net Delay (Destination): 1.634ns (routing 0.390ns, distribution 1.244ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.411 1.411 i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN SLICE_X134Y16 FDRE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y16 FDRE (Prop_GFF2_SLICEL_C_Q) 0.048 1.459 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg/Q net (fo=2, routed) 0.118 1.577 i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg_n_0 SLICE_X134Y16 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.030 1.607 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst_i_1/O net (fo=10, routed) 0.192 1.799 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in SLICE_X140Y16 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync2_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y108 BUFGCE 0.000 0.000 r i_clk125_bufg/O X3Y4 (CLOCK_ROOT) net (fo=3804, routed) 1.634 1.634 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/clk_in SLICE_X140Y16 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync2_reg/C clock pessimism -0.141 1.493 SLICE_X140Y16 FDPE (Remov_FFF2_SLICEL_C_PRE) 0.005 1.498 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync2_reg ------------------------------------------------------------------- required time -1.498 arrival time 1.799 ------------------------------------------------------------------- slack 0.301 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: fabric_clk To Clock: fabric_clk Setup : 0 Failing Endpoints, Worst Slack 8.363ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.136ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 8.363ns (required time - arrival time) Source: SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][19]/CLR (recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 15.755ns (logic 0.139ns (0.882%) route 15.616ns (99.118%)) Logic Levels: 0 Clock Path Skew: -0.237ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.408ns = ( 28.360 - 24.952 ) Source Clock Delay (SCD): 3.727ns Clock Pessimism Removal (CPR): 0.082ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.376ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.408ns Common Clock Delay (CCD): 0.904ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.727ns (routing 0.986ns, distribution 2.741ns) Clock Net Delay (Destination): 3.408ns (routing 0.904ns, distribution 2.504ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.727 3.727 SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X37Y0 FDPE r SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y0 FDPE (Prop_GFF2_SLICEM_C_Q) 0.139 3.866 f SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 15.616 19.482 SFP_GEN[1].ngCCM_gbt/out[0] SLR Crossing[0->1] SLICE_X108Y350 FDCE f SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][19]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y119 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.408 28.360 SFP_GEN[1].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X108Y350 FDCE r SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][19]/C clock pessimism 0.082 28.442 inter-SLR compensation -0.376 28.066 clock uncertainty -0.128 27.938 SLICE_X108Y350 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 27.845 SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][19] ------------------------------------------------------------------- required time 27.845 arrival time -19.482 ------------------------------------------------------------------- slack 8.363 Slack (MET) : 9.224ns (required time - arrival time) Source: SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][17]/PRE (recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 14.626ns (logic 0.139ns (0.950%) route 14.487ns (99.050%)) Logic Levels: 0 Clock Path Skew: -0.553ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.092ns = ( 28.044 - 24.952 ) Source Clock Delay (SCD): 3.727ns Clock Pessimism Removal (CPR): 0.082ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.328ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.092ns Common Clock Delay (CCD): 0.904ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.727ns (routing 0.986ns, distribution 2.741ns) Clock Net Delay (Destination): 3.092ns (routing 0.904ns, distribution 2.188ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.727 3.727 SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X37Y0 FDPE r SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y0 FDPE (Prop_GFF2_SLICEM_C_Q) 0.139 3.866 f SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 14.487 18.353 SFP_GEN[1].ngCCM_gbt/out[0] SLR Crossing[0->1] SLICE_X90Y368 FDPE f SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][17]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y119 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.092 28.044 SFP_GEN[1].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X90Y368 FDPE r SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][17]/C clock pessimism 0.082 28.126 inter-SLR compensation -0.328 27.798 clock uncertainty -0.128 27.670 SLICE_X90Y368 FDPE (Recov_EFF_SLICEM_C_PRE) -0.093 27.577 SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][17] ------------------------------------------------------------------- required time 27.577 arrival time -18.353 ------------------------------------------------------------------- slack 9.224 Slack (MET) : 9.578ns (required time - arrival time) Source: SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][15]/PRE (recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 14.250ns (logic 0.139ns (0.975%) route 14.111ns (99.025%)) Logic Levels: 0 Clock Path Skew: -0.579ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.066ns = ( 28.018 - 24.952 ) Source Clock Delay (SCD): 3.727ns Clock Pessimism Removal (CPR): 0.082ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.324ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.066ns Common Clock Delay (CCD): 0.904ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.727ns (routing 0.986ns, distribution 2.741ns) Clock Net Delay (Destination): 3.066ns (routing 0.904ns, distribution 2.162ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.727 3.727 SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X37Y0 FDPE r SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y0 FDPE (Prop_GFF2_SLICEM_C_Q) 0.139 3.866 f SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 14.111 17.977 SFP_GEN[1].ngCCM_gbt/out[0] SLR Crossing[0->1] SLICE_X77Y365 FDPE f SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][15]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y119 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.066 28.018 SFP_GEN[1].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X77Y365 FDPE r SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][15]/C clock pessimism 0.082 28.100 inter-SLR compensation -0.324 27.776 clock uncertainty -0.128 27.648 SLICE_X77Y365 FDPE (Recov_EFF_SLICEM_C_PRE) -0.093 27.555 SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][15] ------------------------------------------------------------------- required time 27.555 arrival time -17.977 ------------------------------------------------------------------- slack 9.578 Slack (MET) : 9.578ns (required time - arrival time) Source: SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][2]/CLR (recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 14.250ns (logic 0.139ns (0.975%) route 14.111ns (99.025%)) Logic Levels: 0 Clock Path Skew: -0.579ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.066ns = ( 28.018 - 24.952 ) Source Clock Delay (SCD): 3.727ns Clock Pessimism Removal (CPR): 0.082ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.324ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.066ns Common Clock Delay (CCD): 0.904ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.727ns (routing 0.986ns, distribution 2.741ns) Clock Net Delay (Destination): 3.066ns (routing 0.904ns, distribution 2.162ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.727 3.727 SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X37Y0 FDPE r SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y0 FDPE (Prop_GFF2_SLICEM_C_Q) 0.139 3.866 f SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 14.111 17.977 SFP_GEN[1].ngCCM_gbt/out[0] SLR Crossing[0->1] SLICE_X77Y365 FDCE f SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][2]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y119 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.066 28.018 SFP_GEN[1].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X77Y365 FDCE r SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][2]/C clock pessimism 0.082 28.100 inter-SLR compensation -0.324 27.776 clock uncertainty -0.128 27.648 SLICE_X77Y365 FDCE (Recov_EFF2_SLICEM_C_CLR) -0.093 27.555 SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][2] ------------------------------------------------------------------- required time 27.555 arrival time -17.977 ------------------------------------------------------------------- slack 9.578 Slack (MET) : 9.578ns (required time - arrival time) Source: SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][3]/CLR (recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 14.250ns (logic 0.139ns (0.975%) route 14.111ns (99.025%)) Logic Levels: 0 Clock Path Skew: -0.579ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.066ns = ( 28.018 - 24.952 ) Source Clock Delay (SCD): 3.727ns Clock Pessimism Removal (CPR): 0.082ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.324ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.066ns Common Clock Delay (CCD): 0.904ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.727ns (routing 0.986ns, distribution 2.741ns) Clock Net Delay (Destination): 3.066ns (routing 0.904ns, distribution 2.162ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.727 3.727 SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X37Y0 FDPE r SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y0 FDPE (Prop_GFF2_SLICEM_C_Q) 0.139 3.866 f SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 14.111 17.977 SFP_GEN[1].ngCCM_gbt/out[0] SLR Crossing[0->1] SLICE_X77Y365 FDCE f SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][3]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y119 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.066 28.018 SFP_GEN[1].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X77Y365 FDCE r SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][3]/C clock pessimism 0.082 28.100 inter-SLR compensation -0.324 27.776 clock uncertainty -0.128 27.648 SLICE_X77Y365 FDCE (Recov_FFF_SLICEM_C_CLR) -0.093 27.555 SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][3] ------------------------------------------------------------------- required time 27.555 arrival time -17.977 ------------------------------------------------------------------- slack 9.578 Slack (MET) : 9.578ns (required time - arrival time) Source: SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][7]/CLR (recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 14.250ns (logic 0.139ns (0.975%) route 14.111ns (99.025%)) Logic Levels: 0 Clock Path Skew: -0.579ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.066ns = ( 28.018 - 24.952 ) Source Clock Delay (SCD): 3.727ns Clock Pessimism Removal (CPR): 0.082ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.324ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.066ns Common Clock Delay (CCD): 0.904ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.727ns (routing 0.986ns, distribution 2.741ns) Clock Net Delay (Destination): 3.066ns (routing 0.904ns, distribution 2.162ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.727 3.727 SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X37Y0 FDPE r SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y0 FDPE (Prop_GFF2_SLICEM_C_Q) 0.139 3.866 f SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 14.111 17.977 SFP_GEN[1].ngCCM_gbt/out[0] SLR Crossing[0->1] SLICE_X77Y365 FDCE f SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][7]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y119 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.066 28.018 SFP_GEN[1].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X77Y365 FDCE r SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][7]/C clock pessimism 0.082 28.100 inter-SLR compensation -0.324 27.776 clock uncertainty -0.128 27.648 SLICE_X77Y365 FDCE (Recov_FFF2_SLICEM_C_CLR) -0.093 27.555 SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][7] ------------------------------------------------------------------- required time 27.555 arrival time -17.977 ------------------------------------------------------------------- slack 9.578 Slack (MET) : 9.782ns (required time - arrival time) Source: SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[0].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][17]/PRE (recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 13.817ns (logic 0.139ns (1.006%) route 13.678ns (98.994%)) Logic Levels: 0 Clock Path Skew: -0.828ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.932ns = ( 27.884 - 24.952 ) Source Clock Delay (SCD): 3.842ns Clock Pessimism Removal (CPR): 0.082ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.304ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 2.932ns Common Clock Delay (CCD): 0.904ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.842ns (routing 0.986ns, distribution 2.856ns) Clock Net Delay (Destination): 2.932ns (routing 0.904ns, distribution 2.028ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.842 3.842 SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X9Y0 FDPE r SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X9Y0 FDPE (Prop_GFF2_SLICEL_C_Q) 0.139 3.981 f SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 13.678 17.659 SFP_GEN[0].ngCCM_gbt/out[0] SLR Crossing[0->1] SLICE_X68Y382 FDPE f SFP_GEN[0].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][17]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y119 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 2.932 27.884 SFP_GEN[0].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X68Y382 FDPE r SFP_GEN[0].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][17]/C clock pessimism 0.082 27.966 inter-SLR compensation -0.304 27.662 clock uncertainty -0.128 27.534 SLICE_X68Y382 FDPE (Recov_EFF_SLICEL_C_PRE) -0.093 27.441 SFP_GEN[0].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][17] ------------------------------------------------------------------- required time 27.441 arrival time -17.659 ------------------------------------------------------------------- slack 9.782 Slack (MET) : 9.811ns (required time - arrival time) Source: SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][8]/CLR (recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 13.910ns (logic 0.139ns (0.999%) route 13.771ns (99.001%)) Logic Levels: 0 Clock Path Skew: -0.705ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.940ns = ( 27.892 - 24.952 ) Source Clock Delay (SCD): 3.727ns Clock Pessimism Removal (CPR): 0.082ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.305ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 2.940ns Common Clock Delay (CCD): 0.904ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.727ns (routing 0.986ns, distribution 2.741ns) Clock Net Delay (Destination): 2.940ns (routing 0.904ns, distribution 2.036ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.727 3.727 SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X37Y0 FDPE r SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y0 FDPE (Prop_GFF2_SLICEM_C_Q) 0.139 3.866 f SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 13.771 17.637 SFP_GEN[1].ngCCM_gbt/out[0] SLR Crossing[0->1] SLICE_X67Y367 FDCE f SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][8]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y119 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 2.940 27.892 SFP_GEN[1].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X67Y367 FDCE r SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][8]/C clock pessimism 0.082 27.974 inter-SLR compensation -0.305 27.669 clock uncertainty -0.128 27.541 SLICE_X67Y367 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 27.448 SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][8] ------------------------------------------------------------------- required time 27.448 arrival time -17.637 ------------------------------------------------------------------- slack 9.811 Slack (MET) : 9.815ns (required time - arrival time) Source: SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[0].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][15]/PRE (recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 13.794ns (logic 0.139ns (1.008%) route 13.655ns (98.992%)) Logic Levels: 0 Clock Path Skew: -0.816ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.944ns = ( 27.896 - 24.952 ) Source Clock Delay (SCD): 3.842ns Clock Pessimism Removal (CPR): 0.082ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.306ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 2.944ns Common Clock Delay (CCD): 0.904ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.842ns (routing 0.986ns, distribution 2.856ns) Clock Net Delay (Destination): 2.944ns (routing 0.904ns, distribution 2.040ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.842 3.842 SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X9Y0 FDPE r SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X9Y0 FDPE (Prop_GFF2_SLICEL_C_Q) 0.139 3.981 f SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 13.655 17.636 SFP_GEN[0].ngCCM_gbt/out[0] SLR Crossing[0->1] SLICE_X59Y377 FDPE f SFP_GEN[0].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][15]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y119 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 2.944 27.896 SFP_GEN[0].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X59Y377 FDPE r SFP_GEN[0].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][15]/C clock pessimism 0.082 27.978 inter-SLR compensation -0.306 27.672 clock uncertainty -0.128 27.544 SLICE_X59Y377 FDPE (Recov_EFF_SLICEM_C_PRE) -0.093 27.451 SFP_GEN[0].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][15] ------------------------------------------------------------------- required time 27.451 arrival time -17.636 ------------------------------------------------------------------- slack 9.815 Slack (MET) : 9.815ns (required time - arrival time) Source: SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[0].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][2]/CLR (recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 13.794ns (logic 0.139ns (1.008%) route 13.655ns (98.992%)) Logic Levels: 0 Clock Path Skew: -0.816ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.944ns = ( 27.896 - 24.952 ) Source Clock Delay (SCD): 3.842ns Clock Pessimism Removal (CPR): 0.082ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.306ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 2.944ns Common Clock Delay (CCD): 0.904ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.842ns (routing 0.986ns, distribution 2.856ns) Clock Net Delay (Destination): 2.944ns (routing 0.904ns, distribution 2.040ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.842 3.842 SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X9Y0 FDPE r SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X9Y0 FDPE (Prop_GFF2_SLICEL_C_Q) 0.139 3.981 f SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 13.655 17.636 SFP_GEN[0].ngCCM_gbt/out[0] SLR Crossing[0->1] SLICE_X59Y377 FDCE f SFP_GEN[0].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][2]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y119 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 2.944 27.896 SFP_GEN[0].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X59Y377 FDCE r SFP_GEN[0].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][2]/C clock pessimism 0.082 27.978 inter-SLR compensation -0.306 27.672 clock uncertainty -0.128 27.544 SLICE_X59Y377 FDCE (Recov_EFF2_SLICEM_C_CLR) -0.093 27.451 SFP_GEN[0].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][2] ------------------------------------------------------------------- required time 27.451 arrival time -17.636 ------------------------------------------------------------------- slack 9.815 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.136ns (arrival time - required time) Source: SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[27].ngCCM_gbt/recv_RX_to_TX_data_dly_reg/CLR (removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.253ns (logic 0.048ns (18.972%) route 0.205ns (81.028%)) Logic Levels: 0 Clock Path Skew: 0.112ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.398ns Source Clock Delay (SCD): 1.165ns Clock Pessimism Removal (CPR): 0.121ns Clock Net Delay (Source): 1.165ns (routing 0.373ns, distribution 0.792ns) Clock Net Delay (Destination): 1.398ns (routing 0.409ns, distribution 0.989ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.165 1.165 SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X70Y160 FDPE r SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X70Y160 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.213 f SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 0.205 1.418 SFP_GEN[27].ngCCM_gbt/out[0] SLICE_X72Y161 FDCE f SFP_GEN[27].ngCCM_gbt/recv_RX_to_TX_data_dly_reg/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.398 1.398 SFP_GEN[27].ngCCM_gbt/fabric_clk SLICE_X72Y161 FDCE r SFP_GEN[27].ngCCM_gbt/recv_RX_to_TX_data_dly_reg/C clock pessimism -0.121 1.277 SLICE_X72Y161 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.282 SFP_GEN[27].ngCCM_gbt/recv_RX_to_TX_data_dly_reg ------------------------------------------------------------------- required time -1.282 arrival time 1.418 ------------------------------------------------------------------- slack 0.136 Slack (MET) : 0.150ns (arrival time - required time) Source: SFP_GEN[3].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[3].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][11]/PRE (removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.220ns (logic 0.048ns (21.818%) route 0.172ns (78.182%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.594ns Source Clock Delay (SCD): 1.392ns Clock Pessimism Removal (CPR): 0.137ns Clock Net Delay (Source): 1.392ns (routing 0.373ns, distribution 1.019ns) Clock Net Delay (Destination): 1.594ns (routing 0.409ns, distribution 1.185ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.392 1.392 SFP_GEN[3].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X29Y100 FDPE r SFP_GEN[3].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y100 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.440 f SFP_GEN[3].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 0.172 1.612 SFP_GEN[3].ngCCM_gbt/out[0] SLICE_X32Y100 FDPE f SFP_GEN[3].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][11]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.594 1.594 SFP_GEN[3].ngCCM_gbt/fabric_clk SLICE_X32Y100 FDPE r SFP_GEN[3].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][11]/C clock pessimism -0.137 1.457 SLICE_X32Y100 FDPE (Remov_EFF_SLICEL_C_PRE) 0.005 1.462 SFP_GEN[3].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][11] ------------------------------------------------------------------- required time -1.462 arrival time 1.612 ------------------------------------------------------------------- slack 0.150 Slack (MET) : 0.159ns (arrival time - required time) Source: SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[39].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][4]/PRE (removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.227ns (logic 0.048ns (21.145%) route 0.179ns (78.855%)) Logic Levels: 0 Clock Path Skew: 0.063ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.699ns Source Clock Delay (SCD): 1.448ns Clock Pessimism Removal (CPR): 0.188ns Clock Net Delay (Source): 1.448ns (routing 0.373ns, distribution 1.075ns) Clock Net Delay (Destination): 1.699ns (routing 0.409ns, distribution 1.290ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.448 1.448 SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLR Crossing[0->1] SLICE_X7Y455 FDPE r SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y455 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.496 f SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 0.179 1.675 SFP_GEN[39].ngCCM_gbt/out[0] SLICE_X7Y457 FDPE f SFP_GEN[39].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][4]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.699 1.699 SFP_GEN[39].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X7Y457 FDPE r SFP_GEN[39].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][4]/C clock pessimism -0.188 1.511 SLICE_X7Y457 FDPE (Remov_EFF_SLICEM_C_PRE) 0.005 1.516 SFP_GEN[39].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][4] ------------------------------------------------------------------- required time -1.516 arrival time 1.675 ------------------------------------------------------------------- slack 0.159 Slack (MET) : 0.161ns (arrival time - required time) Source: SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[12].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][11]/PRE (removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.235ns (logic 0.048ns (20.426%) route 0.187ns (79.574%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.577ns Source Clock Delay (SCD): 1.368ns Clock Pessimism Removal (CPR): 0.140ns Clock Net Delay (Source): 1.368ns (routing 0.373ns, distribution 0.995ns) Clock Net Delay (Destination): 1.577ns (routing 0.409ns, distribution 1.168ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.368 1.368 SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X101Y113 FDPE r SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X101Y113 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.416 f SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 0.187 1.603 SFP_GEN[12].ngCCM_gbt/out[0] SLICE_X100Y111 FDPE f SFP_GEN[12].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][11]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.577 1.577 SFP_GEN[12].ngCCM_gbt/fabric_clk SLICE_X100Y111 FDPE r SFP_GEN[12].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][11]/C clock pessimism -0.140 1.437 SLICE_X100Y111 FDPE (Remov_AFF_SLICEM_C_PRE) 0.005 1.442 SFP_GEN[12].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][11] ------------------------------------------------------------------- required time -1.442 arrival time 1.603 ------------------------------------------------------------------- slack 0.161 Slack (MET) : 0.163ns (arrival time - required time) Source: SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_scl][2]/PRE (removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.218ns (logic 0.048ns (22.018%) route 0.170ns (77.982%)) Logic Levels: 0 Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.708ns Source Clock Delay (SCD): 1.475ns Clock Pessimism Removal (CPR): 0.183ns Clock Net Delay (Source): 1.475ns (routing 0.373ns, distribution 1.102ns) Clock Net Delay (Destination): 1.708ns (routing 0.409ns, distribution 1.299ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.475 1.475 SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X137Y80 FDPE r SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X137Y80 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.523 f SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 0.170 1.693 SFP_GEN[9].ngCCM_gbt/out[0] SLICE_X136Y79 FDPE f SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_scl][2]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.708 1.708 SFP_GEN[9].ngCCM_gbt/fabric_clk SLICE_X136Y79 FDPE r SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_scl][2]/C clock pessimism -0.183 1.525 SLICE_X136Y79 FDPE (Remov_EFF_SLICEM_C_PRE) 0.005 1.530 SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_scl][2] ------------------------------------------------------------------- required time -1.530 arrival time 1.693 ------------------------------------------------------------------- slack 0.163 Slack (MET) : 0.163ns (arrival time - required time) Source: SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][2]/PRE (removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.218ns (logic 0.048ns (22.018%) route 0.170ns (77.982%)) Logic Levels: 0 Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.708ns Source Clock Delay (SCD): 1.475ns Clock Pessimism Removal (CPR): 0.183ns Clock Net Delay (Source): 1.475ns (routing 0.373ns, distribution 1.102ns) Clock Net Delay (Destination): 1.708ns (routing 0.409ns, distribution 1.299ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.475 1.475 SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X137Y80 FDPE r SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X137Y80 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.523 f SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 0.170 1.693 SFP_GEN[9].ngCCM_gbt/out[0] SLICE_X136Y79 FDPE f SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][2]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.708 1.708 SFP_GEN[9].ngCCM_gbt/fabric_clk SLICE_X136Y79 FDPE r SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][2]/C clock pessimism -0.183 1.525 SLICE_X136Y79 FDPE (Remov_EFF2_SLICEM_C_PRE) 0.005 1.530 SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][2] ------------------------------------------------------------------- required time -1.530 arrival time 1.693 ------------------------------------------------------------------- slack 0.163 Slack (MET) : 0.163ns (arrival time - required time) Source: SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][3]/PRE (removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.218ns (logic 0.048ns (22.018%) route 0.170ns (77.982%)) Logic Levels: 0 Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.708ns Source Clock Delay (SCD): 1.475ns Clock Pessimism Removal (CPR): 0.183ns Clock Net Delay (Source): 1.475ns (routing 0.373ns, distribution 1.102ns) Clock Net Delay (Destination): 1.708ns (routing 0.409ns, distribution 1.299ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.475 1.475 SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X137Y80 FDPE r SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X137Y80 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.523 f SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 0.170 1.693 SFP_GEN[9].ngCCM_gbt/out[0] SLICE_X136Y79 FDPE f SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][3]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.708 1.708 SFP_GEN[9].ngCCM_gbt/fabric_clk SLICE_X136Y79 FDPE r SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][3]/C clock pessimism -0.183 1.525 SLICE_X136Y79 FDPE (Remov_FFF_SLICEM_C_PRE) 0.005 1.530 SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][3] ------------------------------------------------------------------- required time -1.530 arrival time 1.693 ------------------------------------------------------------------- slack 0.163 Slack (MET) : 0.167ns (arrival time - required time) Source: SFP_GEN[35].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[35].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_scl][2]/PRE (removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.215ns (logic 0.048ns (22.326%) route 0.167ns (77.674%)) Logic Levels: 0 Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.561ns Source Clock Delay (SCD): 1.342ns Clock Pessimism Removal (CPR): 0.176ns Clock Net Delay (Source): 1.342ns (routing 0.373ns, distribution 0.969ns) Clock Net Delay (Destination): 1.561ns (routing 0.409ns, distribution 1.152ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.342 1.342 SFP_GEN[35].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X40Y277 FDPE r SFP_GEN[35].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y277 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.390 f SFP_GEN[35].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=377, routed) 0.167 1.557 SFP_GEN[35].ngCCM_gbt/out[0] SLICE_X40Y276 FDPE f SFP_GEN[35].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_scl][2]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.561 1.561 SFP_GEN[35].ngCCM_gbt/fabric_clk SLICE_X40Y276 FDPE r SFP_GEN[35].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_scl][2]/C clock pessimism -0.176 1.385 SLICE_X40Y276 FDPE (Remov_AFF_SLICEL_C_PRE) 0.005 1.390 SFP_GEN[35].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_scl][2] ------------------------------------------------------------------- required time -1.390 arrival time 1.557 ------------------------------------------------------------------- slack 0.167 Slack (MET) : 0.173ns (arrival time - required time) Source: SFP_GEN[36].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[36].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][9]/PRE (removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.347ns (logic 0.048ns (13.833%) route 0.299ns (86.167%)) Logic Levels: 0 Clock Path Skew: 0.169ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.617ns Source Clock Delay (SCD): 1.402ns Clock Pessimism Removal (CPR): 0.046ns Clock Net Delay (Source): 1.402ns (routing 0.373ns, distribution 1.029ns) Clock Net Delay (Destination): 1.617ns (routing 0.409ns, distribution 1.208ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.402 1.402 SFP_GEN[36].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLR Crossing[0->1] SLICE_X36Y432 FDPE r SFP_GEN[36].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y432 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.450 f SFP_GEN[36].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 0.299 1.749 SFP_GEN[36].ngCCM_gbt/out[0] SLICE_X36Y410 FDPE f SFP_GEN[36].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][9]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.617 1.617 SFP_GEN[36].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X36Y410 FDPE r SFP_GEN[36].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][9]/C clock pessimism -0.046 1.571 SLICE_X36Y410 FDPE (Remov_EFF_SLICEL_C_PRE) 0.005 1.576 SFP_GEN[36].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][9] ------------------------------------------------------------------- required time -1.576 arrival time 1.749 ------------------------------------------------------------------- slack 0.173 Slack (MET) : 0.175ns (arrival time - required time) Source: SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[27].ngCCM_gbt/clr_fetch_RX_data_reg/CLR (removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.295ns (logic 0.048ns (16.271%) route 0.247ns (83.729%)) Logic Levels: 0 Clock Path Skew: 0.115ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.401ns Source Clock Delay (SCD): 1.165ns Clock Pessimism Removal (CPR): 0.121ns Clock Net Delay (Source): 1.165ns (routing 0.373ns, distribution 0.792ns) Clock Net Delay (Destination): 1.401ns (routing 0.409ns, distribution 0.992ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.165 1.165 SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X70Y160 FDPE r SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X70Y160 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.213 f SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 0.247 1.460 SFP_GEN[27].ngCCM_gbt/out[0] SLICE_X73Y161 FDCE f SFP_GEN[27].ngCCM_gbt/clr_fetch_RX_data_reg/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y119 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.401 1.401 SFP_GEN[27].ngCCM_gbt/fabric_clk SLICE_X73Y161 FDCE r SFP_GEN[27].ngCCM_gbt/clr_fetch_RX_data_reg/C clock pessimism -0.121 1.280 SLICE_X73Y161 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.285 SFP_GEN[27].ngCCM_gbt/clr_fetch_RX_data_reg ------------------------------------------------------------------- required time -1.285 arrival time 1.460 ------------------------------------------------------------------- slack 0.175 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0] To Clock: gtwiz_userclk_rx_srcclk_out[0] Setup : 0 Failing Endpoints, Worst Slack 3.708ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.215ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.708ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 3.820ns (logic 0.304ns (7.958%) route 3.516ns (92.042%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.661ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.072ns = ( 11.389 - 8.317 ) Source Clock Delay (SCD): 4.020ns Clock Pessimism Removal (CPR): 0.287ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.545ns (routing 1.460ns, distribution 2.085ns) Clock Net Delay (Destination): 2.674ns (routing 1.334ns, distribution 1.340ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.545 4.020 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X130Y71 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y71 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.159 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.984 7.143 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X84Y68 LUT2 (Prop_C6LUT_SLICEL_I0_O) 0.165 7.308 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1/O net (fo=2, routed) 0.532 7.840 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_1 SLICE_X79Y68 FDCE f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.674 11.389 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X79Y68 FDCE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.287 11.677 clock uncertainty -0.035 11.641 SLICE_X79Y68 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 11.548 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 11.548 arrival time -7.840 ------------------------------------------------------------------- slack 3.708 Slack (MET) : 3.708ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 3.820ns (logic 0.304ns (7.958%) route 3.516ns (92.042%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.661ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.072ns = ( 11.389 - 8.317 ) Source Clock Delay (SCD): 4.020ns Clock Pessimism Removal (CPR): 0.287ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.545ns (routing 1.460ns, distribution 2.085ns) Clock Net Delay (Destination): 2.674ns (routing 1.334ns, distribution 1.340ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.545 4.020 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X130Y71 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y71 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.159 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.984 7.143 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X84Y68 LUT2 (Prop_C6LUT_SLICEL_I0_O) 0.165 7.308 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1/O net (fo=2, routed) 0.532 7.840 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_1 SLICE_X79Y68 FDCE f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.674 11.389 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X79Y68 FDCE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.287 11.677 clock uncertainty -0.035 11.641 SLICE_X79Y68 FDCE (Recov_EFF2_SLICEM_C_CLR) -0.093 11.548 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 11.548 arrival time -7.840 ------------------------------------------------------------------- slack 3.708 Slack (MET) : 3.807ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 3.714ns (logic 0.360ns (9.693%) route 3.354ns (90.307%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.668ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.064ns = ( 11.381 - 8.317 ) Source Clock Delay (SCD): 4.020ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.545ns (routing 1.460ns, distribution 2.085ns) Clock Net Delay (Destination): 2.666ns (routing 1.334ns, distribution 1.332ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.545 4.020 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X130Y71 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y71 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.159 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.397 6.556 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y69 LUT3 (Prop_F6LUT_SLICEL_I0_O) 0.221 6.777 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2/O net (fo=15, routed) 0.957 7.734 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X85Y66 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.666 11.381 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[0] SLICE_X85Y66 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/C clock pessimism 0.288 11.669 clock uncertainty -0.035 11.634 SLICE_X85Y66 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 11.541 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0] ------------------------------------------------------------------- required time 11.541 arrival time -7.734 ------------------------------------------------------------------- slack 3.807 Slack (MET) : 3.807ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 3.714ns (logic 0.360ns (9.693%) route 3.354ns (90.307%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.668ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.064ns = ( 11.381 - 8.317 ) Source Clock Delay (SCD): 4.020ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.545ns (routing 1.460ns, distribution 2.085ns) Clock Net Delay (Destination): 2.666ns (routing 1.334ns, distribution 1.332ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.545 4.020 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X130Y71 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y71 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.159 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.397 6.556 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y69 LUT3 (Prop_F6LUT_SLICEL_I0_O) 0.221 6.777 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2/O net (fo=15, routed) 0.957 7.734 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X85Y66 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.666 11.381 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[0] SLICE_X85Y66 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/C clock pessimism 0.288 11.669 clock uncertainty -0.035 11.634 SLICE_X85Y66 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 11.541 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1] ------------------------------------------------------------------- required time 11.541 arrival time -7.734 ------------------------------------------------------------------- slack 3.807 Slack (MET) : 3.807ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 3.714ns (logic 0.360ns (9.693%) route 3.354ns (90.307%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.668ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.064ns = ( 11.381 - 8.317 ) Source Clock Delay (SCD): 4.020ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.545ns (routing 1.460ns, distribution 2.085ns) Clock Net Delay (Destination): 2.666ns (routing 1.334ns, distribution 1.332ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.545 4.020 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X130Y71 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y71 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.159 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.397 6.556 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y69 LUT3 (Prop_F6LUT_SLICEL_I0_O) 0.221 6.777 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2/O net (fo=15, routed) 0.957 7.734 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X85Y66 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.666 11.381 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[0] SLICE_X85Y66 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/C clock pessimism 0.288 11.669 clock uncertainty -0.035 11.634 SLICE_X85Y66 FDCE (Recov_BFF2_SLICEM_C_CLR) -0.093 11.541 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2] ------------------------------------------------------------------- required time 11.541 arrival time -7.734 ------------------------------------------------------------------- slack 3.807 Slack (MET) : 3.807ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 3.714ns (logic 0.360ns (9.693%) route 3.354ns (90.307%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.668ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.064ns = ( 11.381 - 8.317 ) Source Clock Delay (SCD): 4.020ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.545ns (routing 1.460ns, distribution 2.085ns) Clock Net Delay (Destination): 2.666ns (routing 1.334ns, distribution 1.332ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.545 4.020 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X130Y71 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y71 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.159 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.397 6.556 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y69 LUT3 (Prop_F6LUT_SLICEL_I0_O) 0.221 6.777 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2/O net (fo=15, routed) 0.957 7.734 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X85Y66 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.666 11.381 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[0] SLICE_X85Y66 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/C clock pessimism 0.288 11.669 clock uncertainty -0.035 11.634 SLICE_X85Y66 FDCE (Recov_AFF2_SLICEM_C_CLR) -0.093 11.541 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3] ------------------------------------------------------------------- required time 11.541 arrival time -7.734 ------------------------------------------------------------------- slack 3.807 Slack (MET) : 3.807ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 3.714ns (logic 0.360ns (9.693%) route 3.354ns (90.307%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.668ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.064ns = ( 11.381 - 8.317 ) Source Clock Delay (SCD): 4.020ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.545ns (routing 1.460ns, distribution 2.085ns) Clock Net Delay (Destination): 2.666ns (routing 1.334ns, distribution 1.332ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.545 4.020 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X130Y71 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y71 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.159 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.397 6.556 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y69 LUT3 (Prop_F6LUT_SLICEL_I0_O) 0.221 6.777 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2/O net (fo=15, routed) 0.957 7.734 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X85Y66 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.666 11.381 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[0] SLICE_X85Y66 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/C clock pessimism 0.288 11.669 clock uncertainty -0.035 11.634 SLICE_X85Y66 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.541 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4] ------------------------------------------------------------------- required time 11.541 arrival time -7.734 ------------------------------------------------------------------- slack 3.807 Slack (MET) : 3.807ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 3.714ns (logic 0.360ns (9.693%) route 3.354ns (90.307%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.668ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.064ns = ( 11.381 - 8.317 ) Source Clock Delay (SCD): 4.020ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.545ns (routing 1.460ns, distribution 2.085ns) Clock Net Delay (Destination): 2.666ns (routing 1.334ns, distribution 1.332ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.545 4.020 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X130Y71 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y71 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.159 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.397 6.556 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y69 LUT3 (Prop_F6LUT_SLICEL_I0_O) 0.221 6.777 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2/O net (fo=15, routed) 0.957 7.734 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X85Y66 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.666 11.381 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[0] SLICE_X85Y66 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/C clock pessimism 0.288 11.669 clock uncertainty -0.035 11.634 SLICE_X85Y66 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.541 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5] ------------------------------------------------------------------- required time 11.541 arrival time -7.734 ------------------------------------------------------------------- slack 3.807 Slack (MET) : 3.911ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 3.613ns (logic 0.360ns (9.964%) route 3.253ns (90.036%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.664ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.068ns = ( 11.385 - 8.317 ) Source Clock Delay (SCD): 4.020ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.545ns (routing 1.460ns, distribution 2.085ns) Clock Net Delay (Destination): 2.670ns (routing 1.334ns, distribution 1.336ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.545 4.020 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X130Y71 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y71 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.159 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.397 6.556 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y69 LUT3 (Prop_F6LUT_SLICEL_I0_O) 0.221 6.777 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2/O net (fo=15, routed) 0.856 7.633 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X86Y68 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.670 11.385 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[0] SLICE_X86Y68 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/C clock pessimism 0.288 11.673 clock uncertainty -0.035 11.637 SLICE_X86Y68 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.544 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0] ------------------------------------------------------------------- required time 11.544 arrival time -7.633 ------------------------------------------------------------------- slack 3.911 Slack (MET) : 3.916ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 3.612ns (logic 0.360ns (9.967%) route 3.252ns (90.033%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.661ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.072ns = ( 11.389 - 8.317 ) Source Clock Delay (SCD): 4.020ns Clock Pessimism Removal (CPR): 0.287ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.545ns (routing 1.460ns, distribution 2.085ns) Clock Net Delay (Destination): 2.674ns (routing 1.334ns, distribution 1.340ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.545 4.020 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X130Y71 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y71 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.159 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.397 6.556 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y69 LUT3 (Prop_F6LUT_SLICEL_I0_O) 0.221 6.777 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2/O net (fo=15, routed) 0.855 7.632 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X85Y68 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.674 11.389 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[0] SLICE_X85Y68 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/C clock pessimism 0.287 11.677 clock uncertainty -0.035 11.641 SLICE_X85Y68 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.548 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4] ------------------------------------------------------------------- required time 11.548 arrival time -7.632 ------------------------------------------------------------------- slack 3.916 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.215ns (arrival time - required time) Source: SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.295ns (logic 0.048ns (16.271%) route 0.247ns (83.729%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.534ns Source Clock Delay (SCD): 1.290ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 1.172ns (routing 0.610ns, distribution 0.562ns) Clock Net Delay (Destination): 1.369ns (routing 0.687ns, distribution 0.682ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.172 1.290 SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X78Y64 FDPE r SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y64 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.338 f SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.247 1.585 SFP_GEN[0].ngCCM_gbt/sync_m_reg[3][0] SLICE_X81Y65 FDCE f SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.369 1.534 SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X81Y65 FDCE r SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[19]/C clock pessimism -0.169 1.365 SLICE_X81Y65 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.370 SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[19] ------------------------------------------------------------------- required time -1.370 arrival time 1.585 ------------------------------------------------------------------- slack 0.215 Slack (MET) : 0.215ns (arrival time - required time) Source: SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.295ns (logic 0.048ns (16.271%) route 0.247ns (83.729%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.534ns Source Clock Delay (SCD): 1.290ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 1.172ns (routing 0.610ns, distribution 0.562ns) Clock Net Delay (Destination): 1.369ns (routing 0.687ns, distribution 0.682ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.172 1.290 SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X78Y64 FDPE r SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y64 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.338 f SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.247 1.585 SFP_GEN[0].ngCCM_gbt/sync_m_reg[3][0] SLICE_X81Y65 FDCE f SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.369 1.534 SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X81Y65 FDCE r SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[23]/C clock pessimism -0.169 1.365 SLICE_X81Y65 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.370 SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[23] ------------------------------------------------------------------- required time -1.370 arrival time 1.585 ------------------------------------------------------------------- slack 0.215 Slack (MET) : 0.215ns (arrival time - required time) Source: SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.295ns (logic 0.048ns (16.271%) route 0.247ns (83.729%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.534ns Source Clock Delay (SCD): 1.290ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 1.172ns (routing 0.610ns, distribution 0.562ns) Clock Net Delay (Destination): 1.369ns (routing 0.687ns, distribution 0.682ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.172 1.290 SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X78Y64 FDPE r SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y64 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.338 f SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.247 1.585 SFP_GEN[0].ngCCM_gbt/sync_m_reg[3][0] SLICE_X81Y65 FDCE f SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.369 1.534 SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X81Y65 FDCE r SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[26]/C clock pessimism -0.169 1.365 SLICE_X81Y65 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 1.370 SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[26] ------------------------------------------------------------------- required time -1.370 arrival time 1.585 ------------------------------------------------------------------- slack 0.215 Slack (MET) : 0.215ns (arrival time - required time) Source: SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.295ns (logic 0.048ns (16.271%) route 0.247ns (83.729%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.534ns Source Clock Delay (SCD): 1.290ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 1.172ns (routing 0.610ns, distribution 0.562ns) Clock Net Delay (Destination): 1.369ns (routing 0.687ns, distribution 0.682ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.172 1.290 SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X78Y64 FDPE r SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y64 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.338 f SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.247 1.585 SFP_GEN[0].ngCCM_gbt/sync_m_reg[3][0] SLICE_X81Y65 FDCE f SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.369 1.534 SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X81Y65 FDCE r SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[27]/C clock pessimism -0.169 1.365 SLICE_X81Y65 FDCE (Remov_BFF2_SLICEL_C_CLR) 0.005 1.370 SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[27] ------------------------------------------------------------------- required time -1.370 arrival time 1.585 ------------------------------------------------------------------- slack 0.215 Slack (MET) : 0.215ns (arrival time - required time) Source: SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.295ns (logic 0.048ns (16.271%) route 0.247ns (83.729%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.534ns Source Clock Delay (SCD): 1.290ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 1.172ns (routing 0.610ns, distribution 0.562ns) Clock Net Delay (Destination): 1.369ns (routing 0.687ns, distribution 0.682ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.172 1.290 SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X78Y64 FDPE r SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y64 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.338 f SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.247 1.585 SFP_GEN[0].ngCCM_gbt/sync_m_reg[3][0] SLICE_X81Y65 FDCE f SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.369 1.534 SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X81Y65 FDCE r SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[28]/C clock pessimism -0.169 1.365 SLICE_X81Y65 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 1.370 SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[28] ------------------------------------------------------------------- required time -1.370 arrival time 1.585 ------------------------------------------------------------------- slack 0.215 Slack (MET) : 0.215ns (arrival time - required time) Source: SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[31]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.295ns (logic 0.048ns (16.271%) route 0.247ns (83.729%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.534ns Source Clock Delay (SCD): 1.290ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 1.172ns (routing 0.610ns, distribution 0.562ns) Clock Net Delay (Destination): 1.369ns (routing 0.687ns, distribution 0.682ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.172 1.290 SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X78Y64 FDPE r SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y64 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.338 f SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.247 1.585 SFP_GEN[0].ngCCM_gbt/sync_m_reg[3][0] SLICE_X81Y65 FDCE f SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[31]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.369 1.534 SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X81Y65 FDCE r SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[31]/C clock pessimism -0.169 1.365 SLICE_X81Y65 FDCE (Remov_CFF2_SLICEL_C_CLR) 0.005 1.370 SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[31] ------------------------------------------------------------------- required time -1.370 arrival time 1.585 ------------------------------------------------------------------- slack 0.215 Slack (MET) : 0.218ns (arrival time - required time) Source: SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.302ns (logic 0.048ns (15.894%) route 0.254ns (84.106%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.538ns Source Clock Delay (SCD): 1.290ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 1.172ns (routing 0.610ns, distribution 0.562ns) Clock Net Delay (Destination): 1.373ns (routing 0.687ns, distribution 0.686ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.172 1.290 SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X78Y64 FDPE r SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y64 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.338 f SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.254 1.592 SFP_GEN[0].ngCCM_gbt/sync_m_reg[3][0] SLICE_X80Y66 FDCE f SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.373 1.538 SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y66 FDCE r SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[29]/C clock pessimism -0.169 1.369 SLICE_X80Y66 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.374 SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[29] ------------------------------------------------------------------- required time -1.374 arrival time 1.592 ------------------------------------------------------------------- slack 0.218 Slack (MET) : 0.218ns (arrival time - required time) Source: SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.302ns (logic 0.048ns (15.894%) route 0.254ns (84.106%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.538ns Source Clock Delay (SCD): 1.290ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 1.172ns (routing 0.610ns, distribution 0.562ns) Clock Net Delay (Destination): 1.373ns (routing 0.687ns, distribution 0.686ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.172 1.290 SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X78Y64 FDPE r SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y64 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.338 f SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.254 1.592 SFP_GEN[0].ngCCM_gbt/sync_m_reg[3][0] SLICE_X80Y66 FDCE f SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.373 1.538 SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y66 FDCE r SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[30]/C clock pessimism -0.169 1.369 SLICE_X80Y66 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.374 SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[30] ------------------------------------------------------------------- required time -1.374 arrival time 1.592 ------------------------------------------------------------------- slack 0.218 Slack (MET) : 0.218ns (arrival time - required time) Source: SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.302ns (logic 0.048ns (15.894%) route 0.254ns (84.106%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.538ns Source Clock Delay (SCD): 1.290ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 1.172ns (routing 0.610ns, distribution 0.562ns) Clock Net Delay (Destination): 1.373ns (routing 0.687ns, distribution 0.686ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.172 1.290 SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X78Y64 FDPE r SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y64 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.338 f SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.254 1.592 SFP_GEN[0].ngCCM_gbt/sync_m_reg[3][0] SLICE_X80Y66 FDCE f SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.373 1.538 SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y66 FDCE r SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[81]/C clock pessimism -0.169 1.369 SLICE_X80Y66 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 1.374 SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[81] ------------------------------------------------------------------- required time -1.374 arrival time 1.592 ------------------------------------------------------------------- slack 0.218 Slack (MET) : 0.229ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.304ns (logic 0.048ns (15.789%) route 0.256ns (84.211%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.532ns Source Clock Delay (SCD): 1.293ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 1.175ns (routing 0.610ns, distribution 0.565ns) Clock Net Delay (Destination): 1.367ns (routing 0.687ns, distribution 0.680ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.175 1.293 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X79Y60 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X79Y60 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.341 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.256 1.597 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X85Y60 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y43 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.367 1.532 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X85Y60 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism -0.169 1.363 SLICE_X85Y60 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 1.368 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time -1.368 arrival time 1.597 ------------------------------------------------------------------- slack 0.229 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_1 To Clock: gtwiz_userclk_rx_srcclk_out[0]_1 Setup : 0 Failing Endpoints, Worst Slack 4.822ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.114ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.822ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 3.054ns (logic 0.375ns (12.279%) route 2.679ns (87.721%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.313ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.241ns = ( 10.558 - 8.317 ) Source Clock Delay (SCD): 2.766ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.291ns (routing 0.632ns, distribution 1.659ns) Clock Net Delay (Destination): 1.843ns (routing 0.573ns, distribution 1.270ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.291 2.766 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X140Y214 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X140Y214 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.906 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.903 4.809 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X117Y224 LUT2 (Prop_C6LUT_SLICEL_I0_O) 0.235 5.044 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__9/O net (fo=2, routed) 0.776 5.820 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X117Y224 FDCE f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.843 10.558 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X117Y224 FDCE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.212 10.770 clock uncertainty -0.035 10.735 SLICE_X117Y224 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 10.642 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 10.642 arrival time -5.820 ------------------------------------------------------------------- slack 4.822 Slack (MET) : 4.822ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 3.054ns (logic 0.375ns (12.279%) route 2.679ns (87.721%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.313ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.241ns = ( 10.558 - 8.317 ) Source Clock Delay (SCD): 2.766ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.291ns (routing 0.632ns, distribution 1.659ns) Clock Net Delay (Destination): 1.843ns (routing 0.573ns, distribution 1.270ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.291 2.766 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X140Y214 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X140Y214 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.906 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.903 4.809 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X117Y224 LUT2 (Prop_C6LUT_SLICEL_I0_O) 0.235 5.044 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__9/O net (fo=2, routed) 0.776 5.820 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X117Y224 FDCE f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.843 10.558 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X117Y224 FDCE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.212 10.770 clock uncertainty -0.035 10.735 SLICE_X117Y224 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 10.642 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 10.642 arrival time -5.820 ------------------------------------------------------------------- slack 4.822 Slack (MET) : 4.981ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 3.008ns (logic 0.378ns (12.566%) route 2.630ns (87.434%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.200ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.337ns = ( 10.654 - 8.317 ) Source Clock Delay (SCD): 2.766ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.291ns (routing 0.632ns, distribution 1.659ns) Clock Net Delay (Destination): 1.939ns (routing 0.573ns, distribution 1.366ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.291 2.766 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X140Y214 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X140Y214 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.906 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.904 4.810 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X117Y224 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.238 5.048 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/O net (fo=15, routed) 0.726 5.774 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X119Y228 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.939 10.654 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] SLICE_X119Y228 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/C clock pessimism 0.229 10.884 clock uncertainty -0.035 10.848 SLICE_X119Y228 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.755 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1] ------------------------------------------------------------------- required time 10.755 arrival time -5.774 ------------------------------------------------------------------- slack 4.981 Slack (MET) : 4.981ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 3.008ns (logic 0.378ns (12.566%) route 2.630ns (87.434%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.200ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.337ns = ( 10.654 - 8.317 ) Source Clock Delay (SCD): 2.766ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.291ns (routing 0.632ns, distribution 1.659ns) Clock Net Delay (Destination): 1.939ns (routing 0.573ns, distribution 1.366ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.291 2.766 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X140Y214 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X140Y214 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.906 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.904 4.810 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X117Y224 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.238 5.048 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/O net (fo=15, routed) 0.726 5.774 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X119Y228 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.939 10.654 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] SLICE_X119Y228 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/C clock pessimism 0.229 10.884 clock uncertainty -0.035 10.848 SLICE_X119Y228 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 10.755 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2] ------------------------------------------------------------------- required time 10.755 arrival time -5.774 ------------------------------------------------------------------- slack 4.981 Slack (MET) : 4.981ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 3.008ns (logic 0.378ns (12.566%) route 2.630ns (87.434%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.200ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.337ns = ( 10.654 - 8.317 ) Source Clock Delay (SCD): 2.766ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.291ns (routing 0.632ns, distribution 1.659ns) Clock Net Delay (Destination): 1.939ns (routing 0.573ns, distribution 1.366ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.291 2.766 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X140Y214 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X140Y214 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.906 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.904 4.810 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X117Y224 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.238 5.048 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/O net (fo=15, routed) 0.726 5.774 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X119Y228 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.939 10.654 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] SLICE_X119Y228 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/C clock pessimism 0.229 10.884 clock uncertainty -0.035 10.848 SLICE_X119Y228 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.755 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4] ------------------------------------------------------------------- required time 10.755 arrival time -5.774 ------------------------------------------------------------------- slack 4.981 Slack (MET) : 4.986ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 3.001ns (logic 0.378ns (12.596%) route 2.623ns (87.404%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.202ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.335ns = ( 10.652 - 8.317 ) Source Clock Delay (SCD): 2.766ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.291ns (routing 0.632ns, distribution 1.659ns) Clock Net Delay (Destination): 1.937ns (routing 0.573ns, distribution 1.364ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.291 2.766 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X140Y214 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X140Y214 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.906 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.904 4.810 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X117Y224 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.238 5.048 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/O net (fo=15, routed) 0.719 5.767 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X119Y228 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.937 10.652 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] SLICE_X119Y228 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/C clock pessimism 0.229 10.882 clock uncertainty -0.035 10.846 SLICE_X119Y228 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 10.753 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0] ------------------------------------------------------------------- required time 10.753 arrival time -5.767 ------------------------------------------------------------------- slack 4.986 Slack (MET) : 4.986ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 3.001ns (logic 0.378ns (12.596%) route 2.623ns (87.404%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.202ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.335ns = ( 10.652 - 8.317 ) Source Clock Delay (SCD): 2.766ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.291ns (routing 0.632ns, distribution 1.659ns) Clock Net Delay (Destination): 1.937ns (routing 0.573ns, distribution 1.364ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.291 2.766 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X140Y214 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X140Y214 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.906 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.904 4.810 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X117Y224 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.238 5.048 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/O net (fo=15, routed) 0.719 5.767 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X119Y228 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.937 10.652 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] SLICE_X119Y228 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C clock pessimism 0.229 10.882 clock uncertainty -0.035 10.846 SLICE_X119Y228 FDCE (Recov_EFF2_SLICEM_C_CLR) -0.093 10.753 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3] ------------------------------------------------------------------- required time 10.753 arrival time -5.767 ------------------------------------------------------------------- slack 4.986 Slack (MET) : 5.004ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 2.974ns (logic 0.378ns (12.710%) route 2.596ns (87.290%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.211ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.326ns = ( 10.643 - 8.317 ) Source Clock Delay (SCD): 2.766ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.291ns (routing 0.632ns, distribution 1.659ns) Clock Net Delay (Destination): 1.928ns (routing 0.573ns, distribution 1.355ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.291 2.766 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X140Y214 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X140Y214 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.906 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.904 4.810 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X117Y224 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.238 5.048 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/O net (fo=15, routed) 0.692 5.740 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X119Y227 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.928 10.643 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] SLICE_X119Y227 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/C clock pessimism 0.229 10.873 clock uncertainty -0.035 10.837 SLICE_X119Y227 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 10.744 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10] ------------------------------------------------------------------- required time 10.744 arrival time -5.740 ------------------------------------------------------------------- slack 5.004 Slack (MET) : 5.139ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 2.850ns (logic 0.378ns (13.263%) route 2.472ns (86.737%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.200ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.337ns = ( 10.654 - 8.317 ) Source Clock Delay (SCD): 2.766ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.291ns (routing 0.632ns, distribution 1.659ns) Clock Net Delay (Destination): 1.939ns (routing 0.573ns, distribution 1.366ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.291 2.766 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X140Y214 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X140Y214 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.906 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.904 4.810 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X117Y224 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.238 5.048 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/O net (fo=15, routed) 0.568 5.616 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X120Y226 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.939 10.654 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] SLICE_X120Y226 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/C clock pessimism 0.229 10.884 clock uncertainty -0.035 10.848 SLICE_X120Y226 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.755 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5] ------------------------------------------------------------------- required time 10.755 arrival time -5.616 ------------------------------------------------------------------- slack 5.139 Slack (MET) : 5.139ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 2.850ns (logic 0.378ns (13.263%) route 2.472ns (86.737%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.200ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.337ns = ( 10.654 - 8.317 ) Source Clock Delay (SCD): 2.766ns Clock Pessimism Removal (CPR): 0.229ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.291ns (routing 0.632ns, distribution 1.659ns) Clock Net Delay (Destination): 1.939ns (routing 0.573ns, distribution 1.366ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.291 2.766 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X140Y214 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X140Y214 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.906 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.904 4.810 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X117Y224 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.238 5.048 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/O net (fo=15, routed) 0.568 5.616 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X120Y226 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.939 10.654 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] SLICE_X120Y226 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/C clock pessimism 0.229 10.884 clock uncertainty -0.035 10.848 SLICE_X120Y226 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.755 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6] ------------------------------------------------------------------- required time 10.755 arrival time -5.616 ------------------------------------------------------------------- slack 5.139 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.114ns (arrival time - required time) Source: SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[80]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.201ns (logic 0.048ns (23.881%) route 0.153ns (76.119%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.099ns Source Clock Delay (SCD): 0.889ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.771ns (routing 0.275ns, distribution 0.496ns) Clock Net Delay (Destination): 0.934ns (routing 0.312ns, distribution 0.622ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.771 0.889 SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X112Y212 FDPE r SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y212 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 0.937 f SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.153 1.090 SFP_GEN[10].ngCCM_gbt/sync_m_reg[3][0] SLICE_X111Y212 FDCE f SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[80]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.934 1.099 SFP_GEN[10].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y212 FDCE r SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[80]/C clock pessimism -0.128 0.971 SLICE_X111Y212 FDCE (Remov_DFF2_SLICEL_C_CLR) 0.005 0.976 SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[80] ------------------------------------------------------------------- required time -0.976 arrival time 1.090 ------------------------------------------------------------------- slack 0.114 Slack (MET) : 0.114ns (arrival time - required time) Source: SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.201ns (logic 0.048ns (23.881%) route 0.153ns (76.119%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.099ns Source Clock Delay (SCD): 0.889ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.771ns (routing 0.275ns, distribution 0.496ns) Clock Net Delay (Destination): 0.934ns (routing 0.312ns, distribution 0.622ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.771 0.889 SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X112Y212 FDPE r SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y212 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 0.937 f SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.153 1.090 SFP_GEN[10].ngCCM_gbt/sync_m_reg[3][0] SLICE_X111Y212 FDCE f SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.934 1.099 SFP_GEN[10].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y212 FDCE r SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[81]/C clock pessimism -0.128 0.971 SLICE_X111Y212 FDCE (Remov_CFF2_SLICEL_C_CLR) 0.005 0.976 SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[81] ------------------------------------------------------------------- required time -0.976 arrival time 1.090 ------------------------------------------------------------------- slack 0.114 Slack (MET) : 0.114ns (arrival time - required time) Source: SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.201ns (logic 0.048ns (23.881%) route 0.153ns (76.119%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.099ns Source Clock Delay (SCD): 0.889ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.771ns (routing 0.275ns, distribution 0.496ns) Clock Net Delay (Destination): 0.934ns (routing 0.312ns, distribution 0.622ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.771 0.889 SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X112Y212 FDPE r SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y212 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 0.937 f SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.153 1.090 SFP_GEN[10].ngCCM_gbt/sync_m_reg[3][0] SLICE_X111Y212 FDCE f SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.934 1.099 SFP_GEN[10].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y212 FDCE r SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[83]/C clock pessimism -0.128 0.971 SLICE_X111Y212 FDCE (Remov_BFF2_SLICEL_C_CLR) 0.005 0.976 SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[83] ------------------------------------------------------------------- required time -0.976 arrival time 1.090 ------------------------------------------------------------------- slack 0.114 Slack (MET) : 0.114ns (arrival time - required time) Source: SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[10].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.201ns (logic 0.048ns (23.881%) route 0.153ns (76.119%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.099ns Source Clock Delay (SCD): 0.889ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.771ns (routing 0.275ns, distribution 0.496ns) Clock Net Delay (Destination): 0.934ns (routing 0.312ns, distribution 0.622ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.771 0.889 SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X112Y212 FDPE r SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y212 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 0.937 f SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.153 1.090 SFP_GEN[10].ngCCM_gbt/sync_m_reg[3][0] SLICE_X111Y212 FDCE f SFP_GEN[10].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.934 1.099 SFP_GEN[10].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y212 FDCE r SFP_GEN[10].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.128 0.971 SLICE_X111Y212 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 0.976 SFP_GEN[10].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -0.976 arrival time 1.090 ------------------------------------------------------------------- slack 0.114 Slack (MET) : 0.137ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.227ns (logic 0.049ns (21.586%) route 0.178ns (78.414%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.111ns Source Clock Delay (SCD): 0.898ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.780ns (routing 0.275ns, distribution 0.505ns) Clock Net Delay (Destination): 0.946ns (routing 0.312ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.780 0.898 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X116Y218 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X116Y218 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.947 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.178 1.125 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X114Y218 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.946 1.111 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X114Y218 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism -0.128 0.983 SLICE_X114Y218 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 0.988 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time -0.988 arrival time 1.125 ------------------------------------------------------------------- slack 0.137 Slack (MET) : 0.137ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.227ns (logic 0.049ns (21.586%) route 0.178ns (78.414%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.111ns Source Clock Delay (SCD): 0.898ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.780ns (routing 0.275ns, distribution 0.505ns) Clock Net Delay (Destination): 0.946ns (routing 0.312ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.780 0.898 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X116Y218 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X116Y218 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.947 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.178 1.125 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X114Y218 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.946 1.111 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X114Y218 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.128 0.983 SLICE_X114Y218 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 0.988 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -0.988 arrival time 1.125 ------------------------------------------------------------------- slack 0.137 Slack (MET) : 0.137ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.227ns (logic 0.049ns (21.586%) route 0.178ns (78.414%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.111ns Source Clock Delay (SCD): 0.898ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.780ns (routing 0.275ns, distribution 0.505ns) Clock Net Delay (Destination): 0.946ns (routing 0.312ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.780 0.898 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X116Y218 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X116Y218 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.947 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.178 1.125 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X114Y218 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.946 1.111 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X114Y218 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C clock pessimism -0.128 0.983 SLICE_X114Y218 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 0.988 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19] ------------------------------------------------------------------- required time -0.988 arrival time 1.125 ------------------------------------------------------------------- slack 0.137 Slack (MET) : 0.137ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.227ns (logic 0.049ns (21.586%) route 0.178ns (78.414%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.111ns Source Clock Delay (SCD): 0.898ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.780ns (routing 0.275ns, distribution 0.505ns) Clock Net Delay (Destination): 0.946ns (routing 0.312ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.780 0.898 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X116Y218 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X116Y218 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.947 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.178 1.125 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X114Y218 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.946 1.111 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X114Y218 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C clock pessimism -0.128 0.983 SLICE_X114Y218 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 0.988 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8] ------------------------------------------------------------------- required time -0.988 arrival time 1.125 ------------------------------------------------------------------- slack 0.137 Slack (MET) : 0.138ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.228ns (logic 0.049ns (21.491%) route 0.179ns (78.509%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.111ns Source Clock Delay (SCD): 0.898ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.780ns (routing 0.275ns, distribution 0.505ns) Clock Net Delay (Destination): 0.946ns (routing 0.312ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.780 0.898 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X116Y218 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X116Y218 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.947 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.179 1.126 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X113Y218 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.946 1.111 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X113Y218 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C clock pessimism -0.128 0.983 SLICE_X113Y218 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 0.988 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time -0.988 arrival time 1.126 ------------------------------------------------------------------- slack 0.138 Slack (MET) : 0.138ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.228ns (logic 0.049ns (21.491%) route 0.179ns (78.509%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.111ns Source Clock Delay (SCD): 0.898ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.780ns (routing 0.275ns, distribution 0.505ns) Clock Net Delay (Destination): 0.946ns (routing 0.312ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.780 0.898 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X116Y218 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X116Y218 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.947 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.179 1.126 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X113Y218 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.946 1.111 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X113Y218 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C clock pessimism -0.128 0.983 SLICE_X113Y218 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 0.988 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20] ------------------------------------------------------------------- required time -0.988 arrival time 1.126 ------------------------------------------------------------------- slack 0.138 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_10 To Clock: gtwiz_userclk_rx_srcclk_out[0]_10 Setup : 0 Failing Endpoints, Worst Slack 5.268ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.136ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.268ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 2.631ns (logic 0.230ns (8.742%) route 2.401ns (91.258%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.290ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.235ns = ( 10.552 - 8.317 ) Source Clock Delay (SCD): 2.738ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.263ns (routing 0.633ns, distribution 1.630ns) Clock Net Delay (Destination): 1.837ns (routing 0.572ns, distribution 1.265ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.263 2.738 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y186 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y186 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.878 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.785 4.663 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y191 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 4.753 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/O net (fo=15, routed) 0.616 5.369 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X113Y191 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.837 10.552 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] SLICE_X113Y191 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/C clock pessimism 0.213 10.766 clock uncertainty -0.035 10.730 SLICE_X113Y191 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 10.637 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8] ------------------------------------------------------------------- required time 10.637 arrival time -5.369 ------------------------------------------------------------------- slack 5.268 Slack (MET) : 5.279ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 2.651ns (logic 0.228ns (8.601%) route 2.423ns (91.399%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.259ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.266ns = ( 10.583 - 8.317 ) Source Clock Delay (SCD): 2.738ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.263ns (routing 0.633ns, distribution 1.630ns) Clock Net Delay (Destination): 1.868ns (routing 0.572ns, distribution 1.296ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.263 2.738 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y186 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y186 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.878 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.784 4.662 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X111Y191 LUT2 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.750 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__7/O net (fo=2, routed) 0.639 5.389 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X111Y186 FDCE f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.868 10.583 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X111Y186 FDCE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.213 10.796 clock uncertainty -0.035 10.761 SLICE_X111Y186 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.668 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 10.668 arrival time -5.389 ------------------------------------------------------------------- slack 5.279 Slack (MET) : 5.279ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 2.651ns (logic 0.228ns (8.601%) route 2.423ns (91.399%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.259ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.266ns = ( 10.583 - 8.317 ) Source Clock Delay (SCD): 2.738ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.263ns (routing 0.633ns, distribution 1.630ns) Clock Net Delay (Destination): 1.868ns (routing 0.572ns, distribution 1.296ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.263 2.738 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y186 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y186 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.878 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.784 4.662 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X111Y191 LUT2 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.750 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__7/O net (fo=2, routed) 0.639 5.389 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X111Y186 FDCE f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.868 10.583 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X111Y186 FDCE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.213 10.796 clock uncertainty -0.035 10.761 SLICE_X111Y186 FDCE (Recov_AFF2_SLICEL_C_CLR) -0.093 10.668 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 10.668 arrival time -5.389 ------------------------------------------------------------------- slack 5.279 Slack (MET) : 5.336ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 2.563ns (logic 0.230ns (8.974%) route 2.333ns (91.026%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.290ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.235ns = ( 10.552 - 8.317 ) Source Clock Delay (SCD): 2.738ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.263ns (routing 0.633ns, distribution 1.630ns) Clock Net Delay (Destination): 1.837ns (routing 0.572ns, distribution 1.265ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.263 2.738 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y186 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y186 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.878 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.785 4.663 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y191 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 4.753 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/O net (fo=15, routed) 0.548 5.301 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X113Y192 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.837 10.552 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] SLICE_X113Y192 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/C clock pessimism 0.213 10.766 clock uncertainty -0.035 10.730 SLICE_X113Y192 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 10.637 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0] ------------------------------------------------------------------- required time 10.637 arrival time -5.301 ------------------------------------------------------------------- slack 5.336 Slack (MET) : 5.430ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 2.473ns (logic 0.230ns (9.300%) route 2.243ns (90.700%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.286ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.239ns = ( 10.556 - 8.317 ) Source Clock Delay (SCD): 2.738ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.263ns (routing 0.633ns, distribution 1.630ns) Clock Net Delay (Destination): 1.841ns (routing 0.572ns, distribution 1.269ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.263 2.738 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y186 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y186 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.878 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.785 4.663 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y191 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 4.753 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/O net (fo=15, routed) 0.458 5.211 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X112Y192 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.841 10.556 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] SLICE_X112Y192 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/C clock pessimism 0.213 10.769 clock uncertainty -0.035 10.734 SLICE_X112Y192 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.641 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1] ------------------------------------------------------------------- required time 10.641 arrival time -5.211 ------------------------------------------------------------------- slack 5.430 Slack (MET) : 5.430ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 2.473ns (logic 0.230ns (9.300%) route 2.243ns (90.700%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.286ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.239ns = ( 10.556 - 8.317 ) Source Clock Delay (SCD): 2.738ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.263ns (routing 0.633ns, distribution 1.630ns) Clock Net Delay (Destination): 1.841ns (routing 0.572ns, distribution 1.269ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.263 2.738 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y186 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y186 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.878 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.785 4.663 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y191 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 4.753 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/O net (fo=15, routed) 0.458 5.211 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X112Y192 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.841 10.556 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] SLICE_X112Y192 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/C clock pessimism 0.213 10.769 clock uncertainty -0.035 10.734 SLICE_X112Y192 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.641 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3] ------------------------------------------------------------------- required time 10.641 arrival time -5.211 ------------------------------------------------------------------- slack 5.430 Slack (MET) : 5.430ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 2.473ns (logic 0.230ns (9.300%) route 2.243ns (90.700%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.286ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.239ns = ( 10.556 - 8.317 ) Source Clock Delay (SCD): 2.738ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.263ns (routing 0.633ns, distribution 1.630ns) Clock Net Delay (Destination): 1.841ns (routing 0.572ns, distribution 1.269ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.263 2.738 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y186 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y186 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.878 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.785 4.663 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y191 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 4.753 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/O net (fo=15, routed) 0.458 5.211 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X112Y192 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.841 10.556 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] SLICE_X112Y192 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/C clock pessimism 0.213 10.769 clock uncertainty -0.035 10.734 SLICE_X112Y192 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 10.641 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4] ------------------------------------------------------------------- required time 10.641 arrival time -5.211 ------------------------------------------------------------------- slack 5.430 Slack (MET) : 5.430ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 2.473ns (logic 0.230ns (9.300%) route 2.243ns (90.700%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.286ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.239ns = ( 10.556 - 8.317 ) Source Clock Delay (SCD): 2.738ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.263ns (routing 0.633ns, distribution 1.630ns) Clock Net Delay (Destination): 1.841ns (routing 0.572ns, distribution 1.269ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.263 2.738 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y186 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y186 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.878 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.785 4.663 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y191 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 4.753 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/O net (fo=15, routed) 0.458 5.211 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X112Y192 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.841 10.556 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] SLICE_X112Y192 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/C clock pessimism 0.213 10.769 clock uncertainty -0.035 10.734 SLICE_X112Y192 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 10.641 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5] ------------------------------------------------------------------- required time 10.641 arrival time -5.211 ------------------------------------------------------------------- slack 5.430 Slack (MET) : 5.436ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 2.466ns (logic 0.230ns (9.327%) route 2.236ns (90.673%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.287ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.238ns = ( 10.555 - 8.317 ) Source Clock Delay (SCD): 2.738ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.263ns (routing 0.633ns, distribution 1.630ns) Clock Net Delay (Destination): 1.840ns (routing 0.572ns, distribution 1.268ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.263 2.738 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y186 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y186 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.878 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.785 4.663 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y191 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 4.753 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/O net (fo=15, routed) 0.451 5.204 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X112Y192 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.840 10.555 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] SLICE_X112Y192 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/C clock pessimism 0.213 10.768 clock uncertainty -0.035 10.733 SLICE_X112Y192 FDCE (Recov_HFF2_SLICEM_C_CLR) -0.093 10.640 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2] ------------------------------------------------------------------- required time 10.640 arrival time -5.204 ------------------------------------------------------------------- slack 5.436 Slack (MET) : 5.436ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 2.466ns (logic 0.230ns (9.327%) route 2.236ns (90.673%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.287ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.238ns = ( 10.555 - 8.317 ) Source Clock Delay (SCD): 2.738ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.263ns (routing 0.633ns, distribution 1.630ns) Clock Net Delay (Destination): 1.840ns (routing 0.572ns, distribution 1.268ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.263 2.738 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y186 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y186 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.878 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.785 4.663 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y191 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 4.753 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/O net (fo=15, routed) 0.451 5.204 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X112Y192 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.840 10.555 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] SLICE_X112Y192 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/C clock pessimism 0.213 10.768 clock uncertainty -0.035 10.733 SLICE_X112Y192 FDCE (Recov_GFF_SLICEM_C_CLR) -0.093 10.640 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6] ------------------------------------------------------------------- required time 10.640 arrival time -5.204 ------------------------------------------------------------------- slack 5.436 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.136ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[81]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.182ns (logic 0.049ns (26.923%) route 0.133ns (73.077%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.130ns Source Clock Delay (SCD): 0.916ns Clock Pessimism Removal (CPR): 0.173ns Clock Net Delay (Source): 0.798ns (routing 0.275ns, distribution 0.523ns) Clock Net Delay (Destination): 0.965ns (routing 0.314ns, distribution 0.651ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.798 0.916 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X111Y180 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X111Y180 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 0.965 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.133 1.098 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X110Y180 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[81]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.965 1.130 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X110Y180 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[81]/C clock pessimism -0.173 0.957 SLICE_X110Y180 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 0.962 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[81] ------------------------------------------------------------------- required time -0.962 arrival time 1.098 ------------------------------------------------------------------- slack 0.136 Slack (MET) : 0.136ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[83]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.182ns (logic 0.049ns (26.923%) route 0.133ns (73.077%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.130ns Source Clock Delay (SCD): 0.916ns Clock Pessimism Removal (CPR): 0.173ns Clock Net Delay (Source): 0.798ns (routing 0.275ns, distribution 0.523ns) Clock Net Delay (Destination): 0.965ns (routing 0.314ns, distribution 0.651ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.798 0.916 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X111Y180 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X111Y180 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 0.965 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.133 1.098 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X110Y180 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[83]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.965 1.130 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X110Y180 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[83]/C clock pessimism -0.173 0.957 SLICE_X110Y180 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 0.962 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[83] ------------------------------------------------------------------- required time -0.962 arrival time 1.098 ------------------------------------------------------------------- slack 0.136 Slack (MET) : 0.136ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[81]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.182ns (logic 0.049ns (26.923%) route 0.133ns (73.077%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.130ns Source Clock Delay (SCD): 0.916ns Clock Pessimism Removal (CPR): 0.173ns Clock Net Delay (Source): 0.798ns (routing 0.275ns, distribution 0.523ns) Clock Net Delay (Destination): 0.965ns (routing 0.314ns, distribution 0.651ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.798 0.916 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X111Y180 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X111Y180 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 0.965 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.133 1.098 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X110Y180 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[81]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.965 1.130 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X110Y180 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[81]/C clock pessimism -0.173 0.957 SLICE_X110Y180 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 0.962 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[81] ------------------------------------------------------------------- required time -0.962 arrival time 1.098 ------------------------------------------------------------------- slack 0.136 Slack (MET) : 0.136ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[83]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.182ns (logic 0.049ns (26.923%) route 0.133ns (73.077%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.130ns Source Clock Delay (SCD): 0.916ns Clock Pessimism Removal (CPR): 0.173ns Clock Net Delay (Source): 0.798ns (routing 0.275ns, distribution 0.523ns) Clock Net Delay (Destination): 0.965ns (routing 0.314ns, distribution 0.651ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.798 0.916 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X111Y180 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X111Y180 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 0.965 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.133 1.098 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X110Y180 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[83]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.965 1.130 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X110Y180 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[83]/C clock pessimism -0.173 0.957 SLICE_X110Y180 FDCE (Remov_GFF2_SLICEM_C_CLR) 0.005 0.962 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[83] ------------------------------------------------------------------- required time -0.962 arrival time 1.098 ------------------------------------------------------------------- slack 0.136 Slack (MET) : 0.137ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[41]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.185ns (logic 0.049ns (26.486%) route 0.136ns (73.514%)) Logic Levels: 0 Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.132ns Source Clock Delay (SCD): 0.916ns Clock Pessimism Removal (CPR): 0.173ns Clock Net Delay (Source): 0.798ns (routing 0.275ns, distribution 0.523ns) Clock Net Delay (Destination): 0.967ns (routing 0.314ns, distribution 0.653ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.798 0.916 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X111Y180 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X111Y180 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 0.965 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.136 1.101 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X110Y180 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[41]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.967 1.132 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X110Y180 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[41]/C clock pessimism -0.173 0.959 SLICE_X110Y180 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 0.964 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[41] ------------------------------------------------------------------- required time -0.964 arrival time 1.101 ------------------------------------------------------------------- slack 0.137 Slack (MET) : 0.137ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[49]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.185ns (logic 0.049ns (26.486%) route 0.136ns (73.514%)) Logic Levels: 0 Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.132ns Source Clock Delay (SCD): 0.916ns Clock Pessimism Removal (CPR): 0.173ns Clock Net Delay (Source): 0.798ns (routing 0.275ns, distribution 0.523ns) Clock Net Delay (Destination): 0.967ns (routing 0.314ns, distribution 0.653ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.798 0.916 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X111Y180 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X111Y180 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 0.965 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.136 1.101 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X110Y180 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[49]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.967 1.132 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X110Y180 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[49]/C clock pessimism -0.173 0.959 SLICE_X110Y180 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 0.964 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[49] ------------------------------------------------------------------- required time -0.964 arrival time 1.101 ------------------------------------------------------------------- slack 0.137 Slack (MET) : 0.137ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[56]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.185ns (logic 0.049ns (26.486%) route 0.136ns (73.514%)) Logic Levels: 0 Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.132ns Source Clock Delay (SCD): 0.916ns Clock Pessimism Removal (CPR): 0.173ns Clock Net Delay (Source): 0.798ns (routing 0.275ns, distribution 0.523ns) Clock Net Delay (Destination): 0.967ns (routing 0.314ns, distribution 0.653ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.798 0.916 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X111Y180 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X111Y180 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 0.965 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.136 1.101 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X110Y180 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[56]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.967 1.132 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X110Y180 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[56]/C clock pessimism -0.173 0.959 SLICE_X110Y180 FDCE (Remov_BFF_SLICEM_C_CLR) 0.005 0.964 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[56] ------------------------------------------------------------------- required time -0.964 arrival time 1.101 ------------------------------------------------------------------- slack 0.137 Slack (MET) : 0.137ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[57]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.185ns (logic 0.049ns (26.486%) route 0.136ns (73.514%)) Logic Levels: 0 Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.132ns Source Clock Delay (SCD): 0.916ns Clock Pessimism Removal (CPR): 0.173ns Clock Net Delay (Source): 0.798ns (routing 0.275ns, distribution 0.523ns) Clock Net Delay (Destination): 0.967ns (routing 0.314ns, distribution 0.653ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.798 0.916 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X111Y180 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X111Y180 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 0.965 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.136 1.101 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X110Y180 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[57]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.967 1.132 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X110Y180 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[57]/C clock pessimism -0.173 0.959 SLICE_X110Y180 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 0.964 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[57] ------------------------------------------------------------------- required time -0.964 arrival time 1.101 ------------------------------------------------------------------- slack 0.137 Slack (MET) : 0.137ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[41]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.185ns (logic 0.049ns (26.486%) route 0.136ns (73.514%)) Logic Levels: 0 Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.132ns Source Clock Delay (SCD): 0.916ns Clock Pessimism Removal (CPR): 0.173ns Clock Net Delay (Source): 0.798ns (routing 0.275ns, distribution 0.523ns) Clock Net Delay (Destination): 0.967ns (routing 0.314ns, distribution 0.653ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.798 0.916 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X111Y180 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X111Y180 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 0.965 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.136 1.101 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X110Y180 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[41]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.967 1.132 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X110Y180 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[41]/C clock pessimism -0.173 0.959 SLICE_X110Y180 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 0.964 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[41] ------------------------------------------------------------------- required time -0.964 arrival time 1.101 ------------------------------------------------------------------- slack 0.137 Slack (MET) : 0.137ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[49]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.185ns (logic 0.049ns (26.486%) route 0.136ns (73.514%)) Logic Levels: 0 Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.132ns Source Clock Delay (SCD): 0.916ns Clock Pessimism Removal (CPR): 0.173ns Clock Net Delay (Source): 0.798ns (routing 0.275ns, distribution 0.523ns) Clock Net Delay (Destination): 0.967ns (routing 0.314ns, distribution 0.653ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.798 0.916 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X111Y180 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X111Y180 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 0.965 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.136 1.101 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X110Y180 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[49]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.967 1.132 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X110Y180 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[49]/C clock pessimism -0.173 0.959 SLICE_X110Y180 FDCE (Remov_CFF2_SLICEM_C_CLR) 0.005 0.964 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[49] ------------------------------------------------------------------- required time -0.964 arrival time 1.101 ------------------------------------------------------------------- slack 0.137 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_11 To Clock: gtwiz_userclk_rx_srcclk_out[0]_11 Setup : 0 Failing Endpoints, Worst Slack 5.481ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.150ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.481ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 2.521ns (logic 0.363ns (14.399%) route 2.158ns (85.601%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.187ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.316ns = ( 10.633 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.249ns (routing 0.632ns, distribution 1.617ns) Clock Net Delay (Destination): 1.918ns (routing 0.572ns, distribution 1.346ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.249 2.724 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y203 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y203 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.863 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.149 4.012 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X113Y203 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.224 4.236 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/O net (fo=15, routed) 1.009 5.245 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X122Y204 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.918 10.633 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X122Y204 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/C clock pessimism 0.221 10.855 clock uncertainty -0.035 10.819 SLICE_X122Y204 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.726 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3] ------------------------------------------------------------------- required time 10.726 arrival time -5.245 ------------------------------------------------------------------- slack 5.481 Slack (MET) : 5.481ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 2.521ns (logic 0.363ns (14.399%) route 2.158ns (85.601%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.187ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.316ns = ( 10.633 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.249ns (routing 0.632ns, distribution 1.617ns) Clock Net Delay (Destination): 1.918ns (routing 0.572ns, distribution 1.346ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.249 2.724 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y203 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y203 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.863 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.149 4.012 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X113Y203 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.224 4.236 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/O net (fo=15, routed) 1.009 5.245 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X122Y204 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.918 10.633 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X122Y204 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/C clock pessimism 0.221 10.855 clock uncertainty -0.035 10.819 SLICE_X122Y204 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.726 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4] ------------------------------------------------------------------- required time 10.726 arrival time -5.245 ------------------------------------------------------------------- slack 5.481 Slack (MET) : 5.481ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 2.521ns (logic 0.363ns (14.399%) route 2.158ns (85.601%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.187ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.316ns = ( 10.633 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.249ns (routing 0.632ns, distribution 1.617ns) Clock Net Delay (Destination): 1.918ns (routing 0.572ns, distribution 1.346ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.249 2.724 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y203 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y203 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.863 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.149 4.012 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X113Y203 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.224 4.236 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/O net (fo=15, routed) 1.009 5.245 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X122Y204 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.918 10.633 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X122Y204 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/C clock pessimism 0.221 10.855 clock uncertainty -0.035 10.819 SLICE_X122Y204 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.726 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7] ------------------------------------------------------------------- required time 10.726 arrival time -5.245 ------------------------------------------------------------------- slack 5.481 Slack (MET) : 5.489ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 2.511ns (logic 0.363ns (14.456%) route 2.148ns (85.544%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.189ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.314ns = ( 10.631 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.249ns (routing 0.632ns, distribution 1.617ns) Clock Net Delay (Destination): 1.916ns (routing 0.572ns, distribution 1.344ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.249 2.724 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y203 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y203 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.863 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.149 4.012 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X113Y203 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.224 4.236 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/O net (fo=15, routed) 0.999 5.235 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X122Y204 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.916 10.631 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X122Y204 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/C clock pessimism 0.221 10.853 clock uncertainty -0.035 10.817 SLICE_X122Y204 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.724 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5] ------------------------------------------------------------------- required time 10.724 arrival time -5.235 ------------------------------------------------------------------- slack 5.489 Slack (MET) : 5.489ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 2.511ns (logic 0.363ns (14.456%) route 2.148ns (85.544%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.189ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.314ns = ( 10.631 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.249ns (routing 0.632ns, distribution 1.617ns) Clock Net Delay (Destination): 1.916ns (routing 0.572ns, distribution 1.344ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.249 2.724 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y203 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y203 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.863 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.149 4.012 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X113Y203 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.224 4.236 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/O net (fo=15, routed) 0.999 5.235 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X122Y204 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.916 10.631 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X122Y204 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/C clock pessimism 0.221 10.853 clock uncertainty -0.035 10.817 SLICE_X122Y204 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 10.724 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6] ------------------------------------------------------------------- required time 10.724 arrival time -5.235 ------------------------------------------------------------------- slack 5.489 Slack (MET) : 5.652ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 2.368ns (logic 0.363ns (15.329%) route 2.005ns (84.671%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.169ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.334ns = ( 10.651 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.249ns (routing 0.632ns, distribution 1.617ns) Clock Net Delay (Destination): 1.936ns (routing 0.572ns, distribution 1.364ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.249 2.724 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y203 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y203 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.863 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.149 4.012 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X113Y203 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.224 4.236 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/O net (fo=15, routed) 0.856 5.092 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X122Y203 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.936 10.651 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X122Y203 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/C clock pessimism 0.221 10.872 clock uncertainty -0.035 10.837 SLICE_X122Y203 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.744 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1] ------------------------------------------------------------------- required time 10.744 arrival time -5.092 ------------------------------------------------------------------- slack 5.652 Slack (MET) : 5.652ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 2.368ns (logic 0.363ns (15.329%) route 2.005ns (84.671%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.169ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.334ns = ( 10.651 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.249ns (routing 0.632ns, distribution 1.617ns) Clock Net Delay (Destination): 1.936ns (routing 0.572ns, distribution 1.364ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.249 2.724 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y203 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y203 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.863 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.149 4.012 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X113Y203 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.224 4.236 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/O net (fo=15, routed) 0.856 5.092 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X122Y203 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.936 10.651 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X122Y203 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/C clock pessimism 0.221 10.872 clock uncertainty -0.035 10.837 SLICE_X122Y203 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 10.744 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2] ------------------------------------------------------------------- required time 10.744 arrival time -5.092 ------------------------------------------------------------------- slack 5.652 Slack (MET) : 5.658ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 2.355ns (logic 0.363ns (15.414%) route 1.992ns (84.586%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.176ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.327ns = ( 10.644 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.249ns (routing 0.632ns, distribution 1.617ns) Clock Net Delay (Destination): 1.929ns (routing 0.572ns, distribution 1.357ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.249 2.724 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y203 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y203 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.863 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.149 4.012 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X113Y203 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.224 4.236 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/O net (fo=15, routed) 0.843 5.079 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X121Y203 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.929 10.644 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X121Y203 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/C clock pessimism 0.221 10.865 clock uncertainty -0.035 10.830 SLICE_X121Y203 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 10.737 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0] ------------------------------------------------------------------- required time 10.737 arrival time -5.079 ------------------------------------------------------------------- slack 5.658 Slack (MET) : 5.658ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 2.355ns (logic 0.363ns (15.414%) route 1.992ns (84.586%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.176ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.327ns = ( 10.644 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.249ns (routing 0.632ns, distribution 1.617ns) Clock Net Delay (Destination): 1.929ns (routing 0.572ns, distribution 1.357ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.249 2.724 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y203 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y203 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.863 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.149 4.012 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X113Y203 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.224 4.236 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/O net (fo=15, routed) 0.843 5.079 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X121Y203 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.929 10.644 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X121Y203 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/C clock pessimism 0.221 10.865 clock uncertainty -0.035 10.830 SLICE_X121Y203 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 10.737 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5] ------------------------------------------------------------------- required time 10.737 arrival time -5.079 ------------------------------------------------------------------- slack 5.658 Slack (MET) : 5.660ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 2.358ns (logic 0.363ns (15.394%) route 1.995ns (84.606%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.171ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.332ns = ( 10.649 - 8.317 ) Source Clock Delay (SCD): 2.724ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.249ns (routing 0.632ns, distribution 1.617ns) Clock Net Delay (Destination): 1.934ns (routing 0.572ns, distribution 1.362ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.249 2.724 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y203 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y203 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.863 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.149 4.012 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X113Y203 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.224 4.236 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/O net (fo=15, routed) 0.846 5.082 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X122Y203 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.934 10.649 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X122Y203 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/C clock pessimism 0.221 10.870 clock uncertainty -0.035 10.835 SLICE_X122Y203 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 10.742 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0] ------------------------------------------------------------------- required time 10.742 arrival time -5.082 ------------------------------------------------------------------- slack 5.660 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.150ns (arrival time - required time) Source: SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.226ns (logic 0.048ns (21.239%) route 0.178ns (78.761%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.104ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.129ns Clock Net Delay (Source): 0.786ns (routing 0.274ns, distribution 0.512ns) Clock Net Delay (Destination): 0.939ns (routing 0.313ns, distribution 0.626ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y194 FDPE r SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y194 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 0.952 f SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.178 1.130 SFP_GEN[9].ngCCM_gbt/sync_m_reg[3][0] SLICE_X112Y195 FDCE f SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.939 1.104 SFP_GEN[9].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X112Y195 FDCE r SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[0]/C clock pessimism -0.129 0.975 SLICE_X112Y195 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 0.980 SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[0] ------------------------------------------------------------------- required time -0.980 arrival time 1.130 ------------------------------------------------------------------- slack 0.150 Slack (MET) : 0.150ns (arrival time - required time) Source: SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.226ns (logic 0.048ns (21.239%) route 0.178ns (78.761%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.104ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.129ns Clock Net Delay (Source): 0.786ns (routing 0.274ns, distribution 0.512ns) Clock Net Delay (Destination): 0.939ns (routing 0.313ns, distribution 0.626ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y194 FDPE r SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y194 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 0.952 f SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.178 1.130 SFP_GEN[9].ngCCM_gbt/sync_m_reg[3][0] SLICE_X112Y195 FDCE f SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.939 1.104 SFP_GEN[9].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X112Y195 FDCE r SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[2]/C clock pessimism -0.129 0.975 SLICE_X112Y195 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 0.980 SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[2] ------------------------------------------------------------------- required time -0.980 arrival time 1.130 ------------------------------------------------------------------- slack 0.150 Slack (MET) : 0.150ns (arrival time - required time) Source: SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[40]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.226ns (logic 0.048ns (21.239%) route 0.178ns (78.761%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.104ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.129ns Clock Net Delay (Source): 0.786ns (routing 0.274ns, distribution 0.512ns) Clock Net Delay (Destination): 0.939ns (routing 0.313ns, distribution 0.626ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y194 FDPE r SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y194 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 0.952 f SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.178 1.130 SFP_GEN[9].ngCCM_gbt/sync_m_reg[3][0] SLICE_X112Y195 FDCE f SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[40]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.939 1.104 SFP_GEN[9].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X112Y195 FDCE r SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[40]/C clock pessimism -0.129 0.975 SLICE_X112Y195 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 0.980 SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[40] ------------------------------------------------------------------- required time -0.980 arrival time 1.130 ------------------------------------------------------------------- slack 0.150 Slack (MET) : 0.150ns (arrival time - required time) Source: SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[42]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.226ns (logic 0.048ns (21.239%) route 0.178ns (78.761%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.104ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.129ns Clock Net Delay (Source): 0.786ns (routing 0.274ns, distribution 0.512ns) Clock Net Delay (Destination): 0.939ns (routing 0.313ns, distribution 0.626ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y194 FDPE r SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y194 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 0.952 f SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.178 1.130 SFP_GEN[9].ngCCM_gbt/sync_m_reg[3][0] SLICE_X112Y195 FDCE f SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[42]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.939 1.104 SFP_GEN[9].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X112Y195 FDCE r SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[42]/C clock pessimism -0.129 0.975 SLICE_X112Y195 FDCE (Remov_GFF2_SLICEM_C_CLR) 0.005 0.980 SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[42] ------------------------------------------------------------------- required time -0.980 arrival time 1.130 ------------------------------------------------------------------- slack 0.150 Slack (MET) : 0.181ns (arrival time - required time) Source: SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[68]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.048ns (17.844%) route 0.221ns (82.156%)) Logic Levels: 0 Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.116ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.129ns Clock Net Delay (Source): 0.786ns (routing 0.274ns, distribution 0.512ns) Clock Net Delay (Destination): 0.951ns (routing 0.313ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y194 FDPE r SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y194 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 0.952 f SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.221 1.173 SFP_GEN[9].ngCCM_gbt/sync_m_reg[3][0] SLICE_X114Y193 FDCE f SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[68]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.951 1.116 SFP_GEN[9].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X114Y193 FDCE r SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[68]/C clock pessimism -0.129 0.987 SLICE_X114Y193 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 0.992 SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[68] ------------------------------------------------------------------- required time -0.992 arrival time 1.173 ------------------------------------------------------------------- slack 0.181 Slack (MET) : 0.181ns (arrival time - required time) Source: SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[70]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.048ns (17.844%) route 0.221ns (82.156%)) Logic Levels: 0 Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.116ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.129ns Clock Net Delay (Source): 0.786ns (routing 0.274ns, distribution 0.512ns) Clock Net Delay (Destination): 0.951ns (routing 0.313ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y194 FDPE r SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y194 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 0.952 f SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.221 1.173 SFP_GEN[9].ngCCM_gbt/sync_m_reg[3][0] SLICE_X114Y193 FDCE f SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[70]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.951 1.116 SFP_GEN[9].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X114Y193 FDCE r SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[70]/C clock pessimism -0.129 0.987 SLICE_X114Y193 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 0.992 SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[70] ------------------------------------------------------------------- required time -0.992 arrival time 1.173 ------------------------------------------------------------------- slack 0.181 Slack (MET) : 0.184ns (arrival time - required time) Source: SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[48]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.275ns (logic 0.048ns (17.455%) route 0.227ns (82.545%)) Logic Levels: 0 Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.119ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.129ns Clock Net Delay (Source): 0.786ns (routing 0.274ns, distribution 0.512ns) Clock Net Delay (Destination): 0.954ns (routing 0.313ns, distribution 0.641ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y194 FDPE r SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y194 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 0.952 f SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.227 1.179 SFP_GEN[9].ngCCM_gbt/sync_m_reg[3][0] SLICE_X114Y193 FDCE f SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[48]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.954 1.119 SFP_GEN[9].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X114Y193 FDCE r SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[48]/C clock pessimism -0.129 0.990 SLICE_X114Y193 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 0.995 SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[48] ------------------------------------------------------------------- required time -0.995 arrival time 1.179 ------------------------------------------------------------------- slack 0.184 Slack (MET) : 0.184ns (arrival time - required time) Source: SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[50]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.275ns (logic 0.048ns (17.455%) route 0.227ns (82.545%)) Logic Levels: 0 Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.119ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.129ns Clock Net Delay (Source): 0.786ns (routing 0.274ns, distribution 0.512ns) Clock Net Delay (Destination): 0.954ns (routing 0.313ns, distribution 0.641ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y194 FDPE r SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y194 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 0.952 f SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.227 1.179 SFP_GEN[9].ngCCM_gbt/sync_m_reg[3][0] SLICE_X114Y193 FDCE f SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[50]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.954 1.119 SFP_GEN[9].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X114Y193 FDCE r SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[50]/C clock pessimism -0.129 0.990 SLICE_X114Y193 FDCE (Remov_DFF2_SLICEL_C_CLR) 0.005 0.995 SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[50] ------------------------------------------------------------------- required time -0.995 arrival time 1.179 ------------------------------------------------------------------- slack 0.184 Slack (MET) : 0.185ns (arrival time - required time) Source: SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[44]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.275ns (logic 0.048ns (17.455%) route 0.227ns (82.545%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.118ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.129ns Clock Net Delay (Source): 0.786ns (routing 0.274ns, distribution 0.512ns) Clock Net Delay (Destination): 0.953ns (routing 0.313ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y194 FDPE r SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y194 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 0.952 f SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.227 1.179 SFP_GEN[9].ngCCM_gbt/sync_m_reg[3][0] SLICE_X114Y195 FDCE f SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[44]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.953 1.118 SFP_GEN[9].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X114Y195 FDCE r SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[44]/C clock pessimism -0.129 0.989 SLICE_X114Y195 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 0.994 SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[44] ------------------------------------------------------------------- required time -0.994 arrival time 1.179 ------------------------------------------------------------------- slack 0.185 Slack (MET) : 0.185ns (arrival time - required time) Source: SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[46]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.275ns (logic 0.048ns (17.455%) route 0.227ns (82.545%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.118ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.129ns Clock Net Delay (Source): 0.786ns (routing 0.274ns, distribution 0.512ns) Clock Net Delay (Destination): 0.953ns (routing 0.313ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y194 FDPE r SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y194 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 0.952 f SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.227 1.179 SFP_GEN[9].ngCCM_gbt/sync_m_reg[3][0] SLICE_X114Y195 FDCE f SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[46]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.953 1.118 SFP_GEN[9].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X114Y195 FDCE r SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[46]/C clock pessimism -0.129 0.989 SLICE_X114Y195 FDCE (Remov_DFF2_SLICEL_C_CLR) 0.005 0.994 SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[46] ------------------------------------------------------------------- required time -0.994 arrival time 1.179 ------------------------------------------------------------------- slack 0.185 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_12 To Clock: gtwiz_userclk_rx_srcclk_out[0]_12 Setup : 0 Failing Endpoints, Worst Slack 4.590ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.138ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.590ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 3.622ns (logic 0.231ns (6.378%) route 3.391ns (93.622%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.023ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.628ns = ( 10.945 - 8.317 ) Source Clock Delay (SCD): 2.828ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.353ns (routing 0.667ns, distribution 1.686ns) Clock Net Delay (Destination): 2.230ns (routing 0.604ns, distribution 1.626ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.353 2.828 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y420 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y420 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.967 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.770 5.737 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X87Y418 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 5.829 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/O net (fo=15, routed) 0.621 6.450 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X86Y421 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.230 10.945 g_gbt_bank[1].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y421 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/C clock pessimism 0.223 11.168 clock uncertainty -0.035 11.133 SLICE_X86Y421 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 11.040 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0] ------------------------------------------------------------------- required time 11.040 arrival time -6.450 ------------------------------------------------------------------- slack 4.590 Slack (MET) : 4.598ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 3.612ns (logic 0.231ns (6.395%) route 3.381ns (93.605%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.626ns = ( 10.943 - 8.317 ) Source Clock Delay (SCD): 2.828ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.353ns (routing 0.667ns, distribution 1.686ns) Clock Net Delay (Destination): 2.228ns (routing 0.604ns, distribution 1.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.353 2.828 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y420 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y420 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.967 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.770 5.737 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X87Y418 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 5.829 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/O net (fo=15, routed) 0.611 6.440 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X86Y421 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.228 10.943 g_gbt_bank[1].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y421 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/C clock pessimism 0.223 11.166 clock uncertainty -0.035 11.131 SLICE_X86Y421 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 11.038 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1] ------------------------------------------------------------------- required time 11.038 arrival time -6.440 ------------------------------------------------------------------- slack 4.598 Slack (MET) : 4.598ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 3.612ns (logic 0.231ns (6.395%) route 3.381ns (93.605%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.626ns = ( 10.943 - 8.317 ) Source Clock Delay (SCD): 2.828ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.353ns (routing 0.667ns, distribution 1.686ns) Clock Net Delay (Destination): 2.228ns (routing 0.604ns, distribution 1.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.353 2.828 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y420 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y420 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.967 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.770 5.737 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X87Y418 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 5.829 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/O net (fo=15, routed) 0.611 6.440 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X86Y421 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.228 10.943 g_gbt_bank[1].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y421 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/C clock pessimism 0.223 11.166 clock uncertainty -0.035 11.131 SLICE_X86Y421 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 11.038 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0] ------------------------------------------------------------------- required time 11.038 arrival time -6.440 ------------------------------------------------------------------- slack 4.598 Slack (MET) : 4.598ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 3.612ns (logic 0.231ns (6.395%) route 3.381ns (93.605%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.626ns = ( 10.943 - 8.317 ) Source Clock Delay (SCD): 2.828ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.353ns (routing 0.667ns, distribution 1.686ns) Clock Net Delay (Destination): 2.228ns (routing 0.604ns, distribution 1.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.353 2.828 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y420 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y420 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.967 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.770 5.737 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X87Y418 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 5.829 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/O net (fo=15, routed) 0.611 6.440 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X86Y421 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.228 10.943 g_gbt_bank[1].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y421 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/C clock pessimism 0.223 11.166 clock uncertainty -0.035 11.131 SLICE_X86Y421 FDCE (Recov_GFF2_SLICEL_C_CLR) -0.093 11.038 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5] ------------------------------------------------------------------- required time 11.038 arrival time -6.440 ------------------------------------------------------------------- slack 4.598 Slack (MET) : 4.601ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 3.614ns (logic 0.231ns (6.392%) route 3.383ns (93.608%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.026ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.631ns = ( 10.948 - 8.317 ) Source Clock Delay (SCD): 2.828ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.353ns (routing 0.667ns, distribution 1.686ns) Clock Net Delay (Destination): 2.233ns (routing 0.604ns, distribution 1.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.353 2.828 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y420 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y420 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.967 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.770 5.737 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X87Y418 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 5.829 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/O net (fo=15, routed) 0.613 6.442 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X85Y421 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.233 10.948 g_gbt_bank[1].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y421 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/C clock pessimism 0.223 11.171 clock uncertainty -0.035 11.136 SLICE_X85Y421 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.043 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1] ------------------------------------------------------------------- required time 11.043 arrival time -6.442 ------------------------------------------------------------------- slack 4.601 Slack (MET) : 4.601ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 3.614ns (logic 0.231ns (6.392%) route 3.383ns (93.608%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.026ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.631ns = ( 10.948 - 8.317 ) Source Clock Delay (SCD): 2.828ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.353ns (routing 0.667ns, distribution 1.686ns) Clock Net Delay (Destination): 2.233ns (routing 0.604ns, distribution 1.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.353 2.828 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y420 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y420 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.967 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.770 5.737 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X87Y418 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 5.829 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/O net (fo=15, routed) 0.613 6.442 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X85Y421 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.233 10.948 g_gbt_bank[1].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y421 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/C clock pessimism 0.223 11.171 clock uncertainty -0.035 11.136 SLICE_X85Y421 FDCE (Recov_HFF2_SLICEM_C_CLR) -0.093 11.043 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2] ------------------------------------------------------------------- required time 11.043 arrival time -6.442 ------------------------------------------------------------------- slack 4.601 Slack (MET) : 4.601ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 3.614ns (logic 0.231ns (6.392%) route 3.383ns (93.608%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.026ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.631ns = ( 10.948 - 8.317 ) Source Clock Delay (SCD): 2.828ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.353ns (routing 0.667ns, distribution 1.686ns) Clock Net Delay (Destination): 2.233ns (routing 0.604ns, distribution 1.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.353 2.828 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y420 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y420 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.967 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.770 5.737 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X87Y418 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 5.829 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/O net (fo=15, routed) 0.613 6.442 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X85Y421 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.233 10.948 g_gbt_bank[1].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y421 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/C clock pessimism 0.223 11.171 clock uncertainty -0.035 11.136 SLICE_X85Y421 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 11.043 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3] ------------------------------------------------------------------- required time 11.043 arrival time -6.442 ------------------------------------------------------------------- slack 4.601 Slack (MET) : 4.601ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 3.614ns (logic 0.231ns (6.392%) route 3.383ns (93.608%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.026ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.631ns = ( 10.948 - 8.317 ) Source Clock Delay (SCD): 2.828ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.353ns (routing 0.667ns, distribution 1.686ns) Clock Net Delay (Destination): 2.233ns (routing 0.604ns, distribution 1.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.353 2.828 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y420 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y420 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.967 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.770 5.737 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X87Y418 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 5.829 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/O net (fo=15, routed) 0.613 6.442 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X85Y421 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.233 10.948 g_gbt_bank[1].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y421 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/C clock pessimism 0.223 11.171 clock uncertainty -0.035 11.136 SLICE_X85Y421 FDCE (Recov_GFF_SLICEM_C_CLR) -0.093 11.043 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4] ------------------------------------------------------------------- required time 11.043 arrival time -6.442 ------------------------------------------------------------------- slack 4.601 Slack (MET) : 4.665ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 3.531ns (logic 0.231ns (6.542%) route 3.300ns (93.458%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.007ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.612ns = ( 10.929 - 8.317 ) Source Clock Delay (SCD): 2.828ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.353ns (routing 0.667ns, distribution 1.686ns) Clock Net Delay (Destination): 2.214ns (routing 0.604ns, distribution 1.610ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.353 2.828 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y420 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y420 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.967 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.770 5.737 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X87Y418 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 5.829 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/O net (fo=15, routed) 0.530 6.359 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X86Y420 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.214 10.929 g_gbt_bank[1].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y420 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/C clock pessimism 0.223 11.152 clock uncertainty -0.035 11.117 SLICE_X86Y420 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.024 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2] ------------------------------------------------------------------- required time 11.024 arrival time -6.359 ------------------------------------------------------------------- slack 4.665 Slack (MET) : 4.665ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 3.531ns (logic 0.231ns (6.542%) route 3.300ns (93.458%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.007ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.612ns = ( 10.929 - 8.317 ) Source Clock Delay (SCD): 2.828ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.353ns (routing 0.667ns, distribution 1.686ns) Clock Net Delay (Destination): 2.214ns (routing 0.604ns, distribution 1.610ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.353 2.828 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y420 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y420 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.967 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.770 5.737 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X87Y418 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 5.829 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/O net (fo=15, routed) 0.530 6.359 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X86Y420 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.214 10.929 g_gbt_bank[1].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y420 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/C clock pessimism 0.223 11.152 clock uncertainty -0.035 11.117 SLICE_X86Y420 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.024 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3] ------------------------------------------------------------------- required time 11.024 arrival time -6.359 ------------------------------------------------------------------- slack 4.665 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.138ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.334ns Source Clock Delay (SCD): 1.102ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.984ns (routing 0.303ns, distribution 0.681ns) Clock Net Delay (Destination): 1.169ns (routing 0.344ns, distribution 0.825ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.984 1.102 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X80Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y425 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.151 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.175 1.326 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X78Y425 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.169 1.334 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X78Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C clock pessimism -0.151 1.183 SLICE_X78Y425 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.188 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time -1.188 arrival time 1.326 ------------------------------------------------------------------- slack 0.138 Slack (MET) : 0.138ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.334ns Source Clock Delay (SCD): 1.102ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.984ns (routing 0.303ns, distribution 0.681ns) Clock Net Delay (Destination): 1.169ns (routing 0.344ns, distribution 0.825ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.984 1.102 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X80Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y425 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.151 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.175 1.326 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X78Y425 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.169 1.334 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X78Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C clock pessimism -0.151 1.183 SLICE_X78Y425 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.188 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time -1.188 arrival time 1.326 ------------------------------------------------------------------- slack 0.138 Slack (MET) : 0.177ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.263ns (logic 0.049ns (18.631%) route 0.214ns (81.369%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.334ns Source Clock Delay (SCD): 1.102ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.984ns (routing 0.303ns, distribution 0.681ns) Clock Net Delay (Destination): 1.169ns (routing 0.344ns, distribution 0.825ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.984 1.102 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X80Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y425 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.151 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.214 1.365 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X76Y425 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.169 1.334 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X76Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C clock pessimism -0.151 1.183 SLICE_X76Y425 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.188 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11] ------------------------------------------------------------------- required time -1.188 arrival time 1.365 ------------------------------------------------------------------- slack 0.177 Slack (MET) : 0.177ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.263ns (logic 0.049ns (18.631%) route 0.214ns (81.369%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.334ns Source Clock Delay (SCD): 1.102ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.984ns (routing 0.303ns, distribution 0.681ns) Clock Net Delay (Destination): 1.169ns (routing 0.344ns, distribution 0.825ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.984 1.102 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X80Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y425 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.151 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.214 1.365 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X76Y425 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.169 1.334 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X76Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C clock pessimism -0.151 1.183 SLICE_X76Y425 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 1.188 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13] ------------------------------------------------------------------- required time -1.188 arrival time 1.365 ------------------------------------------------------------------- slack 0.177 Slack (MET) : 0.177ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.263ns (logic 0.049ns (18.631%) route 0.214ns (81.369%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.334ns Source Clock Delay (SCD): 1.102ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.984ns (routing 0.303ns, distribution 0.681ns) Clock Net Delay (Destination): 1.169ns (routing 0.344ns, distribution 0.825ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.984 1.102 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X80Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y425 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.151 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.214 1.365 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X76Y425 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.169 1.334 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X76Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C clock pessimism -0.151 1.183 SLICE_X76Y425 FDCE (Remov_BFF_SLICEM_C_CLR) 0.005 1.188 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15] ------------------------------------------------------------------- required time -1.188 arrival time 1.365 ------------------------------------------------------------------- slack 0.177 Slack (MET) : 0.177ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.263ns (logic 0.049ns (18.631%) route 0.214ns (81.369%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.334ns Source Clock Delay (SCD): 1.102ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.984ns (routing 0.303ns, distribution 0.681ns) Clock Net Delay (Destination): 1.169ns (routing 0.344ns, distribution 0.825ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.984 1.102 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X80Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y425 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.151 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.214 1.365 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X76Y425 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.169 1.334 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X76Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism -0.151 1.183 SLICE_X76Y425 FDCE (Remov_BFF2_SLICEM_C_CLR) 0.005 1.188 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time -1.188 arrival time 1.365 ------------------------------------------------------------------- slack 0.177 Slack (MET) : 0.177ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.263ns (logic 0.049ns (18.631%) route 0.214ns (81.369%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.334ns Source Clock Delay (SCD): 1.102ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.984ns (routing 0.303ns, distribution 0.681ns) Clock Net Delay (Destination): 1.169ns (routing 0.344ns, distribution 0.825ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.984 1.102 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X80Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y425 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.151 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.214 1.365 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X76Y425 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.169 1.334 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X76Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C clock pessimism -0.151 1.183 SLICE_X76Y425 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 1.188 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time -1.188 arrival time 1.365 ------------------------------------------------------------------- slack 0.177 Slack (MET) : 0.177ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.263ns (logic 0.049ns (18.631%) route 0.214ns (81.369%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.334ns Source Clock Delay (SCD): 1.102ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.984ns (routing 0.303ns, distribution 0.681ns) Clock Net Delay (Destination): 1.169ns (routing 0.344ns, distribution 0.825ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.984 1.102 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X80Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y425 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.151 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.214 1.365 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X76Y425 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.169 1.334 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X76Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.151 1.183 SLICE_X76Y425 FDCE (Remov_CFF2_SLICEM_C_CLR) 0.005 1.188 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -1.188 arrival time 1.365 ------------------------------------------------------------------- slack 0.177 Slack (MET) : 0.177ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.263ns (logic 0.049ns (18.631%) route 0.214ns (81.369%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.334ns Source Clock Delay (SCD): 1.102ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.984ns (routing 0.303ns, distribution 0.681ns) Clock Net Delay (Destination): 1.169ns (routing 0.344ns, distribution 0.825ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.984 1.102 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X80Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y425 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.151 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.214 1.365 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X76Y425 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.169 1.334 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X76Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C clock pessimism -0.151 1.183 SLICE_X76Y425 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.188 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19] ------------------------------------------------------------------- required time -1.188 arrival time 1.365 ------------------------------------------------------------------- slack 0.177 Slack (MET) : 0.177ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.263ns (logic 0.049ns (18.631%) route 0.214ns (81.369%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.334ns Source Clock Delay (SCD): 1.102ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.984ns (routing 0.303ns, distribution 0.681ns) Clock Net Delay (Destination): 1.169ns (routing 0.344ns, distribution 0.825ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.984 1.102 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X80Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y425 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.151 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.214 1.365 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X76Y425 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.169 1.334 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X76Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C clock pessimism -0.151 1.183 SLICE_X76Y425 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 1.188 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20] ------------------------------------------------------------------- required time -1.188 arrival time 1.365 ------------------------------------------------------------------- slack 0.177 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_13 To Clock: gtwiz_userclk_rx_srcclk_out[0]_13 Setup : 0 Failing Endpoints, Worst Slack 2.594ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.149ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.594ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 5.372ns (logic 0.364ns (6.776%) route 5.008ns (93.224%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.294ns = ( 10.611 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.265ns (routing 0.623ns, distribution 1.642ns) Clock Net Delay (Destination): 1.896ns (routing 0.566ns, distribution 1.330ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.265 2.740 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X137Y577 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y577 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.879 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.776 5.655 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X119Y444 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.880 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/O net (fo=15, routed) 2.232 8.112 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X121Y570 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.896 10.611 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X121Y570 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/C clock pessimism 0.223 10.835 clock uncertainty -0.035 10.799 SLICE_X121Y570 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.706 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1] ------------------------------------------------------------------- required time 10.706 arrival time -8.112 ------------------------------------------------------------------- slack 2.594 Slack (MET) : 2.594ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 5.372ns (logic 0.364ns (6.776%) route 5.008ns (93.224%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.294ns = ( 10.611 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.265ns (routing 0.623ns, distribution 1.642ns) Clock Net Delay (Destination): 1.896ns (routing 0.566ns, distribution 1.330ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.265 2.740 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X137Y577 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y577 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.879 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.776 5.655 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X119Y444 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.880 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/O net (fo=15, routed) 2.232 8.112 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X121Y570 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.896 10.611 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X121Y570 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/C clock pessimism 0.223 10.835 clock uncertainty -0.035 10.799 SLICE_X121Y570 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 10.706 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2] ------------------------------------------------------------------- required time 10.706 arrival time -8.112 ------------------------------------------------------------------- slack 2.594 Slack (MET) : 2.594ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 5.372ns (logic 0.364ns (6.776%) route 5.008ns (93.224%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.294ns = ( 10.611 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.265ns (routing 0.623ns, distribution 1.642ns) Clock Net Delay (Destination): 1.896ns (routing 0.566ns, distribution 1.330ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.265 2.740 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X137Y577 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y577 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.879 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.776 5.655 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X119Y444 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.880 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/O net (fo=15, routed) 2.232 8.112 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X121Y570 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.896 10.611 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X121Y570 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C clock pessimism 0.223 10.835 clock uncertainty -0.035 10.799 SLICE_X121Y570 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.706 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3] ------------------------------------------------------------------- required time 10.706 arrival time -8.112 ------------------------------------------------------------------- slack 2.594 Slack (MET) : 2.594ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 5.372ns (logic 0.364ns (6.776%) route 5.008ns (93.224%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.294ns = ( 10.611 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.265ns (routing 0.623ns, distribution 1.642ns) Clock Net Delay (Destination): 1.896ns (routing 0.566ns, distribution 1.330ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.265 2.740 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X137Y577 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y577 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.879 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.776 5.655 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X119Y444 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.880 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/O net (fo=15, routed) 2.232 8.112 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X121Y570 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.896 10.611 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X121Y570 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/C clock pessimism 0.223 10.835 clock uncertainty -0.035 10.799 SLICE_X121Y570 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.706 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4] ------------------------------------------------------------------- required time 10.706 arrival time -8.112 ------------------------------------------------------------------- slack 2.594 Slack (MET) : 2.676ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 5.281ns (logic 0.364ns (6.893%) route 4.917ns (93.107%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.285ns = ( 10.602 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.265ns (routing 0.623ns, distribution 1.642ns) Clock Net Delay (Destination): 1.887ns (routing 0.566ns, distribution 1.321ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.265 2.740 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X137Y577 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y577 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.879 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.776 5.655 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X119Y444 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.880 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/O net (fo=15, routed) 2.141 8.021 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X122Y569 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.887 10.602 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X122Y569 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/C clock pessimism 0.223 10.826 clock uncertainty -0.035 10.790 SLICE_X122Y569 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 10.697 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0] ------------------------------------------------------------------- required time 10.697 arrival time -8.021 ------------------------------------------------------------------- slack 2.676 Slack (MET) : 2.676ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 5.281ns (logic 0.364ns (6.893%) route 4.917ns (93.107%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.285ns = ( 10.602 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.265ns (routing 0.623ns, distribution 1.642ns) Clock Net Delay (Destination): 1.887ns (routing 0.566ns, distribution 1.321ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.265 2.740 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X137Y577 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y577 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.879 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.776 5.655 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X119Y444 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.880 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/O net (fo=15, routed) 2.141 8.021 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X122Y569 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.887 10.602 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X122Y569 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/C clock pessimism 0.223 10.826 clock uncertainty -0.035 10.790 SLICE_X122Y569 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.697 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1] ------------------------------------------------------------------- required time 10.697 arrival time -8.021 ------------------------------------------------------------------- slack 2.676 Slack (MET) : 2.676ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 5.281ns (logic 0.364ns (6.893%) route 4.917ns (93.107%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.285ns = ( 10.602 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.265ns (routing 0.623ns, distribution 1.642ns) Clock Net Delay (Destination): 1.887ns (routing 0.566ns, distribution 1.321ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.265 2.740 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X137Y577 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y577 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.879 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.776 5.655 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X119Y444 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.880 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/O net (fo=15, routed) 2.141 8.021 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X122Y569 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.887 10.602 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X122Y569 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/C clock pessimism 0.223 10.826 clock uncertainty -0.035 10.790 SLICE_X122Y569 FDCE (Recov_BFF2_SLICEL_C_CLR) -0.093 10.697 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2] ------------------------------------------------------------------- required time 10.697 arrival time -8.021 ------------------------------------------------------------------- slack 2.676 Slack (MET) : 2.684ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 5.271ns (logic 0.364ns (6.906%) route 4.907ns (93.094%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.283ns = ( 10.600 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.265ns (routing 0.623ns, distribution 1.642ns) Clock Net Delay (Destination): 1.885ns (routing 0.566ns, distribution 1.319ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.265 2.740 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X137Y577 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y577 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.879 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.776 5.655 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X119Y444 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.880 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/O net (fo=15, routed) 2.131 8.011 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X122Y569 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.885 10.600 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X122Y569 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/C clock pessimism 0.223 10.824 clock uncertainty -0.035 10.788 SLICE_X122Y569 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.695 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10] ------------------------------------------------------------------- required time 10.695 arrival time -8.011 ------------------------------------------------------------------- slack 2.684 Slack (MET) : 2.684ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 5.271ns (logic 0.364ns (6.906%) route 4.907ns (93.094%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.283ns = ( 10.600 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.265ns (routing 0.623ns, distribution 1.642ns) Clock Net Delay (Destination): 1.885ns (routing 0.566ns, distribution 1.319ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.265 2.740 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X137Y577 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y577 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.879 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.776 5.655 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X119Y444 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.880 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/O net (fo=15, routed) 2.131 8.011 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X122Y569 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.885 10.600 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X122Y569 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/C clock pessimism 0.223 10.824 clock uncertainty -0.035 10.788 SLICE_X122Y569 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 10.695 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0] ------------------------------------------------------------------- required time 10.695 arrival time -8.011 ------------------------------------------------------------------- slack 2.684 Slack (MET) : 2.684ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 5.271ns (logic 0.364ns (6.906%) route 4.907ns (93.094%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.283ns = ( 10.600 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.265ns (routing 0.623ns, distribution 1.642ns) Clock Net Delay (Destination): 1.885ns (routing 0.566ns, distribution 1.319ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.265 2.740 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X137Y577 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y577 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.879 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.776 5.655 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X119Y444 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.880 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/O net (fo=15, routed) 2.131 8.011 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X122Y569 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.885 10.600 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X122Y569 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][5]/C clock pessimism 0.223 10.824 clock uncertainty -0.035 10.788 SLICE_X122Y569 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 10.695 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][5] ------------------------------------------------------------------- required time 10.695 arrival time -8.011 ------------------------------------------------------------------- slack 2.684 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.149ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.225ns (logic 0.049ns (21.778%) route 0.176ns (78.222%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.140ns Source Clock Delay (SCD): 0.928ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 0.810ns (routing 0.271ns, distribution 0.539ns) Clock Net Delay (Destination): 0.975ns (routing 0.311ns, distribution 0.664ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.810 0.928 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X122Y576 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y576 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.977 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.176 1.153 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X124Y575 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.975 1.140 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X124Y575 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C clock pessimism -0.141 0.999 SLICE_X124Y575 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.004 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10] ------------------------------------------------------------------- required time -1.004 arrival time 1.153 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.149ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.225ns (logic 0.049ns (21.778%) route 0.176ns (78.222%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.140ns Source Clock Delay (SCD): 0.928ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 0.810ns (routing 0.271ns, distribution 0.539ns) Clock Net Delay (Destination): 0.975ns (routing 0.311ns, distribution 0.664ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.810 0.928 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X122Y576 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y576 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.977 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.176 1.153 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X124Y575 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.975 1.140 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X124Y575 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C clock pessimism -0.141 0.999 SLICE_X124Y575 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.004 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11] ------------------------------------------------------------------- required time -1.004 arrival time 1.153 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.149ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.225ns (logic 0.049ns (21.778%) route 0.176ns (78.222%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.140ns Source Clock Delay (SCD): 0.928ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 0.810ns (routing 0.271ns, distribution 0.539ns) Clock Net Delay (Destination): 0.975ns (routing 0.311ns, distribution 0.664ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.810 0.928 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X122Y576 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y576 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.977 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.176 1.153 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X124Y575 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.975 1.140 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X124Y575 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C clock pessimism -0.141 0.999 SLICE_X124Y575 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.004 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12] ------------------------------------------------------------------- required time -1.004 arrival time 1.153 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.149ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.225ns (logic 0.049ns (21.778%) route 0.176ns (78.222%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.140ns Source Clock Delay (SCD): 0.928ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 0.810ns (routing 0.271ns, distribution 0.539ns) Clock Net Delay (Destination): 0.975ns (routing 0.311ns, distribution 0.664ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.810 0.928 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X122Y576 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y576 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.977 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.176 1.153 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X124Y575 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.975 1.140 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X124Y575 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C clock pessimism -0.141 0.999 SLICE_X124Y575 FDCE (Remov_FFF2_SLICEL_C_CLR) 0.005 1.004 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13] ------------------------------------------------------------------- required time -1.004 arrival time 1.153 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.149ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.225ns (logic 0.049ns (21.778%) route 0.176ns (78.222%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.140ns Source Clock Delay (SCD): 0.928ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 0.810ns (routing 0.271ns, distribution 0.539ns) Clock Net Delay (Destination): 0.975ns (routing 0.311ns, distribution 0.664ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.810 0.928 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X122Y576 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y576 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.977 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.176 1.153 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X124Y575 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.975 1.140 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X124Y575 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C clock pessimism -0.141 0.999 SLICE_X124Y575 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 1.004 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14] ------------------------------------------------------------------- required time -1.004 arrival time 1.153 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.149ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.225ns (logic 0.049ns (21.778%) route 0.176ns (78.222%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.140ns Source Clock Delay (SCD): 0.928ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 0.810ns (routing 0.271ns, distribution 0.539ns) Clock Net Delay (Destination): 0.975ns (routing 0.311ns, distribution 0.664ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.810 0.928 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X122Y576 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y576 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.977 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.176 1.153 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X124Y575 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.975 1.140 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X124Y575 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C clock pessimism -0.141 0.999 SLICE_X124Y575 FDCE (Remov_GFF2_SLICEL_C_CLR) 0.005 1.004 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15] ------------------------------------------------------------------- required time -1.004 arrival time 1.153 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.149ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.225ns (logic 0.049ns (21.778%) route 0.176ns (78.222%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.140ns Source Clock Delay (SCD): 0.928ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 0.810ns (routing 0.271ns, distribution 0.539ns) Clock Net Delay (Destination): 0.975ns (routing 0.311ns, distribution 0.664ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.810 0.928 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X122Y576 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y576 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.977 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.176 1.153 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X124Y575 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.975 1.140 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X124Y575 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C clock pessimism -0.141 0.999 SLICE_X124Y575 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.004 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8] ------------------------------------------------------------------- required time -1.004 arrival time 1.153 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.149ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.225ns (logic 0.049ns (21.778%) route 0.176ns (78.222%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.140ns Source Clock Delay (SCD): 0.928ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 0.810ns (routing 0.271ns, distribution 0.539ns) Clock Net Delay (Destination): 0.975ns (routing 0.311ns, distribution 0.664ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.810 0.928 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X122Y576 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y576 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.977 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.176 1.153 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X124Y575 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.975 1.140 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X124Y575 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism -0.141 0.999 SLICE_X124Y575 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 1.004 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time -1.004 arrival time 1.153 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.150ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.138ns Source Clock Delay (SCD): 0.928ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 0.810ns (routing 0.271ns, distribution 0.539ns) Clock Net Delay (Destination): 0.973ns (routing 0.311ns, distribution 0.662ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.810 0.928 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X122Y576 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y576 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.977 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.175 1.152 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X123Y575 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.973 1.138 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X123Y575 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C clock pessimism -0.141 0.997 SLICE_X123Y575 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.002 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11] ------------------------------------------------------------------- required time -1.002 arrival time 1.152 ------------------------------------------------------------------- slack 0.150 Slack (MET) : 0.150ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.138ns Source Clock Delay (SCD): 0.928ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 0.810ns (routing 0.271ns, distribution 0.539ns) Clock Net Delay (Destination): 0.973ns (routing 0.311ns, distribution 0.662ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.810 0.928 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X122Y576 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y576 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.977 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.175 1.152 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X123Y575 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.973 1.138 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X123Y575 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C clock pessimism -0.141 0.997 SLICE_X123Y575 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.002 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time -1.002 arrival time 1.152 ------------------------------------------------------------------- slack 0.150 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_14 To Clock: gtwiz_userclk_rx_srcclk_out[0]_14 Setup : 0 Failing Endpoints, Worst Slack 4.428ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.227ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.428ns (required time - arrival time) Source: SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[72]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 3.585ns (logic 0.139ns (3.877%) route 3.446ns (96.123%)) Logic Levels: 0 Clock Path Skew: -0.176ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.215ns = ( 10.532 - 8.317 ) Source Clock Delay (SCD): 2.599ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.124ns (routing 0.620ns, distribution 1.504ns) Clock Net Delay (Destination): 1.817ns (routing 0.564ns, distribution 1.253ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.124 2.599 SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y545 FDPE r SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y545 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 2.738 f SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 3.446 6.184 SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] SLICE_X106Y549 FDCE f SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[72]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.817 10.532 SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y549 FDCE r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[72]/C clock pessimism 0.208 10.740 clock uncertainty -0.035 10.705 SLICE_X106Y549 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.612 SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[72] ------------------------------------------------------------------- required time 10.612 arrival time -6.184 ------------------------------------------------------------------- slack 4.428 Slack (MET) : 4.428ns (required time - arrival time) Source: SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[74]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 3.585ns (logic 0.139ns (3.877%) route 3.446ns (96.123%)) Logic Levels: 0 Clock Path Skew: -0.176ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.215ns = ( 10.532 - 8.317 ) Source Clock Delay (SCD): 2.599ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.124ns (routing 0.620ns, distribution 1.504ns) Clock Net Delay (Destination): 1.817ns (routing 0.564ns, distribution 1.253ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.124 2.599 SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y545 FDPE r SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y545 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 2.738 f SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 3.446 6.184 SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] SLICE_X106Y549 FDCE f SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[74]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.817 10.532 SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y549 FDCE r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[74]/C clock pessimism 0.208 10.740 clock uncertainty -0.035 10.705 SLICE_X106Y549 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 10.612 SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[74] ------------------------------------------------------------------- required time 10.612 arrival time -6.184 ------------------------------------------------------------------- slack 4.428 Slack (MET) : 4.497ns (required time - arrival time) Source: SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[64]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 3.515ns (logic 0.139ns (3.954%) route 3.376ns (96.046%)) Logic Levels: 0 Clock Path Skew: -0.177ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.214ns = ( 10.531 - 8.317 ) Source Clock Delay (SCD): 2.599ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.124ns (routing 0.620ns, distribution 1.504ns) Clock Net Delay (Destination): 1.816ns (routing 0.564ns, distribution 1.252ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.124 2.599 SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y545 FDPE r SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y545 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 2.738 f SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 3.376 6.114 SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] SLICE_X106Y551 FDCE f SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[64]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.816 10.531 SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y551 FDCE r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[64]/C clock pessimism 0.208 10.739 clock uncertainty -0.035 10.704 SLICE_X106Y551 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.611 SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[64] ------------------------------------------------------------------- required time 10.611 arrival time -6.114 ------------------------------------------------------------------- slack 4.497 Slack (MET) : 4.497ns (required time - arrival time) Source: SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[66]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 3.515ns (logic 0.139ns (3.954%) route 3.376ns (96.046%)) Logic Levels: 0 Clock Path Skew: -0.177ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.214ns = ( 10.531 - 8.317 ) Source Clock Delay (SCD): 2.599ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.124ns (routing 0.620ns, distribution 1.504ns) Clock Net Delay (Destination): 1.816ns (routing 0.564ns, distribution 1.252ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.124 2.599 SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y545 FDPE r SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y545 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 2.738 f SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 3.376 6.114 SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] SLICE_X106Y551 FDCE f SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[66]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.816 10.531 SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y551 FDCE r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[66]/C clock pessimism 0.208 10.739 clock uncertainty -0.035 10.704 SLICE_X106Y551 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 10.611 SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[66] ------------------------------------------------------------------- required time 10.611 arrival time -6.114 ------------------------------------------------------------------- slack 4.497 Slack (MET) : 4.502ns (required time - arrival time) Source: SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[68]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 3.508ns (logic 0.139ns (3.962%) route 3.369ns (96.038%)) Logic Levels: 0 Clock Path Skew: -0.179ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.212ns = ( 10.529 - 8.317 ) Source Clock Delay (SCD): 2.599ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.124ns (routing 0.620ns, distribution 1.504ns) Clock Net Delay (Destination): 1.814ns (routing 0.564ns, distribution 1.250ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.124 2.599 SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y545 FDPE r SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y545 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 2.738 f SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 3.369 6.107 SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] SLICE_X106Y551 FDCE f SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[68]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.814 10.529 SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y551 FDCE r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[68]/C clock pessimism 0.208 10.738 clock uncertainty -0.035 10.702 SLICE_X106Y551 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 10.609 SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[68] ------------------------------------------------------------------- required time 10.609 arrival time -6.107 ------------------------------------------------------------------- slack 4.502 Slack (MET) : 4.502ns (required time - arrival time) Source: SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[70]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 3.508ns (logic 0.139ns (3.962%) route 3.369ns (96.038%)) Logic Levels: 0 Clock Path Skew: -0.179ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.212ns = ( 10.529 - 8.317 ) Source Clock Delay (SCD): 2.599ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.124ns (routing 0.620ns, distribution 1.504ns) Clock Net Delay (Destination): 1.814ns (routing 0.564ns, distribution 1.250ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.124 2.599 SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y545 FDPE r SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y545 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 2.738 f SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 3.369 6.107 SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] SLICE_X106Y551 FDCE f SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[70]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.814 10.529 SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y551 FDCE r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[70]/C clock pessimism 0.208 10.738 clock uncertainty -0.035 10.702 SLICE_X106Y551 FDCE (Recov_HFF2_SLICEM_C_CLR) -0.093 10.609 SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[70] ------------------------------------------------------------------- required time 10.609 arrival time -6.107 ------------------------------------------------------------------- slack 4.502 Slack (MET) : 4.607ns (required time - arrival time) Source: SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[76]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 3.414ns (logic 0.139ns (4.071%) route 3.275ns (95.929%)) Logic Levels: 0 Clock Path Skew: -0.168ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.223ns = ( 10.540 - 8.317 ) Source Clock Delay (SCD): 2.599ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.124ns (routing 0.620ns, distribution 1.504ns) Clock Net Delay (Destination): 1.825ns (routing 0.564ns, distribution 1.261ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.124 2.599 SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y545 FDPE r SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y545 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 2.738 f SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 3.275 6.013 SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] SLICE_X105Y551 FDCE f SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[76]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.825 10.540 SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y551 FDCE r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[76]/C clock pessimism 0.208 10.748 clock uncertainty -0.035 10.713 SLICE_X105Y551 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.620 SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[76] ------------------------------------------------------------------- required time 10.620 arrival time -6.013 ------------------------------------------------------------------- slack 4.607 Slack (MET) : 4.607ns (required time - arrival time) Source: SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[78]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 3.414ns (logic 0.139ns (4.071%) route 3.275ns (95.929%)) Logic Levels: 0 Clock Path Skew: -0.168ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.223ns = ( 10.540 - 8.317 ) Source Clock Delay (SCD): 2.599ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.124ns (routing 0.620ns, distribution 1.504ns) Clock Net Delay (Destination): 1.825ns (routing 0.564ns, distribution 1.261ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.124 2.599 SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y545 FDPE r SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y545 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 2.738 f SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 3.275 6.013 SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] SLICE_X105Y551 FDCE f SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[78]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.825 10.540 SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y551 FDCE r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[78]/C clock pessimism 0.208 10.748 clock uncertainty -0.035 10.713 SLICE_X105Y551 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 10.620 SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[78] ------------------------------------------------------------------- required time 10.620 arrival time -6.013 ------------------------------------------------------------------- slack 4.607 Slack (MET) : 4.928ns (required time - arrival time) Source: SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[44]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 3.111ns (logic 0.139ns (4.468%) route 2.972ns (95.532%)) Logic Levels: 0 Clock Path Skew: -0.150ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.241ns = ( 10.558 - 8.317 ) Source Clock Delay (SCD): 2.599ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.124ns (routing 0.620ns, distribution 1.504ns) Clock Net Delay (Destination): 1.843ns (routing 0.564ns, distribution 1.279ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.124 2.599 SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y545 FDPE r SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y545 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 2.738 f SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.972 5.710 SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] SLICE_X102Y553 FDCE f SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[44]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.843 10.558 SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X102Y553 FDCE r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[44]/C clock pessimism 0.208 10.766 clock uncertainty -0.035 10.731 SLICE_X102Y553 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.638 SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[44] ------------------------------------------------------------------- required time 10.638 arrival time -5.710 ------------------------------------------------------------------- slack 4.928 Slack (MET) : 4.928ns (required time - arrival time) Source: SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[46]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 3.111ns (logic 0.139ns (4.468%) route 2.972ns (95.532%)) Logic Levels: 0 Clock Path Skew: -0.150ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.241ns = ( 10.558 - 8.317 ) Source Clock Delay (SCD): 2.599ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.124ns (routing 0.620ns, distribution 1.504ns) Clock Net Delay (Destination): 1.843ns (routing 0.564ns, distribution 1.279ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.124 2.599 SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y545 FDPE r SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y545 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 2.738 f SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.972 5.710 SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] SLICE_X102Y553 FDCE f SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[46]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.843 10.558 SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X102Y553 FDCE r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[46]/C clock pessimism 0.208 10.766 clock uncertainty -0.035 10.731 SLICE_X102Y553 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 10.638 SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[46] ------------------------------------------------------------------- required time 10.638 arrival time -5.710 ------------------------------------------------------------------- slack 4.928 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.227ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.263ns (logic 0.049ns (18.631%) route 0.214ns (81.369%)) Logic Levels: 0 Clock Path Skew: 0.031ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.101ns Source Clock Delay (SCD): 0.899ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.781ns (routing 0.270ns, distribution 0.511ns) Clock Net Delay (Destination): 0.936ns (routing 0.308ns, distribution 0.628ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.781 0.899 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK SLICE_X108Y542 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y542 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 0.948 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.214 1.162 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X107Y542 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.936 1.101 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y542 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.171 0.930 SLICE_X107Y542 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 0.935 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -0.935 arrival time 1.162 ------------------------------------------------------------------- slack 0.227 Slack (MET) : 0.243ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.317ns (logic 0.049ns (15.457%) route 0.268ns (84.543%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.094ns Source Clock Delay (SCD): 0.897ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.779ns (routing 0.270ns, distribution 0.509ns) Clock Net Delay (Destination): 0.929ns (routing 0.308ns, distribution 0.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.779 0.897 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y557 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y557 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.946 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.268 1.214 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X106Y554 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.929 1.094 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X106Y554 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C clock pessimism -0.128 0.966 SLICE_X106Y554 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 0.971 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12] ------------------------------------------------------------------- required time -0.971 arrival time 1.214 ------------------------------------------------------------------- slack 0.243 Slack (MET) : 0.243ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.317ns (logic 0.049ns (15.457%) route 0.268ns (84.543%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.094ns Source Clock Delay (SCD): 0.897ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.779ns (routing 0.270ns, distribution 0.509ns) Clock Net Delay (Destination): 0.929ns (routing 0.308ns, distribution 0.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.779 0.897 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y557 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y557 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.946 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.268 1.214 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X106Y554 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.929 1.094 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X106Y554 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C clock pessimism -0.128 0.966 SLICE_X106Y554 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 0.971 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14] ------------------------------------------------------------------- required time -0.971 arrival time 1.214 ------------------------------------------------------------------- slack 0.243 Slack (MET) : 0.278ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.355ns (logic 0.049ns (13.803%) route 0.306ns (86.197%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.097ns Source Clock Delay (SCD): 0.897ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.779ns (routing 0.270ns, distribution 0.509ns) Clock Net Delay (Destination): 0.932ns (routing 0.308ns, distribution 0.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.779 0.897 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y557 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y557 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.946 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.306 1.252 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X105Y554 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.932 1.097 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X105Y554 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C clock pessimism -0.128 0.969 SLICE_X105Y554 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 0.974 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time -0.974 arrival time 1.252 ------------------------------------------------------------------- slack 0.278 Slack (MET) : 0.278ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.355ns (logic 0.049ns (13.803%) route 0.306ns (86.197%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.097ns Source Clock Delay (SCD): 0.897ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.779ns (routing 0.270ns, distribution 0.509ns) Clock Net Delay (Destination): 0.932ns (routing 0.308ns, distribution 0.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.779 0.897 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y557 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y557 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.946 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.306 1.252 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X105Y554 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.932 1.097 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X105Y554 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C clock pessimism -0.128 0.969 SLICE_X105Y554 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 0.974 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13] ------------------------------------------------------------------- required time -0.974 arrival time 1.252 ------------------------------------------------------------------- slack 0.278 Slack (MET) : 0.278ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.355ns (logic 0.049ns (13.803%) route 0.306ns (86.197%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.097ns Source Clock Delay (SCD): 0.897ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.779ns (routing 0.270ns, distribution 0.509ns) Clock Net Delay (Destination): 0.932ns (routing 0.308ns, distribution 0.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.779 0.897 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y557 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y557 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.946 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.306 1.252 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X105Y554 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.932 1.097 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X105Y554 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C clock pessimism -0.128 0.969 SLICE_X105Y554 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 0.974 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15] ------------------------------------------------------------------- required time -0.974 arrival time 1.252 ------------------------------------------------------------------- slack 0.278 Slack (MET) : 0.278ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.355ns (logic 0.049ns (13.803%) route 0.306ns (86.197%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.097ns Source Clock Delay (SCD): 0.897ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.779ns (routing 0.270ns, distribution 0.509ns) Clock Net Delay (Destination): 0.932ns (routing 0.308ns, distribution 0.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.779 0.897 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y557 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y557 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.946 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.306 1.252 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X105Y554 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.932 1.097 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X105Y554 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C clock pessimism -0.128 0.969 SLICE_X105Y554 FDCE (Remov_FFF2_SLICEL_C_CLR) 0.005 0.974 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time -0.974 arrival time 1.252 ------------------------------------------------------------------- slack 0.278 Slack (MET) : 0.278ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.355ns (logic 0.049ns (13.803%) route 0.306ns (86.197%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.097ns Source Clock Delay (SCD): 0.897ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.779ns (routing 0.270ns, distribution 0.509ns) Clock Net Delay (Destination): 0.932ns (routing 0.308ns, distribution 0.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.779 0.897 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y557 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y557 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.946 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.306 1.252 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X105Y554 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.932 1.097 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X105Y554 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C clock pessimism -0.128 0.969 SLICE_X105Y554 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 0.974 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time -0.974 arrival time 1.252 ------------------------------------------------------------------- slack 0.278 Slack (MET) : 0.280ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.364ns (logic 0.049ns (13.462%) route 0.315ns (86.538%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.104ns Source Clock Delay (SCD): 0.897ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.779ns (routing 0.270ns, distribution 0.509ns) Clock Net Delay (Destination): 0.939ns (routing 0.308ns, distribution 0.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.779 0.897 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y557 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y557 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.946 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.315 1.261 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X101Y560 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.939 1.104 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X101Y560 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C clock pessimism -0.128 0.976 SLICE_X101Y560 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 0.981 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4] ------------------------------------------------------------------- required time -0.981 arrival time 1.261 ------------------------------------------------------------------- slack 0.280 Slack (MET) : 0.280ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.364ns (logic 0.049ns (13.462%) route 0.315ns (86.538%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.104ns Source Clock Delay (SCD): 0.897ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.779ns (routing 0.270ns, distribution 0.509ns) Clock Net Delay (Destination): 0.939ns (routing 0.308ns, distribution 0.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.779 0.897 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y557 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y557 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.946 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.315 1.261 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X101Y560 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.939 1.104 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X101Y560 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C clock pessimism -0.128 0.976 SLICE_X101Y560 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 0.981 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6] ------------------------------------------------------------------- required time -0.981 arrival time 1.261 ------------------------------------------------------------------- slack 0.280 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_15 To Clock: gtwiz_userclk_rx_srcclk_out[0]_15 Setup : 0 Failing Endpoints, Worst Slack 4.233ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.140ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.233ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 4.009ns (logic 0.305ns (7.608%) route 3.704ns (92.392%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.654ns = ( 10.971 - 8.317 ) Source Clock Delay (SCD): 2.821ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.346ns (routing 0.665ns, distribution 1.681ns) Clock Net Delay (Destination): 2.256ns (routing 0.604ns, distribution 1.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.346 2.821 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y440 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y440 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.960 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.827 5.787 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X88Y432 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.166 5.953 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/O net (fo=15, routed) 0.877 6.830 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X81Y434 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.256 10.971 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X81Y434 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/C clock pessimism 0.220 11.191 clock uncertainty -0.035 11.156 SLICE_X81Y434 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.063 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5] ------------------------------------------------------------------- required time 11.063 arrival time -6.830 ------------------------------------------------------------------- slack 4.233 Slack (MET) : 4.233ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 4.009ns (logic 0.305ns (7.608%) route 3.704ns (92.392%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.654ns = ( 10.971 - 8.317 ) Source Clock Delay (SCD): 2.821ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.346ns (routing 0.665ns, distribution 1.681ns) Clock Net Delay (Destination): 2.256ns (routing 0.604ns, distribution 1.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.346 2.821 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y440 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y440 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.960 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.827 5.787 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X88Y432 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.166 5.953 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/O net (fo=15, routed) 0.877 6.830 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X81Y434 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.256 10.971 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X81Y434 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/C clock pessimism 0.220 11.191 clock uncertainty -0.035 11.156 SLICE_X81Y434 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.063 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6] ------------------------------------------------------------------- required time 11.063 arrival time -6.830 ------------------------------------------------------------------- slack 4.233 Slack (MET) : 4.233ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 4.009ns (logic 0.305ns (7.608%) route 3.704ns (92.392%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.654ns = ( 10.971 - 8.317 ) Source Clock Delay (SCD): 2.821ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.346ns (routing 0.665ns, distribution 1.681ns) Clock Net Delay (Destination): 2.256ns (routing 0.604ns, distribution 1.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.346 2.821 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y440 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y440 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.960 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.827 5.787 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X88Y432 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.166 5.953 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/O net (fo=15, routed) 0.877 6.830 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X81Y434 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.256 10.971 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X81Y434 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/C clock pessimism 0.220 11.191 clock uncertainty -0.035 11.156 SLICE_X81Y434 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 11.063 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7] ------------------------------------------------------------------- required time 11.063 arrival time -6.830 ------------------------------------------------------------------- slack 4.233 Slack (MET) : 4.241ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 3.999ns (logic 0.305ns (7.627%) route 3.694ns (92.373%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.051ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.652ns = ( 10.969 - 8.317 ) Source Clock Delay (SCD): 2.821ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.346ns (routing 0.665ns, distribution 1.681ns) Clock Net Delay (Destination): 2.254ns (routing 0.604ns, distribution 1.650ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.346 2.821 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y440 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y440 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.960 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.827 5.787 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X88Y432 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.166 5.953 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/O net (fo=15, routed) 0.867 6.820 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X81Y434 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.254 10.969 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X81Y434 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/C clock pessimism 0.220 11.189 clock uncertainty -0.035 11.154 SLICE_X81Y434 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 11.061 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3] ------------------------------------------------------------------- required time 11.061 arrival time -6.820 ------------------------------------------------------------------- slack 4.241 Slack (MET) : 4.307ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 3.934ns (logic 0.305ns (7.753%) route 3.629ns (92.247%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.653ns = ( 10.970 - 8.317 ) Source Clock Delay (SCD): 2.821ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.346ns (routing 0.665ns, distribution 1.681ns) Clock Net Delay (Destination): 2.255ns (routing 0.604ns, distribution 1.651ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.346 2.821 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y440 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y440 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.960 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.827 5.787 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X88Y432 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.166 5.953 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/O net (fo=15, routed) 0.802 6.755 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X81Y435 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.255 10.970 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X81Y435 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/C clock pessimism 0.220 11.190 clock uncertainty -0.035 11.155 SLICE_X81Y435 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.062 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1] ------------------------------------------------------------------- required time 11.062 arrival time -6.755 ------------------------------------------------------------------- slack 4.307 Slack (MET) : 4.315ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 3.924ns (logic 0.305ns (7.773%) route 3.619ns (92.227%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.050ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.651ns = ( 10.968 - 8.317 ) Source Clock Delay (SCD): 2.821ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.346ns (routing 0.665ns, distribution 1.681ns) Clock Net Delay (Destination): 2.253ns (routing 0.604ns, distribution 1.649ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.346 2.821 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y440 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y440 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.960 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.827 5.787 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X88Y432 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.166 5.953 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/O net (fo=15, routed) 0.792 6.745 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X81Y435 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.253 10.968 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X81Y435 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/C clock pessimism 0.220 11.188 clock uncertainty -0.035 11.153 SLICE_X81Y435 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 11.060 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1] ------------------------------------------------------------------- required time 11.060 arrival time -6.745 ------------------------------------------------------------------- slack 4.315 Slack (MET) : 4.315ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 3.924ns (logic 0.305ns (7.773%) route 3.619ns (92.227%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.050ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.651ns = ( 10.968 - 8.317 ) Source Clock Delay (SCD): 2.821ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.346ns (routing 0.665ns, distribution 1.681ns) Clock Net Delay (Destination): 2.253ns (routing 0.604ns, distribution 1.649ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.346 2.821 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y440 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y440 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.960 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.827 5.787 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X88Y432 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.166 5.953 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/O net (fo=15, routed) 0.792 6.745 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X81Y435 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.253 10.968 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X81Y435 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/C clock pessimism 0.220 11.188 clock uncertainty -0.035 11.153 SLICE_X81Y435 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 11.060 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2] ------------------------------------------------------------------- required time 11.060 arrival time -6.745 ------------------------------------------------------------------- slack 4.315 Slack (MET) : 4.315ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 3.924ns (logic 0.305ns (7.773%) route 3.619ns (92.227%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.050ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.651ns = ( 10.968 - 8.317 ) Source Clock Delay (SCD): 2.821ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.346ns (routing 0.665ns, distribution 1.681ns) Clock Net Delay (Destination): 2.253ns (routing 0.604ns, distribution 1.649ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.346 2.821 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y440 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y440 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.960 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.827 5.787 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X88Y432 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.166 5.953 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/O net (fo=15, routed) 0.792 6.745 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X81Y435 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.253 10.968 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X81Y435 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/C clock pessimism 0.220 11.188 clock uncertainty -0.035 11.153 SLICE_X81Y435 FDCE (Recov_FFF_SLICEL_C_CLR) -0.093 11.060 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4] ------------------------------------------------------------------- required time 11.060 arrival time -6.745 ------------------------------------------------------------------- slack 4.315 Slack (MET) : 4.315ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 3.924ns (logic 0.305ns (7.773%) route 3.619ns (92.227%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.050ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.651ns = ( 10.968 - 8.317 ) Source Clock Delay (SCD): 2.821ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.346ns (routing 0.665ns, distribution 1.681ns) Clock Net Delay (Destination): 2.253ns (routing 0.604ns, distribution 1.649ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.346 2.821 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y440 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y440 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.960 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.827 5.787 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X88Y432 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.166 5.953 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/O net (fo=15, routed) 0.792 6.745 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X81Y435 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.253 10.968 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X81Y435 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/C clock pessimism 0.220 11.188 clock uncertainty -0.035 11.153 SLICE_X81Y435 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 11.060 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] ------------------------------------------------------------------- required time 11.060 arrival time -6.745 ------------------------------------------------------------------- slack 4.315 Slack (MET) : 4.399ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 3.833ns (logic 0.305ns (7.957%) route 3.528ns (92.043%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.644ns = ( 10.961 - 8.317 ) Source Clock Delay (SCD): 2.821ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.346ns (routing 0.665ns, distribution 1.681ns) Clock Net Delay (Destination): 2.246ns (routing 0.604ns, distribution 1.642ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.346 2.821 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y440 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y440 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.960 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.827 5.787 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X88Y432 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.166 5.953 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/O net (fo=15, routed) 0.701 6.654 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X81Y436 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.246 10.961 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X81Y436 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/C clock pessimism 0.220 11.181 clock uncertainty -0.035 11.146 SLICE_X81Y436 FDCE (Recov_BFF2_SLICEL_C_CLR) -0.093 11.053 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0] ------------------------------------------------------------------- required time 11.053 arrival time -6.654 ------------------------------------------------------------------- slack 4.399 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.140ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.227ns (logic 0.048ns (21.145%) route 0.179ns (78.855%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.353ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.999ns (routing 0.300ns, distribution 0.699ns) Clock Net Delay (Destination): 1.188ns (routing 0.344ns, distribution 0.844ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.117 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X77Y442 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.179 1.344 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X79Y442 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.188 1.353 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X79Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism -0.154 1.199 SLICE_X79Y442 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.204 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time -1.204 arrival time 1.344 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.140ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.227ns (logic 0.048ns (21.145%) route 0.179ns (78.855%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.353ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.999ns (routing 0.300ns, distribution 0.699ns) Clock Net Delay (Destination): 1.188ns (routing 0.344ns, distribution 0.844ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.117 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X77Y442 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.179 1.344 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X79Y442 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.188 1.353 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X79Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C clock pessimism -0.154 1.199 SLICE_X79Y442 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.204 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11] ------------------------------------------------------------------- required time -1.204 arrival time 1.344 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.140ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.227ns (logic 0.048ns (21.145%) route 0.179ns (78.855%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.353ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.999ns (routing 0.300ns, distribution 0.699ns) Clock Net Delay (Destination): 1.188ns (routing 0.344ns, distribution 0.844ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.117 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X77Y442 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.179 1.344 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X79Y442 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.188 1.353 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X79Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C clock pessimism -0.154 1.199 SLICE_X79Y442 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.204 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15] ------------------------------------------------------------------- required time -1.204 arrival time 1.344 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.140ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.227ns (logic 0.048ns (21.145%) route 0.179ns (78.855%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.353ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.999ns (routing 0.300ns, distribution 0.699ns) Clock Net Delay (Destination): 1.188ns (routing 0.344ns, distribution 0.844ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.117 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X77Y442 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.179 1.344 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X79Y442 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.188 1.353 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X79Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.154 1.199 SLICE_X79Y442 FDCE (Remov_FFF2_SLICEM_C_CLR) 0.005 1.204 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -1.204 arrival time 1.344 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.140ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.227ns (logic 0.048ns (21.145%) route 0.179ns (78.855%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.353ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.999ns (routing 0.300ns, distribution 0.699ns) Clock Net Delay (Destination): 1.188ns (routing 0.344ns, distribution 0.844ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.117 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X77Y442 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.179 1.344 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X79Y442 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.188 1.353 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X79Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C clock pessimism -0.154 1.199 SLICE_X79Y442 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.204 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3] ------------------------------------------------------------------- required time -1.204 arrival time 1.344 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.230ns (logic 0.048ns (20.870%) route 0.182ns (79.130%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.355ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.999ns (routing 0.300ns, distribution 0.699ns) Clock Net Delay (Destination): 1.190ns (routing 0.344ns, distribution 0.846ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.117 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X77Y442 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.182 1.347 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X79Y442 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.190 1.355 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X79Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C clock pessimism -0.154 1.201 SLICE_X79Y442 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.206 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13] ------------------------------------------------------------------- required time -1.206 arrival time 1.347 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.230ns (logic 0.048ns (20.870%) route 0.182ns (79.130%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.355ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.999ns (routing 0.300ns, distribution 0.699ns) Clock Net Delay (Destination): 1.190ns (routing 0.344ns, distribution 0.846ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.117 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X77Y442 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.182 1.347 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X79Y442 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.190 1.355 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X79Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C clock pessimism -0.154 1.201 SLICE_X79Y442 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 1.206 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13] ------------------------------------------------------------------- required time -1.206 arrival time 1.347 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.230ns (logic 0.048ns (20.870%) route 0.182ns (79.130%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.355ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.999ns (routing 0.300ns, distribution 0.699ns) Clock Net Delay (Destination): 1.190ns (routing 0.344ns, distribution 0.846ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.117 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X77Y442 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.182 1.347 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X79Y442 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.190 1.355 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X79Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism -0.154 1.201 SLICE_X79Y442 FDCE (Remov_BFF_SLICEM_C_CLR) 0.005 1.206 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time -1.206 arrival time 1.347 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.230ns (logic 0.048ns (20.870%) route 0.182ns (79.130%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.355ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.999ns (routing 0.300ns, distribution 0.699ns) Clock Net Delay (Destination): 1.190ns (routing 0.344ns, distribution 0.846ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.117 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X77Y442 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.182 1.347 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X79Y442 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.190 1.355 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X79Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism -0.154 1.201 SLICE_X79Y442 FDCE (Remov_BFF2_SLICEM_C_CLR) 0.005 1.206 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time -1.206 arrival time 1.347 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.230ns (logic 0.048ns (20.870%) route 0.182ns (79.130%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.355ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.999ns (routing 0.300ns, distribution 0.699ns) Clock Net Delay (Destination): 1.190ns (routing 0.344ns, distribution 0.846ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.117 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X77Y442 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.182 1.347 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X79Y442 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.190 1.355 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X79Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C clock pessimism -0.154 1.201 SLICE_X79Y442 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 1.206 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[5] ------------------------------------------------------------------- required time -1.206 arrival time 1.347 ------------------------------------------------------------------- slack 0.141 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_16 To Clock: gtwiz_userclk_rx_srcclk_out[0]_16 Setup : 0 Failing Endpoints, Worst Slack 4.940ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.177ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.940ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0]/PRE (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 3.308ns (logic 0.139ns (4.202%) route 3.169ns (95.798%)) Logic Levels: 0 Clock Path Skew: 0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.644ns = ( 10.961 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.683ns, distribution 1.650ns) Clock Net Delay (Destination): 2.246ns (routing 0.619ns, distribution 1.627ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y443 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y443 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.169 6.116 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/AS[0] SLICE_X90Y441 FDPE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0]/PRE (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.246 10.961 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y441 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0]/C clock pessimism 0.223 11.184 clock uncertainty -0.035 11.149 SLICE_X90Y441 FDPE (Recov_AFF_SLICEM_C_PRE) -0.093 11.056 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0] ------------------------------------------------------------------- required time 11.056 arrival time -6.116 ------------------------------------------------------------------- slack 4.940 Slack (MET) : 4.940ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 3.308ns (logic 0.139ns (4.202%) route 3.169ns (95.798%)) Logic Levels: 0 Clock Path Skew: 0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.644ns = ( 10.961 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.683ns, distribution 1.650ns) Clock Net Delay (Destination): 2.246ns (routing 0.619ns, distribution 1.627ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y443 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y443 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.169 6.116 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/AS[0] SLICE_X90Y441 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.246 10.961 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y441 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[1]/C clock pessimism 0.223 11.184 clock uncertainty -0.035 11.149 SLICE_X90Y441 FDCE (Recov_AFF2_SLICEM_C_CLR) -0.093 11.056 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[1] ------------------------------------------------------------------- required time 11.056 arrival time -6.116 ------------------------------------------------------------------- slack 4.940 Slack (MET) : 4.940ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 3.308ns (logic 0.139ns (4.202%) route 3.169ns (95.798%)) Logic Levels: 0 Clock Path Skew: 0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.644ns = ( 10.961 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.683ns, distribution 1.650ns) Clock Net Delay (Destination): 2.246ns (routing 0.619ns, distribution 1.627ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y443 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y443 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.169 6.116 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/AS[0] SLICE_X90Y441 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.246 10.961 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y441 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[2]/C clock pessimism 0.223 11.184 clock uncertainty -0.035 11.149 SLICE_X90Y441 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 11.056 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[2] ------------------------------------------------------------------- required time 11.056 arrival time -6.116 ------------------------------------------------------------------- slack 4.940 Slack (MET) : 5.064ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 3.201ns (logic 0.139ns (4.342%) route 3.062ns (95.658%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.661ns = ( 10.978 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.683ns, distribution 1.650ns) Clock Net Delay (Destination): 2.263ns (routing 0.619ns, distribution 1.644ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y443 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y443 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.062 6.009 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/AS[0] SLICE_X91Y439 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.263 10.978 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y439 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_reg/C clock pessimism 0.223 11.201 clock uncertainty -0.035 11.166 SLICE_X91Y439 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 11.073 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_reg ------------------------------------------------------------------- required time 11.073 arrival time -6.009 ------------------------------------------------------------------- slack 5.064 Slack (MET) : 5.161ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 3.071ns (logic 0.285ns (9.280%) route 2.786ns (90.720%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.628ns = ( 10.945 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.683ns, distribution 1.650ns) Clock Net Delay (Destination): 2.230ns (routing 0.619ns, distribution 1.611ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y443 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y443 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.285 5.232 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y431 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.146 5.378 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/O net (fo=15, routed) 0.501 5.879 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X94Y434 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.230 10.945 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] SLICE_X94Y434 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/C clock pessimism 0.223 11.168 clock uncertainty -0.035 11.133 SLICE_X94Y434 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 11.040 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1] ------------------------------------------------------------------- required time 11.040 arrival time -5.879 ------------------------------------------------------------------- slack 5.161 Slack (MET) : 5.161ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 3.071ns (logic 0.285ns (9.280%) route 2.786ns (90.720%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.628ns = ( 10.945 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.683ns, distribution 1.650ns) Clock Net Delay (Destination): 2.230ns (routing 0.619ns, distribution 1.611ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y443 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y443 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.285 5.232 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y431 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.146 5.378 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/O net (fo=15, routed) 0.501 5.879 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X94Y434 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.230 10.945 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] SLICE_X94Y434 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/C clock pessimism 0.223 11.168 clock uncertainty -0.035 11.133 SLICE_X94Y434 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 11.040 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2] ------------------------------------------------------------------- required time 11.040 arrival time -5.879 ------------------------------------------------------------------- slack 5.161 Slack (MET) : 5.161ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 3.071ns (logic 0.285ns (9.280%) route 2.786ns (90.720%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.628ns = ( 10.945 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.683ns, distribution 1.650ns) Clock Net Delay (Destination): 2.230ns (routing 0.619ns, distribution 1.611ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y443 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y443 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.285 5.232 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y431 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.146 5.378 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/O net (fo=15, routed) 0.501 5.879 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X94Y434 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.230 10.945 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] SLICE_X94Y434 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C clock pessimism 0.223 11.168 clock uncertainty -0.035 11.133 SLICE_X94Y434 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.040 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3] ------------------------------------------------------------------- required time 11.040 arrival time -5.879 ------------------------------------------------------------------- slack 5.161 Slack (MET) : 5.161ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 3.071ns (logic 0.285ns (9.280%) route 2.786ns (90.720%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.628ns = ( 10.945 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.683ns, distribution 1.650ns) Clock Net Delay (Destination): 2.230ns (routing 0.619ns, distribution 1.611ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y443 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y443 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.285 5.232 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y431 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.146 5.378 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/O net (fo=15, routed) 0.501 5.879 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X94Y434 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.230 10.945 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] SLICE_X94Y434 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/C clock pessimism 0.223 11.168 clock uncertainty -0.035 11.133 SLICE_X94Y434 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 11.040 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4] ------------------------------------------------------------------- required time 11.040 arrival time -5.879 ------------------------------------------------------------------- slack 5.161 Slack (MET) : 5.184ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 3.066ns (logic 0.383ns (12.492%) route 2.683ns (87.508%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.646ns = ( 10.963 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.683ns, distribution 1.650ns) Clock Net Delay (Destination): 2.248ns (routing 0.619ns, distribution 1.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y443 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y443 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.084 5.031 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X92Y431 LUT2 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.275 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__13/O net (fo=2, routed) 0.599 5.874 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X92Y431 FDCE f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.248 10.963 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X92Y431 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.223 11.186 clock uncertainty -0.035 11.151 SLICE_X92Y431 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 11.058 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 11.058 arrival time -5.874 ------------------------------------------------------------------- slack 5.184 Slack (MET) : 5.184ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 3.066ns (logic 0.383ns (12.492%) route 2.683ns (87.508%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.646ns = ( 10.963 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.683ns, distribution 1.650ns) Clock Net Delay (Destination): 2.248ns (routing 0.619ns, distribution 1.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y443 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y443 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.084 5.031 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X92Y431 LUT2 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.275 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__13/O net (fo=2, routed) 0.599 5.874 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X92Y431 FDCE f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.248 10.963 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X92Y431 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.223 11.186 clock uncertainty -0.035 11.151 SLICE_X92Y431 FDCE (Recov_EFF2_SLICEM_C_CLR) -0.093 11.058 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 11.058 arrival time -5.874 ------------------------------------------------------------------- slack 5.184 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.177ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.232ns (logic 0.049ns (21.121%) route 0.183ns (78.879%)) Logic Levels: 0 Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.323ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 0.999ns (routing 0.306ns, distribution 0.693ns) Clock Net Delay (Destination): 1.158ns (routing 0.352ns, distribution 0.806ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.117 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X91Y432 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X91Y432 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.166 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.183 1.349 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X92Y434 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.158 1.323 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X92Y434 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.156 1.167 SLICE_X92Y434 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.172 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -1.172 arrival time 1.349 ------------------------------------------------------------------- slack 0.177 Slack (MET) : 0.183ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[66]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.049ns (18.846%) route 0.211ns (81.154%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.345ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 0.999ns (routing 0.306ns, distribution 0.693ns) Clock Net Delay (Destination): 1.180ns (routing 0.352ns, distribution 0.828ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.117 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X91Y432 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X91Y432 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.166 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.211 1.377 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X88Y436 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[66]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.180 1.345 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y436 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[66]/C clock pessimism -0.156 1.189 SLICE_X88Y436 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.194 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[66] ------------------------------------------------------------------- required time -1.194 arrival time 1.377 ------------------------------------------------------------------- slack 0.183 Slack (MET) : 0.183ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[73]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.049ns (18.846%) route 0.211ns (81.154%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.345ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 0.999ns (routing 0.306ns, distribution 0.693ns) Clock Net Delay (Destination): 1.180ns (routing 0.352ns, distribution 0.828ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.117 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X91Y432 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X91Y432 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.166 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.211 1.377 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X88Y436 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[73]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.180 1.345 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y436 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[73]/C clock pessimism -0.156 1.189 SLICE_X88Y436 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 1.194 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[73] ------------------------------------------------------------------- required time -1.194 arrival time 1.377 ------------------------------------------------------------------- slack 0.183 Slack (MET) : 0.183ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[74]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.049ns (18.846%) route 0.211ns (81.154%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.345ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 0.999ns (routing 0.306ns, distribution 0.693ns) Clock Net Delay (Destination): 1.180ns (routing 0.352ns, distribution 0.828ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.117 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X91Y432 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X91Y432 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.166 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.211 1.377 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X88Y436 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[74]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.180 1.345 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y436 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[74]/C clock pessimism -0.156 1.189 SLICE_X88Y436 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.194 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[74] ------------------------------------------------------------------- required time -1.194 arrival time 1.377 ------------------------------------------------------------------- slack 0.183 Slack (MET) : 0.183ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[66]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.049ns (18.846%) route 0.211ns (81.154%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.345ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 0.999ns (routing 0.306ns, distribution 0.693ns) Clock Net Delay (Destination): 1.180ns (routing 0.352ns, distribution 0.828ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.117 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X91Y432 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X91Y432 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.166 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.211 1.377 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X88Y436 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[66]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.180 1.345 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y436 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[66]/C clock pessimism -0.156 1.189 SLICE_X88Y436 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 1.194 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[66] ------------------------------------------------------------------- required time -1.194 arrival time 1.377 ------------------------------------------------------------------- slack 0.183 Slack (MET) : 0.183ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[73]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.049ns (18.846%) route 0.211ns (81.154%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.345ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 0.999ns (routing 0.306ns, distribution 0.693ns) Clock Net Delay (Destination): 1.180ns (routing 0.352ns, distribution 0.828ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.117 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X91Y432 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X91Y432 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.166 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.211 1.377 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X88Y436 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[73]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.180 1.345 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y436 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[73]/C clock pessimism -0.156 1.189 SLICE_X88Y436 FDCE (Remov_GFF2_SLICEL_C_CLR) 0.005 1.194 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[73] ------------------------------------------------------------------- required time -1.194 arrival time 1.377 ------------------------------------------------------------------- slack 0.183 Slack (MET) : 0.183ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[74]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.049ns (18.846%) route 0.211ns (81.154%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.345ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 0.999ns (routing 0.306ns, distribution 0.693ns) Clock Net Delay (Destination): 1.180ns (routing 0.352ns, distribution 0.828ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.117 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X91Y432 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X91Y432 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.166 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.211 1.377 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X88Y436 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[74]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.180 1.345 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y436 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[74]/C clock pessimism -0.156 1.189 SLICE_X88Y436 FDCE (Remov_FFF2_SLICEL_C_CLR) 0.005 1.194 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[74] ------------------------------------------------------------------- required time -1.194 arrival time 1.377 ------------------------------------------------------------------- slack 0.183 Slack (MET) : 0.186ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[64]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.266ns (logic 0.049ns (18.421%) route 0.217ns (81.579%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.348ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 0.999ns (routing 0.306ns, distribution 0.693ns) Clock Net Delay (Destination): 1.183ns (routing 0.352ns, distribution 0.831ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.117 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X91Y432 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X91Y432 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.166 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.217 1.383 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X88Y436 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[64]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.183 1.348 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y436 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[64]/C clock pessimism -0.156 1.192 SLICE_X88Y436 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 1.197 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[64] ------------------------------------------------------------------- required time -1.197 arrival time 1.383 ------------------------------------------------------------------- slack 0.186 Slack (MET) : 0.186ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[65]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.266ns (logic 0.049ns (18.421%) route 0.217ns (81.579%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.348ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 0.999ns (routing 0.306ns, distribution 0.693ns) Clock Net Delay (Destination): 1.183ns (routing 0.352ns, distribution 0.831ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.117 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X91Y432 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X91Y432 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.166 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.217 1.383 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X88Y436 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[65]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.183 1.348 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y436 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[65]/C clock pessimism -0.156 1.192 SLICE_X88Y436 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 1.197 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[65] ------------------------------------------------------------------- required time -1.197 arrival time 1.383 ------------------------------------------------------------------- slack 0.186 Slack (MET) : 0.186ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[75]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.266ns (logic 0.049ns (18.421%) route 0.217ns (81.579%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.348ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 0.999ns (routing 0.306ns, distribution 0.693ns) Clock Net Delay (Destination): 1.183ns (routing 0.352ns, distribution 0.831ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.117 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X91Y432 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X91Y432 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.166 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.217 1.383 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X88Y436 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[75]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.183 1.348 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y436 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[75]/C clock pessimism -0.156 1.192 SLICE_X88Y436 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 1.197 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[75] ------------------------------------------------------------------- required time -1.197 arrival time 1.383 ------------------------------------------------------------------- slack 0.186 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_17 To Clock: gtwiz_userclk_rx_srcclk_out[0]_17 Setup : 0 Failing Endpoints, Worst Slack 5.083ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.157ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.083ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 2.760ns (logic 0.285ns (10.326%) route 2.475ns (89.674%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.346ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.263ns = ( 10.580 - 8.317 ) Source Clock Delay (SCD): 2.824ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.349ns (routing 0.664ns, distribution 1.685ns) Clock Net Delay (Destination): 1.865ns (routing 0.602ns, distribution 1.263ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.349 2.824 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y462 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y462 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.963 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.901 4.864 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X107Y431 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 5.010 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/O net (fo=15, routed) 0.574 5.584 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X107Y434 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.865 10.580 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X107Y434 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/C clock pessimism 0.215 10.795 clock uncertainty -0.035 10.760 SLICE_X107Y434 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.667 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6] ------------------------------------------------------------------- required time 10.667 arrival time -5.584 ------------------------------------------------------------------- slack 5.083 Slack (MET) : 5.083ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 2.760ns (logic 0.285ns (10.326%) route 2.475ns (89.674%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.346ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.263ns = ( 10.580 - 8.317 ) Source Clock Delay (SCD): 2.824ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.349ns (routing 0.664ns, distribution 1.685ns) Clock Net Delay (Destination): 1.865ns (routing 0.602ns, distribution 1.263ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.349 2.824 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y462 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y462 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.963 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.901 4.864 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X107Y431 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 5.010 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/O net (fo=15, routed) 0.574 5.584 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X107Y434 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.865 10.580 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X107Y434 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/C clock pessimism 0.215 10.795 clock uncertainty -0.035 10.760 SLICE_X107Y434 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.667 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7] ------------------------------------------------------------------- required time 10.667 arrival time -5.584 ------------------------------------------------------------------- slack 5.083 Slack (MET) : 5.083ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 2.760ns (logic 0.285ns (10.326%) route 2.475ns (89.674%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.346ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.263ns = ( 10.580 - 8.317 ) Source Clock Delay (SCD): 2.824ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.349ns (routing 0.664ns, distribution 1.685ns) Clock Net Delay (Destination): 1.865ns (routing 0.602ns, distribution 1.263ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.349 2.824 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y462 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y462 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.963 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.901 4.864 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X107Y431 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 5.010 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/O net (fo=15, routed) 0.574 5.584 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X107Y434 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.865 10.580 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X107Y434 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/C clock pessimism 0.215 10.795 clock uncertainty -0.035 10.760 SLICE_X107Y434 FDCE (Recov_BFF2_SLICEM_C_CLR) -0.093 10.667 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0] ------------------------------------------------------------------- required time 10.667 arrival time -5.584 ------------------------------------------------------------------- slack 5.083 Slack (MET) : 5.133ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 2.734ns (logic 0.285ns (10.424%) route 2.449ns (89.576%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.322ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.288ns = ( 10.605 - 8.317 ) Source Clock Delay (SCD): 2.824ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.349ns (routing 0.664ns, distribution 1.685ns) Clock Net Delay (Destination): 1.890ns (routing 0.602ns, distribution 1.288ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.349 2.824 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y462 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y462 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.963 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.901 4.864 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X107Y431 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 5.010 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/O net (fo=15, routed) 0.548 5.558 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X108Y433 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.890 10.605 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X108Y433 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/C clock pessimism 0.214 10.820 clock uncertainty -0.035 10.784 SLICE_X108Y433 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.691 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4] ------------------------------------------------------------------- required time 10.691 arrival time -5.558 ------------------------------------------------------------------- slack 5.133 Slack (MET) : 5.133ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 2.734ns (logic 0.285ns (10.424%) route 2.449ns (89.576%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.322ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.288ns = ( 10.605 - 8.317 ) Source Clock Delay (SCD): 2.824ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.349ns (routing 0.664ns, distribution 1.685ns) Clock Net Delay (Destination): 1.890ns (routing 0.602ns, distribution 1.288ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.349 2.824 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y462 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y462 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.963 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.901 4.864 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X107Y431 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 5.010 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/O net (fo=15, routed) 0.548 5.558 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X108Y433 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.890 10.605 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X108Y433 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/C clock pessimism 0.214 10.820 clock uncertainty -0.035 10.784 SLICE_X108Y433 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.691 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5] ------------------------------------------------------------------- required time 10.691 arrival time -5.558 ------------------------------------------------------------------- slack 5.133 Slack (MET) : 5.133ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 2.733ns (logic 0.285ns (10.428%) route 2.448ns (89.572%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.323ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.287ns = ( 10.604 - 8.317 ) Source Clock Delay (SCD): 2.824ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.349ns (routing 0.664ns, distribution 1.685ns) Clock Net Delay (Destination): 1.889ns (routing 0.602ns, distribution 1.287ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.349 2.824 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y462 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y462 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.963 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.901 4.864 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X107Y431 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 5.010 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/O net (fo=15, routed) 0.547 5.557 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X107Y433 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.889 10.604 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X107Y433 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/C clock pessimism 0.214 10.819 clock uncertainty -0.035 10.783 SLICE_X107Y433 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.690 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1] ------------------------------------------------------------------- required time 10.690 arrival time -5.557 ------------------------------------------------------------------- slack 5.133 Slack (MET) : 5.133ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 2.733ns (logic 0.285ns (10.428%) route 2.448ns (89.572%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.323ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.287ns = ( 10.604 - 8.317 ) Source Clock Delay (SCD): 2.824ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.349ns (routing 0.664ns, distribution 1.685ns) Clock Net Delay (Destination): 1.889ns (routing 0.602ns, distribution 1.287ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.349 2.824 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y462 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y462 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.963 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.901 4.864 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X107Y431 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 5.010 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/O net (fo=15, routed) 0.547 5.557 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X107Y433 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.889 10.604 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X107Y433 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/C clock pessimism 0.214 10.819 clock uncertainty -0.035 10.783 SLICE_X107Y433 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 10.690 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2] ------------------------------------------------------------------- required time 10.690 arrival time -5.557 ------------------------------------------------------------------- slack 5.133 Slack (MET) : 5.133ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 2.733ns (logic 0.285ns (10.428%) route 2.448ns (89.572%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.323ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.287ns = ( 10.604 - 8.317 ) Source Clock Delay (SCD): 2.824ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.349ns (routing 0.664ns, distribution 1.685ns) Clock Net Delay (Destination): 1.889ns (routing 0.602ns, distribution 1.287ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.349 2.824 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y462 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y462 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.963 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.901 4.864 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X107Y431 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 5.010 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/O net (fo=15, routed) 0.547 5.557 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X107Y433 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.889 10.604 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X107Y433 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C clock pessimism 0.214 10.819 clock uncertainty -0.035 10.783 SLICE_X107Y433 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 10.690 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3] ------------------------------------------------------------------- required time 10.690 arrival time -5.557 ------------------------------------------------------------------- slack 5.133 Slack (MET) : 5.138ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 2.726ns (logic 0.285ns (10.455%) route 2.441ns (89.545%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.325ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.285ns = ( 10.602 - 8.317 ) Source Clock Delay (SCD): 2.824ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.349ns (routing 0.664ns, distribution 1.685ns) Clock Net Delay (Destination): 1.887ns (routing 0.602ns, distribution 1.285ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.349 2.824 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y462 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y462 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.963 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.901 4.864 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X107Y431 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 5.010 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/O net (fo=15, routed) 0.540 5.550 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X107Y433 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.887 10.602 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X107Y433 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/C clock pessimism 0.214 10.817 clock uncertainty -0.035 10.781 SLICE_X107Y433 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 10.688 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3] ------------------------------------------------------------------- required time 10.688 arrival time -5.550 ------------------------------------------------------------------- slack 5.138 Slack (MET) : 5.138ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 2.726ns (logic 0.285ns (10.455%) route 2.441ns (89.545%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.325ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.285ns = ( 10.602 - 8.317 ) Source Clock Delay (SCD): 2.824ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.349ns (routing 0.664ns, distribution 1.685ns) Clock Net Delay (Destination): 1.887ns (routing 0.602ns, distribution 1.285ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.349 2.824 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y462 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y462 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.963 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.901 4.864 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X107Y431 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 5.010 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/O net (fo=15, routed) 0.540 5.550 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X107Y433 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.887 10.602 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X107Y433 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]/C clock pessimism 0.214 10.817 clock uncertainty -0.035 10.781 SLICE_X107Y433 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 10.688 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5] ------------------------------------------------------------------- required time 10.688 arrival time -5.550 ------------------------------------------------------------------- slack 5.138 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.157ns (arrival time - required time) Source: SFP_GEN[15].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[15].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.244ns (logic 0.048ns (19.672%) route 0.196ns (80.328%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.142ns Source Clock Delay (SCD): 0.928ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.810ns (routing 0.301ns, distribution 0.509ns) Clock Net Delay (Destination): 0.977ns (routing 0.342ns, distribution 0.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.810 0.928 SFP_GEN[15].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y421 FDPE r SFP_GEN[15].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X105Y421 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 0.976 f SFP_GEN[15].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.196 1.172 SFP_GEN[15].ngCCM_gbt/sync_m_reg[3][0] SLICE_X104Y421 FDCE f SFP_GEN[15].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.977 1.142 SFP_GEN[15].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X104Y421 FDCE r SFP_GEN[15].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.132 1.010 SLICE_X104Y421 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.015 SFP_GEN[15].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.015 arrival time 1.172 ------------------------------------------------------------------- slack 0.157 Slack (MET) : 0.163ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.233ns (logic 0.048ns (20.601%) route 0.185ns (79.399%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.134ns Source Clock Delay (SCD): 0.937ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.819ns (routing 0.301ns, distribution 0.518ns) Clock Net Delay (Destination): 0.969ns (routing 0.342ns, distribution 0.627ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.819 0.937 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y429 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y429 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 0.985 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.185 1.170 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X109Y431 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.969 1.134 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/CLK SLICE_X109Y431 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_reg/C clock pessimism -0.132 1.002 SLICE_X109Y431 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.007 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_reg ------------------------------------------------------------------- required time -1.007 arrival time 1.170 ------------------------------------------------------------------- slack 0.163 Slack (MET) : 0.164ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.236ns (logic 0.048ns (20.339%) route 0.188ns (79.661%)) Logic Levels: 0 Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.136ns Source Clock Delay (SCD): 0.937ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.819ns (routing 0.301ns, distribution 0.518ns) Clock Net Delay (Destination): 0.971ns (routing 0.342ns, distribution 0.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.819 0.937 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y429 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y429 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 0.985 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.188 1.173 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X109Y431 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.971 1.136 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/CLK SLICE_X109Y431 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C clock pessimism -0.132 1.004 SLICE_X109Y431 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 1.009 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg ------------------------------------------------------------------- required time -1.009 arrival time 1.173 ------------------------------------------------------------------- slack 0.164 Slack (MET) : 0.196ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.048ns (18.113%) route 0.217ns (81.887%)) Logic Levels: 0 Clock Path Skew: 0.064ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.133ns Source Clock Delay (SCD): 0.937ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.819ns (routing 0.301ns, distribution 0.518ns) Clock Net Delay (Destination): 0.968ns (routing 0.342ns, distribution 0.626ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.819 0.937 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y429 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y429 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 0.985 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.217 1.202 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X106Y427 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.968 1.133 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X106Y427 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C clock pessimism -0.132 1.001 SLICE_X106Y427 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.006 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time -1.006 arrival time 1.202 ------------------------------------------------------------------- slack 0.196 Slack (MET) : 0.196ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.048ns (18.113%) route 0.217ns (81.887%)) Logic Levels: 0 Clock Path Skew: 0.064ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.133ns Source Clock Delay (SCD): 0.937ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.819ns (routing 0.301ns, distribution 0.518ns) Clock Net Delay (Destination): 0.968ns (routing 0.342ns, distribution 0.626ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.819 0.937 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y429 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y429 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 0.985 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.217 1.202 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X106Y427 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.968 1.133 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X106Y427 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C clock pessimism -0.132 1.001 SLICE_X106Y427 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 1.006 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time -1.006 arrival time 1.202 ------------------------------------------------------------------- slack 0.196 Slack (MET) : 0.196ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.048ns (18.113%) route 0.217ns (81.887%)) Logic Levels: 0 Clock Path Skew: 0.064ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.133ns Source Clock Delay (SCD): 0.937ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.819ns (routing 0.301ns, distribution 0.518ns) Clock Net Delay (Destination): 0.968ns (routing 0.342ns, distribution 0.626ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.819 0.937 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y429 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y429 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 0.985 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.217 1.202 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X106Y427 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.968 1.133 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X106Y427 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C clock pessimism -0.132 1.001 SLICE_X106Y427 FDCE (Remov_BFF_SLICEM_C_CLR) 0.005 1.006 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4] ------------------------------------------------------------------- required time -1.006 arrival time 1.202 ------------------------------------------------------------------- slack 0.196 Slack (MET) : 0.196ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.048ns (18.113%) route 0.217ns (81.887%)) Logic Levels: 0 Clock Path Skew: 0.064ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.133ns Source Clock Delay (SCD): 0.937ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.819ns (routing 0.301ns, distribution 0.518ns) Clock Net Delay (Destination): 0.968ns (routing 0.342ns, distribution 0.626ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.819 0.937 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y429 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y429 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 0.985 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.217 1.202 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X106Y427 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.968 1.133 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X106Y427 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C clock pessimism -0.132 1.001 SLICE_X106Y427 FDCE (Remov_BFF2_SLICEM_C_CLR) 0.005 1.006 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6] ------------------------------------------------------------------- required time -1.006 arrival time 1.202 ------------------------------------------------------------------- slack 0.196 Slack (MET) : 0.196ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.048ns (18.113%) route 0.217ns (81.887%)) Logic Levels: 0 Clock Path Skew: 0.064ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.133ns Source Clock Delay (SCD): 0.937ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.819ns (routing 0.301ns, distribution 0.518ns) Clock Net Delay (Destination): 0.968ns (routing 0.342ns, distribution 0.626ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.819 0.937 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y429 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y429 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 0.985 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.217 1.202 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X106Y427 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.968 1.133 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X106Y427 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism -0.132 1.001 SLICE_X106Y427 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.006 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time -1.006 arrival time 1.202 ------------------------------------------------------------------- slack 0.196 Slack (MET) : 0.200ns (arrival time - required time) Source: SFP_GEN[15].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[15].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.279ns (logic 0.048ns (17.204%) route 0.231ns (82.796%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.134ns Source Clock Delay (SCD): 0.928ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.810ns (routing 0.301ns, distribution 0.509ns) Clock Net Delay (Destination): 0.969ns (routing 0.342ns, distribution 0.627ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.810 0.928 SFP_GEN[15].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y421 FDPE r SFP_GEN[15].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X105Y421 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 0.976 f SFP_GEN[15].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.231 1.207 SFP_GEN[15].ngCCM_gbt/sync_m_reg[3][0] SLICE_X104Y422 FDCE f SFP_GEN[15].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.969 1.134 SFP_GEN[15].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X104Y422 FDCE r SFP_GEN[15].ngCCM_gbt/RX_Word_rx40_reg[30]/C clock pessimism -0.132 1.002 SLICE_X104Y422 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.007 SFP_GEN[15].ngCCM_gbt/RX_Word_rx40_reg[30] ------------------------------------------------------------------- required time -1.007 arrival time 1.207 ------------------------------------------------------------------- slack 0.200 Slack (MET) : 0.200ns (arrival time - required time) Source: SFP_GEN[15].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[15].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.279ns (logic 0.048ns (17.204%) route 0.231ns (82.796%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.134ns Source Clock Delay (SCD): 0.928ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.810ns (routing 0.301ns, distribution 0.509ns) Clock Net Delay (Destination): 0.969ns (routing 0.342ns, distribution 0.627ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.810 0.928 SFP_GEN[15].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y421 FDPE r SFP_GEN[15].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X105Y421 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 0.976 f SFP_GEN[15].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.231 1.207 SFP_GEN[15].ngCCM_gbt/sync_m_reg[3][0] SLICE_X104Y422 FDCE f SFP_GEN[15].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y184 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.969 1.134 SFP_GEN[15].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X104Y422 FDCE r SFP_GEN[15].ngCCM_gbt/RX_Word_rx40_reg[32]/C clock pessimism -0.132 1.002 SLICE_X104Y422 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.007 SFP_GEN[15].ngCCM_gbt/RX_Word_rx40_reg[32] ------------------------------------------------------------------- required time -1.007 arrival time 1.207 ------------------------------------------------------------------- slack 0.200 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_18 To Clock: gtwiz_userclk_rx_srcclk_out[0]_18 Setup : 0 Failing Endpoints, Worst Slack 4.426ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.137ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.426ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 3.886ns (logic 0.364ns (9.367%) route 3.522ns (90.633%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.123ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.639ns = ( 10.956 - 8.317 ) Source Clock Delay (SCD): 2.736ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.261ns (routing 0.633ns, distribution 1.628ns) Clock Net Delay (Destination): 2.241ns (routing 0.572ns, distribution 1.669ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.261 2.736 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y484 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.875 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.264 5.139 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y477 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.364 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/O net (fo=15, routed) 1.258 6.622 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X87Y483 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.241 10.956 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X87Y483 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/C clock pessimism 0.220 11.177 clock uncertainty -0.035 11.141 SLICE_X87Y483 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 11.048 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0] ------------------------------------------------------------------- required time 11.048 arrival time -6.622 ------------------------------------------------------------------- slack 4.426 Slack (MET) : 4.426ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 3.886ns (logic 0.364ns (9.367%) route 3.522ns (90.633%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.123ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.639ns = ( 10.956 - 8.317 ) Source Clock Delay (SCD): 2.736ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.261ns (routing 0.633ns, distribution 1.628ns) Clock Net Delay (Destination): 2.241ns (routing 0.572ns, distribution 1.669ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.261 2.736 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y484 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.875 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.264 5.139 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y477 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.364 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/O net (fo=15, routed) 1.258 6.622 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X87Y483 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.241 10.956 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X87Y483 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/C clock pessimism 0.220 11.177 clock uncertainty -0.035 11.141 SLICE_X87Y483 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.048 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1] ------------------------------------------------------------------- required time 11.048 arrival time -6.622 ------------------------------------------------------------------- slack 4.426 Slack (MET) : 4.426ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 3.886ns (logic 0.364ns (9.367%) route 3.522ns (90.633%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.123ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.639ns = ( 10.956 - 8.317 ) Source Clock Delay (SCD): 2.736ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.261ns (routing 0.633ns, distribution 1.628ns) Clock Net Delay (Destination): 2.241ns (routing 0.572ns, distribution 1.669ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.261 2.736 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y484 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.875 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.264 5.139 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y477 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.364 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/O net (fo=15, routed) 1.258 6.622 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X87Y483 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.241 10.956 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X87Y483 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/C clock pessimism 0.220 11.177 clock uncertainty -0.035 11.141 SLICE_X87Y483 FDCE (Recov_HFF2_SLICEM_C_CLR) -0.093 11.048 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2] ------------------------------------------------------------------- required time 11.048 arrival time -6.622 ------------------------------------------------------------------- slack 4.426 Slack (MET) : 4.426ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 3.886ns (logic 0.364ns (9.367%) route 3.522ns (90.633%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.123ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.639ns = ( 10.956 - 8.317 ) Source Clock Delay (SCD): 2.736ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.261ns (routing 0.633ns, distribution 1.628ns) Clock Net Delay (Destination): 2.241ns (routing 0.572ns, distribution 1.669ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.261 2.736 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y484 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.875 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.264 5.139 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y477 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.364 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/O net (fo=15, routed) 1.258 6.622 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X87Y483 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.241 10.956 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X87Y483 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/C clock pessimism 0.220 11.177 clock uncertainty -0.035 11.141 SLICE_X87Y483 FDCE (Recov_EFF2_SLICEM_C_CLR) -0.093 11.048 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3] ------------------------------------------------------------------- required time 11.048 arrival time -6.622 ------------------------------------------------------------------- slack 4.426 Slack (MET) : 4.426ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 3.886ns (logic 0.364ns (9.367%) route 3.522ns (90.633%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.123ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.639ns = ( 10.956 - 8.317 ) Source Clock Delay (SCD): 2.736ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.261ns (routing 0.633ns, distribution 1.628ns) Clock Net Delay (Destination): 2.241ns (routing 0.572ns, distribution 1.669ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.261 2.736 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y484 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.875 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.264 5.139 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y477 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.364 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/O net (fo=15, routed) 1.258 6.622 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X87Y483 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.241 10.956 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X87Y483 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/C clock pessimism 0.220 11.177 clock uncertainty -0.035 11.141 SLICE_X87Y483 FDCE (Recov_GFF_SLICEM_C_CLR) -0.093 11.048 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4] ------------------------------------------------------------------- required time 11.048 arrival time -6.622 ------------------------------------------------------------------- slack 4.426 Slack (MET) : 4.426ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 3.886ns (logic 0.364ns (9.367%) route 3.522ns (90.633%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.123ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.639ns = ( 10.956 - 8.317 ) Source Clock Delay (SCD): 2.736ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.261ns (routing 0.633ns, distribution 1.628ns) Clock Net Delay (Destination): 2.241ns (routing 0.572ns, distribution 1.669ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.261 2.736 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y484 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.875 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.264 5.139 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y477 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.364 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/O net (fo=15, routed) 1.258 6.622 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X87Y483 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.241 10.956 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X87Y483 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][5]/C clock pessimism 0.220 11.177 clock uncertainty -0.035 11.141 SLICE_X87Y483 FDCE (Recov_FFF_SLICEM_C_CLR) -0.093 11.048 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][5] ------------------------------------------------------------------- required time 11.048 arrival time -6.622 ------------------------------------------------------------------- slack 4.426 Slack (MET) : 4.546ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 3.769ns (logic 0.364ns (9.658%) route 3.405ns (90.342%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.126ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.642ns = ( 10.959 - 8.317 ) Source Clock Delay (SCD): 2.736ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.261ns (routing 0.633ns, distribution 1.628ns) Clock Net Delay (Destination): 2.244ns (routing 0.572ns, distribution 1.672ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.261 2.736 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y484 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.875 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.264 5.139 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y477 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.364 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/O net (fo=15, routed) 1.141 6.505 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X87Y480 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.244 10.959 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X87Y480 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/C clock pessimism 0.220 11.180 clock uncertainty -0.035 11.144 SLICE_X87Y480 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.051 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1] ------------------------------------------------------------------- required time 11.051 arrival time -6.505 ------------------------------------------------------------------- slack 4.546 Slack (MET) : 4.546ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 3.769ns (logic 0.364ns (9.658%) route 3.405ns (90.342%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.126ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.642ns = ( 10.959 - 8.317 ) Source Clock Delay (SCD): 2.736ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.261ns (routing 0.633ns, distribution 1.628ns) Clock Net Delay (Destination): 2.244ns (routing 0.572ns, distribution 1.672ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.261 2.736 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y484 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.875 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.264 5.139 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y477 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.364 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/O net (fo=15, routed) 1.141 6.505 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X87Y480 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.244 10.959 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X87Y480 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C clock pessimism 0.220 11.180 clock uncertainty -0.035 11.144 SLICE_X87Y480 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 11.051 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2] ------------------------------------------------------------------- required time 11.051 arrival time -6.505 ------------------------------------------------------------------- slack 4.546 Slack (MET) : 4.546ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 3.769ns (logic 0.364ns (9.658%) route 3.405ns (90.342%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.126ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.642ns = ( 10.959 - 8.317 ) Source Clock Delay (SCD): 2.736ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.261ns (routing 0.633ns, distribution 1.628ns) Clock Net Delay (Destination): 2.244ns (routing 0.572ns, distribution 1.672ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.261 2.736 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y484 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.875 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.264 5.139 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y477 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.364 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/O net (fo=15, routed) 1.141 6.505 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X87Y480 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.244 10.959 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X87Y480 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C clock pessimism 0.220 11.180 clock uncertainty -0.035 11.144 SLICE_X87Y480 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.051 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4] ------------------------------------------------------------------- required time 11.051 arrival time -6.505 ------------------------------------------------------------------- slack 4.546 Slack (MET) : 4.551ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 3.762ns (logic 0.364ns (9.676%) route 3.398ns (90.324%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.124ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.640ns = ( 10.957 - 8.317 ) Source Clock Delay (SCD): 2.736ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.261ns (routing 0.633ns, distribution 1.628ns) Clock Net Delay (Destination): 2.242ns (routing 0.572ns, distribution 1.670ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.261 2.736 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y484 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.875 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.264 5.139 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y477 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.364 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/O net (fo=15, routed) 1.134 6.498 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X87Y480 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.242 10.957 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X87Y480 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/C clock pessimism 0.220 11.178 clock uncertainty -0.035 11.142 SLICE_X87Y480 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.049 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4] ------------------------------------------------------------------- required time 11.049 arrival time -6.498 ------------------------------------------------------------------- slack 4.551 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.137ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.217ns (logic 0.048ns (22.120%) route 0.169ns (77.880%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.316ns Source Clock Delay (SCD): 1.092ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 0.974ns (routing 0.275ns, distribution 0.699ns) Clock Net Delay (Destination): 1.151ns (routing 0.314ns, distribution 0.837ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.092 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y487 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X88Y487 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.140 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.169 1.309 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X85Y487 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.151 1.316 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X85Y487 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C clock pessimism -0.149 1.167 SLICE_X85Y487 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.172 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time -1.172 arrival time 1.309 ------------------------------------------------------------------- slack 0.137 Slack (MET) : 0.147ns (arrival time - required time) Source: SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[72]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.190ns (logic 0.048ns (25.263%) route 0.142ns (74.737%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.333ns Source Clock Delay (SCD): 1.102ns Clock Pessimism Removal (CPR): 0.193ns Clock Net Delay (Source): 0.984ns (routing 0.275ns, distribution 0.709ns) Clock Net Delay (Destination): 1.168ns (routing 0.314ns, distribution 0.854ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.984 1.102 SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y482 FDPE r SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X85Y482 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.150 f SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.142 1.292 SFP_GEN[16].ngCCM_gbt/sync_m_reg[3][0] SLICE_X85Y482 FDCE f SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[72]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.168 1.333 SFP_GEN[16].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y482 FDCE r SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[72]/C clock pessimism -0.193 1.140 SLICE_X85Y482 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.145 SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[72] ------------------------------------------------------------------- required time -1.145 arrival time 1.292 ------------------------------------------------------------------- slack 0.147 Slack (MET) : 0.147ns (arrival time - required time) Source: SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[74]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.190ns (logic 0.048ns (25.263%) route 0.142ns (74.737%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.333ns Source Clock Delay (SCD): 1.102ns Clock Pessimism Removal (CPR): 0.193ns Clock Net Delay (Source): 0.984ns (routing 0.275ns, distribution 0.709ns) Clock Net Delay (Destination): 1.168ns (routing 0.314ns, distribution 0.854ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.984 1.102 SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y482 FDPE r SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X85Y482 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.150 f SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.142 1.292 SFP_GEN[16].ngCCM_gbt/sync_m_reg[3][0] SLICE_X85Y482 FDCE f SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[74]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.168 1.333 SFP_GEN[16].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y482 FDCE r SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[74]/C clock pessimism -0.193 1.140 SLICE_X85Y482 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.145 SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[74] ------------------------------------------------------------------- required time -1.145 arrival time 1.292 ------------------------------------------------------------------- slack 0.147 Slack (MET) : 0.147ns (arrival time - required time) Source: SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[76]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.190ns (logic 0.048ns (25.263%) route 0.142ns (74.737%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.333ns Source Clock Delay (SCD): 1.102ns Clock Pessimism Removal (CPR): 0.193ns Clock Net Delay (Source): 0.984ns (routing 0.275ns, distribution 0.709ns) Clock Net Delay (Destination): 1.168ns (routing 0.314ns, distribution 0.854ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.984 1.102 SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y482 FDPE r SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X85Y482 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.150 f SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.142 1.292 SFP_GEN[16].ngCCM_gbt/sync_m_reg[3][0] SLICE_X85Y482 FDCE f SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[76]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.168 1.333 SFP_GEN[16].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y482 FDCE r SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[76]/C clock pessimism -0.193 1.140 SLICE_X85Y482 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.145 SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[76] ------------------------------------------------------------------- required time -1.145 arrival time 1.292 ------------------------------------------------------------------- slack 0.147 Slack (MET) : 0.147ns (arrival time - required time) Source: SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[78]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.190ns (logic 0.048ns (25.263%) route 0.142ns (74.737%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.333ns Source Clock Delay (SCD): 1.102ns Clock Pessimism Removal (CPR): 0.193ns Clock Net Delay (Source): 0.984ns (routing 0.275ns, distribution 0.709ns) Clock Net Delay (Destination): 1.168ns (routing 0.314ns, distribution 0.854ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.984 1.102 SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y482 FDPE r SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X85Y482 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.150 f SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.142 1.292 SFP_GEN[16].ngCCM_gbt/sync_m_reg[3][0] SLICE_X85Y482 FDCE f SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[78]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.168 1.333 SFP_GEN[16].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y482 FDCE r SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[78]/C clock pessimism -0.193 1.140 SLICE_X85Y482 FDCE (Remov_GFF2_SLICEM_C_CLR) 0.005 1.145 SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[78] ------------------------------------------------------------------- required time -1.145 arrival time 1.292 ------------------------------------------------------------------- slack 0.147 Slack (MET) : 0.147ns (arrival time - required time) Source: SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.190ns (logic 0.048ns (25.263%) route 0.142ns (74.737%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.333ns Source Clock Delay (SCD): 1.102ns Clock Pessimism Removal (CPR): 0.193ns Clock Net Delay (Source): 0.984ns (routing 0.275ns, distribution 0.709ns) Clock Net Delay (Destination): 1.168ns (routing 0.314ns, distribution 0.854ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.984 1.102 SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y482 FDPE r SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X85Y482 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.150 f SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.142 1.292 SFP_GEN[16].ngCCM_gbt/sync_m_reg[3][0] SLICE_X85Y482 FDCE f SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.168 1.333 SFP_GEN[16].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y482 FDCE r SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[81]/C clock pessimism -0.193 1.140 SLICE_X85Y482 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.145 SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[81] ------------------------------------------------------------------- required time -1.145 arrival time 1.292 ------------------------------------------------------------------- slack 0.147 Slack (MET) : 0.163ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.258ns (logic 0.048ns (18.605%) route 0.210ns (81.395%)) Logic Levels: 0 Clock Path Skew: 0.090ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.331ns Source Clock Delay (SCD): 1.092ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 0.974ns (routing 0.275ns, distribution 0.699ns) Clock Net Delay (Destination): 1.166ns (routing 0.314ns, distribution 0.852ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.092 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y487 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X88Y487 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.140 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.210 1.350 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X85Y488 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.166 1.331 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X85Y488 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C clock pessimism -0.149 1.182 SLICE_X85Y488 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.187 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20] ------------------------------------------------------------------- required time -1.187 arrival time 1.350 ------------------------------------------------------------------- slack 0.163 Slack (MET) : 0.163ns (arrival time - required time) Source: SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[16].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.238ns (logic 0.048ns (20.168%) route 0.190ns (79.832%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.321ns Source Clock Delay (SCD): 1.102ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 0.984ns (routing 0.275ns, distribution 0.709ns) Clock Net Delay (Destination): 1.156ns (routing 0.314ns, distribution 0.842ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.984 1.102 SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y482 FDPE r SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X85Y482 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.150 f SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.190 1.340 SFP_GEN[16].ngCCM_gbt/sync_m_reg[3][0] SLICE_X84Y480 FDCE f SFP_GEN[16].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.156 1.321 SFP_GEN[16].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y480 FDCE r SFP_GEN[16].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.149 1.172 SLICE_X84Y480 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.177 SFP_GEN[16].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.177 arrival time 1.340 ------------------------------------------------------------------- slack 0.163 Slack (MET) : 0.167ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.263ns (logic 0.048ns (18.251%) route 0.215ns (81.749%)) Logic Levels: 0 Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.332ns Source Clock Delay (SCD): 1.092ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 0.974ns (routing 0.275ns, distribution 0.699ns) Clock Net Delay (Destination): 1.167ns (routing 0.314ns, distribution 0.853ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.092 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y487 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X88Y487 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.140 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.215 1.355 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X86Y488 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.167 1.332 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X86Y488 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C clock pessimism -0.149 1.183 SLICE_X86Y488 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.188 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time -1.188 arrival time 1.355 ------------------------------------------------------------------- slack 0.167 Slack (MET) : 0.167ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.263ns (logic 0.048ns (18.251%) route 0.215ns (81.749%)) Logic Levels: 0 Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.332ns Source Clock Delay (SCD): 1.092ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 0.974ns (routing 0.275ns, distribution 0.699ns) Clock Net Delay (Destination): 1.167ns (routing 0.314ns, distribution 0.853ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.092 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y487 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X88Y487 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.140 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.215 1.355 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X86Y488 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.167 1.332 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X86Y488 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism -0.149 1.183 SLICE_X86Y488 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.188 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time -1.188 arrival time 1.355 ------------------------------------------------------------------- slack 0.167 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_19 To Clock: gtwiz_userclk_rx_srcclk_out[0]_19 Setup : 0 Failing Endpoints, Worst Slack 4.835ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.214ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.835ns (required time - arrival time) Source: SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[64]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 2.881ns (logic 0.139ns (4.825%) route 2.742ns (95.175%)) Logic Levels: 0 Clock Path Skew: -0.473ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.243ns = ( 10.560 - 8.317 ) Source Clock Delay (SCD): 2.938ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.463ns (routing 0.630ns, distribution 1.833ns) Clock Net Delay (Destination): 1.845ns (routing 0.571ns, distribution 1.274ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.463 2.938 SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y482 FDPE r SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y482 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.077 f SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.742 5.819 SFP_GEN[17].ngCCM_gbt/sync_m_reg[3][0] SLICE_X114Y488 FDCE f SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[64]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.845 10.560 SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X114Y488 FDCE r SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[64]/C clock pessimism 0.222 10.782 clock uncertainty -0.035 10.747 SLICE_X114Y488 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.654 SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[64] ------------------------------------------------------------------- required time 10.654 arrival time -5.819 ------------------------------------------------------------------- slack 4.835 Slack (MET) : 4.835ns (required time - arrival time) Source: SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[66]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 2.881ns (logic 0.139ns (4.825%) route 2.742ns (95.175%)) Logic Levels: 0 Clock Path Skew: -0.473ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.243ns = ( 10.560 - 8.317 ) Source Clock Delay (SCD): 2.938ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.463ns (routing 0.630ns, distribution 1.833ns) Clock Net Delay (Destination): 1.845ns (routing 0.571ns, distribution 1.274ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.463 2.938 SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y482 FDPE r SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y482 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.077 f SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.742 5.819 SFP_GEN[17].ngCCM_gbt/sync_m_reg[3][0] SLICE_X114Y488 FDCE f SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[66]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.845 10.560 SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X114Y488 FDCE r SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[66]/C clock pessimism 0.222 10.782 clock uncertainty -0.035 10.747 SLICE_X114Y488 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 10.654 SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[66] ------------------------------------------------------------------- required time 10.654 arrival time -5.819 ------------------------------------------------------------------- slack 4.835 Slack (MET) : 4.938ns (required time - arrival time) Source: SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 2.774ns (logic 0.139ns (5.011%) route 2.635ns (94.989%)) Logic Levels: 0 Clock Path Skew: -0.477ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.239ns = ( 10.556 - 8.317 ) Source Clock Delay (SCD): 2.938ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.463ns (routing 0.630ns, distribution 1.833ns) Clock Net Delay (Destination): 1.841ns (routing 0.571ns, distribution 1.270ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.463 2.938 SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y482 FDPE r SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y482 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.077 f SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.635 5.712 SFP_GEN[17].ngCCM_gbt/sync_m_reg[3][0] SLICE_X110Y487 FDCE f SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.841 10.556 SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X110Y487 FDCE r SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[52]/C clock pessimism 0.222 10.778 clock uncertainty -0.035 10.743 SLICE_X110Y487 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 10.650 SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[52] ------------------------------------------------------------------- required time 10.650 arrival time -5.712 ------------------------------------------------------------------- slack 4.938 Slack (MET) : 4.938ns (required time - arrival time) Source: SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[54]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 2.774ns (logic 0.139ns (5.011%) route 2.635ns (94.989%)) Logic Levels: 0 Clock Path Skew: -0.477ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.239ns = ( 10.556 - 8.317 ) Source Clock Delay (SCD): 2.938ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.463ns (routing 0.630ns, distribution 1.833ns) Clock Net Delay (Destination): 1.841ns (routing 0.571ns, distribution 1.270ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.463 2.938 SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y482 FDPE r SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y482 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.077 f SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.635 5.712 SFP_GEN[17].ngCCM_gbt/sync_m_reg[3][0] SLICE_X110Y487 FDCE f SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[54]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.841 10.556 SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X110Y487 FDCE r SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[54]/C clock pessimism 0.222 10.778 clock uncertainty -0.035 10.743 SLICE_X110Y487 FDCE (Recov_HFF2_SLICEM_C_CLR) -0.093 10.650 SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[54] ------------------------------------------------------------------- required time 10.650 arrival time -5.712 ------------------------------------------------------------------- slack 4.938 Slack (MET) : 5.140ns (required time - arrival time) Source: SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[56]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 2.592ns (logic 0.139ns (5.363%) route 2.453ns (94.637%)) Logic Levels: 0 Clock Path Skew: -0.457ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.259ns = ( 10.576 - 8.317 ) Source Clock Delay (SCD): 2.938ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.463ns (routing 0.630ns, distribution 1.833ns) Clock Net Delay (Destination): 1.861ns (routing 0.571ns, distribution 1.290ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.463 2.938 SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y482 FDPE r SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y482 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.077 f SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.453 5.530 SFP_GEN[17].ngCCM_gbt/sync_m_reg[3][0] SLICE_X114Y486 FDCE f SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[56]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.861 10.576 SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X114Y486 FDCE r SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[56]/C clock pessimism 0.222 10.798 clock uncertainty -0.035 10.763 SLICE_X114Y486 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.670 SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[56] ------------------------------------------------------------------- required time 10.670 arrival time -5.530 ------------------------------------------------------------------- slack 5.140 Slack (MET) : 5.140ns (required time - arrival time) Source: SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[58]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 2.592ns (logic 0.139ns (5.363%) route 2.453ns (94.637%)) Logic Levels: 0 Clock Path Skew: -0.457ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.259ns = ( 10.576 - 8.317 ) Source Clock Delay (SCD): 2.938ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.463ns (routing 0.630ns, distribution 1.833ns) Clock Net Delay (Destination): 1.861ns (routing 0.571ns, distribution 1.290ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.463 2.938 SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y482 FDPE r SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y482 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.077 f SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.453 5.530 SFP_GEN[17].ngCCM_gbt/sync_m_reg[3][0] SLICE_X114Y486 FDCE f SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[58]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.861 10.576 SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X114Y486 FDCE r SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[58]/C clock pessimism 0.222 10.798 clock uncertainty -0.035 10.763 SLICE_X114Y486 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 10.670 SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[58] ------------------------------------------------------------------- required time 10.670 arrival time -5.530 ------------------------------------------------------------------- slack 5.140 Slack (MET) : 5.140ns (required time - arrival time) Source: SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[76]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 2.592ns (logic 0.139ns (5.363%) route 2.453ns (94.637%)) Logic Levels: 0 Clock Path Skew: -0.457ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.259ns = ( 10.576 - 8.317 ) Source Clock Delay (SCD): 2.938ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.463ns (routing 0.630ns, distribution 1.833ns) Clock Net Delay (Destination): 1.861ns (routing 0.571ns, distribution 1.290ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.463 2.938 SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y482 FDPE r SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y482 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.077 f SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.453 5.530 SFP_GEN[17].ngCCM_gbt/sync_m_reg[3][0] SLICE_X114Y486 FDCE f SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[76]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.861 10.576 SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X114Y486 FDCE r SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[76]/C clock pessimism 0.222 10.798 clock uncertainty -0.035 10.763 SLICE_X114Y486 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.670 SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[76] ------------------------------------------------------------------- required time 10.670 arrival time -5.530 ------------------------------------------------------------------- slack 5.140 Slack (MET) : 5.140ns (required time - arrival time) Source: SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[78]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 2.592ns (logic 0.139ns (5.363%) route 2.453ns (94.637%)) Logic Levels: 0 Clock Path Skew: -0.457ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.259ns = ( 10.576 - 8.317 ) Source Clock Delay (SCD): 2.938ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.463ns (routing 0.630ns, distribution 1.833ns) Clock Net Delay (Destination): 1.861ns (routing 0.571ns, distribution 1.290ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.463 2.938 SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y482 FDPE r SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y482 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.077 f SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.453 5.530 SFP_GEN[17].ngCCM_gbt/sync_m_reg[3][0] SLICE_X114Y486 FDCE f SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[78]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.861 10.576 SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X114Y486 FDCE r SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[78]/C clock pessimism 0.222 10.798 clock uncertainty -0.035 10.763 SLICE_X114Y486 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 10.670 SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[78] ------------------------------------------------------------------- required time 10.670 arrival time -5.530 ------------------------------------------------------------------- slack 5.140 Slack (MET) : 5.148ns (required time - arrival time) Source: SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[60]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 2.582ns (logic 0.139ns (5.383%) route 2.443ns (94.617%)) Logic Levels: 0 Clock Path Skew: -0.459ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.257ns = ( 10.574 - 8.317 ) Source Clock Delay (SCD): 2.938ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.463ns (routing 0.630ns, distribution 1.833ns) Clock Net Delay (Destination): 1.859ns (routing 0.571ns, distribution 1.288ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.463 2.938 SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y482 FDPE r SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y482 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.077 f SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.443 5.520 SFP_GEN[17].ngCCM_gbt/sync_m_reg[3][0] SLICE_X114Y486 FDCE f SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[60]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.859 10.574 SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X114Y486 FDCE r SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[60]/C clock pessimism 0.222 10.796 clock uncertainty -0.035 10.761 SLICE_X114Y486 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.668 SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[60] ------------------------------------------------------------------- required time 10.668 arrival time -5.520 ------------------------------------------------------------------- slack 5.148 Slack (MET) : 5.148ns (required time - arrival time) Source: SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[62]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 2.582ns (logic 0.139ns (5.383%) route 2.443ns (94.617%)) Logic Levels: 0 Clock Path Skew: -0.459ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.257ns = ( 10.574 - 8.317 ) Source Clock Delay (SCD): 2.938ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.463ns (routing 0.630ns, distribution 1.833ns) Clock Net Delay (Destination): 1.859ns (routing 0.571ns, distribution 1.288ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.463 2.938 SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y482 FDPE r SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y482 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.077 f SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.443 5.520 SFP_GEN[17].ngCCM_gbt/sync_m_reg[3][0] SLICE_X114Y486 FDCE f SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[62]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.859 10.574 SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X114Y486 FDCE r SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[62]/C clock pessimism 0.222 10.796 clock uncertainty -0.035 10.761 SLICE_X114Y486 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 10.668 SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[62] ------------------------------------------------------------------- required time 10.668 arrival time -5.520 ------------------------------------------------------------------- slack 5.148 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.214ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.254ns (logic 0.049ns (19.291%) route 0.205ns (80.709%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.098ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.786ns (routing 0.275ns, distribution 0.511ns) Clock Net Delay (Destination): 0.933ns (routing 0.312ns, distribution 0.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK SLICE_X109Y485 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y485 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.953 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.205 1.158 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X109Y487 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.933 1.098 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y487 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.159 0.939 SLICE_X109Y487 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 0.944 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -0.944 arrival time 1.158 ------------------------------------------------------------------- slack 0.214 Slack (MET) : 0.250ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.296ns (logic 0.049ns (16.554%) route 0.247ns (83.446%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.104ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.786ns (routing 0.275ns, distribution 0.511ns) Clock Net Delay (Destination): 0.939ns (routing 0.312ns, distribution 0.627ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK SLICE_X109Y485 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y485 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.953 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.247 1.200 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X109Y489 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.939 1.104 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y489 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C clock pessimism -0.159 0.945 SLICE_X109Y489 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 0.950 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg ------------------------------------------------------------------- required time -0.950 arrival time 1.200 ------------------------------------------------------------------- slack 0.250 Slack (MET) : 0.251ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.299ns (logic 0.049ns (16.388%) route 0.250ns (83.612%)) Logic Levels: 0 Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.106ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.786ns (routing 0.275ns, distribution 0.511ns) Clock Net Delay (Destination): 0.941ns (routing 0.312ns, distribution 0.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK SLICE_X109Y485 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y485 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.953 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.250 1.203 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X109Y489 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.941 1.106 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y489 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C clock pessimism -0.159 0.947 SLICE_X109Y489 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 0.952 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0] ------------------------------------------------------------------- required time -0.952 arrival time 1.203 ------------------------------------------------------------------- slack 0.251 Slack (MET) : 0.253ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.320ns (logic 0.049ns (15.312%) route 0.271ns (84.687%)) Logic Levels: 0 Clock Path Skew: 0.062ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.093ns Source Clock Delay (SCD): 0.903ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.785ns (routing 0.275ns, distribution 0.510ns) Clock Net Delay (Destination): 0.928ns (routing 0.312ns, distribution 0.616ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.785 0.903 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y489 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y489 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.952 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.271 1.223 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X110Y489 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.928 1.093 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X110Y489 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C clock pessimism -0.128 0.965 SLICE_X110Y489 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 0.970 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5] ------------------------------------------------------------------- required time -0.970 arrival time 1.223 ------------------------------------------------------------------- slack 0.253 Slack (MET) : 0.260ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[45]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.349ns (logic 0.049ns (14.040%) route 0.300ns (85.960%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.116ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.786ns (routing 0.275ns, distribution 0.511ns) Clock Net Delay (Destination): 0.951ns (routing 0.312ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK SLICE_X109Y485 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y485 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.953 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.300 1.253 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X111Y490 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[45]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.951 1.116 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y490 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[45]/C clock pessimism -0.128 0.988 SLICE_X111Y490 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 0.993 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[45] ------------------------------------------------------------------- required time -0.993 arrival time 1.253 ------------------------------------------------------------------- slack 0.260 Slack (MET) : 0.260ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[13]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.349ns (logic 0.049ns (14.040%) route 0.300ns (85.960%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.116ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.786ns (routing 0.275ns, distribution 0.511ns) Clock Net Delay (Destination): 0.951ns (routing 0.312ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK SLICE_X109Y485 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y485 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.953 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.300 1.253 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X111Y490 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[13]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.951 1.116 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y490 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[13]/C clock pessimism -0.128 0.988 SLICE_X111Y490 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 0.993 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[13] ------------------------------------------------------------------- required time -0.993 arrival time 1.253 ------------------------------------------------------------------- slack 0.260 Slack (MET) : 0.260ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[45]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.349ns (logic 0.049ns (14.040%) route 0.300ns (85.960%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.116ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.786ns (routing 0.275ns, distribution 0.511ns) Clock Net Delay (Destination): 0.951ns (routing 0.312ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK SLICE_X109Y485 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y485 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.953 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.300 1.253 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X111Y490 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[45]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.951 1.116 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y490 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[45]/C clock pessimism -0.128 0.988 SLICE_X111Y490 FDCE (Remov_GFF2_SLICEL_C_CLR) 0.005 0.993 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[45] ------------------------------------------------------------------- required time -0.993 arrival time 1.253 ------------------------------------------------------------------- slack 0.260 Slack (MET) : 0.260ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[53]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.349ns (logic 0.049ns (14.040%) route 0.300ns (85.960%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.116ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.786ns (routing 0.275ns, distribution 0.511ns) Clock Net Delay (Destination): 0.951ns (routing 0.312ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK SLICE_X109Y485 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y485 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.953 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.300 1.253 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X111Y490 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[53]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.951 1.116 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y490 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[53]/C clock pessimism -0.128 0.988 SLICE_X111Y490 FDCE (Remov_FFF2_SLICEL_C_CLR) 0.005 0.993 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[53] ------------------------------------------------------------------- required time -0.993 arrival time 1.253 ------------------------------------------------------------------- slack 0.260 Slack (MET) : 0.260ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[5]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.349ns (logic 0.049ns (14.040%) route 0.300ns (85.960%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.116ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.786ns (routing 0.275ns, distribution 0.511ns) Clock Net Delay (Destination): 0.951ns (routing 0.312ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK SLICE_X109Y485 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y485 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.953 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.300 1.253 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X111Y490 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.951 1.116 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y490 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[5]/C clock pessimism -0.128 0.988 SLICE_X111Y490 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 0.993 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[5] ------------------------------------------------------------------- required time -0.993 arrival time 1.253 ------------------------------------------------------------------- slack 0.260 Slack (MET) : 0.261ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[60]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.350ns (logic 0.049ns (14.000%) route 0.301ns (86.000%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.116ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.786ns (routing 0.275ns, distribution 0.511ns) Clock Net Delay (Destination): 0.951ns (routing 0.312ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK SLICE_X109Y485 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y485 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.953 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.301 1.254 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X110Y490 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[60]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.951 1.116 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X110Y490 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[60]/C clock pessimism -0.128 0.988 SLICE_X110Y490 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 0.993 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[60] ------------------------------------------------------------------- required time -0.993 arrival time 1.254 ------------------------------------------------------------------- slack 0.261 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_2 To Clock: gtwiz_userclk_rx_srcclk_out[0]_2 Setup : 0 Failing Endpoints, Worst Slack 5.700ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.146ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.700ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 2.236ns (logic 0.362ns (16.190%) route 1.874ns (83.810%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.253ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.373ns = ( 10.690 - 8.317 ) Source Clock Delay (SCD): 2.762ns Clock Pessimism Removal (CPR): 0.136ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.287ns (routing 0.630ns, distribution 1.657ns) Clock Net Delay (Destination): 1.975ns (routing 0.571ns, distribution 1.404ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.287 2.762 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y236 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.901 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.226 4.127 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X120Y236 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 4.350 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/O net (fo=15, routed) 0.648 4.998 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X119Y240 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.975 10.690 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] SLICE_X119Y240 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/C clock pessimism 0.136 10.826 clock uncertainty -0.035 10.791 SLICE_X119Y240 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.698 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3] ------------------------------------------------------------------- required time 10.698 arrival time -4.998 ------------------------------------------------------------------- slack 5.700 Slack (MET) : 5.700ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 2.236ns (logic 0.362ns (16.190%) route 1.874ns (83.810%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.253ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.373ns = ( 10.690 - 8.317 ) Source Clock Delay (SCD): 2.762ns Clock Pessimism Removal (CPR): 0.136ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.287ns (routing 0.630ns, distribution 1.657ns) Clock Net Delay (Destination): 1.975ns (routing 0.571ns, distribution 1.404ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.287 2.762 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y236 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.901 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.226 4.127 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X120Y236 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 4.350 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/O net (fo=15, routed) 0.648 4.998 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X119Y240 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.975 10.690 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] SLICE_X119Y240 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/C clock pessimism 0.136 10.826 clock uncertainty -0.035 10.791 SLICE_X119Y240 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.698 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6] ------------------------------------------------------------------- required time 10.698 arrival time -4.998 ------------------------------------------------------------------- slack 5.700 Slack (MET) : 5.700ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 2.236ns (logic 0.362ns (16.190%) route 1.874ns (83.810%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.253ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.373ns = ( 10.690 - 8.317 ) Source Clock Delay (SCD): 2.762ns Clock Pessimism Removal (CPR): 0.136ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.287ns (routing 0.630ns, distribution 1.657ns) Clock Net Delay (Destination): 1.975ns (routing 0.571ns, distribution 1.404ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.287 2.762 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y236 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.901 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.226 4.127 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X120Y236 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 4.350 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/O net (fo=15, routed) 0.648 4.998 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X119Y240 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.975 10.690 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] SLICE_X119Y240 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/C clock pessimism 0.136 10.826 clock uncertainty -0.035 10.791 SLICE_X119Y240 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 10.698 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7] ------------------------------------------------------------------- required time 10.698 arrival time -4.998 ------------------------------------------------------------------- slack 5.700 Slack (MET) : 5.775ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 2.225ns (logic 0.362ns (16.270%) route 1.863ns (83.730%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.189ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.350ns = ( 10.667 - 8.317 ) Source Clock Delay (SCD): 2.762ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.287ns (routing 0.630ns, distribution 1.657ns) Clock Net Delay (Destination): 1.952ns (routing 0.571ns, distribution 1.381ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.287 2.762 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y236 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.901 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.226 4.127 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X120Y236 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 4.350 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/O net (fo=15, routed) 0.637 4.987 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X119Y239 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.952 10.667 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] SLICE_X119Y239 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/C clock pessimism 0.223 10.890 clock uncertainty -0.035 10.855 SLICE_X119Y239 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.762 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11] ------------------------------------------------------------------- required time 10.762 arrival time -4.987 ------------------------------------------------------------------- slack 5.775 Slack (MET) : 5.775ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 2.225ns (logic 0.362ns (16.270%) route 1.863ns (83.730%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.189ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.350ns = ( 10.667 - 8.317 ) Source Clock Delay (SCD): 2.762ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.287ns (routing 0.630ns, distribution 1.657ns) Clock Net Delay (Destination): 1.952ns (routing 0.571ns, distribution 1.381ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.287 2.762 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y236 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.901 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.226 4.127 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X120Y236 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 4.350 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/O net (fo=15, routed) 0.637 4.987 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X119Y239 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.952 10.667 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] SLICE_X119Y239 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/C clock pessimism 0.223 10.890 clock uncertainty -0.035 10.855 SLICE_X119Y239 FDCE (Recov_BFF2_SLICEM_C_CLR) -0.093 10.762 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0] ------------------------------------------------------------------- required time 10.762 arrival time -4.987 ------------------------------------------------------------------- slack 5.775 Slack (MET) : 5.947ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 2.044ns (logic 0.288ns (14.090%) route 1.756ns (85.910%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.198ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.341ns = ( 10.658 - 8.317 ) Source Clock Delay (SCD): 2.762ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.287ns (routing 0.630ns, distribution 1.657ns) Clock Net Delay (Destination): 1.943ns (routing 0.571ns, distribution 1.372ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.287 2.762 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y236 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.901 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.216 4.117 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X115Y236 LUT2 (Prop_D6LUT_SLICEM_I0_O) 0.149 4.266 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__10/O net (fo=2, routed) 0.540 4.806 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X119Y236 FDCE f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.943 10.658 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X119Y236 FDCE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.223 10.881 clock uncertainty -0.035 10.846 SLICE_X119Y236 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 10.753 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 10.753 arrival time -4.806 ------------------------------------------------------------------- slack 5.947 Slack (MET) : 5.947ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 2.044ns (logic 0.288ns (14.090%) route 1.756ns (85.910%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.198ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.341ns = ( 10.658 - 8.317 ) Source Clock Delay (SCD): 2.762ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.287ns (routing 0.630ns, distribution 1.657ns) Clock Net Delay (Destination): 1.943ns (routing 0.571ns, distribution 1.372ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.287 2.762 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y236 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.901 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.216 4.117 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X115Y236 LUT2 (Prop_D6LUT_SLICEM_I0_O) 0.149 4.266 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__10/O net (fo=2, routed) 0.540 4.806 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X119Y236 FDCE f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.943 10.658 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X119Y236 FDCE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.223 10.881 clock uncertainty -0.035 10.846 SLICE_X119Y236 FDCE (Recov_AFF2_SLICEM_C_CLR) -0.093 10.753 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 10.753 arrival time -4.806 ------------------------------------------------------------------- slack 5.947 Slack (MET) : 5.966ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 2.023ns (logic 0.362ns (17.894%) route 1.661ns (82.106%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.200ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.339ns = ( 10.656 - 8.317 ) Source Clock Delay (SCD): 2.762ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.287ns (routing 0.630ns, distribution 1.657ns) Clock Net Delay (Destination): 1.941ns (routing 0.571ns, distribution 1.370ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.287 2.762 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y236 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.901 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.226 4.127 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X120Y236 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 4.350 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/O net (fo=15, routed) 0.435 4.785 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X122Y238 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.941 10.656 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] SLICE_X122Y238 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/C clock pessimism 0.223 10.879 clock uncertainty -0.035 10.844 SLICE_X122Y238 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.751 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1] ------------------------------------------------------------------- required time 10.751 arrival time -4.785 ------------------------------------------------------------------- slack 5.966 Slack (MET) : 5.966ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 2.023ns (logic 0.362ns (17.894%) route 1.661ns (82.106%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.200ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.339ns = ( 10.656 - 8.317 ) Source Clock Delay (SCD): 2.762ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.287ns (routing 0.630ns, distribution 1.657ns) Clock Net Delay (Destination): 1.941ns (routing 0.571ns, distribution 1.370ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.287 2.762 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y236 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.901 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.226 4.127 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X120Y236 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 4.350 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/O net (fo=15, routed) 0.435 4.785 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X122Y238 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.941 10.656 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] SLICE_X122Y238 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/C clock pessimism 0.223 10.879 clock uncertainty -0.035 10.844 SLICE_X122Y238 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 10.751 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2] ------------------------------------------------------------------- required time 10.751 arrival time -4.785 ------------------------------------------------------------------- slack 5.966 Slack (MET) : 5.966ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 2.023ns (logic 0.362ns (17.894%) route 1.661ns (82.106%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.200ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.339ns = ( 10.656 - 8.317 ) Source Clock Delay (SCD): 2.762ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.287ns (routing 0.630ns, distribution 1.657ns) Clock Net Delay (Destination): 1.941ns (routing 0.571ns, distribution 1.370ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.287 2.762 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y236 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.901 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.226 4.127 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X120Y236 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 4.350 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/O net (fo=15, routed) 0.435 4.785 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X122Y238 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.941 10.656 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] SLICE_X122Y238 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/C clock pessimism 0.223 10.879 clock uncertainty -0.035 10.844 SLICE_X122Y238 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 10.751 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3] ------------------------------------------------------------------- required time 10.751 arrival time -4.785 ------------------------------------------------------------------- slack 5.966 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.146ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[43]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.235ns (logic 0.049ns (20.851%) route 0.186ns (79.149%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.173ns Source Clock Delay (SCD): 0.955ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.837ns (routing 0.275ns, distribution 0.562ns) Clock Net Delay (Destination): 1.008ns (routing 0.312ns, distribution 0.696ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.837 0.955 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X119Y237 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X119Y237 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.004 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.186 1.190 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X122Y237 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[43]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.173 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X122Y237 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[43]/C clock pessimism -0.134 1.039 SLICE_X122Y237 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.044 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[43] ------------------------------------------------------------------- required time -1.044 arrival time 1.190 ------------------------------------------------------------------- slack 0.146 Slack (MET) : 0.146ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[46]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.235ns (logic 0.049ns (20.851%) route 0.186ns (79.149%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.173ns Source Clock Delay (SCD): 0.955ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.837ns (routing 0.275ns, distribution 0.562ns) Clock Net Delay (Destination): 1.008ns (routing 0.312ns, distribution 0.696ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.837 0.955 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X119Y237 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X119Y237 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.004 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.186 1.190 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X122Y237 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[46]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.173 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X122Y237 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[46]/C clock pessimism -0.134 1.039 SLICE_X122Y237 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 1.044 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[46] ------------------------------------------------------------------- required time -1.044 arrival time 1.190 ------------------------------------------------------------------- slack 0.146 Slack (MET) : 0.146ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[50]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.235ns (logic 0.049ns (20.851%) route 0.186ns (79.149%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.173ns Source Clock Delay (SCD): 0.955ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.837ns (routing 0.275ns, distribution 0.562ns) Clock Net Delay (Destination): 1.008ns (routing 0.312ns, distribution 0.696ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.837 0.955 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X119Y237 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X119Y237 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.004 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.186 1.190 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X122Y237 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[50]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.173 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X122Y237 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[50]/C clock pessimism -0.134 1.039 SLICE_X122Y237 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.044 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[50] ------------------------------------------------------------------- required time -1.044 arrival time 1.190 ------------------------------------------------------------------- slack 0.146 Slack (MET) : 0.146ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[23]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.235ns (logic 0.049ns (20.851%) route 0.186ns (79.149%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.173ns Source Clock Delay (SCD): 0.955ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.837ns (routing 0.275ns, distribution 0.562ns) Clock Net Delay (Destination): 1.008ns (routing 0.312ns, distribution 0.696ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.837 0.955 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X119Y237 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X119Y237 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.004 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.186 1.190 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X122Y237 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[23]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.173 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X122Y237 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[23]/C clock pessimism -0.134 1.039 SLICE_X122Y237 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 1.044 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[23] ------------------------------------------------------------------- required time -1.044 arrival time 1.190 ------------------------------------------------------------------- slack 0.146 Slack (MET) : 0.146ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[26]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.235ns (logic 0.049ns (20.851%) route 0.186ns (79.149%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.173ns Source Clock Delay (SCD): 0.955ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.837ns (routing 0.275ns, distribution 0.562ns) Clock Net Delay (Destination): 1.008ns (routing 0.312ns, distribution 0.696ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.837 0.955 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X119Y237 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X119Y237 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.004 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.186 1.190 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X122Y237 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[26]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.173 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X122Y237 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[26]/C clock pessimism -0.134 1.039 SLICE_X122Y237 FDCE (Remov_GFF2_SLICEL_C_CLR) 0.005 1.044 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[26] ------------------------------------------------------------------- required time -1.044 arrival time 1.190 ------------------------------------------------------------------- slack 0.146 Slack (MET) : 0.146ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[46]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.235ns (logic 0.049ns (20.851%) route 0.186ns (79.149%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.173ns Source Clock Delay (SCD): 0.955ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.837ns (routing 0.275ns, distribution 0.562ns) Clock Net Delay (Destination): 1.008ns (routing 0.312ns, distribution 0.696ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.837 0.955 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X119Y237 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X119Y237 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.004 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.186 1.190 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X122Y237 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[46]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.173 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X122Y237 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[46]/C clock pessimism -0.134 1.039 SLICE_X122Y237 FDCE (Remov_FFF2_SLICEL_C_CLR) 0.005 1.044 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[46] ------------------------------------------------------------------- required time -1.044 arrival time 1.190 ------------------------------------------------------------------- slack 0.146 Slack (MET) : 0.146ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[50]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.235ns (logic 0.049ns (20.851%) route 0.186ns (79.149%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.173ns Source Clock Delay (SCD): 0.955ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.837ns (routing 0.275ns, distribution 0.562ns) Clock Net Delay (Destination): 1.008ns (routing 0.312ns, distribution 0.696ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.837 0.955 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X119Y237 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X119Y237 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.004 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.186 1.190 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X122Y237 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[50]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.173 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X122Y237 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[50]/C clock pessimism -0.134 1.039 SLICE_X122Y237 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.044 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[50] ------------------------------------------------------------------- required time -1.044 arrival time 1.190 ------------------------------------------------------------------- slack 0.146 Slack (MET) : 0.149ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[26]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.241ns (logic 0.049ns (20.332%) route 0.192ns (79.668%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.176ns Source Clock Delay (SCD): 0.955ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.837ns (routing 0.275ns, distribution 0.562ns) Clock Net Delay (Destination): 1.011ns (routing 0.312ns, distribution 0.699ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.837 0.955 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X119Y237 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X119Y237 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.004 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.192 1.196 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X122Y237 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[26]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.011 1.176 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X122Y237 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[26]/C clock pessimism -0.134 1.042 SLICE_X122Y237 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 1.047 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[26] ------------------------------------------------------------------- required time -1.047 arrival time 1.196 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.149ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[27]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.241ns (logic 0.049ns (20.332%) route 0.192ns (79.668%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.176ns Source Clock Delay (SCD): 0.955ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.837ns (routing 0.275ns, distribution 0.562ns) Clock Net Delay (Destination): 1.011ns (routing 0.312ns, distribution 0.699ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.837 0.955 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X119Y237 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X119Y237 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.004 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.192 1.196 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X122Y237 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[27]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.011 1.176 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X122Y237 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[27]/C clock pessimism -0.134 1.042 SLICE_X122Y237 FDCE (Remov_DFF2_SLICEL_C_CLR) 0.005 1.047 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[27] ------------------------------------------------------------------- required time -1.047 arrival time 1.196 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.149ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[43]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.241ns (logic 0.049ns (20.332%) route 0.192ns (79.668%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.176ns Source Clock Delay (SCD): 0.955ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.837ns (routing 0.275ns, distribution 0.562ns) Clock Net Delay (Destination): 1.011ns (routing 0.312ns, distribution 0.699ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.837 0.955 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X119Y237 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X119Y237 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.004 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.192 1.196 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X122Y237 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[43]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.011 1.176 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X122Y237 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[43]/C clock pessimism -0.134 1.042 SLICE_X122Y237 FDCE (Remov_CFF2_SLICEL_C_CLR) 0.005 1.047 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[43] ------------------------------------------------------------------- required time -1.047 arrival time 1.196 ------------------------------------------------------------------- slack 0.149 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_20 To Clock: gtwiz_userclk_rx_srcclk_out[0]_20 Setup : 0 Failing Endpoints, Worst Slack 4.552ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.113ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.552ns (required time - arrival time) Source: SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 3.449ns (logic 0.139ns (4.030%) route 3.310ns (95.970%)) Logic Levels: 0 Clock Path Skew: -0.188ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.232ns = ( 10.549 - 8.317 ) Source Clock Delay (SCD): 2.633ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.158ns (routing 0.632ns, distribution 1.526ns) Clock Net Delay (Destination): 1.834ns (routing 0.573ns, distribution 1.261ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.158 2.633 SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y487 FDPE r SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y487 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 2.772 f SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 3.310 6.082 SFP_GEN[18].ngCCM_gbt/sync_m_reg[3][0] SLICE_X102Y513 FDCE f SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.834 10.549 SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X102Y513 FDCE r SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[18]/C clock pessimism 0.213 10.763 clock uncertainty -0.035 10.727 SLICE_X102Y513 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.634 SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[18] ------------------------------------------------------------------- required time 10.634 arrival time -6.082 ------------------------------------------------------------------- slack 4.552 Slack (MET) : 4.552ns (required time - arrival time) Source: SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 3.449ns (logic 0.139ns (4.030%) route 3.310ns (95.970%)) Logic Levels: 0 Clock Path Skew: -0.188ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.232ns = ( 10.549 - 8.317 ) Source Clock Delay (SCD): 2.633ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.158ns (routing 0.632ns, distribution 1.526ns) Clock Net Delay (Destination): 1.834ns (routing 0.573ns, distribution 1.261ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.158 2.633 SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y487 FDPE r SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y487 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 2.772 f SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 3.310 6.082 SFP_GEN[18].ngCCM_gbt/sync_m_reg[3][0] SLICE_X102Y513 FDCE f SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.834 10.549 SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X102Y513 FDCE r SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[19]/C clock pessimism 0.213 10.763 clock uncertainty -0.035 10.727 SLICE_X102Y513 FDCE (Recov_AFF2_SLICEL_C_CLR) -0.093 10.634 SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[19] ------------------------------------------------------------------- required time 10.634 arrival time -6.082 ------------------------------------------------------------------- slack 4.552 Slack (MET) : 4.552ns (required time - arrival time) Source: SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 3.449ns (logic 0.139ns (4.030%) route 3.310ns (95.970%)) Logic Levels: 0 Clock Path Skew: -0.188ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.232ns = ( 10.549 - 8.317 ) Source Clock Delay (SCD): 2.633ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.158ns (routing 0.632ns, distribution 1.526ns) Clock Net Delay (Destination): 1.834ns (routing 0.573ns, distribution 1.261ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.158 2.633 SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y487 FDPE r SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y487 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 2.772 f SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 3.310 6.082 SFP_GEN[18].ngCCM_gbt/sync_m_reg[3][0] SLICE_X102Y513 FDCE f SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.834 10.549 SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X102Y513 FDCE r SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[20]/C clock pessimism 0.213 10.763 clock uncertainty -0.035 10.727 SLICE_X102Y513 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.634 SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[20] ------------------------------------------------------------------- required time 10.634 arrival time -6.082 ------------------------------------------------------------------- slack 4.552 Slack (MET) : 4.552ns (required time - arrival time) Source: SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 3.449ns (logic 0.139ns (4.030%) route 3.310ns (95.970%)) Logic Levels: 0 Clock Path Skew: -0.188ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.232ns = ( 10.549 - 8.317 ) Source Clock Delay (SCD): 2.633ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.158ns (routing 0.632ns, distribution 1.526ns) Clock Net Delay (Destination): 1.834ns (routing 0.573ns, distribution 1.261ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.158 2.633 SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y487 FDPE r SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y487 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 2.772 f SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 3.310 6.082 SFP_GEN[18].ngCCM_gbt/sync_m_reg[3][0] SLICE_X102Y513 FDCE f SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.834 10.549 SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X102Y513 FDCE r SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[25]/C clock pessimism 0.213 10.763 clock uncertainty -0.035 10.727 SLICE_X102Y513 FDCE (Recov_BFF2_SLICEL_C_CLR) -0.093 10.634 SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[25] ------------------------------------------------------------------- required time 10.634 arrival time -6.082 ------------------------------------------------------------------- slack 4.552 Slack (MET) : 4.598ns (required time - arrival time) Source: SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[64]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 3.416ns (logic 0.139ns (4.069%) route 3.277ns (95.931%)) Logic Levels: 0 Clock Path Skew: -0.175ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.245ns = ( 10.562 - 8.317 ) Source Clock Delay (SCD): 2.633ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.158ns (routing 0.632ns, distribution 1.526ns) Clock Net Delay (Destination): 1.847ns (routing 0.573ns, distribution 1.274ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.158 2.633 SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y487 FDPE r SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y487 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 2.772 f SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 3.277 6.049 SFP_GEN[18].ngCCM_gbt/sync_m_reg[3][0] SLICE_X107Y507 FDCE f SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[64]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.847 10.562 SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y507 FDCE r SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[64]/C clock pessimism 0.213 10.775 clock uncertainty -0.035 10.740 SLICE_X107Y507 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 10.647 SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[64] ------------------------------------------------------------------- required time 10.647 arrival time -6.049 ------------------------------------------------------------------- slack 4.598 Slack (MET) : 4.598ns (required time - arrival time) Source: SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[66]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 3.416ns (logic 0.139ns (4.069%) route 3.277ns (95.931%)) Logic Levels: 0 Clock Path Skew: -0.175ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.245ns = ( 10.562 - 8.317 ) Source Clock Delay (SCD): 2.633ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.158ns (routing 0.632ns, distribution 1.526ns) Clock Net Delay (Destination): 1.847ns (routing 0.573ns, distribution 1.274ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.158 2.633 SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y487 FDPE r SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y487 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 2.772 f SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 3.277 6.049 SFP_GEN[18].ngCCM_gbt/sync_m_reg[3][0] SLICE_X107Y507 FDCE f SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[66]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.847 10.562 SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y507 FDCE r SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[66]/C clock pessimism 0.213 10.775 clock uncertainty -0.035 10.740 SLICE_X107Y507 FDCE (Recov_HFF2_SLICEM_C_CLR) -0.093 10.647 SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[66] ------------------------------------------------------------------- required time 10.647 arrival time -6.049 ------------------------------------------------------------------- slack 4.598 Slack (MET) : 4.598ns (required time - arrival time) Source: SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[68]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 3.416ns (logic 0.139ns (4.069%) route 3.277ns (95.931%)) Logic Levels: 0 Clock Path Skew: -0.175ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.245ns = ( 10.562 - 8.317 ) Source Clock Delay (SCD): 2.633ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.158ns (routing 0.632ns, distribution 1.526ns) Clock Net Delay (Destination): 1.847ns (routing 0.573ns, distribution 1.274ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.158 2.633 SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y487 FDPE r SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y487 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 2.772 f SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 3.277 6.049 SFP_GEN[18].ngCCM_gbt/sync_m_reg[3][0] SLICE_X107Y507 FDCE f SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[68]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.847 10.562 SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y507 FDCE r SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[68]/C clock pessimism 0.213 10.775 clock uncertainty -0.035 10.740 SLICE_X107Y507 FDCE (Recov_GFF_SLICEM_C_CLR) -0.093 10.647 SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[68] ------------------------------------------------------------------- required time 10.647 arrival time -6.049 ------------------------------------------------------------------- slack 4.598 Slack (MET) : 4.598ns (required time - arrival time) Source: SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[70]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 3.416ns (logic 0.139ns (4.069%) route 3.277ns (95.931%)) Logic Levels: 0 Clock Path Skew: -0.175ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.245ns = ( 10.562 - 8.317 ) Source Clock Delay (SCD): 2.633ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.158ns (routing 0.632ns, distribution 1.526ns) Clock Net Delay (Destination): 1.847ns (routing 0.573ns, distribution 1.274ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.158 2.633 SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y487 FDPE r SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y487 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 2.772 f SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 3.277 6.049 SFP_GEN[18].ngCCM_gbt/sync_m_reg[3][0] SLICE_X107Y507 FDCE f SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[70]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.847 10.562 SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y507 FDCE r SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[70]/C clock pessimism 0.213 10.775 clock uncertainty -0.035 10.740 SLICE_X107Y507 FDCE (Recov_GFF2_SLICEM_C_CLR) -0.093 10.647 SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[70] ------------------------------------------------------------------- required time 10.647 arrival time -6.049 ------------------------------------------------------------------- slack 4.598 Slack (MET) : 4.598ns (required time - arrival time) Source: SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[72]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 3.416ns (logic 0.139ns (4.069%) route 3.277ns (95.931%)) Logic Levels: 0 Clock Path Skew: -0.175ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.245ns = ( 10.562 - 8.317 ) Source Clock Delay (SCD): 2.633ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.158ns (routing 0.632ns, distribution 1.526ns) Clock Net Delay (Destination): 1.847ns (routing 0.573ns, distribution 1.274ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.158 2.633 SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y487 FDPE r SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y487 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 2.772 f SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 3.277 6.049 SFP_GEN[18].ngCCM_gbt/sync_m_reg[3][0] SLICE_X107Y507 FDCE f SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[72]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.847 10.562 SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y507 FDCE r SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[72]/C clock pessimism 0.213 10.775 clock uncertainty -0.035 10.740 SLICE_X107Y507 FDCE (Recov_FFF_SLICEM_C_CLR) -0.093 10.647 SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[72] ------------------------------------------------------------------- required time 10.647 arrival time -6.049 ------------------------------------------------------------------- slack 4.598 Slack (MET) : 4.598ns (required time - arrival time) Source: SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[74]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 3.416ns (logic 0.139ns (4.069%) route 3.277ns (95.931%)) Logic Levels: 0 Clock Path Skew: -0.175ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.245ns = ( 10.562 - 8.317 ) Source Clock Delay (SCD): 2.633ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.158ns (routing 0.632ns, distribution 1.526ns) Clock Net Delay (Destination): 1.847ns (routing 0.573ns, distribution 1.274ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.158 2.633 SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y487 FDPE r SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y487 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 2.772 f SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 3.277 6.049 SFP_GEN[18].ngCCM_gbt/sync_m_reg[3][0] SLICE_X107Y507 FDCE f SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[74]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.847 10.562 SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y507 FDCE r SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[74]/C clock pessimism 0.213 10.775 clock uncertainty -0.035 10.740 SLICE_X107Y507 FDCE (Recov_FFF2_SLICEM_C_CLR) -0.093 10.647 SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[74] ------------------------------------------------------------------- required time 10.647 arrival time -6.049 ------------------------------------------------------------------- slack 4.598 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.113ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.213ns (logic 0.049ns (23.005%) route 0.164ns (76.995%)) Logic Levels: 0 Clock Path Skew: 0.095ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.107ns Source Clock Delay (SCD): 0.884ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.766ns (routing 0.275ns, distribution 0.491ns) Clock Net Delay (Destination): 0.942ns (routing 0.312ns, distribution 0.630ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.766 0.884 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK SLICE_X109Y509 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y509 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 0.933 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.164 1.097 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X107Y508 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.942 1.107 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X107Y508 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.128 0.979 SLICE_X107Y508 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 0.984 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -0.984 arrival time 1.097 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.225ns (arrival time - required time) Source: SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.266ns (logic 0.048ns (18.045%) route 0.218ns (81.955%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.125ns Source Clock Delay (SCD): 0.927ns Clock Pessimism Removal (CPR): 0.162ns Clock Net Delay (Source): 0.809ns (routing 0.275ns, distribution 0.534ns) Clock Net Delay (Destination): 0.960ns (routing 0.312ns, distribution 0.648ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.809 0.927 SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y487 FDPE r SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y487 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 0.975 f SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.218 1.193 SFP_GEN[18].ngCCM_gbt/sync_m_reg[3][0] SLICE_X96Y485 FDCE f SFP_GEN[18].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.960 1.125 SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y485 FDCE r SFP_GEN[18].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.162 0.963 SLICE_X96Y485 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 0.968 SFP_GEN[18].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -0.968 arrival time 1.193 ------------------------------------------------------------------- slack 0.225 Slack (MET) : 0.252ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.316ns (logic 0.049ns (15.506%) route 0.267ns (84.494%)) Logic Levels: 0 Clock Path Skew: 0.059ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.095ns Source Clock Delay (SCD): 0.908ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.790ns (routing 0.275ns, distribution 0.515ns) Clock Net Delay (Destination): 0.930ns (routing 0.312ns, distribution 0.618ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.790 0.908 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X108Y518 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y518 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.957 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.267 1.224 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X105Y518 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.930 1.095 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X105Y518 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C clock pessimism -0.128 0.967 SLICE_X105Y518 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 0.972 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14] ------------------------------------------------------------------- required time -0.972 arrival time 1.224 ------------------------------------------------------------------- slack 0.252 Slack (MET) : 0.252ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.316ns (logic 0.049ns (15.506%) route 0.267ns (84.494%)) Logic Levels: 0 Clock Path Skew: 0.059ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.095ns Source Clock Delay (SCD): 0.908ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.790ns (routing 0.275ns, distribution 0.515ns) Clock Net Delay (Destination): 0.930ns (routing 0.312ns, distribution 0.618ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.790 0.908 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X108Y518 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y518 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.957 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.267 1.224 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X105Y518 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.930 1.095 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X105Y518 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism -0.128 0.967 SLICE_X105Y518 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 0.972 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time -0.972 arrival time 1.224 ------------------------------------------------------------------- slack 0.252 Slack (MET) : 0.252ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.316ns (logic 0.049ns (15.506%) route 0.267ns (84.494%)) Logic Levels: 0 Clock Path Skew: 0.059ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.095ns Source Clock Delay (SCD): 0.908ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.790ns (routing 0.275ns, distribution 0.515ns) Clock Net Delay (Destination): 0.930ns (routing 0.312ns, distribution 0.618ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.790 0.908 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X108Y518 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y518 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.957 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.267 1.224 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X105Y518 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.930 1.095 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X105Y518 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C clock pessimism -0.128 0.967 SLICE_X105Y518 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 0.972 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6] ------------------------------------------------------------------- required time -0.972 arrival time 1.224 ------------------------------------------------------------------- slack 0.252 Slack (MET) : 0.268ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[27]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.359ns (logic 0.049ns (13.649%) route 0.310ns (86.351%)) Logic Levels: 0 Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.098ns Source Clock Delay (SCD): 0.884ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.766ns (routing 0.275ns, distribution 0.491ns) Clock Net Delay (Destination): 0.933ns (routing 0.312ns, distribution 0.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.766 0.884 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK SLICE_X109Y509 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y509 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 0.933 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.310 1.243 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X108Y514 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[27]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.933 1.098 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X108Y514 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[27]/C clock pessimism -0.128 0.970 SLICE_X108Y514 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 0.975 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[27] ------------------------------------------------------------------- required time -0.975 arrival time 1.243 ------------------------------------------------------------------- slack 0.268 Slack (MET) : 0.268ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[32]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.359ns (logic 0.049ns (13.649%) route 0.310ns (86.351%)) Logic Levels: 0 Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.098ns Source Clock Delay (SCD): 0.884ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.766ns (routing 0.275ns, distribution 0.491ns) Clock Net Delay (Destination): 0.933ns (routing 0.312ns, distribution 0.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.766 0.884 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK SLICE_X109Y509 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y509 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 0.933 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.310 1.243 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X108Y514 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[32]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.933 1.098 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X108Y514 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[32]/C clock pessimism -0.128 0.970 SLICE_X108Y514 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 0.975 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[32] ------------------------------------------------------------------- required time -0.975 arrival time 1.243 ------------------------------------------------------------------- slack 0.268 Slack (MET) : 0.268ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[33]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.359ns (logic 0.049ns (13.649%) route 0.310ns (86.351%)) Logic Levels: 0 Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.098ns Source Clock Delay (SCD): 0.884ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.766ns (routing 0.275ns, distribution 0.491ns) Clock Net Delay (Destination): 0.933ns (routing 0.312ns, distribution 0.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.766 0.884 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK SLICE_X109Y509 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y509 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 0.933 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.310 1.243 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X108Y514 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[33]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.933 1.098 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X108Y514 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[33]/C clock pessimism -0.128 0.970 SLICE_X108Y514 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 0.975 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[33] ------------------------------------------------------------------- required time -0.975 arrival time 1.243 ------------------------------------------------------------------- slack 0.268 Slack (MET) : 0.301ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[41]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.411ns (logic 0.049ns (11.922%) route 0.362ns (88.078%)) Logic Levels: 0 Clock Path Skew: 0.105ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.117ns Source Clock Delay (SCD): 0.884ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.766ns (routing 0.275ns, distribution 0.491ns) Clock Net Delay (Destination): 0.952ns (routing 0.312ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.766 0.884 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK SLICE_X109Y509 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y509 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 0.933 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.362 1.295 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X107Y517 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[41]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.952 1.117 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X107Y517 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[41]/C clock pessimism -0.128 0.989 SLICE_X107Y517 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 0.994 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[41] ------------------------------------------------------------------- required time -0.994 arrival time 1.295 ------------------------------------------------------------------- slack 0.301 Slack (MET) : 0.301ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[44]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.411ns (logic 0.049ns (11.922%) route 0.362ns (88.078%)) Logic Levels: 0 Clock Path Skew: 0.105ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.117ns Source Clock Delay (SCD): 0.884ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.766ns (routing 0.275ns, distribution 0.491ns) Clock Net Delay (Destination): 0.952ns (routing 0.312ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.766 0.884 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK SLICE_X109Y509 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y509 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 0.933 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.362 1.295 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X107Y517 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[44]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.952 1.117 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X107Y517 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[44]/C clock pessimism -0.128 0.989 SLICE_X107Y517 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 0.994 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[44] ------------------------------------------------------------------- required time -0.994 arrival time 1.295 ------------------------------------------------------------------- slack 0.301 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_21 To Clock: gtwiz_userclk_rx_srcclk_out[0]_21 Setup : 0 Failing Endpoints, Worst Slack 4.999ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.161ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.999ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 3.031ns (logic 0.227ns (7.489%) route 2.804ns (92.511%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.334ns = ( 10.651 - 8.317 ) Source Clock Delay (SCD): 2.714ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.239ns (routing 0.632ns, distribution 1.607ns) Clock Net Delay (Destination): 1.936ns (routing 0.572ns, distribution 1.364ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.239 2.714 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y510 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y510 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.853 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.694 4.547 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X120Y484 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.635 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/O net (fo=15, routed) 1.110 5.745 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X127Y483 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.936 10.651 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X127Y483 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/C clock pessimism 0.221 10.872 clock uncertainty -0.035 10.837 SLICE_X127Y483 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.744 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3] ------------------------------------------------------------------- required time 10.744 arrival time -5.745 ------------------------------------------------------------------- slack 4.999 Slack (MET) : 4.999ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 3.031ns (logic 0.227ns (7.489%) route 2.804ns (92.511%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.334ns = ( 10.651 - 8.317 ) Source Clock Delay (SCD): 2.714ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.239ns (routing 0.632ns, distribution 1.607ns) Clock Net Delay (Destination): 1.936ns (routing 0.572ns, distribution 1.364ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.239 2.714 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y510 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y510 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.853 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.694 4.547 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X120Y484 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.635 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/O net (fo=15, routed) 1.110 5.745 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X127Y483 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.936 10.651 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X127Y483 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/C clock pessimism 0.221 10.872 clock uncertainty -0.035 10.837 SLICE_X127Y483 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.744 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4] ------------------------------------------------------------------- required time 10.744 arrival time -5.745 ------------------------------------------------------------------- slack 4.999 Slack (MET) : 4.999ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 3.031ns (logic 0.227ns (7.489%) route 2.804ns (92.511%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.334ns = ( 10.651 - 8.317 ) Source Clock Delay (SCD): 2.714ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.239ns (routing 0.632ns, distribution 1.607ns) Clock Net Delay (Destination): 1.936ns (routing 0.572ns, distribution 1.364ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.239 2.714 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y510 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y510 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.853 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.694 4.547 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X120Y484 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.635 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/O net (fo=15, routed) 1.110 5.745 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X127Y483 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.936 10.651 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X127Y483 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/C clock pessimism 0.221 10.872 clock uncertainty -0.035 10.837 SLICE_X127Y483 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.744 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6] ------------------------------------------------------------------- required time 10.744 arrival time -5.745 ------------------------------------------------------------------- slack 4.999 Slack (MET) : 4.999ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 3.031ns (logic 0.227ns (7.489%) route 2.804ns (92.511%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.334ns = ( 10.651 - 8.317 ) Source Clock Delay (SCD): 2.714ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.239ns (routing 0.632ns, distribution 1.607ns) Clock Net Delay (Destination): 1.936ns (routing 0.572ns, distribution 1.364ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.239 2.714 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y510 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y510 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.853 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.694 4.547 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X120Y484 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.635 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/O net (fo=15, routed) 1.110 5.745 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X127Y483 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.936 10.651 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X127Y483 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/C clock pessimism 0.221 10.872 clock uncertainty -0.035 10.837 SLICE_X127Y483 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.744 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7] ------------------------------------------------------------------- required time 10.744 arrival time -5.745 ------------------------------------------------------------------- slack 4.999 Slack (MET) : 5.007ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 3.021ns (logic 0.227ns (7.514%) route 2.794ns (92.486%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.161ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.332ns = ( 10.649 - 8.317 ) Source Clock Delay (SCD): 2.714ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.239ns (routing 0.632ns, distribution 1.607ns) Clock Net Delay (Destination): 1.934ns (routing 0.572ns, distribution 1.362ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.239 2.714 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y510 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y510 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.853 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.694 4.547 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X120Y484 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.635 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/O net (fo=15, routed) 1.100 5.735 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X127Y483 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.934 10.649 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X127Y483 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/C clock pessimism 0.221 10.871 clock uncertainty -0.035 10.835 SLICE_X127Y483 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 10.742 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5] ------------------------------------------------------------------- required time 10.742 arrival time -5.735 ------------------------------------------------------------------- slack 5.007 Slack (MET) : 5.167ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 2.863ns (logic 0.227ns (7.929%) route 2.636ns (92.071%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.334ns = ( 10.651 - 8.317 ) Source Clock Delay (SCD): 2.714ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.239ns (routing 0.632ns, distribution 1.607ns) Clock Net Delay (Destination): 1.936ns (routing 0.572ns, distribution 1.364ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.239 2.714 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y510 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y510 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.853 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.694 4.547 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X120Y484 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.635 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/O net (fo=15, routed) 0.942 5.577 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X127Y485 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.936 10.651 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X127Y485 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C clock pessimism 0.221 10.872 clock uncertainty -0.035 10.837 SLICE_X127Y485 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.744 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3] ------------------------------------------------------------------- required time 10.744 arrival time -5.577 ------------------------------------------------------------------- slack 5.167 Slack (MET) : 5.167ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 2.863ns (logic 0.227ns (7.929%) route 2.636ns (92.071%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.334ns = ( 10.651 - 8.317 ) Source Clock Delay (SCD): 2.714ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.239ns (routing 0.632ns, distribution 1.607ns) Clock Net Delay (Destination): 1.936ns (routing 0.572ns, distribution 1.364ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.239 2.714 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y510 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y510 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.853 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.694 4.547 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X120Y484 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.635 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/O net (fo=15, routed) 0.942 5.577 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X127Y485 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.936 10.651 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X127Y485 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/C clock pessimism 0.221 10.872 clock uncertainty -0.035 10.837 SLICE_X127Y485 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.744 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4] ------------------------------------------------------------------- required time 10.744 arrival time -5.577 ------------------------------------------------------------------- slack 5.167 Slack (MET) : 5.510ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 2.528ns (logic 0.227ns (8.979%) route 2.301ns (91.021%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.151ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.342ns = ( 10.659 - 8.317 ) Source Clock Delay (SCD): 2.714ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.239ns (routing 0.632ns, distribution 1.607ns) Clock Net Delay (Destination): 1.944ns (routing 0.572ns, distribution 1.372ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.239 2.714 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y510 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y510 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.853 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.694 4.547 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X120Y484 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.635 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/O net (fo=15, routed) 0.607 5.242 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X127Y484 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.944 10.659 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X127Y484 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/C clock pessimism 0.221 10.880 clock uncertainty -0.035 10.845 SLICE_X127Y484 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.752 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7] ------------------------------------------------------------------- required time 10.752 arrival time -5.242 ------------------------------------------------------------------- slack 5.510 Slack (MET) : 5.510ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 2.528ns (logic 0.227ns (8.979%) route 2.301ns (91.021%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.151ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.342ns = ( 10.659 - 8.317 ) Source Clock Delay (SCD): 2.714ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.239ns (routing 0.632ns, distribution 1.607ns) Clock Net Delay (Destination): 1.944ns (routing 0.572ns, distribution 1.372ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.239 2.714 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y510 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y510 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.853 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.694 4.547 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X120Y484 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.635 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/O net (fo=15, routed) 0.607 5.242 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X127Y484 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.944 10.659 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X127Y484 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/C clock pessimism 0.221 10.880 clock uncertainty -0.035 10.845 SLICE_X127Y484 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 10.752 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0] ------------------------------------------------------------------- required time 10.752 arrival time -5.242 ------------------------------------------------------------------- slack 5.510 Slack (MET) : 5.510ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 2.528ns (logic 0.227ns (8.979%) route 2.301ns (91.021%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.151ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.342ns = ( 10.659 - 8.317 ) Source Clock Delay (SCD): 2.714ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.239ns (routing 0.632ns, distribution 1.607ns) Clock Net Delay (Destination): 1.944ns (routing 0.572ns, distribution 1.372ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.239 2.714 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y510 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y510 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.853 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.694 4.547 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X120Y484 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.635 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/O net (fo=15, routed) 0.607 5.242 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X127Y484 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.944 10.659 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X127Y484 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/C clock pessimism 0.221 10.880 clock uncertainty -0.035 10.845 SLICE_X127Y484 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.752 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1] ------------------------------------------------------------------- required time 10.752 arrival time -5.242 ------------------------------------------------------------------- slack 5.510 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.161ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.242ns (logic 0.049ns (20.248%) route 0.193ns (79.752%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.156ns Source Clock Delay (SCD): 0.947ns Clock Pessimism Removal (CPR): 0.133ns Clock Net Delay (Source): 0.829ns (routing 0.274ns, distribution 0.555ns) Clock Net Delay (Destination): 0.991ns (routing 0.313ns, distribution 0.678ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.829 0.947 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X123Y486 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y486 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 0.996 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.193 1.189 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X127Y486 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.991 1.156 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X127Y486 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.133 1.023 SLICE_X127Y486 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.028 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -1.028 arrival time 1.189 ------------------------------------------------------------------- slack 0.161 Slack (MET) : 0.162ns (arrival time - required time) Source: SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.273ns (logic 0.048ns (17.582%) route 0.225ns (82.418%)) Logic Levels: 0 Clock Path Skew: 0.106ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.135ns Source Clock Delay (SCD): 0.900ns Clock Pessimism Removal (CPR): 0.129ns Clock Net Delay (Source): 0.782ns (routing 0.274ns, distribution 0.508ns) Clock Net Delay (Destination): 0.970ns (routing 0.313ns, distribution 0.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.782 0.900 SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X117Y484 FDPE r SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y484 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 0.948 f SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.225 1.173 SFP_GEN[19].ngCCM_gbt/sync_m_reg[3][0] SLICE_X120Y484 FDCE f SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.970 1.135 SFP_GEN[19].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X120Y484 FDCE r SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[17]/C clock pessimism -0.129 1.006 SLICE_X120Y484 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.011 SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[17] ------------------------------------------------------------------- required time -1.011 arrival time 1.173 ------------------------------------------------------------------- slack 0.162 Slack (MET) : 0.162ns (arrival time - required time) Source: SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.273ns (logic 0.048ns (17.582%) route 0.225ns (82.418%)) Logic Levels: 0 Clock Path Skew: 0.106ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.135ns Source Clock Delay (SCD): 0.900ns Clock Pessimism Removal (CPR): 0.129ns Clock Net Delay (Source): 0.782ns (routing 0.274ns, distribution 0.508ns) Clock Net Delay (Destination): 0.970ns (routing 0.313ns, distribution 0.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.782 0.900 SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X117Y484 FDPE r SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y484 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 0.948 f SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.225 1.173 SFP_GEN[19].ngCCM_gbt/sync_m_reg[3][0] SLICE_X120Y484 FDCE f SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.970 1.135 SFP_GEN[19].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X120Y484 FDCE r SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[21]/C clock pessimism -0.129 1.006 SLICE_X120Y484 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.011 SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[21] ------------------------------------------------------------------- required time -1.011 arrival time 1.173 ------------------------------------------------------------------- slack 0.162 Slack (MET) : 0.162ns (arrival time - required time) Source: SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.273ns (logic 0.048ns (17.582%) route 0.225ns (82.418%)) Logic Levels: 0 Clock Path Skew: 0.106ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.135ns Source Clock Delay (SCD): 0.900ns Clock Pessimism Removal (CPR): 0.129ns Clock Net Delay (Source): 0.782ns (routing 0.274ns, distribution 0.508ns) Clock Net Delay (Destination): 0.970ns (routing 0.313ns, distribution 0.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.782 0.900 SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X117Y484 FDPE r SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y484 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 0.948 f SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.225 1.173 SFP_GEN[19].ngCCM_gbt/sync_m_reg[3][0] SLICE_X120Y484 FDCE f SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.970 1.135 SFP_GEN[19].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X120Y484 FDCE r SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[23]/C clock pessimism -0.129 1.006 SLICE_X120Y484 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 1.011 SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[23] ------------------------------------------------------------------- required time -1.011 arrival time 1.173 ------------------------------------------------------------------- slack 0.162 Slack (MET) : 0.162ns (arrival time - required time) Source: SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.273ns (logic 0.048ns (17.582%) route 0.225ns (82.418%)) Logic Levels: 0 Clock Path Skew: 0.106ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.135ns Source Clock Delay (SCD): 0.900ns Clock Pessimism Removal (CPR): 0.129ns Clock Net Delay (Source): 0.782ns (routing 0.274ns, distribution 0.508ns) Clock Net Delay (Destination): 0.970ns (routing 0.313ns, distribution 0.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.782 0.900 SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X117Y484 FDPE r SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y484 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 0.948 f SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.225 1.173 SFP_GEN[19].ngCCM_gbt/sync_m_reg[3][0] SLICE_X120Y484 FDCE f SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.970 1.135 SFP_GEN[19].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X120Y484 FDCE r SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[24]/C clock pessimism -0.129 1.006 SLICE_X120Y484 FDCE (Remov_BFF2_SLICEL_C_CLR) 0.005 1.011 SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[24] ------------------------------------------------------------------- required time -1.011 arrival time 1.173 ------------------------------------------------------------------- slack 0.162 Slack (MET) : 0.162ns (arrival time - required time) Source: SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.273ns (logic 0.048ns (17.582%) route 0.225ns (82.418%)) Logic Levels: 0 Clock Path Skew: 0.106ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.135ns Source Clock Delay (SCD): 0.900ns Clock Pessimism Removal (CPR): 0.129ns Clock Net Delay (Source): 0.782ns (routing 0.274ns, distribution 0.508ns) Clock Net Delay (Destination): 0.970ns (routing 0.313ns, distribution 0.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.782 0.900 SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X117Y484 FDPE r SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y484 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 0.948 f SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.225 1.173 SFP_GEN[19].ngCCM_gbt/sync_m_reg[3][0] SLICE_X120Y484 FDCE f SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.970 1.135 SFP_GEN[19].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X120Y484 FDCE r SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[28]/C clock pessimism -0.129 1.006 SLICE_X120Y484 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 1.011 SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[28] ------------------------------------------------------------------- required time -1.011 arrival time 1.173 ------------------------------------------------------------------- slack 0.162 Slack (MET) : 0.172ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.223ns (logic 0.049ns (21.973%) route 0.174ns (78.027%)) Logic Levels: 0 Clock Path Skew: 0.046ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.158ns Source Clock Delay (SCD): 0.947ns Clock Pessimism Removal (CPR): 0.165ns Clock Net Delay (Source): 0.829ns (routing 0.274ns, distribution 0.555ns) Clock Net Delay (Destination): 0.993ns (routing 0.313ns, distribution 0.680ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.829 0.947 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X127Y488 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y488 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 0.996 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.174 1.170 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X126Y486 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.993 1.158 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X126Y486 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.165 0.993 SLICE_X126Y486 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 0.998 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -0.998 arrival time 1.170 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.179ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.212ns (logic 0.049ns (23.113%) route 0.163ns (76.887%)) Logic Levels: 0 Clock Path Skew: 0.028ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.140ns Source Clock Delay (SCD): 0.947ns Clock Pessimism Removal (CPR): 0.165ns Clock Net Delay (Source): 0.829ns (routing 0.274ns, distribution 0.555ns) Clock Net Delay (Destination): 0.975ns (routing 0.313ns, distribution 0.662ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.829 0.947 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X127Y488 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y488 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 0.996 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.163 1.159 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X127Y487 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.975 1.140 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X127Y487 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism -0.165 0.975 SLICE_X127Y487 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 0.980 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time -0.980 arrival time 1.159 ------------------------------------------------------------------- slack 0.179 Slack (MET) : 0.188ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.259ns (logic 0.049ns (18.919%) route 0.210ns (81.081%)) Logic Levels: 0 Clock Path Skew: 0.066ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.146ns Source Clock Delay (SCD): 0.947ns Clock Pessimism Removal (CPR): 0.133ns Clock Net Delay (Source): 0.829ns (routing 0.274ns, distribution 0.555ns) Clock Net Delay (Destination): 0.981ns (routing 0.313ns, distribution 0.668ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.829 0.947 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X127Y488 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y488 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 0.996 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.210 1.206 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X125Y486 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.981 1.146 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X125Y486 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C clock pessimism -0.133 1.013 SLICE_X125Y486 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.018 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20] ------------------------------------------------------------------- required time -1.018 arrival time 1.206 ------------------------------------------------------------------- slack 0.188 Slack (MET) : 0.190ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.274ns (logic 0.049ns (17.883%) route 0.225ns (82.117%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.159ns Source Clock Delay (SCD): 0.947ns Clock Pessimism Removal (CPR): 0.133ns Clock Net Delay (Source): 0.829ns (routing 0.274ns, distribution 0.555ns) Clock Net Delay (Destination): 0.994ns (routing 0.313ns, distribution 0.681ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.829 0.947 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X127Y488 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y488 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 0.996 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.225 1.221 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X123Y486 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.994 1.159 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X123Y486 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C clock pessimism -0.133 1.026 SLICE_X123Y486 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.031 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11] ------------------------------------------------------------------- required time -1.031 arrival time 1.221 ------------------------------------------------------------------- slack 0.190 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_22 To Clock: gtwiz_userclk_rx_srcclk_out[0]_22 Setup : 0 Failing Endpoints, Worst Slack 5.126ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.206ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.126ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 2.714ns (logic 0.227ns (8.364%) route 2.487ns (91.636%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.349ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.212ns = ( 10.529 - 8.317 ) Source Clock Delay (SCD): 2.772ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.628ns, distribution 1.669ns) Clock Net Delay (Destination): 1.814ns (routing 0.568ns, distribution 1.246ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.772 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y545 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.911 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.671 4.582 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y540 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.670 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0/O net (fo=15, routed) 0.816 5.486 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X116Y545 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.814 10.529 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X116Y545 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/C clock pessimism 0.211 10.740 clock uncertainty -0.035 10.705 SLICE_X116Y545 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.612 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1] ------------------------------------------------------------------- required time 10.612 arrival time -5.486 ------------------------------------------------------------------- slack 5.126 Slack (MET) : 5.126ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 2.714ns (logic 0.227ns (8.364%) route 2.487ns (91.636%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.349ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.212ns = ( 10.529 - 8.317 ) Source Clock Delay (SCD): 2.772ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.628ns, distribution 1.669ns) Clock Net Delay (Destination): 1.814ns (routing 0.568ns, distribution 1.246ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.772 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y545 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.911 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.671 4.582 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y540 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.670 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0/O net (fo=15, routed) 0.816 5.486 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X116Y545 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.814 10.529 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X116Y545 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/C clock pessimism 0.211 10.740 clock uncertainty -0.035 10.705 SLICE_X116Y545 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 10.612 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2] ------------------------------------------------------------------- required time 10.612 arrival time -5.486 ------------------------------------------------------------------- slack 5.126 Slack (MET) : 5.126ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 2.714ns (logic 0.227ns (8.364%) route 2.487ns (91.636%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.349ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.212ns = ( 10.529 - 8.317 ) Source Clock Delay (SCD): 2.772ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.628ns, distribution 1.669ns) Clock Net Delay (Destination): 1.814ns (routing 0.568ns, distribution 1.246ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.772 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y545 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.911 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.671 4.582 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y540 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.670 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0/O net (fo=15, routed) 0.816 5.486 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X116Y545 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.814 10.529 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X116Y545 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/C clock pessimism 0.211 10.740 clock uncertainty -0.035 10.705 SLICE_X116Y545 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.612 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3] ------------------------------------------------------------------- required time 10.612 arrival time -5.486 ------------------------------------------------------------------- slack 5.126 Slack (MET) : 5.126ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 2.714ns (logic 0.227ns (8.364%) route 2.487ns (91.636%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.349ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.212ns = ( 10.529 - 8.317 ) Source Clock Delay (SCD): 2.772ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.628ns, distribution 1.669ns) Clock Net Delay (Destination): 1.814ns (routing 0.568ns, distribution 1.246ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.772 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y545 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.911 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.671 4.582 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y540 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.670 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0/O net (fo=15, routed) 0.816 5.486 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X116Y545 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.814 10.529 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X116Y545 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/C clock pessimism 0.211 10.740 clock uncertainty -0.035 10.705 SLICE_X116Y545 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.612 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4] ------------------------------------------------------------------- required time 10.612 arrival time -5.486 ------------------------------------------------------------------- slack 5.126 Slack (MET) : 5.219ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 2.621ns (logic 0.227ns (8.661%) route 2.394ns (91.339%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.348ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.213ns = ( 10.530 - 8.317 ) Source Clock Delay (SCD): 2.772ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.628ns, distribution 1.669ns) Clock Net Delay (Destination): 1.815ns (routing 0.568ns, distribution 1.247ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.772 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y545 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.911 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.671 4.582 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y540 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.670 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0/O net (fo=15, routed) 0.723 5.393 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X113Y543 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.815 10.530 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X113Y543 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/C clock pessimism 0.211 10.741 clock uncertainty -0.035 10.705 SLICE_X113Y543 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.612 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1] ------------------------------------------------------------------- required time 10.612 arrival time -5.393 ------------------------------------------------------------------- slack 5.219 Slack (MET) : 5.219ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 2.621ns (logic 0.227ns (8.661%) route 2.394ns (91.339%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.348ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.213ns = ( 10.530 - 8.317 ) Source Clock Delay (SCD): 2.772ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.628ns, distribution 1.669ns) Clock Net Delay (Destination): 1.815ns (routing 0.568ns, distribution 1.247ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.772 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y545 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.911 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.671 4.582 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y540 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.670 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0/O net (fo=15, routed) 0.723 5.393 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X113Y543 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.815 10.530 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X113Y543 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/C clock pessimism 0.211 10.741 clock uncertainty -0.035 10.705 SLICE_X113Y543 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.612 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5] ------------------------------------------------------------------- required time 10.612 arrival time -5.393 ------------------------------------------------------------------- slack 5.219 Slack (MET) : 5.219ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 2.621ns (logic 0.227ns (8.661%) route 2.394ns (91.339%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.348ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.213ns = ( 10.530 - 8.317 ) Source Clock Delay (SCD): 2.772ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.628ns, distribution 1.669ns) Clock Net Delay (Destination): 1.815ns (routing 0.568ns, distribution 1.247ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.772 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y545 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.911 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.671 4.582 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y540 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.670 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0/O net (fo=15, routed) 0.723 5.393 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X113Y543 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.815 10.530 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X113Y543 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/C clock pessimism 0.211 10.741 clock uncertainty -0.035 10.705 SLICE_X113Y543 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 10.612 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6] ------------------------------------------------------------------- required time 10.612 arrival time -5.393 ------------------------------------------------------------------- slack 5.219 Slack (MET) : 5.219ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 2.621ns (logic 0.227ns (8.661%) route 2.394ns (91.339%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.348ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.213ns = ( 10.530 - 8.317 ) Source Clock Delay (SCD): 2.772ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.628ns, distribution 1.669ns) Clock Net Delay (Destination): 1.815ns (routing 0.568ns, distribution 1.247ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.772 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y545 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.911 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.671 4.582 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y540 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.670 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0/O net (fo=15, routed) 0.723 5.393 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X113Y543 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.815 10.530 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X113Y543 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/C clock pessimism 0.211 10.741 clock uncertainty -0.035 10.705 SLICE_X113Y543 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 10.612 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7] ------------------------------------------------------------------- required time 10.612 arrival time -5.393 ------------------------------------------------------------------- slack 5.219 Slack (MET) : 5.337ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 2.513ns (logic 0.228ns (9.073%) route 2.285ns (90.927%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.339ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.223ns = ( 10.540 - 8.317 ) Source Clock Delay (SCD): 2.772ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.628ns, distribution 1.669ns) Clock Net Delay (Destination): 1.825ns (routing 0.568ns, distribution 1.257ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.772 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y545 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.911 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.671 4.582 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X111Y540 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.089 4.671 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__19/O net (fo=2, routed) 0.614 5.285 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X111Y540 FDCE f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.825 10.540 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK SLICE_X111Y540 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.210 10.751 clock uncertainty -0.035 10.715 SLICE_X111Y540 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 10.622 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 10.622 arrival time -5.285 ------------------------------------------------------------------- slack 5.337 Slack (MET) : 5.337ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 2.513ns (logic 0.228ns (9.073%) route 2.285ns (90.927%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.339ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.223ns = ( 10.540 - 8.317 ) Source Clock Delay (SCD): 2.772ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.628ns, distribution 1.669ns) Clock Net Delay (Destination): 1.825ns (routing 0.568ns, distribution 1.257ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.772 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y545 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.911 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.671 4.582 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X111Y540 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.089 4.671 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__19/O net (fo=2, routed) 0.614 5.285 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X111Y540 FDCE f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.825 10.540 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK SLICE_X111Y540 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.210 10.751 clock uncertainty -0.035 10.715 SLICE_X111Y540 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 10.622 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 10.622 arrival time -5.285 ------------------------------------------------------------------- slack 5.337 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.206ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.049ns (18.491%) route 0.216ns (81.509%)) Logic Levels: 0 Clock Path Skew: 0.054ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.164ns Source Clock Delay (SCD): 0.945ns Clock Pessimism Removal (CPR): 0.165ns Clock Net Delay (Source): 0.827ns (routing 0.273ns, distribution 0.554ns) Clock Net Delay (Destination): 0.999ns (routing 0.314ns, distribution 0.685ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.827 0.945 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X119Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X119Y545 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.994 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.216 1.210 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X120Y546 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.164 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X120Y546 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C clock pessimism -0.165 0.999 SLICE_X120Y546 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.004 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time -1.004 arrival time 1.210 ------------------------------------------------------------------- slack 0.206 Slack (MET) : 0.206ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.049ns (18.491%) route 0.216ns (81.509%)) Logic Levels: 0 Clock Path Skew: 0.054ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.164ns Source Clock Delay (SCD): 0.945ns Clock Pessimism Removal (CPR): 0.165ns Clock Net Delay (Source): 0.827ns (routing 0.273ns, distribution 0.554ns) Clock Net Delay (Destination): 0.999ns (routing 0.314ns, distribution 0.685ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.827 0.945 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X119Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X119Y545 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.994 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.216 1.210 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X120Y546 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.164 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X120Y546 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C clock pessimism -0.165 0.999 SLICE_X120Y546 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.004 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19] ------------------------------------------------------------------- required time -1.004 arrival time 1.210 ------------------------------------------------------------------- slack 0.206 Slack (MET) : 0.206ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.049ns (18.491%) route 0.216ns (81.509%)) Logic Levels: 0 Clock Path Skew: 0.054ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.164ns Source Clock Delay (SCD): 0.945ns Clock Pessimism Removal (CPR): 0.165ns Clock Net Delay (Source): 0.827ns (routing 0.273ns, distribution 0.554ns) Clock Net Delay (Destination): 0.999ns (routing 0.314ns, distribution 0.685ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.827 0.945 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X119Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X119Y545 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.994 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.216 1.210 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X120Y546 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.164 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X120Y546 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C clock pessimism -0.165 0.999 SLICE_X120Y546 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.004 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5] ------------------------------------------------------------------- required time -1.004 arrival time 1.210 ------------------------------------------------------------------- slack 0.206 Slack (MET) : 0.208ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.249ns (logic 0.049ns (19.679%) route 0.200ns (80.321%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.101ns Source Clock Delay (SCD): 0.902ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 0.784ns (routing 0.273ns, distribution 0.511ns) Clock Net Delay (Destination): 0.936ns (routing 0.314ns, distribution 0.622ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.784 0.902 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK SLICE_X112Y543 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X112Y543 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.951 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.200 1.151 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X112Y545 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.936 1.101 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X112Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.163 0.938 SLICE_X112Y545 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 0.943 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -0.943 arrival time 1.151 ------------------------------------------------------------------- slack 0.208 Slack (MET) : 0.226ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.279ns (logic 0.049ns (17.563%) route 0.230ns (82.437%)) Logic Levels: 0 Clock Path Skew: 0.048ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.158ns Source Clock Delay (SCD): 0.945ns Clock Pessimism Removal (CPR): 0.165ns Clock Net Delay (Source): 0.827ns (routing 0.273ns, distribution 0.554ns) Clock Net Delay (Destination): 0.993ns (routing 0.314ns, distribution 0.679ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.827 0.945 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X119Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X119Y545 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.994 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.230 1.224 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X119Y543 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.993 1.158 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X119Y543 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C clock pessimism -0.165 0.993 SLICE_X119Y543 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 0.998 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14] ------------------------------------------------------------------- required time -0.998 arrival time 1.224 ------------------------------------------------------------------- slack 0.226 Slack (MET) : 0.226ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.279ns (logic 0.049ns (17.563%) route 0.230ns (82.437%)) Logic Levels: 0 Clock Path Skew: 0.048ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.158ns Source Clock Delay (SCD): 0.945ns Clock Pessimism Removal (CPR): 0.165ns Clock Net Delay (Source): 0.827ns (routing 0.273ns, distribution 0.554ns) Clock Net Delay (Destination): 0.993ns (routing 0.314ns, distribution 0.679ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.827 0.945 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X119Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X119Y545 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.994 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.230 1.224 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X119Y543 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.993 1.158 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X119Y543 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.165 0.993 SLICE_X119Y543 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 0.998 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -0.998 arrival time 1.224 ------------------------------------------------------------------- slack 0.226 Slack (MET) : 0.248ns (arrival time - required time) Source: SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.291ns (logic 0.048ns (16.495%) route 0.243ns (83.505%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.122ns Source Clock Delay (SCD): 0.912ns Clock Pessimism Removal (CPR): 0.172ns Clock Net Delay (Source): 0.794ns (routing 0.273ns, distribution 0.521ns) Clock Net Delay (Destination): 0.957ns (routing 0.314ns, distribution 0.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.794 0.912 SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X110Y543 FDPE r SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y543 FDPE (Prop_GFF2_SLICEM_C_Q) 0.048 0.960 f SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.243 1.203 SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] SLICE_X111Y543 FDCE f SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.957 1.122 SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y543 FDCE r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[18]/C clock pessimism -0.172 0.950 SLICE_X111Y543 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 0.955 SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[18] ------------------------------------------------------------------- required time -0.955 arrival time 1.203 ------------------------------------------------------------------- slack 0.248 Slack (MET) : 0.248ns (arrival time - required time) Source: SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.291ns (logic 0.048ns (16.495%) route 0.243ns (83.505%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.122ns Source Clock Delay (SCD): 0.912ns Clock Pessimism Removal (CPR): 0.172ns Clock Net Delay (Source): 0.794ns (routing 0.273ns, distribution 0.521ns) Clock Net Delay (Destination): 0.957ns (routing 0.314ns, distribution 0.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.794 0.912 SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X110Y543 FDPE r SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y543 FDPE (Prop_GFF2_SLICEM_C_Q) 0.048 0.960 f SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.243 1.203 SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] SLICE_X111Y543 FDCE f SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.957 1.122 SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y543 FDCE r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[21]/C clock pessimism -0.172 0.950 SLICE_X111Y543 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 0.955 SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[21] ------------------------------------------------------------------- required time -0.955 arrival time 1.203 ------------------------------------------------------------------- slack 0.248 Slack (MET) : 0.248ns (arrival time - required time) Source: SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.291ns (logic 0.048ns (16.495%) route 0.243ns (83.505%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.122ns Source Clock Delay (SCD): 0.912ns Clock Pessimism Removal (CPR): 0.172ns Clock Net Delay (Source): 0.794ns (routing 0.273ns, distribution 0.521ns) Clock Net Delay (Destination): 0.957ns (routing 0.314ns, distribution 0.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.794 0.912 SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X110Y543 FDPE r SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y543 FDPE (Prop_GFF2_SLICEM_C_Q) 0.048 0.960 f SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.243 1.203 SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] SLICE_X111Y543 FDCE f SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.957 1.122 SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y543 FDCE r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[23]/C clock pessimism -0.172 0.950 SLICE_X111Y543 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 0.955 SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[23] ------------------------------------------------------------------- required time -0.955 arrival time 1.203 ------------------------------------------------------------------- slack 0.248 Slack (MET) : 0.248ns (arrival time - required time) Source: SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.291ns (logic 0.048ns (16.495%) route 0.243ns (83.505%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.122ns Source Clock Delay (SCD): 0.912ns Clock Pessimism Removal (CPR): 0.172ns Clock Net Delay (Source): 0.794ns (routing 0.273ns, distribution 0.521ns) Clock Net Delay (Destination): 0.957ns (routing 0.314ns, distribution 0.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.794 0.912 SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X110Y543 FDPE r SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y543 FDPE (Prop_GFF2_SLICEM_C_Q) 0.048 0.960 f SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.243 1.203 SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] SLICE_X111Y543 FDCE f SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.957 1.122 SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y543 FDCE r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[24]/C clock pessimism -0.172 0.950 SLICE_X111Y543 FDCE (Remov_BFF2_SLICEL_C_CLR) 0.005 0.955 SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[24] ------------------------------------------------------------------- required time -0.955 arrival time 1.203 ------------------------------------------------------------------- slack 0.248 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_23 To Clock: gtwiz_userclk_rx_srcclk_out[0]_23 Setup : 0 Failing Endpoints, Worst Slack 3.755ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.149ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.755ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[112]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 3.815ns (logic 0.140ns (3.670%) route 3.675ns (96.330%)) Logic Levels: 0 Clock Path Skew: -0.619ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.299ns = ( 11.616 - 8.317 ) Source Clock Delay (SCD): 4.112ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.637ns (routing 1.356ns, distribution 2.281ns) Clock Net Delay (Destination): 2.901ns (routing 1.239ns, distribution 1.662ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.637 4.112 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X94Y538 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X94Y538 FDPE (Prop_AFF_SLICEL_C_Q) 0.140 4.252 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 3.675 7.927 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X98Y554 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[112]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.901 11.616 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X98Y554 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[112]/C clock pessimism 0.194 11.810 clock uncertainty -0.035 11.775 SLICE_X98Y554 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.682 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[112] ------------------------------------------------------------------- required time 11.682 arrival time -7.927 ------------------------------------------------------------------- slack 3.755 Slack (MET) : 4.147ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 3.835ns (logic 0.377ns (9.831%) route 3.458ns (90.170%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.207ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.586ns = ( 11.903 - 8.317 ) Source Clock Delay (SCD): 3.987ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.512ns (routing 1.356ns, distribution 2.156ns) Clock Net Delay (Destination): 3.188ns (routing 1.239ns, distribution 1.949ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.512 3.987 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y563 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y563 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.127 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.745 6.872 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X94Y534 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.237 7.109 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__20/O net (fo=2, routed) 0.713 7.822 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X94Y536 FDCE f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.188 11.903 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X94Y536 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.194 12.097 clock uncertainty -0.035 12.062 SLICE_X94Y536 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.969 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 11.969 arrival time -7.822 ------------------------------------------------------------------- slack 4.147 Slack (MET) : 4.147ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 3.835ns (logic 0.377ns (9.831%) route 3.458ns (90.170%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.207ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.586ns = ( 11.903 - 8.317 ) Source Clock Delay (SCD): 3.987ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.512ns (routing 1.356ns, distribution 2.156ns) Clock Net Delay (Destination): 3.188ns (routing 1.239ns, distribution 1.949ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.512 3.987 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y563 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y563 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.127 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.745 6.872 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X94Y534 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.237 7.109 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__20/O net (fo=2, routed) 0.713 7.822 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X94Y536 FDCE f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.188 11.903 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X94Y536 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.194 12.097 clock uncertainty -0.035 12.062 SLICE_X94Y536 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 11.969 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 11.969 arrival time -7.822 ------------------------------------------------------------------- slack 4.147 Slack (MET) : 4.170ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 3.820ns (logic 0.375ns (9.817%) route 3.445ns (90.183%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.199ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.594ns = ( 11.911 - 8.317 ) Source Clock Delay (SCD): 3.987ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.512ns (routing 1.356ns, distribution 2.156ns) Clock Net Delay (Destination): 3.196ns (routing 1.239ns, distribution 1.957ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.512 3.987 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y563 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y563 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.127 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.750 6.877 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y534 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 7.112 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0/O net (fo=15, routed) 0.695 7.807 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X94Y538 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.196 11.911 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 SLICE_X94Y538 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C clock pessimism 0.194 12.105 clock uncertainty -0.035 12.070 SLICE_X94Y538 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.977 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3] ------------------------------------------------------------------- required time 11.977 arrival time -7.807 ------------------------------------------------------------------- slack 4.170 Slack (MET) : 4.170ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 3.820ns (logic 0.375ns (9.817%) route 3.445ns (90.183%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.199ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.594ns = ( 11.911 - 8.317 ) Source Clock Delay (SCD): 3.987ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.512ns (routing 1.356ns, distribution 2.156ns) Clock Net Delay (Destination): 3.196ns (routing 1.239ns, distribution 1.957ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.512 3.987 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y563 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y563 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.127 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.750 6.877 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y534 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 7.112 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0/O net (fo=15, routed) 0.695 7.807 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X94Y538 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.196 11.911 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 SLICE_X94Y538 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/C clock pessimism 0.194 12.105 clock uncertainty -0.035 12.070 SLICE_X94Y538 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 11.977 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4] ------------------------------------------------------------------- required time 11.977 arrival time -7.807 ------------------------------------------------------------------- slack 4.170 Slack (MET) : 4.170ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 3.820ns (logic 0.375ns (9.817%) route 3.445ns (90.183%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.199ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.594ns = ( 11.911 - 8.317 ) Source Clock Delay (SCD): 3.987ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.512ns (routing 1.356ns, distribution 2.156ns) Clock Net Delay (Destination): 3.196ns (routing 1.239ns, distribution 1.957ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.512 3.987 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y563 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y563 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.127 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.750 6.877 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y534 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 7.112 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0/O net (fo=15, routed) 0.695 7.807 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X94Y538 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.196 11.911 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 SLICE_X94Y538 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/C clock pessimism 0.194 12.105 clock uncertainty -0.035 12.070 SLICE_X94Y538 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 11.977 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5] ------------------------------------------------------------------- required time 11.977 arrival time -7.807 ------------------------------------------------------------------- slack 4.170 Slack (MET) : 4.171ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 3.805ns (logic 0.375ns (9.855%) route 3.430ns (90.145%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.213ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.580ns = ( 11.897 - 8.317 ) Source Clock Delay (SCD): 3.987ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.512ns (routing 1.356ns, distribution 2.156ns) Clock Net Delay (Destination): 3.182ns (routing 1.239ns, distribution 1.943ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.512 3.987 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y563 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y563 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.127 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.750 6.877 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y534 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 7.112 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0/O net (fo=15, routed) 0.680 7.792 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X95Y538 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.182 11.897 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 SLICE_X95Y538 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/C clock pessimism 0.194 12.091 clock uncertainty -0.035 12.056 SLICE_X95Y538 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.963 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9] ------------------------------------------------------------------- required time 11.963 arrival time -7.792 ------------------------------------------------------------------- slack 4.171 Slack (MET) : 4.171ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 3.805ns (logic 0.375ns (9.855%) route 3.430ns (90.145%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.213ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.580ns = ( 11.897 - 8.317 ) Source Clock Delay (SCD): 3.987ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.512ns (routing 1.356ns, distribution 2.156ns) Clock Net Delay (Destination): 3.182ns (routing 1.239ns, distribution 1.943ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.512 3.987 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y563 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y563 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.127 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.750 6.877 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y534 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 7.112 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0/O net (fo=15, routed) 0.680 7.792 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X95Y538 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.182 11.897 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 SLICE_X95Y538 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/C clock pessimism 0.194 12.091 clock uncertainty -0.035 12.056 SLICE_X95Y538 FDCE (Recov_BFF2_SLICEM_C_CLR) -0.093 11.963 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0] ------------------------------------------------------------------- required time 11.963 arrival time -7.792 ------------------------------------------------------------------- slack 4.171 Slack (MET) : 4.226ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 3.766ns (logic 0.375ns (9.958%) route 3.391ns (90.042%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.197ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.596ns = ( 11.913 - 8.317 ) Source Clock Delay (SCD): 3.987ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.512ns (routing 1.356ns, distribution 2.156ns) Clock Net Delay (Destination): 3.198ns (routing 1.239ns, distribution 1.959ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.512 3.987 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y563 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y563 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.127 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.750 6.877 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y534 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 7.112 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0/O net (fo=15, routed) 0.641 7.753 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X94Y537 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.198 11.913 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 SLICE_X94Y537 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/C clock pessimism 0.194 12.107 clock uncertainty -0.035 12.072 SLICE_X94Y537 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.979 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1] ------------------------------------------------------------------- required time 11.979 arrival time -7.753 ------------------------------------------------------------------- slack 4.226 Slack (MET) : 4.234ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 3.756ns (logic 0.375ns (9.984%) route 3.381ns (90.016%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.199ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.594ns = ( 11.911 - 8.317 ) Source Clock Delay (SCD): 3.987ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.512ns (routing 1.356ns, distribution 2.156ns) Clock Net Delay (Destination): 3.196ns (routing 1.239ns, distribution 1.957ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.512 3.987 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y563 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y563 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.127 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.750 6.877 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y534 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 7.112 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0/O net (fo=15, routed) 0.631 7.743 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X94Y537 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 3.196 11.911 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 SLICE_X94Y537 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/C clock pessimism 0.194 12.105 clock uncertainty -0.035 12.070 SLICE_X94Y537 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.977 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0] ------------------------------------------------------------------- required time 11.977 arrival time -7.743 ------------------------------------------------------------------- slack 4.234 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.149ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.226ns (logic 0.049ns (21.681%) route 0.177ns (78.319%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.776ns Source Clock Delay (SCD): 1.503ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.385ns (routing 0.571ns, distribution 0.814ns) Clock Net Delay (Destination): 1.611ns (routing 0.638ns, distribution 0.973ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.385 1.503 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y550 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y550 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.552 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.177 1.729 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X91Y549 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.611 1.776 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X91Y549 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C clock pessimism -0.201 1.575 SLICE_X91Y549 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.580 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time -1.580 arrival time 1.729 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.149ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.226ns (logic 0.049ns (21.681%) route 0.177ns (78.319%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.776ns Source Clock Delay (SCD): 1.503ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.385ns (routing 0.571ns, distribution 0.814ns) Clock Net Delay (Destination): 1.611ns (routing 0.638ns, distribution 0.973ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.385 1.503 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y550 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y550 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.552 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.177 1.729 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X91Y549 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.611 1.776 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X91Y549 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C clock pessimism -0.201 1.575 SLICE_X91Y549 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.580 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time -1.580 arrival time 1.729 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.191ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.262ns (logic 0.049ns (18.702%) route 0.213ns (81.298%)) Logic Levels: 0 Clock Path Skew: 0.066ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.770ns Source Clock Delay (SCD): 1.503ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.385ns (routing 0.571ns, distribution 0.814ns) Clock Net Delay (Destination): 1.605ns (routing 0.638ns, distribution 0.967ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.385 1.503 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y550 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y550 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.552 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.213 1.765 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X90Y548 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.605 1.770 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X90Y548 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.201 1.569 SLICE_X90Y548 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.574 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -1.574 arrival time 1.765 ------------------------------------------------------------------- slack 0.191 Slack (MET) : 0.191ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.262ns (logic 0.049ns (18.702%) route 0.213ns (81.298%)) Logic Levels: 0 Clock Path Skew: 0.066ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.770ns Source Clock Delay (SCD): 1.503ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.385ns (routing 0.571ns, distribution 0.814ns) Clock Net Delay (Destination): 1.605ns (routing 0.638ns, distribution 0.967ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.385 1.503 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y550 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y550 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.552 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.213 1.765 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X90Y548 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.605 1.770 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X90Y548 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C clock pessimism -0.201 1.569 SLICE_X90Y548 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.574 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time -1.574 arrival time 1.765 ------------------------------------------------------------------- slack 0.191 Slack (MET) : 0.191ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.262ns (logic 0.049ns (18.702%) route 0.213ns (81.298%)) Logic Levels: 0 Clock Path Skew: 0.066ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.770ns Source Clock Delay (SCD): 1.503ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.385ns (routing 0.571ns, distribution 0.814ns) Clock Net Delay (Destination): 1.605ns (routing 0.638ns, distribution 0.967ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.385 1.503 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y550 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y550 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.552 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.213 1.765 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X90Y548 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.605 1.770 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X90Y548 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C clock pessimism -0.201 1.569 SLICE_X90Y548 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.574 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4] ------------------------------------------------------------------- required time -1.574 arrival time 1.765 ------------------------------------------------------------------- slack 0.191 Slack (MET) : 0.204ns (arrival time - required time) Source: SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.048ns (17.844%) route 0.221ns (82.156%)) Logic Levels: 0 Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.772ns Source Clock Delay (SCD): 1.511ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.393ns (routing 0.571ns, distribution 0.822ns) Clock Net Delay (Destination): 1.607ns (routing 0.638ns, distribution 0.969ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.393 1.511 SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y541 FDPE r SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y541 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.559 f SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.221 1.780 SFP_GEN[21].ngCCM_gbt/sync_m_reg[3][0] SLICE_X93Y543 FDCE f SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.607 1.772 SFP_GEN[21].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y543 FDCE r SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[20]/C clock pessimism -0.201 1.571 SLICE_X93Y543 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.576 SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[20] ------------------------------------------------------------------- required time -1.576 arrival time 1.780 ------------------------------------------------------------------- slack 0.204 Slack (MET) : 0.204ns (arrival time - required time) Source: SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.048ns (17.844%) route 0.221ns (82.156%)) Logic Levels: 0 Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.772ns Source Clock Delay (SCD): 1.511ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.393ns (routing 0.571ns, distribution 0.822ns) Clock Net Delay (Destination): 1.607ns (routing 0.638ns, distribution 0.969ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.393 1.511 SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y541 FDPE r SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y541 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.559 f SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.221 1.780 SFP_GEN[21].ngCCM_gbt/sync_m_reg[3][0] SLICE_X93Y543 FDCE f SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.607 1.772 SFP_GEN[21].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y543 FDCE r SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[25]/C clock pessimism -0.201 1.571 SLICE_X93Y543 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.576 SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[25] ------------------------------------------------------------------- required time -1.576 arrival time 1.780 ------------------------------------------------------------------- slack 0.204 Slack (MET) : 0.204ns (arrival time - required time) Source: SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.048ns (17.844%) route 0.221ns (82.156%)) Logic Levels: 0 Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.772ns Source Clock Delay (SCD): 1.511ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.393ns (routing 0.571ns, distribution 0.822ns) Clock Net Delay (Destination): 1.607ns (routing 0.638ns, distribution 0.969ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.393 1.511 SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y541 FDPE r SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y541 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.559 f SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.221 1.780 SFP_GEN[21].ngCCM_gbt/sync_m_reg[3][0] SLICE_X93Y543 FDCE f SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.607 1.772 SFP_GEN[21].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y543 FDCE r SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[26]/C clock pessimism -0.201 1.571 SLICE_X93Y543 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 1.576 SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[26] ------------------------------------------------------------------- required time -1.576 arrival time 1.780 ------------------------------------------------------------------- slack 0.204 Slack (MET) : 0.204ns (arrival time - required time) Source: SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.048ns (17.844%) route 0.221ns (82.156%)) Logic Levels: 0 Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.772ns Source Clock Delay (SCD): 1.511ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.393ns (routing 0.571ns, distribution 0.822ns) Clock Net Delay (Destination): 1.607ns (routing 0.638ns, distribution 0.969ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.393 1.511 SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y541 FDPE r SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y541 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.559 f SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.221 1.780 SFP_GEN[21].ngCCM_gbt/sync_m_reg[3][0] SLICE_X93Y543 FDCE f SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.607 1.772 SFP_GEN[21].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y543 FDCE r SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[27]/C clock pessimism -0.201 1.571 SLICE_X93Y543 FDCE (Remov_BFF2_SLICEL_C_CLR) 0.005 1.576 SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[27] ------------------------------------------------------------------- required time -1.576 arrival time 1.780 ------------------------------------------------------------------- slack 0.204 Slack (MET) : 0.204ns (arrival time - required time) Source: SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.048ns (17.844%) route 0.221ns (82.156%)) Logic Levels: 0 Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.772ns Source Clock Delay (SCD): 1.511ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.393ns (routing 0.571ns, distribution 0.822ns) Clock Net Delay (Destination): 1.607ns (routing 0.638ns, distribution 0.969ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.393 1.511 SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y541 FDPE r SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y541 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.559 f SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.221 1.780 SFP_GEN[21].ngCCM_gbt/sync_m_reg[3][0] SLICE_X93Y543 FDCE f SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.607 1.772 SFP_GEN[21].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y543 FDCE r SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[28]/C clock pessimism -0.201 1.571 SLICE_X93Y543 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 1.576 SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[28] ------------------------------------------------------------------- required time -1.576 arrival time 1.780 ------------------------------------------------------------------- slack 0.204 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_24 To Clock: gtwiz_userclk_rx_srcclk_out[0]_24 Setup : 0 Failing Endpoints, Worst Slack 3.383ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.142ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.383ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 4.806ns (logic 0.305ns (6.346%) route 4.501ns (93.654%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.663ns = ( 10.980 - 8.317 ) Source Clock Delay (SCD): 2.875ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.450ns (routing 0.794ns, distribution 1.656ns) Clock Net Delay (Destination): 2.287ns (routing 0.710ns, distribution 1.577ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.450 2.875 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y123 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y123 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.014 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.636 6.650 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y163 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 6.816 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/O net (fo=15, routed) 0.865 7.681 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X62Y177 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.287 10.980 g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X62Y177 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/C clock pessimism 0.212 11.192 clock uncertainty -0.035 11.157 SLICE_X62Y177 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.064 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4] ------------------------------------------------------------------- required time 11.064 arrival time -7.681 ------------------------------------------------------------------- slack 3.383 Slack (MET) : 3.383ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 4.806ns (logic 0.305ns (6.346%) route 4.501ns (93.654%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.663ns = ( 10.980 - 8.317 ) Source Clock Delay (SCD): 2.875ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.450ns (routing 0.794ns, distribution 1.656ns) Clock Net Delay (Destination): 2.287ns (routing 0.710ns, distribution 1.577ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.450 2.875 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y123 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y123 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.014 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.636 6.650 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y163 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 6.816 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/O net (fo=15, routed) 0.865 7.681 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X62Y177 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.287 10.980 g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X62Y177 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/C clock pessimism 0.212 11.192 clock uncertainty -0.035 11.157 SLICE_X62Y177 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.064 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5] ------------------------------------------------------------------- required time 11.064 arrival time -7.681 ------------------------------------------------------------------- slack 3.383 Slack (MET) : 3.383ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 4.806ns (logic 0.305ns (6.346%) route 4.501ns (93.654%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.663ns = ( 10.980 - 8.317 ) Source Clock Delay (SCD): 2.875ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.450ns (routing 0.794ns, distribution 1.656ns) Clock Net Delay (Destination): 2.287ns (routing 0.710ns, distribution 1.577ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.450 2.875 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y123 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y123 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.014 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.636 6.650 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y163 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 6.816 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/O net (fo=15, routed) 0.865 7.681 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X62Y177 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.287 10.980 g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X62Y177 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/C clock pessimism 0.212 11.192 clock uncertainty -0.035 11.157 SLICE_X62Y177 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 11.064 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6] ------------------------------------------------------------------- required time 11.064 arrival time -7.681 ------------------------------------------------------------------- slack 3.383 Slack (MET) : 3.527ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 4.671ns (logic 0.305ns (6.530%) route 4.366ns (93.470%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.009ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.672ns = ( 10.989 - 8.317 ) Source Clock Delay (SCD): 2.875ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.450ns (routing 0.794ns, distribution 1.656ns) Clock Net Delay (Destination): 2.296ns (routing 0.710ns, distribution 1.586ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.450 2.875 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y123 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y123 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.014 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.636 6.650 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y163 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 6.816 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/O net (fo=15, routed) 0.730 7.546 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X62Y179 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.296 10.989 g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X62Y179 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/C clock pessimism 0.212 11.201 clock uncertainty -0.035 11.166 SLICE_X62Y179 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.073 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0] ------------------------------------------------------------------- required time 11.073 arrival time -7.546 ------------------------------------------------------------------- slack 3.527 Slack (MET) : 3.527ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 4.671ns (logic 0.305ns (6.530%) route 4.366ns (93.470%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.009ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.672ns = ( 10.989 - 8.317 ) Source Clock Delay (SCD): 2.875ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.450ns (routing 0.794ns, distribution 1.656ns) Clock Net Delay (Destination): 2.296ns (routing 0.710ns, distribution 1.586ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.450 2.875 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y123 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y123 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.014 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.636 6.650 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y163 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 6.816 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/O net (fo=15, routed) 0.730 7.546 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X62Y179 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.296 10.989 g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X62Y179 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/C clock pessimism 0.212 11.201 clock uncertainty -0.035 11.166 SLICE_X62Y179 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 11.073 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0] ------------------------------------------------------------------- required time 11.073 arrival time -7.546 ------------------------------------------------------------------- slack 3.527 Slack (MET) : 3.527ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 4.671ns (logic 0.305ns (6.530%) route 4.366ns (93.470%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.009ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.672ns = ( 10.989 - 8.317 ) Source Clock Delay (SCD): 2.875ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.450ns (routing 0.794ns, distribution 1.656ns) Clock Net Delay (Destination): 2.296ns (routing 0.710ns, distribution 1.586ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.450 2.875 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y123 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y123 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.014 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.636 6.650 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y163 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 6.816 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/O net (fo=15, routed) 0.730 7.546 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X62Y179 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.296 10.989 g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X62Y179 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/C clock pessimism 0.212 11.201 clock uncertainty -0.035 11.166 SLICE_X62Y179 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.073 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5] ------------------------------------------------------------------- required time 11.073 arrival time -7.546 ------------------------------------------------------------------- slack 3.527 Slack (MET) : 3.532ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 4.664ns (logic 0.305ns (6.539%) route 4.359ns (93.461%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.007ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.670ns = ( 10.987 - 8.317 ) Source Clock Delay (SCD): 2.875ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.450ns (routing 0.794ns, distribution 1.656ns) Clock Net Delay (Destination): 2.294ns (routing 0.710ns, distribution 1.584ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.450 2.875 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y123 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y123 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.014 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.636 6.650 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y163 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 6.816 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/O net (fo=15, routed) 0.723 7.539 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X62Y179 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.294 10.987 g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X62Y179 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/C clock pessimism 0.212 11.199 clock uncertainty -0.035 11.164 SLICE_X62Y179 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.071 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1] ------------------------------------------------------------------- required time 11.071 arrival time -7.539 ------------------------------------------------------------------- slack 3.532 Slack (MET) : 3.532ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 4.664ns (logic 0.305ns (6.539%) route 4.359ns (93.461%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.007ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.670ns = ( 10.987 - 8.317 ) Source Clock Delay (SCD): 2.875ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.450ns (routing 0.794ns, distribution 1.656ns) Clock Net Delay (Destination): 2.294ns (routing 0.710ns, distribution 1.584ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.450 2.875 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y123 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y123 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.014 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.636 6.650 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y163 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 6.816 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/O net (fo=15, routed) 0.723 7.539 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X62Y179 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.294 10.987 g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X62Y179 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/C clock pessimism 0.212 11.199 clock uncertainty -0.035 11.164 SLICE_X62Y179 FDCE (Recov_GFF_SLICEM_C_CLR) -0.093 11.071 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2] ------------------------------------------------------------------- required time 11.071 arrival time -7.539 ------------------------------------------------------------------- slack 3.532 Slack (MET) : 3.532ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 4.664ns (logic 0.305ns (6.539%) route 4.359ns (93.461%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.007ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.670ns = ( 10.987 - 8.317 ) Source Clock Delay (SCD): 2.875ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.450ns (routing 0.794ns, distribution 1.656ns) Clock Net Delay (Destination): 2.294ns (routing 0.710ns, distribution 1.584ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.450 2.875 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y123 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y123 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.014 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.636 6.650 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y163 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 6.816 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/O net (fo=15, routed) 0.723 7.539 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X62Y179 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.294 10.987 g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X62Y179 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/C clock pessimism 0.212 11.199 clock uncertainty -0.035 11.164 SLICE_X62Y179 FDCE (Recov_FFF_SLICEM_C_CLR) -0.093 11.071 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3] ------------------------------------------------------------------- required time 11.071 arrival time -7.539 ------------------------------------------------------------------- slack 3.532 Slack (MET) : 3.532ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 4.664ns (logic 0.305ns (6.539%) route 4.359ns (93.461%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.007ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.670ns = ( 10.987 - 8.317 ) Source Clock Delay (SCD): 2.875ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.450ns (routing 0.794ns, distribution 1.656ns) Clock Net Delay (Destination): 2.294ns (routing 0.710ns, distribution 1.584ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.450 2.875 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y123 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y123 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.014 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.636 6.650 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y163 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 6.816 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/O net (fo=15, routed) 0.723 7.539 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X62Y179 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.294 10.987 g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X62Y179 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/C clock pessimism 0.212 11.199 clock uncertainty -0.035 11.164 SLICE_X62Y179 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 11.071 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7] ------------------------------------------------------------------- required time 11.071 arrival time -7.539 ------------------------------------------------------------------- slack 3.532 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.142ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[91]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.188ns (logic 0.049ns (26.064%) route 0.139ns (73.936%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.372ns Source Clock Delay (SCD): 1.130ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.014ns (routing 0.377ns, distribution 0.637ns) Clock Net Delay (Destination): 1.220ns (routing 0.443ns, distribution 0.777ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.130 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X60Y159 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y159 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.179 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.139 1.318 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X59Y159 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[91]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.220 1.372 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X59Y159 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[91]/C clock pessimism -0.201 1.171 SLICE_X59Y159 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.176 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[91] ------------------------------------------------------------------- required time -1.176 arrival time 1.318 ------------------------------------------------------------------- slack 0.142 Slack (MET) : 0.142ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[96]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.188ns (logic 0.049ns (26.064%) route 0.139ns (73.936%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.372ns Source Clock Delay (SCD): 1.130ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.014ns (routing 0.377ns, distribution 0.637ns) Clock Net Delay (Destination): 1.220ns (routing 0.443ns, distribution 0.777ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.130 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X60Y159 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y159 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.179 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.139 1.318 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X59Y159 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[96]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.220 1.372 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X59Y159 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[96]/C clock pessimism -0.201 1.171 SLICE_X59Y159 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.176 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[96] ------------------------------------------------------------------- required time -1.176 arrival time 1.318 ------------------------------------------------------------------- slack 0.142 Slack (MET) : 0.142ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[98]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.188ns (logic 0.049ns (26.064%) route 0.139ns (73.936%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.372ns Source Clock Delay (SCD): 1.130ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.014ns (routing 0.377ns, distribution 0.637ns) Clock Net Delay (Destination): 1.220ns (routing 0.443ns, distribution 0.777ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.130 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X60Y159 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y159 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.179 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.139 1.318 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X59Y159 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[98]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.220 1.372 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X59Y159 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[98]/C clock pessimism -0.201 1.171 SLICE_X59Y159 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.176 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[98] ------------------------------------------------------------------- required time -1.176 arrival time 1.318 ------------------------------------------------------------------- slack 0.142 Slack (MET) : 0.142ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[56]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.188ns (logic 0.049ns (26.064%) route 0.139ns (73.936%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.372ns Source Clock Delay (SCD): 1.130ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.014ns (routing 0.377ns, distribution 0.637ns) Clock Net Delay (Destination): 1.220ns (routing 0.443ns, distribution 0.777ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.130 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X60Y159 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y159 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.179 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.139 1.318 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X59Y159 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[56]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.220 1.372 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X59Y159 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[56]/C clock pessimism -0.201 1.171 SLICE_X59Y159 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.176 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[56] ------------------------------------------------------------------- required time -1.176 arrival time 1.318 ------------------------------------------------------------------- slack 0.142 Slack (MET) : 0.142ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[91]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.188ns (logic 0.049ns (26.064%) route 0.139ns (73.936%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.372ns Source Clock Delay (SCD): 1.130ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.014ns (routing 0.377ns, distribution 0.637ns) Clock Net Delay (Destination): 1.220ns (routing 0.443ns, distribution 0.777ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.130 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X60Y159 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y159 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.179 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.139 1.318 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X59Y159 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[91]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.220 1.372 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X59Y159 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[91]/C clock pessimism -0.201 1.171 SLICE_X59Y159 FDCE (Remov_GFF2_SLICEM_C_CLR) 0.005 1.176 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[91] ------------------------------------------------------------------- required time -1.176 arrival time 1.318 ------------------------------------------------------------------- slack 0.142 Slack (MET) : 0.142ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[96]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.188ns (logic 0.049ns (26.064%) route 0.139ns (73.936%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.372ns Source Clock Delay (SCD): 1.130ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.014ns (routing 0.377ns, distribution 0.637ns) Clock Net Delay (Destination): 1.220ns (routing 0.443ns, distribution 0.777ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.130 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X60Y159 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y159 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.179 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.139 1.318 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X59Y159 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[96]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.220 1.372 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X59Y159 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[96]/C clock pessimism -0.201 1.171 SLICE_X59Y159 FDCE (Remov_FFF2_SLICEM_C_CLR) 0.005 1.176 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[96] ------------------------------------------------------------------- required time -1.176 arrival time 1.318 ------------------------------------------------------------------- slack 0.142 Slack (MET) : 0.142ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[98]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.188ns (logic 0.049ns (26.064%) route 0.139ns (73.936%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.372ns Source Clock Delay (SCD): 1.130ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.014ns (routing 0.377ns, distribution 0.637ns) Clock Net Delay (Destination): 1.220ns (routing 0.443ns, distribution 0.777ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.130 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X60Y159 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y159 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.179 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.139 1.318 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X59Y159 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[98]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.220 1.372 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X59Y159 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[98]/C clock pessimism -0.201 1.171 SLICE_X59Y159 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.176 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[98] ------------------------------------------------------------------- required time -1.176 arrival time 1.318 ------------------------------------------------------------------- slack 0.142 Slack (MET) : 0.143ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[51]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.191ns (logic 0.049ns (25.654%) route 0.142ns (74.346%)) Logic Levels: 0 Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.374ns Source Clock Delay (SCD): 1.130ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.014ns (routing 0.377ns, distribution 0.637ns) Clock Net Delay (Destination): 1.222ns (routing 0.443ns, distribution 0.779ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.130 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X60Y159 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y159 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.179 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.142 1.321 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X59Y159 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[51]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.222 1.374 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X59Y159 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[51]/C clock pessimism -0.201 1.173 SLICE_X59Y159 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 1.178 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[51] ------------------------------------------------------------------- required time -1.178 arrival time 1.321 ------------------------------------------------------------------- slack 0.143 Slack (MET) : 0.143ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[56]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.191ns (logic 0.049ns (25.654%) route 0.142ns (74.346%)) Logic Levels: 0 Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.374ns Source Clock Delay (SCD): 1.130ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.014ns (routing 0.377ns, distribution 0.637ns) Clock Net Delay (Destination): 1.222ns (routing 0.443ns, distribution 0.779ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.130 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X60Y159 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y159 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.179 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.142 1.321 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X59Y159 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[56]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.222 1.374 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X59Y159 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[56]/C clock pessimism -0.201 1.173 SLICE_X59Y159 FDCE (Remov_CFF2_SLICEM_C_CLR) 0.005 1.178 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[56] ------------------------------------------------------------------- required time -1.178 arrival time 1.321 ------------------------------------------------------------------- slack 0.143 Slack (MET) : 0.143ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[58]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.191ns (logic 0.049ns (25.654%) route 0.142ns (74.346%)) Logic Levels: 0 Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.374ns Source Clock Delay (SCD): 1.130ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.014ns (routing 0.377ns, distribution 0.637ns) Clock Net Delay (Destination): 1.222ns (routing 0.443ns, distribution 0.779ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.130 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X60Y159 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y159 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.179 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.142 1.321 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X59Y159 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[58]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.222 1.374 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X59Y159 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[58]/C clock pessimism -0.201 1.173 SLICE_X59Y159 FDCE (Remov_BFF2_SLICEM_C_CLR) 0.005 1.178 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[58] ------------------------------------------------------------------- required time -1.178 arrival time 1.321 ------------------------------------------------------------------- slack 0.143 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_25 To Clock: gtwiz_userclk_rx_srcclk_out[0]_25 Setup : 0 Failing Endpoints, Worst Slack 5.131ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.147ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.131ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 2.741ns (logic 0.286ns (10.434%) route 2.455ns (89.566%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.317ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.307ns = ( 10.624 - 8.317 ) Source Clock Delay (SCD): 2.827ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.402ns (routing 0.759ns, distribution 1.643ns) Clock Net Delay (Destination): 1.931ns (routing 0.680ns, distribution 1.251ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.402 2.827 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y275 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y275 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.967 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.555 4.522 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X39Y269 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 4.668 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/O net (fo=15, routed) 0.900 5.568 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X39Y272 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.931 10.624 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7 SLICE_X39Y272 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/C clock pessimism 0.203 10.828 clock uncertainty -0.035 10.792 SLICE_X39Y272 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 10.699 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2] ------------------------------------------------------------------- required time 10.699 arrival time -5.568 ------------------------------------------------------------------- slack 5.131 Slack (MET) : 5.131ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 2.741ns (logic 0.286ns (10.434%) route 2.455ns (89.566%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.317ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.307ns = ( 10.624 - 8.317 ) Source Clock Delay (SCD): 2.827ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.402ns (routing 0.759ns, distribution 1.643ns) Clock Net Delay (Destination): 1.931ns (routing 0.680ns, distribution 1.251ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.402 2.827 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y275 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y275 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.967 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.555 4.522 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X39Y269 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 4.668 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/O net (fo=15, routed) 0.900 5.568 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X39Y272 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.931 10.624 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7 SLICE_X39Y272 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/C clock pessimism 0.203 10.828 clock uncertainty -0.035 10.792 SLICE_X39Y272 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.699 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3] ------------------------------------------------------------------- required time 10.699 arrival time -5.568 ------------------------------------------------------------------- slack 5.131 Slack (MET) : 5.131ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 2.741ns (logic 0.286ns (10.434%) route 2.455ns (89.566%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.317ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.307ns = ( 10.624 - 8.317 ) Source Clock Delay (SCD): 2.827ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.402ns (routing 0.759ns, distribution 1.643ns) Clock Net Delay (Destination): 1.931ns (routing 0.680ns, distribution 1.251ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.402 2.827 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y275 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y275 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.967 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.555 4.522 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X39Y269 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 4.668 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/O net (fo=15, routed) 0.900 5.568 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X39Y272 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.931 10.624 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7 SLICE_X39Y272 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/C clock pessimism 0.203 10.828 clock uncertainty -0.035 10.792 SLICE_X39Y272 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 10.699 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4] ------------------------------------------------------------------- required time 10.699 arrival time -5.568 ------------------------------------------------------------------- slack 5.131 Slack (MET) : 5.136ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 2.734ns (logic 0.286ns (10.461%) route 2.448ns (89.539%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.319ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.305ns = ( 10.622 - 8.317 ) Source Clock Delay (SCD): 2.827ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.402ns (routing 0.759ns, distribution 1.643ns) Clock Net Delay (Destination): 1.929ns (routing 0.680ns, distribution 1.249ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.402 2.827 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y275 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y275 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.967 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.555 4.522 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X39Y269 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 4.668 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/O net (fo=15, routed) 0.893 5.561 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X39Y272 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.929 10.622 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7 SLICE_X39Y272 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/C clock pessimism 0.203 10.826 clock uncertainty -0.035 10.790 SLICE_X39Y272 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 10.697 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6] ------------------------------------------------------------------- required time 10.697 arrival time -5.561 ------------------------------------------------------------------- slack 5.136 Slack (MET) : 5.136ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 2.734ns (logic 0.286ns (10.461%) route 2.448ns (89.539%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.319ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.305ns = ( 10.622 - 8.317 ) Source Clock Delay (SCD): 2.827ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.402ns (routing 0.759ns, distribution 1.643ns) Clock Net Delay (Destination): 1.929ns (routing 0.680ns, distribution 1.249ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.402 2.827 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y275 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y275 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.967 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.555 4.522 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X39Y269 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 4.668 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/O net (fo=15, routed) 0.893 5.561 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X39Y272 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.929 10.622 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7 SLICE_X39Y272 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/C clock pessimism 0.203 10.826 clock uncertainty -0.035 10.790 SLICE_X39Y272 FDCE (Recov_GFF_SLICEM_C_CLR) -0.093 10.697 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7] ------------------------------------------------------------------- required time 10.697 arrival time -5.561 ------------------------------------------------------------------- slack 5.136 Slack (MET) : 5.374ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 2.494ns (logic 0.365ns (14.635%) route 2.129ns (85.365%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.321ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.303ns = ( 10.620 - 8.317 ) Source Clock Delay (SCD): 2.827ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.402ns (routing 0.759ns, distribution 1.643ns) Clock Net Delay (Destination): 1.927ns (routing 0.680ns, distribution 1.247ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.402 2.827 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y275 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y275 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.967 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.368 4.335 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X37Y270 LUT2 (Prop_D6LUT_SLICEM_I0_O) 0.225 4.560 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__33/O net (fo=2, routed) 0.761 5.321 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X37Y270 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.927 10.620 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/CLK SLICE_X37Y270 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.203 10.824 clock uncertainty -0.035 10.788 SLICE_X37Y270 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 10.695 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 10.695 arrival time -5.321 ------------------------------------------------------------------- slack 5.374 Slack (MET) : 5.374ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 2.494ns (logic 0.365ns (14.635%) route 2.129ns (85.365%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.321ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.303ns = ( 10.620 - 8.317 ) Source Clock Delay (SCD): 2.827ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.402ns (routing 0.759ns, distribution 1.643ns) Clock Net Delay (Destination): 1.927ns (routing 0.680ns, distribution 1.247ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.402 2.827 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y275 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y275 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.967 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.368 4.335 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X37Y270 LUT2 (Prop_D6LUT_SLICEM_I0_O) 0.225 4.560 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__33/O net (fo=2, routed) 0.761 5.321 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X37Y270 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.927 10.620 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/CLK SLICE_X37Y270 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.203 10.824 clock uncertainty -0.035 10.788 SLICE_X37Y270 FDCE (Recov_EFF2_SLICEM_C_CLR) -0.093 10.695 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 10.695 arrival time -5.321 ------------------------------------------------------------------- slack 5.374 Slack (MET) : 5.389ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 2.484ns (logic 0.286ns (11.514%) route 2.198ns (88.486%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.316ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.308ns = ( 10.625 - 8.317 ) Source Clock Delay (SCD): 2.827ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.402ns (routing 0.759ns, distribution 1.643ns) Clock Net Delay (Destination): 1.932ns (routing 0.680ns, distribution 1.252ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.402 2.827 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y275 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y275 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.967 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.555 4.522 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X39Y269 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 4.668 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/O net (fo=15, routed) 0.643 5.311 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X39Y273 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.932 10.625 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7 SLICE_X39Y273 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/C clock pessimism 0.203 10.829 clock uncertainty -0.035 10.793 SLICE_X39Y273 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 10.700 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5] ------------------------------------------------------------------- required time 10.700 arrival time -5.311 ------------------------------------------------------------------- slack 5.389 Slack (MET) : 5.394ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 2.498ns (logic 0.286ns (11.449%) route 2.212ns (88.551%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.297ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.327ns = ( 10.644 - 8.317 ) Source Clock Delay (SCD): 2.827ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.402ns (routing 0.759ns, distribution 1.643ns) Clock Net Delay (Destination): 1.951ns (routing 0.680ns, distribution 1.271ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.402 2.827 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y275 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y275 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.967 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.555 4.522 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X39Y269 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 4.668 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/O net (fo=15, routed) 0.657 5.325 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X38Y273 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.951 10.644 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7 SLICE_X38Y273 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/C clock pessimism 0.203 10.847 clock uncertainty -0.035 10.812 SLICE_X38Y273 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.719 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10] ------------------------------------------------------------------- required time 10.719 arrival time -5.325 ------------------------------------------------------------------- slack 5.394 Slack (MET) : 5.394ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 2.477ns (logic 0.286ns (11.546%) route 2.191ns (88.454%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.318ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.306ns = ( 10.623 - 8.317 ) Source Clock Delay (SCD): 2.827ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.402ns (routing 0.759ns, distribution 1.643ns) Clock Net Delay (Destination): 1.930ns (routing 0.680ns, distribution 1.250ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.402 2.827 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y275 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y275 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.967 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.555 4.522 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X39Y269 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 4.668 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/O net (fo=15, routed) 0.636 5.304 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X39Y273 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.930 10.623 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7 SLICE_X39Y273 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/C clock pessimism 0.203 10.827 clock uncertainty -0.035 10.791 SLICE_X39Y273 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 10.698 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0] ------------------------------------------------------------------- required time 10.698 arrival time -5.304 ------------------------------------------------------------------- slack 5.394 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.147ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.218ns (logic 0.049ns (22.477%) route 0.169ns (77.523%)) Logic Levels: 0 Clock Path Skew: 0.066ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.197ns Source Clock Delay (SCD): 0.989ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.873ns (routing 0.364ns, distribution 0.509ns) Clock Net Delay (Destination): 1.045ns (routing 0.427ns, distribution 0.618ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.873 0.989 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X34Y276 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X34Y276 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.038 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.169 1.207 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X33Y276 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.045 1.197 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/CLK SLICE_X33Y276 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/READY_O_reg/C clock pessimism -0.142 1.055 SLICE_X33Y276 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.060 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/READY_O_reg ------------------------------------------------------------------- required time -1.060 arrival time 1.207 ------------------------------------------------------------------- slack 0.147 Slack (MET) : 0.176ns (arrival time - required time) Source: SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.262ns (logic 0.048ns (18.321%) route 0.214ns (81.679%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.210ns Source Clock Delay (SCD): 0.987ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.871ns (routing 0.364ns, distribution 0.507ns) Clock Net Delay (Destination): 1.058ns (routing 0.427ns, distribution 0.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.871 0.987 SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X36Y271 FDPE r SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y271 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.035 f SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.214 1.249 SFP_GEN[34].ngCCM_gbt/sync_m_reg[3][0] SLICE_X37Y273 FDCE f SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.058 1.210 SFP_GEN[34].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X37Y273 FDCE r SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[32]/C clock pessimism -0.142 1.068 SLICE_X37Y273 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.073 SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[32] ------------------------------------------------------------------- required time -1.073 arrival time 1.249 ------------------------------------------------------------------- slack 0.176 Slack (MET) : 0.176ns (arrival time - required time) Source: SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.262ns (logic 0.048ns (18.321%) route 0.214ns (81.679%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.210ns Source Clock Delay (SCD): 0.987ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.871ns (routing 0.364ns, distribution 0.507ns) Clock Net Delay (Destination): 1.058ns (routing 0.427ns, distribution 0.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.871 0.987 SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X36Y271 FDPE r SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y271 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.035 f SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.214 1.249 SFP_GEN[34].ngCCM_gbt/sync_m_reg[3][0] SLICE_X37Y273 FDCE f SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.058 1.210 SFP_GEN[34].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X37Y273 FDCE r SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[34]/C clock pessimism -0.142 1.068 SLICE_X37Y273 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 1.073 SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[34] ------------------------------------------------------------------- required time -1.073 arrival time 1.249 ------------------------------------------------------------------- slack 0.176 Slack (MET) : 0.176ns (arrival time - required time) Source: SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.262ns (logic 0.048ns (18.321%) route 0.214ns (81.679%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.210ns Source Clock Delay (SCD): 0.987ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.871ns (routing 0.364ns, distribution 0.507ns) Clock Net Delay (Destination): 1.058ns (routing 0.427ns, distribution 0.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.871 0.987 SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X36Y271 FDPE r SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y271 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.035 f SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.214 1.249 SFP_GEN[34].ngCCM_gbt/sync_m_reg[3][0] SLICE_X37Y273 FDCE f SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.058 1.210 SFP_GEN[34].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X37Y273 FDCE r SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[36]/C clock pessimism -0.142 1.068 SLICE_X37Y273 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 1.073 SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[36] ------------------------------------------------------------------- required time -1.073 arrival time 1.249 ------------------------------------------------------------------- slack 0.176 Slack (MET) : 0.176ns (arrival time - required time) Source: SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.262ns (logic 0.048ns (18.321%) route 0.214ns (81.679%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.210ns Source Clock Delay (SCD): 0.987ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.871ns (routing 0.364ns, distribution 0.507ns) Clock Net Delay (Destination): 1.058ns (routing 0.427ns, distribution 0.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.871 0.987 SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X36Y271 FDPE r SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y271 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.035 f SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.214 1.249 SFP_GEN[34].ngCCM_gbt/sync_m_reg[3][0] SLICE_X37Y273 FDCE f SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.058 1.210 SFP_GEN[34].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X37Y273 FDCE r SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[38]/C clock pessimism -0.142 1.068 SLICE_X37Y273 FDCE (Remov_CFF2_SLICEM_C_CLR) 0.005 1.073 SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[38] ------------------------------------------------------------------- required time -1.073 arrival time 1.249 ------------------------------------------------------------------- slack 0.176 Slack (MET) : 0.176ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.249ns (logic 0.049ns (19.679%) route 0.200ns (80.321%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.199ns Source Clock Delay (SCD): 0.989ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.873ns (routing 0.364ns, distribution 0.509ns) Clock Net Delay (Destination): 1.047ns (routing 0.427ns, distribution 0.620ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.873 0.989 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X34Y276 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X34Y276 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.038 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.200 1.238 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X37Y278 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.047 1.199 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X37Y278 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C clock pessimism -0.142 1.057 SLICE_X37Y278 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.062 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time -1.062 arrival time 1.238 ------------------------------------------------------------------- slack 0.176 Slack (MET) : 0.176ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.249ns (logic 0.049ns (19.679%) route 0.200ns (80.321%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.199ns Source Clock Delay (SCD): 0.989ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.873ns (routing 0.364ns, distribution 0.509ns) Clock Net Delay (Destination): 1.047ns (routing 0.427ns, distribution 0.620ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.873 0.989 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X34Y276 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X34Y276 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.038 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.200 1.238 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X37Y278 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.047 1.199 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X37Y278 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C clock pessimism -0.142 1.057 SLICE_X37Y278 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.062 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11] ------------------------------------------------------------------- required time -1.062 arrival time 1.238 ------------------------------------------------------------------- slack 0.176 Slack (MET) : 0.176ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.249ns (logic 0.049ns (19.679%) route 0.200ns (80.321%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.199ns Source Clock Delay (SCD): 0.989ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.873ns (routing 0.364ns, distribution 0.509ns) Clock Net Delay (Destination): 1.047ns (routing 0.427ns, distribution 0.620ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.873 0.989 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X34Y276 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X34Y276 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.038 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.200 1.238 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X37Y278 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.047 1.199 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X37Y278 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C clock pessimism -0.142 1.057 SLICE_X37Y278 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.062 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12] ------------------------------------------------------------------- required time -1.062 arrival time 1.238 ------------------------------------------------------------------- slack 0.176 Slack (MET) : 0.176ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.249ns (logic 0.049ns (19.679%) route 0.200ns (80.321%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.199ns Source Clock Delay (SCD): 0.989ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.873ns (routing 0.364ns, distribution 0.509ns) Clock Net Delay (Destination): 1.047ns (routing 0.427ns, distribution 0.620ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.873 0.989 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X34Y276 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X34Y276 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.038 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.200 1.238 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X37Y278 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.047 1.199 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X37Y278 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C clock pessimism -0.142 1.057 SLICE_X37Y278 FDCE (Remov_FFF2_SLICEM_C_CLR) 0.005 1.062 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14] ------------------------------------------------------------------- required time -1.062 arrival time 1.238 ------------------------------------------------------------------- slack 0.176 Slack (MET) : 0.176ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.249ns (logic 0.049ns (19.679%) route 0.200ns (80.321%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.199ns Source Clock Delay (SCD): 0.989ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.873ns (routing 0.364ns, distribution 0.509ns) Clock Net Delay (Destination): 1.047ns (routing 0.427ns, distribution 0.620ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.873 0.989 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X34Y276 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X34Y276 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.038 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.200 1.238 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X37Y278 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y112 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.047 1.199 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X37Y278 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism -0.142 1.057 SLICE_X37Y278 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.062 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time -1.062 arrival time 1.238 ------------------------------------------------------------------- slack 0.176 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_26 To Clock: gtwiz_userclk_rx_srcclk_out[0]_26 Setup : 0 Failing Endpoints, Worst Slack 4.278ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.141ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.278ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 3.880ns (logic 0.285ns (7.345%) route 3.595ns (92.655%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.639ns = ( 10.956 - 8.317 ) Source Clock Delay (SCD): 2.884ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.459ns (routing 0.781ns, distribution 1.678ns) Clock Net Delay (Destination): 2.263ns (routing 0.697ns, distribution 1.566ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.459 2.884 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y295 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y295 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.023 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.857 5.880 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X61Y291 LUT2 (Prop_C6LUT_SLICEM_I0_O) 0.146 6.026 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__34/O net (fo=2, routed) 0.738 6.764 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X56Y287 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.263 10.956 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK SLICE_X56Y287 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.214 11.170 clock uncertainty -0.035 11.135 SLICE_X56Y287 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 11.042 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 11.042 arrival time -6.764 ------------------------------------------------------------------- slack 4.278 Slack (MET) : 4.278ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 3.880ns (logic 0.285ns (7.345%) route 3.595ns (92.655%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.639ns = ( 10.956 - 8.317 ) Source Clock Delay (SCD): 2.884ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.459ns (routing 0.781ns, distribution 1.678ns) Clock Net Delay (Destination): 2.263ns (routing 0.697ns, distribution 1.566ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.459 2.884 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y295 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y295 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.023 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.857 5.880 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X61Y291 LUT2 (Prop_C6LUT_SLICEM_I0_O) 0.146 6.026 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__34/O net (fo=2, routed) 0.738 6.764 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X56Y287 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.263 10.956 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK SLICE_X56Y287 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.214 11.170 clock uncertainty -0.035 11.135 SLICE_X56Y287 FDCE (Recov_AFF2_SLICEL_C_CLR) -0.093 11.042 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 11.042 arrival time -6.764 ------------------------------------------------------------------- slack 4.278 Slack (MET) : 4.435ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 3.753ns (logic 0.288ns (7.674%) route 3.465ns (92.326%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.001ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.669ns = ( 10.986 - 8.317 ) Source Clock Delay (SCD): 2.884ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.459ns (routing 0.781ns, distribution 1.678ns) Clock Net Delay (Destination): 2.293ns (routing 0.697ns, distribution 1.596ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.459 2.884 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y295 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y295 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.023 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.859 5.882 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y291 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.031 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1/O net (fo=15, routed) 0.606 6.637 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X62Y285 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.293 10.986 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X62Y285 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/C clock pessimism 0.214 11.200 clock uncertainty -0.035 11.165 SLICE_X62Y285 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.072 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5] ------------------------------------------------------------------- required time 11.072 arrival time -6.637 ------------------------------------------------------------------- slack 4.435 Slack (MET) : 4.435ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 3.753ns (logic 0.288ns (7.674%) route 3.465ns (92.326%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.001ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.669ns = ( 10.986 - 8.317 ) Source Clock Delay (SCD): 2.884ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.459ns (routing 0.781ns, distribution 1.678ns) Clock Net Delay (Destination): 2.293ns (routing 0.697ns, distribution 1.596ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.459 2.884 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y295 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y295 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.023 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.859 5.882 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y291 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.031 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1/O net (fo=15, routed) 0.606 6.637 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X62Y285 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.293 10.986 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X62Y285 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/C clock pessimism 0.214 11.200 clock uncertainty -0.035 11.165 SLICE_X62Y285 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.072 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6] ------------------------------------------------------------------- required time 11.072 arrival time -6.637 ------------------------------------------------------------------- slack 4.435 Slack (MET) : 4.435ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 3.753ns (logic 0.288ns (7.674%) route 3.465ns (92.326%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.001ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.669ns = ( 10.986 - 8.317 ) Source Clock Delay (SCD): 2.884ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.459ns (routing 0.781ns, distribution 1.678ns) Clock Net Delay (Destination): 2.293ns (routing 0.697ns, distribution 1.596ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.459 2.884 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y295 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y295 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.023 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.859 5.882 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y291 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.031 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1/O net (fo=15, routed) 0.606 6.637 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X62Y285 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.293 10.986 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X62Y285 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/C clock pessimism 0.214 11.200 clock uncertainty -0.035 11.165 SLICE_X62Y285 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 11.072 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7] ------------------------------------------------------------------- required time 11.072 arrival time -6.637 ------------------------------------------------------------------- slack 4.435 Slack (MET) : 4.435ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 3.754ns (logic 0.288ns (7.672%) route 3.466ns (92.328%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.670ns = ( 10.987 - 8.317 ) Source Clock Delay (SCD): 2.884ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.459ns (routing 0.781ns, distribution 1.678ns) Clock Net Delay (Destination): 2.294ns (routing 0.697ns, distribution 1.597ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.459 2.884 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y295 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y295 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.023 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.859 5.882 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y291 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.031 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1/O net (fo=15, routed) 0.607 6.638 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X63Y285 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.294 10.987 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X63Y285 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/C clock pessimism 0.214 11.201 clock uncertainty -0.035 11.166 SLICE_X63Y285 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 11.073 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0] ------------------------------------------------------------------- required time 11.073 arrival time -6.638 ------------------------------------------------------------------- slack 4.435 Slack (MET) : 4.435ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 3.754ns (logic 0.288ns (7.672%) route 3.466ns (92.328%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.670ns = ( 10.987 - 8.317 ) Source Clock Delay (SCD): 2.884ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.459ns (routing 0.781ns, distribution 1.678ns) Clock Net Delay (Destination): 2.294ns (routing 0.697ns, distribution 1.597ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.459 2.884 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y295 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y295 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.023 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.859 5.882 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y291 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.031 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1/O net (fo=15, routed) 0.607 6.638 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X63Y285 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.294 10.987 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X63Y285 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/C clock pessimism 0.214 11.201 clock uncertainty -0.035 11.166 SLICE_X63Y285 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.073 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4] ------------------------------------------------------------------- required time 11.073 arrival time -6.638 ------------------------------------------------------------------- slack 4.435 Slack (MET) : 4.440ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 3.746ns (logic 0.288ns (7.688%) route 3.458ns (92.312%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.003ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.667ns = ( 10.984 - 8.317 ) Source Clock Delay (SCD): 2.884ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.459ns (routing 0.781ns, distribution 1.678ns) Clock Net Delay (Destination): 2.291ns (routing 0.697ns, distribution 1.594ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.459 2.884 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y295 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y295 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.023 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.859 5.882 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y291 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.031 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1/O net (fo=15, routed) 0.599 6.630 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X62Y285 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.291 10.984 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X62Y285 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/C clock pessimism 0.214 11.198 clock uncertainty -0.035 11.163 SLICE_X62Y285 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.070 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11] ------------------------------------------------------------------- required time 11.070 arrival time -6.630 ------------------------------------------------------------------- slack 4.440 Slack (MET) : 4.467ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 3.708ns (logic 0.288ns (7.767%) route 3.420ns (92.233%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.014ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.656ns = ( 10.973 - 8.317 ) Source Clock Delay (SCD): 2.884ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.459ns (routing 0.781ns, distribution 1.678ns) Clock Net Delay (Destination): 2.280ns (routing 0.697ns, distribution 1.583ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.459 2.884 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y295 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y295 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.023 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.859 5.882 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y291 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.031 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1/O net (fo=15, routed) 0.561 6.592 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X61Y285 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.280 10.973 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X61Y285 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/C clock pessimism 0.214 11.187 clock uncertainty -0.035 11.152 SLICE_X61Y285 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 11.059 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1] ------------------------------------------------------------------- required time 11.059 arrival time -6.592 ------------------------------------------------------------------- slack 4.467 Slack (MET) : 4.467ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 3.708ns (logic 0.288ns (7.767%) route 3.420ns (92.233%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.014ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.656ns = ( 10.973 - 8.317 ) Source Clock Delay (SCD): 2.884ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.459ns (routing 0.781ns, distribution 1.678ns) Clock Net Delay (Destination): 2.280ns (routing 0.697ns, distribution 1.583ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.459 2.884 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y295 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y295 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.023 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.859 5.882 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y291 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.031 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1/O net (fo=15, routed) 0.561 6.592 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X61Y285 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.280 10.973 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X61Y285 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/C clock pessimism 0.214 11.187 clock uncertainty -0.035 11.152 SLICE_X61Y285 FDCE (Recov_BFF2_SLICEM_C_CLR) -0.093 11.059 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2] ------------------------------------------------------------------- required time 11.059 arrival time -6.592 ------------------------------------------------------------------- slack 4.467 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.048ns (20.779%) route 0.183ns (79.221%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.381ns Source Clock Delay (SCD): 1.138ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.022ns (routing 0.373ns, distribution 0.649ns) Clock Net Delay (Destination): 1.229ns (routing 0.438ns, distribution 0.791ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.022 1.138 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y291 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X59Y291 FDCE (Prop_HFF_SLICEM_C_Q) 0.048 1.186 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.183 1.369 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X61Y291 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.229 1.381 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X61Y291 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C clock pessimism -0.158 1.223 SLICE_X61Y291 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.228 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10] ------------------------------------------------------------------- required time -1.228 arrival time 1.369 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.048ns (20.779%) route 0.183ns (79.221%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.381ns Source Clock Delay (SCD): 1.138ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.022ns (routing 0.373ns, distribution 0.649ns) Clock Net Delay (Destination): 1.229ns (routing 0.438ns, distribution 0.791ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.022 1.138 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y291 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X59Y291 FDCE (Prop_HFF_SLICEM_C_Q) 0.048 1.186 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.183 1.369 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X61Y291 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.229 1.381 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X61Y291 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C clock pessimism -0.158 1.223 SLICE_X61Y291 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 1.228 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11] ------------------------------------------------------------------- required time -1.228 arrival time 1.369 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.048ns (20.779%) route 0.183ns (79.221%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.381ns Source Clock Delay (SCD): 1.138ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.022ns (routing 0.373ns, distribution 0.649ns) Clock Net Delay (Destination): 1.229ns (routing 0.438ns, distribution 0.791ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.022 1.138 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y291 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X59Y291 FDCE (Prop_HFF_SLICEM_C_Q) 0.048 1.186 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.183 1.369 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X61Y291 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.229 1.381 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X61Y291 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C clock pessimism -0.158 1.223 SLICE_X61Y291 FDCE (Remov_BFF_SLICEM_C_CLR) 0.005 1.228 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13] ------------------------------------------------------------------- required time -1.228 arrival time 1.369 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.048ns (20.779%) route 0.183ns (79.221%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.381ns Source Clock Delay (SCD): 1.138ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.022ns (routing 0.373ns, distribution 0.649ns) Clock Net Delay (Destination): 1.229ns (routing 0.438ns, distribution 0.791ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.022 1.138 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y291 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X59Y291 FDCE (Prop_HFF_SLICEM_C_Q) 0.048 1.186 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.183 1.369 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X61Y291 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.229 1.381 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X61Y291 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C clock pessimism -0.158 1.223 SLICE_X61Y291 FDCE (Remov_BFF2_SLICEM_C_CLR) 0.005 1.228 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15] ------------------------------------------------------------------- required time -1.228 arrival time 1.369 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.048ns (20.779%) route 0.183ns (79.221%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.381ns Source Clock Delay (SCD): 1.138ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.022ns (routing 0.373ns, distribution 0.649ns) Clock Net Delay (Destination): 1.229ns (routing 0.438ns, distribution 0.791ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.022 1.138 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y291 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X59Y291 FDCE (Prop_HFF_SLICEM_C_Q) 0.048 1.186 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.183 1.369 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X61Y291 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.229 1.381 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X61Y291 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C clock pessimism -0.158 1.223 SLICE_X61Y291 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 1.228 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5] ------------------------------------------------------------------- required time -1.228 arrival time 1.369 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.048ns (20.779%) route 0.183ns (79.221%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.381ns Source Clock Delay (SCD): 1.138ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.022ns (routing 0.373ns, distribution 0.649ns) Clock Net Delay (Destination): 1.229ns (routing 0.438ns, distribution 0.791ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.022 1.138 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y291 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X59Y291 FDCE (Prop_HFF_SLICEM_C_Q) 0.048 1.186 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.183 1.369 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X61Y291 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.229 1.381 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X61Y291 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C clock pessimism -0.158 1.223 SLICE_X61Y291 FDCE (Remov_CFF2_SLICEM_C_CLR) 0.005 1.228 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7] ------------------------------------------------------------------- required time -1.228 arrival time 1.369 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.048ns (20.779%) route 0.183ns (79.221%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.381ns Source Clock Delay (SCD): 1.138ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.022ns (routing 0.373ns, distribution 0.649ns) Clock Net Delay (Destination): 1.229ns (routing 0.438ns, distribution 0.791ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.022 1.138 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y291 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X59Y291 FDCE (Prop_HFF_SLICEM_C_Q) 0.048 1.186 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.183 1.369 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X61Y291 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.229 1.381 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X61Y291 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C clock pessimism -0.158 1.223 SLICE_X61Y291 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.228 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8] ------------------------------------------------------------------- required time -1.228 arrival time 1.369 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.048ns (20.779%) route 0.183ns (79.221%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.381ns Source Clock Delay (SCD): 1.138ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.022ns (routing 0.373ns, distribution 0.649ns) Clock Net Delay (Destination): 1.229ns (routing 0.438ns, distribution 0.791ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.022 1.138 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y291 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X59Y291 FDCE (Prop_HFF_SLICEM_C_Q) 0.048 1.186 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.183 1.369 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X61Y291 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.229 1.381 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X61Y291 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism -0.158 1.223 SLICE_X61Y291 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 1.228 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time -1.228 arrival time 1.369 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.143ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.181ns (logic 0.048ns (26.519%) route 0.133ns (73.481%)) Logic Levels: 0 Clock Path Skew: 0.033ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.372ns Source Clock Delay (SCD): 1.138ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.022ns (routing 0.373ns, distribution 0.649ns) Clock Net Delay (Destination): 1.220ns (routing 0.438ns, distribution 0.782ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.022 1.138 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y291 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X59Y291 FDCE (Prop_HFF_SLICEM_C_Q) 0.048 1.186 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.133 1.319 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X60Y291 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.220 1.372 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X60Y291 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C clock pessimism -0.201 1.171 SLICE_X60Y291 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.176 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4] ------------------------------------------------------------------- required time -1.176 arrival time 1.319 ------------------------------------------------------------------- slack 0.143 Slack (MET) : 0.149ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.223ns (logic 0.048ns (21.525%) route 0.175ns (78.475%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.365ns Source Clock Delay (SCD): 1.138ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.022ns (routing 0.373ns, distribution 0.649ns) Clock Net Delay (Destination): 1.213ns (routing 0.438ns, distribution 0.775ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.022 1.138 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y291 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X59Y291 FDCE (Prop_HFF_SLICEM_C_Q) 0.048 1.186 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.175 1.361 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X58Y291 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y115 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.213 1.365 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X58Y291 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C clock pessimism -0.158 1.207 SLICE_X58Y291 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.212 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6] ------------------------------------------------------------------- required time -1.212 arrival time 1.361 ------------------------------------------------------------------- slack 0.149 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_27 To Clock: gtwiz_userclk_rx_srcclk_out[0]_27 Setup : 0 Failing Endpoints, Worst Slack 4.474ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.150ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.474ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 3.868ns (logic 0.307ns (7.937%) route 3.561ns (92.063%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.153ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.664ns = ( 10.981 - 8.317 ) Source Clock Delay (SCD): 2.722ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.789ns, distribution 1.508ns) Clock Net Delay (Destination): 2.288ns (routing 0.708ns, distribution 1.580ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.722 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X27Y177 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X27Y177 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.862 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.693 5.555 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X65Y180 LUT2 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.722 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__24/O net (fo=2, routed) 0.868 6.590 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X62Y177 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.288 10.981 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X62Y177 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.211 11.193 clock uncertainty -0.035 11.157 SLICE_X62Y177 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 11.064 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 11.064 arrival time -6.590 ------------------------------------------------------------------- slack 4.474 Slack (MET) : 4.474ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 3.868ns (logic 0.307ns (7.937%) route 3.561ns (92.063%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.153ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.664ns = ( 10.981 - 8.317 ) Source Clock Delay (SCD): 2.722ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.789ns, distribution 1.508ns) Clock Net Delay (Destination): 2.288ns (routing 0.708ns, distribution 1.580ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.722 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X27Y177 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X27Y177 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.862 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.693 5.555 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X65Y180 LUT2 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.722 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__24/O net (fo=2, routed) 0.868 6.590 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X62Y177 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.288 10.981 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X62Y177 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.211 11.193 clock uncertainty -0.035 11.157 SLICE_X62Y177 FDCE (Recov_EFF2_SLICEM_C_CLR) -0.093 11.064 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 11.064 arrival time -6.590 ------------------------------------------------------------------- slack 4.474 Slack (MET) : 4.684ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 3.666ns (logic 0.311ns (8.483%) route 3.355ns (91.517%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.161ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.672ns = ( 10.989 - 8.317 ) Source Clock Delay (SCD): 2.722ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.789ns, distribution 1.508ns) Clock Net Delay (Destination): 2.296ns (routing 0.708ns, distribution 1.588ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.722 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X27Y177 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X27Y177 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.862 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.697 5.559 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X65Y180 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.171 5.730 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/O net (fo=15, routed) 0.658 6.388 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X69Y179 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.296 10.989 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X69Y179 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/C clock pessimism 0.211 11.201 clock uncertainty -0.035 11.165 SLICE_X69Y179 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.072 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3] ------------------------------------------------------------------- required time 11.072 arrival time -6.388 ------------------------------------------------------------------- slack 4.684 Slack (MET) : 4.684ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 3.666ns (logic 0.311ns (8.483%) route 3.355ns (91.517%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.161ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.672ns = ( 10.989 - 8.317 ) Source Clock Delay (SCD): 2.722ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.789ns, distribution 1.508ns) Clock Net Delay (Destination): 2.296ns (routing 0.708ns, distribution 1.588ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.722 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X27Y177 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X27Y177 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.862 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.697 5.559 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X65Y180 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.171 5.730 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/O net (fo=15, routed) 0.658 6.388 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X69Y179 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.296 10.989 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X69Y179 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/C clock pessimism 0.211 11.201 clock uncertainty -0.035 11.165 SLICE_X69Y179 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.072 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5] ------------------------------------------------------------------- required time 11.072 arrival time -6.388 ------------------------------------------------------------------- slack 4.684 Slack (MET) : 4.684ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 3.666ns (logic 0.311ns (8.483%) route 3.355ns (91.517%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.161ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.672ns = ( 10.989 - 8.317 ) Source Clock Delay (SCD): 2.722ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.789ns, distribution 1.508ns) Clock Net Delay (Destination): 2.296ns (routing 0.708ns, distribution 1.588ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.722 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X27Y177 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X27Y177 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.862 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.697 5.559 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X65Y180 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.171 5.730 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/O net (fo=15, routed) 0.658 6.388 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X69Y179 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.296 10.989 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X69Y179 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/C clock pessimism 0.211 11.201 clock uncertainty -0.035 11.165 SLICE_X69Y179 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 11.072 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6] ------------------------------------------------------------------- required time 11.072 arrival time -6.388 ------------------------------------------------------------------- slack 4.684 Slack (MET) : 4.692ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 3.656ns (logic 0.311ns (8.507%) route 3.345ns (91.493%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.670ns = ( 10.987 - 8.317 ) Source Clock Delay (SCD): 2.722ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.789ns, distribution 1.508ns) Clock Net Delay (Destination): 2.294ns (routing 0.708ns, distribution 1.586ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.722 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X27Y177 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X27Y177 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.862 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.697 5.559 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X65Y180 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.171 5.730 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/O net (fo=15, routed) 0.648 6.378 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X69Y179 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.294 10.987 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X69Y179 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/C clock pessimism 0.211 11.199 clock uncertainty -0.035 11.163 SLICE_X69Y179 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 11.070 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7] ------------------------------------------------------------------- required time 11.070 arrival time -6.378 ------------------------------------------------------------------- slack 4.692 Slack (MET) : 4.810ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 3.553ns (logic 0.311ns (8.753%) route 3.242ns (91.247%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.174ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.685ns = ( 11.002 - 8.317 ) Source Clock Delay (SCD): 2.722ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.789ns, distribution 1.508ns) Clock Net Delay (Destination): 2.309ns (routing 0.708ns, distribution 1.601ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.722 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X27Y177 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X27Y177 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.862 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.697 5.559 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X65Y180 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.171 5.730 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/O net (fo=15, routed) 0.545 6.275 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X68Y179 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.309 11.002 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X68Y179 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/C clock pessimism 0.211 11.214 clock uncertainty -0.035 11.178 SLICE_X68Y179 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.085 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1] ------------------------------------------------------------------- required time 11.085 arrival time -6.275 ------------------------------------------------------------------- slack 4.810 Slack (MET) : 4.810ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 3.553ns (logic 0.311ns (8.753%) route 3.242ns (91.247%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.174ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.685ns = ( 11.002 - 8.317 ) Source Clock Delay (SCD): 2.722ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.789ns, distribution 1.508ns) Clock Net Delay (Destination): 2.309ns (routing 0.708ns, distribution 1.601ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.722 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X27Y177 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X27Y177 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.862 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.697 5.559 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X65Y180 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.171 5.730 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/O net (fo=15, routed) 0.545 6.275 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X68Y179 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.309 11.002 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X68Y179 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/C clock pessimism 0.211 11.214 clock uncertainty -0.035 11.178 SLICE_X68Y179 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 11.085 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2] ------------------------------------------------------------------- required time 11.085 arrival time -6.275 ------------------------------------------------------------------- slack 4.810 Slack (MET) : 4.810ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 3.553ns (logic 0.311ns (8.753%) route 3.242ns (91.247%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.174ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.685ns = ( 11.002 - 8.317 ) Source Clock Delay (SCD): 2.722ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.789ns, distribution 1.508ns) Clock Net Delay (Destination): 2.309ns (routing 0.708ns, distribution 1.601ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.722 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X27Y177 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X27Y177 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.862 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.697 5.559 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X65Y180 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.171 5.730 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/O net (fo=15, routed) 0.545 6.275 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X68Y179 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.309 11.002 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X68Y179 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/C clock pessimism 0.211 11.214 clock uncertainty -0.035 11.178 SLICE_X68Y179 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 11.085 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4] ------------------------------------------------------------------- required time 11.085 arrival time -6.275 ------------------------------------------------------------------- slack 4.810 Slack (MET) : 4.815ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 3.545ns (logic 0.311ns (8.773%) route 3.234ns (91.227%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.171ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.682ns = ( 10.999 - 8.317 ) Source Clock Delay (SCD): 2.722ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.789ns, distribution 1.508ns) Clock Net Delay (Destination): 2.306ns (routing 0.708ns, distribution 1.598ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.722 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X27Y177 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X27Y177 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.862 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.697 5.559 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X65Y180 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.171 5.730 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/O net (fo=15, routed) 0.537 6.267 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X67Y179 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.306 10.999 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X67Y179 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/C clock pessimism 0.211 11.211 clock uncertainty -0.035 11.175 SLICE_X67Y179 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.082 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0] ------------------------------------------------------------------- required time 11.082 arrival time -6.267 ------------------------------------------------------------------- slack 4.815 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.150ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.239ns (logic 0.048ns (20.084%) route 0.191ns (79.916%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.386ns Source Clock Delay (SCD): 1.145ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.029ns (routing 0.376ns, distribution 0.653ns) Clock Net Delay (Destination): 1.234ns (routing 0.440ns, distribution 0.794ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.029 1.145 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y175 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X63Y175 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.193 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.191 1.384 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X66Y175 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.234 1.386 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X66Y175 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C clock pessimism -0.157 1.229 SLICE_X66Y175 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.234 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time -1.234 arrival time 1.384 ------------------------------------------------------------------- slack 0.150 Slack (MET) : 0.150ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.239ns (logic 0.048ns (20.084%) route 0.191ns (79.916%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.386ns Source Clock Delay (SCD): 1.145ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.029ns (routing 0.376ns, distribution 0.653ns) Clock Net Delay (Destination): 1.234ns (routing 0.440ns, distribution 0.794ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.029 1.145 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y175 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X63Y175 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.193 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.191 1.384 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X66Y175 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.234 1.386 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X66Y175 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C clock pessimism -0.157 1.229 SLICE_X66Y175 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.234 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10] ------------------------------------------------------------------- required time -1.234 arrival time 1.384 ------------------------------------------------------------------- slack 0.150 Slack (MET) : 0.150ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.239ns (logic 0.048ns (20.084%) route 0.191ns (79.916%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.386ns Source Clock Delay (SCD): 1.145ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.029ns (routing 0.376ns, distribution 0.653ns) Clock Net Delay (Destination): 1.234ns (routing 0.440ns, distribution 0.794ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.029 1.145 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y175 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X63Y175 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.193 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.191 1.384 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X66Y175 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.234 1.386 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X66Y175 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C clock pessimism -0.157 1.229 SLICE_X66Y175 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 1.234 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12] ------------------------------------------------------------------- required time -1.234 arrival time 1.384 ------------------------------------------------------------------- slack 0.150 Slack (MET) : 0.150ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.239ns (logic 0.048ns (20.084%) route 0.191ns (79.916%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.386ns Source Clock Delay (SCD): 1.145ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.029ns (routing 0.376ns, distribution 0.653ns) Clock Net Delay (Destination): 1.234ns (routing 0.440ns, distribution 0.794ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.029 1.145 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y175 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X63Y175 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.193 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.191 1.384 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X66Y175 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.234 1.386 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X66Y175 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C clock pessimism -0.157 1.229 SLICE_X66Y175 FDCE (Remov_BFF2_SLICEL_C_CLR) 0.005 1.234 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14] ------------------------------------------------------------------- required time -1.234 arrival time 1.384 ------------------------------------------------------------------- slack 0.150 Slack (MET) : 0.150ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.239ns (logic 0.048ns (20.084%) route 0.191ns (79.916%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.386ns Source Clock Delay (SCD): 1.145ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.029ns (routing 0.376ns, distribution 0.653ns) Clock Net Delay (Destination): 1.234ns (routing 0.440ns, distribution 0.794ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.029 1.145 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y175 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X63Y175 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.193 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.191 1.384 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X66Y175 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.234 1.386 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X66Y175 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C clock pessimism -0.157 1.229 SLICE_X66Y175 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 1.234 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time -1.234 arrival time 1.384 ------------------------------------------------------------------- slack 0.150 Slack (MET) : 0.150ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.239ns (logic 0.048ns (20.084%) route 0.191ns (79.916%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.386ns Source Clock Delay (SCD): 1.145ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.029ns (routing 0.376ns, distribution 0.653ns) Clock Net Delay (Destination): 1.234ns (routing 0.440ns, distribution 0.794ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.029 1.145 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y175 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X63Y175 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.193 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.191 1.384 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X66Y175 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.234 1.386 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X66Y175 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C clock pessimism -0.157 1.229 SLICE_X66Y175 FDCE (Remov_CFF2_SLICEL_C_CLR) 0.005 1.234 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4] ------------------------------------------------------------------- required time -1.234 arrival time 1.384 ------------------------------------------------------------------- slack 0.150 Slack (MET) : 0.150ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.239ns (logic 0.048ns (20.084%) route 0.191ns (79.916%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.386ns Source Clock Delay (SCD): 1.145ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.029ns (routing 0.376ns, distribution 0.653ns) Clock Net Delay (Destination): 1.234ns (routing 0.440ns, distribution 0.794ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.029 1.145 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y175 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X63Y175 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.193 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.191 1.384 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X66Y175 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.234 1.386 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X66Y175 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C clock pessimism -0.157 1.229 SLICE_X66Y175 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 1.234 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6] ------------------------------------------------------------------- required time -1.234 arrival time 1.384 ------------------------------------------------------------------- slack 0.150 Slack (MET) : 0.150ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.239ns (logic 0.048ns (20.084%) route 0.191ns (79.916%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.386ns Source Clock Delay (SCD): 1.145ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.029ns (routing 0.376ns, distribution 0.653ns) Clock Net Delay (Destination): 1.234ns (routing 0.440ns, distribution 0.794ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.029 1.145 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y175 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X63Y175 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.193 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.191 1.384 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X66Y175 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.234 1.386 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X66Y175 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C clock pessimism -0.157 1.229 SLICE_X66Y175 FDCE (Remov_DFF2_SLICEL_C_CLR) 0.005 1.234 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8] ------------------------------------------------------------------- required time -1.234 arrival time 1.384 ------------------------------------------------------------------- slack 0.150 Slack (MET) : 0.203ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[61]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.303ns (logic 0.049ns (16.172%) route 0.254ns (83.828%)) Logic Levels: 0 Clock Path Skew: 0.095ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.390ns Source Clock Delay (SCD): 1.137ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.021ns (routing 0.376ns, distribution 0.645ns) Clock Net Delay (Destination): 1.238ns (routing 0.440ns, distribution 0.798ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.021 1.137 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X64Y179 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X64Y179 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.186 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.254 1.440 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X62Y176 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[61]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.238 1.390 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X62Y176 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[61]/C clock pessimism -0.158 1.232 SLICE_X62Y176 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.237 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[61] ------------------------------------------------------------------- required time -1.237 arrival time 1.440 ------------------------------------------------------------------- slack 0.203 Slack (MET) : 0.203ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[62]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.303ns (logic 0.049ns (16.172%) route 0.254ns (83.828%)) Logic Levels: 0 Clock Path Skew: 0.095ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.390ns Source Clock Delay (SCD): 1.137ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.021ns (routing 0.376ns, distribution 0.645ns) Clock Net Delay (Destination): 1.238ns (routing 0.440ns, distribution 0.798ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.021 1.137 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X64Y179 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X64Y179 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.186 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.254 1.440 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X62Y176 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[62]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.238 1.390 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X62Y176 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[62]/C clock pessimism -0.158 1.232 SLICE_X62Y176 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.237 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[62] ------------------------------------------------------------------- required time -1.237 arrival time 1.440 ------------------------------------------------------------------- slack 0.203 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_28 To Clock: gtwiz_userclk_rx_srcclk_out[0]_28 Setup : 0 Failing Endpoints, Worst Slack 6.277ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.141ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 6.277ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[13]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 1.774ns (logic 0.139ns (7.835%) route 1.635ns (92.165%)) Logic Levels: 0 Clock Path Skew: -0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.349ns = ( 10.666 - 8.317 ) Source Clock Delay (SCD): 2.690ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.265ns (routing 0.772ns, distribution 1.493ns) Clock Net Delay (Destination): 1.973ns (routing 0.693ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.265 2.690 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X31Y169 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y169 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 2.829 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.635 4.464 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X26Y158 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[13]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.973 10.666 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X26Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[13]/C clock pessimism 0.203 10.870 clock uncertainty -0.035 10.834 SLICE_X26Y158 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.741 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[13] ------------------------------------------------------------------- required time 10.741 arrival time -4.464 ------------------------------------------------------------------- slack 6.277 Slack (MET) : 6.277ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[14]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 1.774ns (logic 0.139ns (7.835%) route 1.635ns (92.165%)) Logic Levels: 0 Clock Path Skew: -0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.349ns = ( 10.666 - 8.317 ) Source Clock Delay (SCD): 2.690ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.265ns (routing 0.772ns, distribution 1.493ns) Clock Net Delay (Destination): 1.973ns (routing 0.693ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.265 2.690 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X31Y169 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y169 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 2.829 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.635 4.464 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X26Y158 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[14]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.973 10.666 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X26Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[14]/C clock pessimism 0.203 10.870 clock uncertainty -0.035 10.834 SLICE_X26Y158 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.741 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[14] ------------------------------------------------------------------- required time 10.741 arrival time -4.464 ------------------------------------------------------------------- slack 6.277 Slack (MET) : 6.277ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 1.774ns (logic 0.139ns (7.835%) route 1.635ns (92.165%)) Logic Levels: 0 Clock Path Skew: -0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.349ns = ( 10.666 - 8.317 ) Source Clock Delay (SCD): 2.690ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.265ns (routing 0.772ns, distribution 1.493ns) Clock Net Delay (Destination): 1.973ns (routing 0.693ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.265 2.690 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X31Y169 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y169 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 2.829 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.635 4.464 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X26Y158 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.973 10.666 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X26Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[5]/C clock pessimism 0.203 10.870 clock uncertainty -0.035 10.834 SLICE_X26Y158 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.741 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[5] ------------------------------------------------------------------- required time 10.741 arrival time -4.464 ------------------------------------------------------------------- slack 6.277 Slack (MET) : 6.277ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 1.774ns (logic 0.139ns (7.835%) route 1.635ns (92.165%)) Logic Levels: 0 Clock Path Skew: -0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.349ns = ( 10.666 - 8.317 ) Source Clock Delay (SCD): 2.690ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.265ns (routing 0.772ns, distribution 1.493ns) Clock Net Delay (Destination): 1.973ns (routing 0.693ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.265 2.690 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X31Y169 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y169 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 2.829 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.635 4.464 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X26Y158 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.973 10.666 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X26Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[6]/C clock pessimism 0.203 10.870 clock uncertainty -0.035 10.834 SLICE_X26Y158 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.741 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[6] ------------------------------------------------------------------- required time 10.741 arrival time -4.464 ------------------------------------------------------------------- slack 6.277 Slack (MET) : 6.277ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[13]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 1.774ns (logic 0.139ns (7.835%) route 1.635ns (92.165%)) Logic Levels: 0 Clock Path Skew: -0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.349ns = ( 10.666 - 8.317 ) Source Clock Delay (SCD): 2.690ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.265ns (routing 0.772ns, distribution 1.493ns) Clock Net Delay (Destination): 1.973ns (routing 0.693ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.265 2.690 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X31Y169 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y169 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 2.829 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.635 4.464 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X26Y158 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[13]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.973 10.666 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X26Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[13]/C clock pessimism 0.203 10.870 clock uncertainty -0.035 10.834 SLICE_X26Y158 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 10.741 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[13] ------------------------------------------------------------------- required time 10.741 arrival time -4.464 ------------------------------------------------------------------- slack 6.277 Slack (MET) : 6.277ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[14]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 1.774ns (logic 0.139ns (7.835%) route 1.635ns (92.165%)) Logic Levels: 0 Clock Path Skew: -0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.349ns = ( 10.666 - 8.317 ) Source Clock Delay (SCD): 2.690ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.265ns (routing 0.772ns, distribution 1.493ns) Clock Net Delay (Destination): 1.973ns (routing 0.693ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.265 2.690 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X31Y169 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y169 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 2.829 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.635 4.464 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X26Y158 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[14]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.973 10.666 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X26Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[14]/C clock pessimism 0.203 10.870 clock uncertainty -0.035 10.834 SLICE_X26Y158 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 10.741 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[14] ------------------------------------------------------------------- required time 10.741 arrival time -4.464 ------------------------------------------------------------------- slack 6.277 Slack (MET) : 6.277ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 1.774ns (logic 0.139ns (7.835%) route 1.635ns (92.165%)) Logic Levels: 0 Clock Path Skew: -0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.349ns = ( 10.666 - 8.317 ) Source Clock Delay (SCD): 2.690ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.265ns (routing 0.772ns, distribution 1.493ns) Clock Net Delay (Destination): 1.973ns (routing 0.693ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.265 2.690 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X31Y169 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y169 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 2.829 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.635 4.464 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X26Y158 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.973 10.666 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X26Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[5]/C clock pessimism 0.203 10.870 clock uncertainty -0.035 10.834 SLICE_X26Y158 FDCE (Recov_BFF2_SLICEL_C_CLR) -0.093 10.741 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[5] ------------------------------------------------------------------- required time 10.741 arrival time -4.464 ------------------------------------------------------------------- slack 6.277 Slack (MET) : 6.285ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[86]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 1.764ns (logic 0.139ns (7.880%) route 1.625ns (92.120%)) Logic Levels: 0 Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.347ns = ( 10.664 - 8.317 ) Source Clock Delay (SCD): 2.690ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.265ns (routing 0.772ns, distribution 1.493ns) Clock Net Delay (Destination): 1.971ns (routing 0.693ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.265 2.690 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X31Y169 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y169 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 2.829 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.625 4.454 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X26Y158 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[86]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.971 10.664 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X26Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[86]/C clock pessimism 0.203 10.868 clock uncertainty -0.035 10.832 SLICE_X26Y158 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.739 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[86] ------------------------------------------------------------------- required time 10.739 arrival time -4.454 ------------------------------------------------------------------- slack 6.285 Slack (MET) : 6.285ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[93]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 1.764ns (logic 0.139ns (7.880%) route 1.625ns (92.120%)) Logic Levels: 0 Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.347ns = ( 10.664 - 8.317 ) Source Clock Delay (SCD): 2.690ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.265ns (routing 0.772ns, distribution 1.493ns) Clock Net Delay (Destination): 1.971ns (routing 0.693ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.265 2.690 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X31Y169 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y169 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 2.829 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.625 4.454 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X26Y158 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[93]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.971 10.664 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X26Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[93]/C clock pessimism 0.203 10.868 clock uncertainty -0.035 10.832 SLICE_X26Y158 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 10.739 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[93] ------------------------------------------------------------------- required time 10.739 arrival time -4.454 ------------------------------------------------------------------- slack 6.285 Slack (MET) : 6.285ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 1.764ns (logic 0.139ns (7.880%) route 1.625ns (92.120%)) Logic Levels: 0 Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.347ns = ( 10.664 - 8.317 ) Source Clock Delay (SCD): 2.690ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.265ns (routing 0.772ns, distribution 1.493ns) Clock Net Delay (Destination): 1.971ns (routing 0.693ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.265 2.690 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X31Y169 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y169 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 2.829 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.625 4.454 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X26Y158 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.971 10.664 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X26Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[6]/C clock pessimism 0.203 10.868 clock uncertainty -0.035 10.832 SLICE_X26Y158 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 10.739 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[6] ------------------------------------------------------------------- required time 10.739 arrival time -4.454 ------------------------------------------------------------------- slack 6.285 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.224ns Source Clock Delay (SCD): 1.002ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.886ns (routing 0.368ns, distribution 0.518ns) Clock Net Delay (Destination): 1.072ns (routing 0.432ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.886 1.002 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X32Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X32Y161 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.051 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.175 1.226 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X30Y161 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.072 1.224 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X30Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C clock pessimism -0.144 1.080 SLICE_X30Y161 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.085 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10] ------------------------------------------------------------------- required time -1.085 arrival time 1.226 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.224ns Source Clock Delay (SCD): 1.002ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.886ns (routing 0.368ns, distribution 0.518ns) Clock Net Delay (Destination): 1.072ns (routing 0.432ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.886 1.002 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X32Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X32Y161 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.051 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.175 1.226 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X30Y161 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.072 1.224 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X30Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C clock pessimism -0.144 1.080 SLICE_X30Y161 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.085 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11] ------------------------------------------------------------------- required time -1.085 arrival time 1.226 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.224ns Source Clock Delay (SCD): 1.002ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.886ns (routing 0.368ns, distribution 0.518ns) Clock Net Delay (Destination): 1.072ns (routing 0.432ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.886 1.002 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X32Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X32Y161 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.051 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.175 1.226 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X30Y161 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.072 1.224 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X30Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C clock pessimism -0.144 1.080 SLICE_X30Y161 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.085 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4] ------------------------------------------------------------------- required time -1.085 arrival time 1.226 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.224ns Source Clock Delay (SCD): 1.002ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.886ns (routing 0.368ns, distribution 0.518ns) Clock Net Delay (Destination): 1.072ns (routing 0.432ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.886 1.002 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X32Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X32Y161 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.051 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.175 1.226 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X30Y161 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.072 1.224 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X30Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C clock pessimism -0.144 1.080 SLICE_X30Y161 FDCE (Remov_FFF2_SLICEL_C_CLR) 0.005 1.085 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5] ------------------------------------------------------------------- required time -1.085 arrival time 1.226 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.224ns Source Clock Delay (SCD): 1.002ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.886ns (routing 0.368ns, distribution 0.518ns) Clock Net Delay (Destination): 1.072ns (routing 0.432ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.886 1.002 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X32Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X32Y161 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.051 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.175 1.226 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X30Y161 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.072 1.224 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X30Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C clock pessimism -0.144 1.080 SLICE_X30Y161 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 1.085 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6] ------------------------------------------------------------------- required time -1.085 arrival time 1.226 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.224ns Source Clock Delay (SCD): 1.002ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.886ns (routing 0.368ns, distribution 0.518ns) Clock Net Delay (Destination): 1.072ns (routing 0.432ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.886 1.002 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X32Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X32Y161 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.051 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.175 1.226 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X30Y161 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.072 1.224 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X30Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C clock pessimism -0.144 1.080 SLICE_X30Y161 FDCE (Remov_GFF2_SLICEL_C_CLR) 0.005 1.085 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8] ------------------------------------------------------------------- required time -1.085 arrival time 1.226 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.224ns Source Clock Delay (SCD): 1.002ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.886ns (routing 0.368ns, distribution 0.518ns) Clock Net Delay (Destination): 1.072ns (routing 0.432ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.886 1.002 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X32Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X32Y161 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.051 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.175 1.226 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X30Y161 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.072 1.224 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X30Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism -0.144 1.080 SLICE_X30Y161 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.085 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time -1.085 arrival time 1.226 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.144ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.230ns (logic 0.049ns (21.304%) route 0.181ns (78.696%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.227ns Source Clock Delay (SCD): 1.002ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.886ns (routing 0.368ns, distribution 0.518ns) Clock Net Delay (Destination): 1.075ns (routing 0.432ns, distribution 0.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.886 1.002 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X32Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X32Y161 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.051 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.181 1.232 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X30Y161 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.075 1.227 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X30Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism -0.144 1.083 SLICE_X30Y161 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.088 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time -1.088 arrival time 1.232 ------------------------------------------------------------------- slack 0.144 Slack (MET) : 0.164ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.258ns (logic 0.049ns (18.992%) route 0.209ns (81.008%)) Logic Levels: 0 Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.235ns Source Clock Delay (SCD): 1.002ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.886ns (routing 0.368ns, distribution 0.518ns) Clock Net Delay (Destination): 1.083ns (routing 0.432ns, distribution 0.651ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.886 1.002 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X32Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X32Y161 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.051 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.209 1.260 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X29Y162 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.083 1.235 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X29Y162 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C clock pessimism -0.144 1.091 SLICE_X29Y162 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.096 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15] ------------------------------------------------------------------- required time -1.096 arrival time 1.260 ------------------------------------------------------------------- slack 0.164 Slack (MET) : 0.165ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.261ns (logic 0.049ns (18.774%) route 0.212ns (81.226%)) Logic Levels: 0 Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.237ns Source Clock Delay (SCD): 1.002ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.886ns (routing 0.368ns, distribution 0.518ns) Clock Net Delay (Destination): 1.085ns (routing 0.432ns, distribution 0.653ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.886 1.002 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X32Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X32Y161 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.051 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.212 1.263 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X29Y162 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.085 1.237 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X29Y162 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C clock pessimism -0.144 1.093 SLICE_X29Y162 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.098 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13] ------------------------------------------------------------------- required time -1.098 arrival time 1.263 ------------------------------------------------------------------- slack 0.165 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_29 To Clock: gtwiz_userclk_rx_srcclk_out[0]_29 Setup : 0 Failing Endpoints, Worst Slack 3.470ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.163ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.470ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 4.751ns (logic 0.286ns (6.020%) route 4.465ns (93.980%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.644ns = ( 10.961 - 8.317 ) Source Clock Delay (SCD): 2.820ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.395ns (routing 0.775ns, distribution 1.620ns) Clock Net Delay (Destination): 2.268ns (routing 0.697ns, distribution 1.571ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.395 2.820 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X14Y174 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X14Y174 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.959 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.741 6.700 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X69Y175 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.147 6.847 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/O net (fo=15, routed) 0.724 7.571 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X66Y178 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.268 10.961 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X66Y178 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/C clock pessimism 0.208 11.170 clock uncertainty -0.035 11.134 SLICE_X66Y178 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 11.041 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3] ------------------------------------------------------------------- required time 11.041 arrival time -7.571 ------------------------------------------------------------------- slack 3.470 Slack (MET) : 3.470ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 4.751ns (logic 0.286ns (6.020%) route 4.465ns (93.980%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.644ns = ( 10.961 - 8.317 ) Source Clock Delay (SCD): 2.820ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.395ns (routing 0.775ns, distribution 1.620ns) Clock Net Delay (Destination): 2.268ns (routing 0.697ns, distribution 1.571ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.395 2.820 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X14Y174 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X14Y174 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.959 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.741 6.700 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X69Y175 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.147 6.847 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/O net (fo=15, routed) 0.724 7.571 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X66Y178 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.268 10.961 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X66Y178 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/C clock pessimism 0.208 11.170 clock uncertainty -0.035 11.134 SLICE_X66Y178 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 11.041 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0] ------------------------------------------------------------------- required time 11.041 arrival time -7.571 ------------------------------------------------------------------- slack 3.470 Slack (MET) : 3.529ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 4.702ns (logic 0.286ns (6.083%) route 4.416ns (93.917%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.654ns = ( 10.971 - 8.317 ) Source Clock Delay (SCD): 2.820ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.395ns (routing 0.775ns, distribution 1.620ns) Clock Net Delay (Destination): 2.278ns (routing 0.697ns, distribution 1.581ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.395 2.820 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X14Y174 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X14Y174 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.959 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.741 6.700 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X69Y175 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.147 6.847 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/O net (fo=15, routed) 0.675 7.522 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X66Y177 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.278 10.971 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X66Y177 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C clock pessimism 0.208 11.180 clock uncertainty -0.035 11.144 SLICE_X66Y177 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.051 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3] ------------------------------------------------------------------- required time 11.051 arrival time -7.522 ------------------------------------------------------------------- slack 3.529 Slack (MET) : 3.529ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 4.702ns (logic 0.286ns (6.083%) route 4.416ns (93.917%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.654ns = ( 10.971 - 8.317 ) Source Clock Delay (SCD): 2.820ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.395ns (routing 0.775ns, distribution 1.620ns) Clock Net Delay (Destination): 2.278ns (routing 0.697ns, distribution 1.581ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.395 2.820 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X14Y174 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X14Y174 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.959 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.741 6.700 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X69Y175 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.147 6.847 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/O net (fo=15, routed) 0.675 7.522 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X66Y177 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.278 10.971 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X66Y177 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/C clock pessimism 0.208 11.180 clock uncertainty -0.035 11.144 SLICE_X66Y177 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.051 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4] ------------------------------------------------------------------- required time 11.051 arrival time -7.522 ------------------------------------------------------------------- slack 3.529 Slack (MET) : 3.529ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 4.702ns (logic 0.286ns (6.083%) route 4.416ns (93.917%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.654ns = ( 10.971 - 8.317 ) Source Clock Delay (SCD): 2.820ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.395ns (routing 0.775ns, distribution 1.620ns) Clock Net Delay (Destination): 2.278ns (routing 0.697ns, distribution 1.581ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.395 2.820 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X14Y174 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X14Y174 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.959 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.741 6.700 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X69Y175 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.147 6.847 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/O net (fo=15, routed) 0.675 7.522 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X66Y177 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.278 10.971 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X66Y177 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/C clock pessimism 0.208 11.180 clock uncertainty -0.035 11.144 SLICE_X66Y177 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 11.051 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5] ------------------------------------------------------------------- required time 11.051 arrival time -7.522 ------------------------------------------------------------------- slack 3.529 Slack (MET) : 3.529ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 4.702ns (logic 0.286ns (6.083%) route 4.416ns (93.917%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.654ns = ( 10.971 - 8.317 ) Source Clock Delay (SCD): 2.820ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.395ns (routing 0.775ns, distribution 1.620ns) Clock Net Delay (Destination): 2.278ns (routing 0.697ns, distribution 1.581ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.395 2.820 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X14Y174 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X14Y174 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.959 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.741 6.700 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X69Y175 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.147 6.847 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/O net (fo=15, routed) 0.675 7.522 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X66Y177 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.278 10.971 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X66Y177 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/C clock pessimism 0.208 11.180 clock uncertainty -0.035 11.144 SLICE_X66Y177 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 11.051 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6] ------------------------------------------------------------------- required time 11.051 arrival time -7.522 ------------------------------------------------------------------- slack 3.529 Slack (MET) : 3.537ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 4.692ns (logic 0.286ns (6.095%) route 4.406ns (93.905%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.040ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.652ns = ( 10.969 - 8.317 ) Source Clock Delay (SCD): 2.820ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.395ns (routing 0.775ns, distribution 1.620ns) Clock Net Delay (Destination): 2.276ns (routing 0.697ns, distribution 1.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.395 2.820 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X14Y174 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X14Y174 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.959 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.741 6.700 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X69Y175 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.147 6.847 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/O net (fo=15, routed) 0.665 7.512 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X66Y177 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.276 10.969 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X66Y177 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/C clock pessimism 0.208 11.178 clock uncertainty -0.035 11.142 SLICE_X66Y177 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 11.049 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1] ------------------------------------------------------------------- required time 11.049 arrival time -7.512 ------------------------------------------------------------------- slack 3.537 Slack (MET) : 3.537ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 4.692ns (logic 0.286ns (6.095%) route 4.406ns (93.905%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.040ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.652ns = ( 10.969 - 8.317 ) Source Clock Delay (SCD): 2.820ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.395ns (routing 0.775ns, distribution 1.620ns) Clock Net Delay (Destination): 2.276ns (routing 0.697ns, distribution 1.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.395 2.820 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X14Y174 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X14Y174 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.959 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.741 6.700 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X69Y175 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.147 6.847 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/O net (fo=15, routed) 0.665 7.512 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X66Y177 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.276 10.969 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X66Y177 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/C clock pessimism 0.208 11.178 clock uncertainty -0.035 11.142 SLICE_X66Y177 FDCE (Recov_GFF2_SLICEL_C_CLR) -0.093 11.049 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2] ------------------------------------------------------------------- required time 11.049 arrival time -7.512 ------------------------------------------------------------------- slack 3.537 Slack (MET) : 3.537ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 4.692ns (logic 0.286ns (6.095%) route 4.406ns (93.905%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.040ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.652ns = ( 10.969 - 8.317 ) Source Clock Delay (SCD): 2.820ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.395ns (routing 0.775ns, distribution 1.620ns) Clock Net Delay (Destination): 2.276ns (routing 0.697ns, distribution 1.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.395 2.820 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X14Y174 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X14Y174 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.959 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.741 6.700 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X69Y175 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.147 6.847 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/O net (fo=15, routed) 0.665 7.512 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X66Y177 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.276 10.969 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X66Y177 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/C clock pessimism 0.208 11.178 clock uncertainty -0.035 11.142 SLICE_X66Y177 FDCE (Recov_FFF_SLICEL_C_CLR) -0.093 11.049 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7] ------------------------------------------------------------------- required time 11.049 arrival time -7.512 ------------------------------------------------------------------- slack 3.537 Slack (MET) : 3.623ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 4.624ns (logic 0.286ns (6.185%) route 4.338ns (93.815%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.058ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.670ns = ( 10.987 - 8.317 ) Source Clock Delay (SCD): 2.820ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.395ns (routing 0.775ns, distribution 1.620ns) Clock Net Delay (Destination): 2.294ns (routing 0.697ns, distribution 1.597ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.395 2.820 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X14Y174 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X14Y174 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.959 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.741 6.700 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X69Y175 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.147 6.847 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/O net (fo=15, routed) 0.597 7.444 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X67Y174 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.294 10.987 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X67Y174 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]/C clock pessimism 0.208 11.196 clock uncertainty -0.035 11.160 SLICE_X67Y174 FDCE (Recov_AFF2_SLICEM_C_CLR) -0.093 11.067 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5] ------------------------------------------------------------------- required time 11.067 arrival time -7.444 ------------------------------------------------------------------- slack 3.623 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.163ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.048ns (18.750%) route 0.208ns (81.250%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.386ns Source Clock Delay (SCD): 1.142ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.026ns (routing 0.369ns, distribution 0.657ns) Clock Net Delay (Destination): 1.234ns (routing 0.431ns, distribution 0.803ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.026 1.142 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X66Y168 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X66Y168 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.190 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.208 1.398 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X68Y169 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.234 1.386 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/CLK SLICE_X68Y169 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_reg/C clock pessimism -0.156 1.230 SLICE_X68Y169 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.235 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_reg ------------------------------------------------------------------- required time -1.235 arrival time 1.398 ------------------------------------------------------------------- slack 0.163 Slack (MET) : 0.166ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.262ns (logic 0.048ns (18.321%) route 0.214ns (81.679%)) Logic Levels: 0 Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.389ns Source Clock Delay (SCD): 1.142ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.026ns (routing 0.369ns, distribution 0.657ns) Clock Net Delay (Destination): 1.237ns (routing 0.431ns, distribution 0.806ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.026 1.142 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X66Y168 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X66Y168 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.190 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.214 1.404 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X68Y169 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.237 1.389 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/CLK SLICE_X68Y169 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C clock pessimism -0.156 1.233 SLICE_X68Y169 FDCE (Remov_DFF2_SLICEL_C_CLR) 0.005 1.238 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg ------------------------------------------------------------------- required time -1.238 arrival time 1.404 ------------------------------------------------------------------- slack 0.166 Slack (MET) : 0.171ns (arrival time - required time) Source: SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[48]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.254ns (logic 0.048ns (18.898%) route 0.206ns (81.102%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.361ns Source Clock Delay (SCD): 1.126ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.010ns (routing 0.369ns, distribution 0.641ns) Clock Net Delay (Destination): 1.209ns (routing 0.431ns, distribution 0.778ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.010 1.126 SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y155 FDPE r SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y155 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.174 f SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.206 1.380 SFP_GEN[27].ngCCM_gbt/sync_m_reg[3][0] SLICE_X70Y160 FDCE f SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[48]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.209 1.361 SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X70Y160 FDCE r SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[48]/C clock pessimism -0.157 1.204 SLICE_X70Y160 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.209 SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[48] ------------------------------------------------------------------- required time -1.209 arrival time 1.380 ------------------------------------------------------------------- slack 0.171 Slack (MET) : 0.171ns (arrival time - required time) Source: SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[50]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.254ns (logic 0.048ns (18.898%) route 0.206ns (81.102%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.361ns Source Clock Delay (SCD): 1.126ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.010ns (routing 0.369ns, distribution 0.641ns) Clock Net Delay (Destination): 1.209ns (routing 0.431ns, distribution 0.778ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.010 1.126 SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y155 FDPE r SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y155 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.174 f SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.206 1.380 SFP_GEN[27].ngCCM_gbt/sync_m_reg[3][0] SLICE_X70Y160 FDCE f SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[50]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.209 1.361 SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X70Y160 FDCE r SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[50]/C clock pessimism -0.157 1.204 SLICE_X70Y160 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.209 SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[50] ------------------------------------------------------------------- required time -1.209 arrival time 1.380 ------------------------------------------------------------------- slack 0.171 Slack (MET) : 0.177ns (arrival time - required time) Source: SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[72]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.267ns (logic 0.048ns (17.978%) route 0.219ns (82.022%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.368ns Source Clock Delay (SCD): 1.126ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.010ns (routing 0.369ns, distribution 0.641ns) Clock Net Delay (Destination): 1.216ns (routing 0.431ns, distribution 0.785ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.010 1.126 SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y155 FDPE r SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y155 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.174 f SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.219 1.393 SFP_GEN[27].ngCCM_gbt/sync_m_reg[3][0] SLICE_X70Y159 FDCE f SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[72]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.216 1.368 SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X70Y159 FDCE r SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[72]/C clock pessimism -0.157 1.211 SLICE_X70Y159 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.216 SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[72] ------------------------------------------------------------------- required time -1.216 arrival time 1.393 ------------------------------------------------------------------- slack 0.177 Slack (MET) : 0.177ns (arrival time - required time) Source: SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[74]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.267ns (logic 0.048ns (17.978%) route 0.219ns (82.022%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.368ns Source Clock Delay (SCD): 1.126ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.010ns (routing 0.369ns, distribution 0.641ns) Clock Net Delay (Destination): 1.216ns (routing 0.431ns, distribution 0.785ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.010 1.126 SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y155 FDPE r SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y155 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.174 f SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.219 1.393 SFP_GEN[27].ngCCM_gbt/sync_m_reg[3][0] SLICE_X70Y159 FDCE f SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[74]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.216 1.368 SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X70Y159 FDCE r SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[74]/C clock pessimism -0.157 1.211 SLICE_X70Y159 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.216 SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[74] ------------------------------------------------------------------- required time -1.216 arrival time 1.393 ------------------------------------------------------------------- slack 0.177 Slack (MET) : 0.198ns (arrival time - required time) Source: SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[56]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.282ns (logic 0.048ns (17.021%) route 0.234ns (82.979%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.362ns Source Clock Delay (SCD): 1.126ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.010ns (routing 0.369ns, distribution 0.641ns) Clock Net Delay (Destination): 1.210ns (routing 0.431ns, distribution 0.779ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.010 1.126 SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y155 FDPE r SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y155 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.174 f SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.234 1.408 SFP_GEN[27].ngCCM_gbt/sync_m_reg[3][0] SLICE_X68Y156 FDCE f SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[56]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.210 1.362 SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X68Y156 FDCE r SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[56]/C clock pessimism -0.157 1.205 SLICE_X68Y156 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 1.210 SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[56] ------------------------------------------------------------------- required time -1.210 arrival time 1.408 ------------------------------------------------------------------- slack 0.198 Slack (MET) : 0.198ns (arrival time - required time) Source: SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[58]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.282ns (logic 0.048ns (17.021%) route 0.234ns (82.979%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.362ns Source Clock Delay (SCD): 1.126ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.010ns (routing 0.369ns, distribution 0.641ns) Clock Net Delay (Destination): 1.210ns (routing 0.431ns, distribution 0.779ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.010 1.126 SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y155 FDPE r SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y155 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.174 f SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.234 1.408 SFP_GEN[27].ngCCM_gbt/sync_m_reg[3][0] SLICE_X68Y156 FDCE f SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[58]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.210 1.362 SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X68Y156 FDCE r SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[58]/C clock pessimism -0.157 1.205 SLICE_X68Y156 FDCE (Remov_DFF2_SLICEL_C_CLR) 0.005 1.210 SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[58] ------------------------------------------------------------------- required time -1.210 arrival time 1.408 ------------------------------------------------------------------- slack 0.198 Slack (MET) : 0.198ns (arrival time - required time) Source: SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.282ns (logic 0.048ns (17.021%) route 0.234ns (82.979%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.362ns Source Clock Delay (SCD): 1.126ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.010ns (routing 0.369ns, distribution 0.641ns) Clock Net Delay (Destination): 1.210ns (routing 0.431ns, distribution 0.779ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.010 1.126 SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y155 FDPE r SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y155 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.174 f SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.234 1.408 SFP_GEN[27].ngCCM_gbt/sync_m_reg[3][0] SLICE_X68Y156 FDCE f SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.210 1.362 SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X68Y156 FDCE r SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[81]/C clock pessimism -0.157 1.205 SLICE_X68Y156 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.210 SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[81] ------------------------------------------------------------------- required time -1.210 arrival time 1.408 ------------------------------------------------------------------- slack 0.198 Slack (MET) : 0.198ns (arrival time - required time) Source: SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.282ns (logic 0.048ns (17.021%) route 0.234ns (82.979%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.362ns Source Clock Delay (SCD): 1.126ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.010ns (routing 0.369ns, distribution 0.641ns) Clock Net Delay (Destination): 1.210ns (routing 0.431ns, distribution 0.779ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.010 1.126 SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y155 FDPE r SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y155 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.174 f SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.234 1.408 SFP_GEN[27].ngCCM_gbt/sync_m_reg[3][0] SLICE_X68Y156 FDCE f SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.210 1.362 SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X68Y156 FDCE r SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[83]/C clock pessimism -0.157 1.205 SLICE_X68Y156 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.210 SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[83] ------------------------------------------------------------------- required time -1.210 arrival time 1.408 ------------------------------------------------------------------- slack 0.198 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_3 To Clock: gtwiz_userclk_rx_srcclk_out[0]_3 Setup : 0 Failing Endpoints, Worst Slack 3.227ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.130ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.227ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 4.265ns (logic 0.289ns (6.776%) route 3.976ns (93.224%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.697ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.015ns = ( 11.332 - 8.317 ) Source Clock Delay (SCD): 4.002ns Clock Pessimism Removal (CPR): 0.290ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.527ns (routing 1.459ns, distribution 2.068ns) Clock Net Delay (Destination): 2.617ns (routing 1.332ns, distribution 1.285ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.527 4.002 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y82 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y82 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.141 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.455 7.596 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X85Y88 LUT2 (Prop_B6LUT_SLICEM_I0_O) 0.150 7.746 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__0/O net (fo=2, routed) 0.521 8.267 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X82Y88 FDCE f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.617 11.332 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X82Y88 FDCE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.290 11.622 clock uncertainty -0.035 11.587 SLICE_X82Y88 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 11.494 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 11.494 arrival time -8.267 ------------------------------------------------------------------- slack 3.227 Slack (MET) : 3.227ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 4.265ns (logic 0.289ns (6.776%) route 3.976ns (93.224%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.697ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.015ns = ( 11.332 - 8.317 ) Source Clock Delay (SCD): 4.002ns Clock Pessimism Removal (CPR): 0.290ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.527ns (routing 1.459ns, distribution 2.068ns) Clock Net Delay (Destination): 2.617ns (routing 1.332ns, distribution 1.285ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.527 4.002 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y82 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y82 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.141 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.455 7.596 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X85Y88 LUT2 (Prop_B6LUT_SLICEM_I0_O) 0.150 7.746 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__0/O net (fo=2, routed) 0.521 8.267 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X82Y88 FDCE f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.617 11.332 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X82Y88 FDCE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.290 11.622 clock uncertainty -0.035 11.587 SLICE_X82Y88 FDCE (Recov_EFF2_SLICEM_C_CLR) -0.093 11.494 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 11.494 arrival time -8.267 ------------------------------------------------------------------- slack 3.227 Slack (MET) : 3.907ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 3.591ns (logic 0.311ns (8.661%) route 3.280ns (91.339%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.691ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.021ns = ( 11.338 - 8.317 ) Source Clock Delay (SCD): 4.002ns Clock Pessimism Removal (CPR): 0.290ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.527ns (routing 1.459ns, distribution 2.068ns) Clock Net Delay (Destination): 2.623ns (routing 1.332ns, distribution 1.291ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.527 4.002 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y82 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y82 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.141 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.141 6.282 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y84 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.172 6.454 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/O net (fo=15, routed) 1.139 7.593 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X83Y88 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.623 11.338 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] SLICE_X83Y88 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/C clock pessimism 0.290 11.628 clock uncertainty -0.035 11.593 SLICE_X83Y88 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.500 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6] ------------------------------------------------------------------- required time 11.500 arrival time -7.593 ------------------------------------------------------------------- slack 3.907 Slack (MET) : 3.907ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 3.591ns (logic 0.311ns (8.661%) route 3.280ns (91.339%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.691ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.021ns = ( 11.338 - 8.317 ) Source Clock Delay (SCD): 4.002ns Clock Pessimism Removal (CPR): 0.290ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.527ns (routing 1.459ns, distribution 2.068ns) Clock Net Delay (Destination): 2.623ns (routing 1.332ns, distribution 1.291ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.527 4.002 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y82 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y82 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.141 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.141 6.282 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y84 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.172 6.454 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/O net (fo=15, routed) 1.139 7.593 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X83Y88 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.623 11.338 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] SLICE_X83Y88 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/C clock pessimism 0.290 11.628 clock uncertainty -0.035 11.593 SLICE_X83Y88 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 11.500 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7] ------------------------------------------------------------------- required time 11.500 arrival time -7.593 ------------------------------------------------------------------- slack 3.907 Slack (MET) : 3.912ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 3.584ns (logic 0.311ns (8.677%) route 3.273ns (91.323%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.693ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.019ns = ( 11.336 - 8.317 ) Source Clock Delay (SCD): 4.002ns Clock Pessimism Removal (CPR): 0.290ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.527ns (routing 1.459ns, distribution 2.068ns) Clock Net Delay (Destination): 2.621ns (routing 1.332ns, distribution 1.289ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.527 4.002 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y82 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y82 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.141 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.141 6.282 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y84 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.172 6.454 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/O net (fo=15, routed) 1.132 7.586 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X83Y88 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.621 11.336 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] SLICE_X83Y88 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/C clock pessimism 0.290 11.626 clock uncertainty -0.035 11.591 SLICE_X83Y88 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.498 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5] ------------------------------------------------------------------- required time 11.498 arrival time -7.586 ------------------------------------------------------------------- slack 3.912 Slack (MET) : 3.912ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 3.584ns (logic 0.311ns (8.677%) route 3.273ns (91.323%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.693ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.019ns = ( 11.336 - 8.317 ) Source Clock Delay (SCD): 4.002ns Clock Pessimism Removal (CPR): 0.290ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.527ns (routing 1.459ns, distribution 2.068ns) Clock Net Delay (Destination): 2.621ns (routing 1.332ns, distribution 1.289ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.527 4.002 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y82 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y82 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.141 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.141 6.282 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y84 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.172 6.454 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/O net (fo=15, routed) 1.132 7.586 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X83Y88 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.621 11.336 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] SLICE_X83Y88 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/C clock pessimism 0.290 11.626 clock uncertainty -0.035 11.591 SLICE_X83Y88 FDCE (Recov_HFF2_SLICEM_C_CLR) -0.093 11.498 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] ------------------------------------------------------------------- required time 11.498 arrival time -7.586 ------------------------------------------------------------------- slack 3.912 Slack (MET) : 3.987ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 3.519ns (logic 0.311ns (8.838%) route 3.208ns (91.162%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.683ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.029ns = ( 11.346 - 8.317 ) Source Clock Delay (SCD): 4.002ns Clock Pessimism Removal (CPR): 0.290ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.527ns (routing 1.459ns, distribution 2.068ns) Clock Net Delay (Destination): 2.631ns (routing 1.332ns, distribution 1.299ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.527 4.002 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y82 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y82 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.141 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.141 6.282 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y84 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.172 6.454 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/O net (fo=15, routed) 1.067 7.521 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X81Y88 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.631 11.346 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] SLICE_X81Y88 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/C clock pessimism 0.290 11.636 clock uncertainty -0.035 11.601 SLICE_X81Y88 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.508 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1] ------------------------------------------------------------------- required time 11.508 arrival time -7.521 ------------------------------------------------------------------- slack 3.987 Slack (MET) : 3.987ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 3.519ns (logic 0.311ns (8.838%) route 3.208ns (91.162%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.683ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.029ns = ( 11.346 - 8.317 ) Source Clock Delay (SCD): 4.002ns Clock Pessimism Removal (CPR): 0.290ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.527ns (routing 1.459ns, distribution 2.068ns) Clock Net Delay (Destination): 2.631ns (routing 1.332ns, distribution 1.299ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.527 4.002 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y82 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y82 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.141 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.141 6.282 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y84 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.172 6.454 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/O net (fo=15, routed) 1.067 7.521 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X81Y88 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.631 11.346 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] SLICE_X81Y88 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/C clock pessimism 0.290 11.636 clock uncertainty -0.035 11.601 SLICE_X81Y88 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 11.508 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2] ------------------------------------------------------------------- required time 11.508 arrival time -7.521 ------------------------------------------------------------------- slack 3.987 Slack (MET) : 3.987ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 3.519ns (logic 0.311ns (8.838%) route 3.208ns (91.162%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.683ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.029ns = ( 11.346 - 8.317 ) Source Clock Delay (SCD): 4.002ns Clock Pessimism Removal (CPR): 0.290ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.527ns (routing 1.459ns, distribution 2.068ns) Clock Net Delay (Destination): 2.631ns (routing 1.332ns, distribution 1.299ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.527 4.002 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y82 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y82 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.141 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.141 6.282 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y84 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.172 6.454 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/O net (fo=15, routed) 1.067 7.521 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X81Y88 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.631 11.346 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] SLICE_X81Y88 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/C clock pessimism 0.290 11.636 clock uncertainty -0.035 11.601 SLICE_X81Y88 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.508 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4] ------------------------------------------------------------------- required time 11.508 arrival time -7.521 ------------------------------------------------------------------- slack 3.987 Slack (MET) : 3.995ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 3.509ns (logic 0.311ns (8.863%) route 3.198ns (91.137%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.685ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.027ns = ( 11.344 - 8.317 ) Source Clock Delay (SCD): 4.002ns Clock Pessimism Removal (CPR): 0.290ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.527ns (routing 1.459ns, distribution 2.068ns) Clock Net Delay (Destination): 2.629ns (routing 1.332ns, distribution 1.297ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.527 4.002 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y82 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y82 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.141 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.141 6.282 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y84 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.172 6.454 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/O net (fo=15, routed) 1.057 7.511 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X81Y88 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.629 11.344 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] SLICE_X81Y88 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C clock pessimism 0.290 11.634 clock uncertainty -0.035 11.599 SLICE_X81Y88 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.506 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3] ------------------------------------------------------------------- required time 11.506 arrival time -7.511 ------------------------------------------------------------------- slack 3.995 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.130ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.228ns (logic 0.049ns (21.491%) route 0.179ns (78.509%)) Logic Levels: 0 Clock Path Skew: 0.093ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.538ns Source Clock Delay (SCD): 1.277ns Clock Pessimism Removal (CPR): 0.168ns Clock Net Delay (Source): 1.159ns (routing 0.610ns, distribution 0.549ns) Clock Net Delay (Destination): 1.373ns (routing 0.686ns, distribution 0.687ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.159 1.277 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X79Y77 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X79Y77 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.326 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.179 1.505 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X77Y76 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.373 1.538 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/CLK SLICE_X77Y76 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/READY_O_reg/C clock pessimism -0.168 1.370 SLICE_X77Y76 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.375 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/READY_O_reg ------------------------------------------------------------------- required time -1.375 arrival time 1.505 ------------------------------------------------------------------- slack 0.130 Slack (MET) : 0.153ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.066ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.495ns Source Clock Delay (SCD): 1.261ns Clock Pessimism Removal (CPR): 0.168ns Clock Net Delay (Source): 1.143ns (routing 0.610ns, distribution 0.533ns) Clock Net Delay (Destination): 1.330ns (routing 0.686ns, distribution 0.644ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.143 1.261 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X81Y83 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y83 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.310 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.175 1.485 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X82Y83 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.330 1.495 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X82Y83 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.168 1.327 SLICE_X82Y83 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.332 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -1.332 arrival time 1.485 ------------------------------------------------------------------- slack 0.153 Slack (MET) : 0.180ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[29]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.289ns (logic 0.049ns (16.955%) route 0.240ns (83.045%)) Logic Levels: 0 Clock Path Skew: 0.104ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.533ns Source Clock Delay (SCD): 1.261ns Clock Pessimism Removal (CPR): 0.168ns Clock Net Delay (Source): 1.143ns (routing 0.610ns, distribution 0.533ns) Clock Net Delay (Destination): 1.368ns (routing 0.686ns, distribution 0.682ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.143 1.261 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X81Y83 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y83 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.310 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.240 1.550 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X79Y78 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[29]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.368 1.533 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X79Y78 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[29]/C clock pessimism -0.168 1.365 SLICE_X79Y78 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.370 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[29] ------------------------------------------------------------------- required time -1.370 arrival time 1.550 ------------------------------------------------------------------- slack 0.180 Slack (MET) : 0.180ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[30]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.289ns (logic 0.049ns (16.955%) route 0.240ns (83.045%)) Logic Levels: 0 Clock Path Skew: 0.104ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.533ns Source Clock Delay (SCD): 1.261ns Clock Pessimism Removal (CPR): 0.168ns Clock Net Delay (Source): 1.143ns (routing 0.610ns, distribution 0.533ns) Clock Net Delay (Destination): 1.368ns (routing 0.686ns, distribution 0.682ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.143 1.261 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X81Y83 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y83 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.310 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.240 1.550 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X79Y78 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[30]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.368 1.533 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X79Y78 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[30]/C clock pessimism -0.168 1.365 SLICE_X79Y78 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.370 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[30] ------------------------------------------------------------------- required time -1.370 arrival time 1.550 ------------------------------------------------------------------- slack 0.180 Slack (MET) : 0.180ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[36]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.289ns (logic 0.049ns (16.955%) route 0.240ns (83.045%)) Logic Levels: 0 Clock Path Skew: 0.104ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.533ns Source Clock Delay (SCD): 1.261ns Clock Pessimism Removal (CPR): 0.168ns Clock Net Delay (Source): 1.143ns (routing 0.610ns, distribution 0.533ns) Clock Net Delay (Destination): 1.368ns (routing 0.686ns, distribution 0.682ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.143 1.261 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X81Y83 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y83 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.310 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.240 1.550 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X79Y78 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[36]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.368 1.533 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X79Y78 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[36]/C clock pessimism -0.168 1.365 SLICE_X79Y78 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.370 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[36] ------------------------------------------------------------------- required time -1.370 arrival time 1.550 ------------------------------------------------------------------- slack 0.180 Slack (MET) : 0.180ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[28]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.289ns (logic 0.049ns (16.955%) route 0.240ns (83.045%)) Logic Levels: 0 Clock Path Skew: 0.104ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.533ns Source Clock Delay (SCD): 1.261ns Clock Pessimism Removal (CPR): 0.168ns Clock Net Delay (Source): 1.143ns (routing 0.610ns, distribution 0.533ns) Clock Net Delay (Destination): 1.368ns (routing 0.686ns, distribution 0.682ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.143 1.261 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X81Y83 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y83 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.310 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.240 1.550 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X79Y78 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[28]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.368 1.533 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X79Y78 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[28]/C clock pessimism -0.168 1.365 SLICE_X79Y78 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.370 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[28] ------------------------------------------------------------------- required time -1.370 arrival time 1.550 ------------------------------------------------------------------- slack 0.180 Slack (MET) : 0.180ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[30]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.289ns (logic 0.049ns (16.955%) route 0.240ns (83.045%)) Logic Levels: 0 Clock Path Skew: 0.104ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.533ns Source Clock Delay (SCD): 1.261ns Clock Pessimism Removal (CPR): 0.168ns Clock Net Delay (Source): 1.143ns (routing 0.610ns, distribution 0.533ns) Clock Net Delay (Destination): 1.368ns (routing 0.686ns, distribution 0.682ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.143 1.261 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X81Y83 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y83 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.310 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.240 1.550 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X79Y78 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[30]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.368 1.533 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X79Y78 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[30]/C clock pessimism -0.168 1.365 SLICE_X79Y78 FDCE (Remov_GFF2_SLICEM_C_CLR) 0.005 1.370 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[30] ------------------------------------------------------------------- required time -1.370 arrival time 1.550 ------------------------------------------------------------------- slack 0.180 Slack (MET) : 0.180ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[36]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.289ns (logic 0.049ns (16.955%) route 0.240ns (83.045%)) Logic Levels: 0 Clock Path Skew: 0.104ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.533ns Source Clock Delay (SCD): 1.261ns Clock Pessimism Removal (CPR): 0.168ns Clock Net Delay (Source): 1.143ns (routing 0.610ns, distribution 0.533ns) Clock Net Delay (Destination): 1.368ns (routing 0.686ns, distribution 0.682ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.143 1.261 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X81Y83 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y83 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.310 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.240 1.550 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X79Y78 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[36]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.368 1.533 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X79Y78 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[36]/C clock pessimism -0.168 1.365 SLICE_X79Y78 FDCE (Remov_FFF2_SLICEM_C_CLR) 0.005 1.370 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[36] ------------------------------------------------------------------- required time -1.370 arrival time 1.550 ------------------------------------------------------------------- slack 0.180 Slack (MET) : 0.181ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[27]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.292ns (logic 0.049ns (16.781%) route 0.243ns (83.219%)) Logic Levels: 0 Clock Path Skew: 0.106ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.535ns Source Clock Delay (SCD): 1.261ns Clock Pessimism Removal (CPR): 0.168ns Clock Net Delay (Source): 1.143ns (routing 0.610ns, distribution 0.533ns) Clock Net Delay (Destination): 1.370ns (routing 0.686ns, distribution 0.684ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.143 1.261 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X81Y83 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y83 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.310 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.243 1.553 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X79Y78 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[27]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.370 1.535 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X79Y78 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[27]/C clock pessimism -0.168 1.367 SLICE_X79Y78 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.372 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[27] ------------------------------------------------------------------- required time -1.372 arrival time 1.553 ------------------------------------------------------------------- slack 0.181 Slack (MET) : 0.181ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[28]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.292ns (logic 0.049ns (16.781%) route 0.243ns (83.219%)) Logic Levels: 0 Clock Path Skew: 0.106ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.535ns Source Clock Delay (SCD): 1.261ns Clock Pessimism Removal (CPR): 0.168ns Clock Net Delay (Source): 1.143ns (routing 0.610ns, distribution 0.533ns) Clock Net Delay (Destination): 1.370ns (routing 0.686ns, distribution 0.684ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.143 1.261 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X81Y83 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y83 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.310 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.243 1.553 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X79Y78 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[28]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y45 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.370 1.535 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X79Y78 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[28]/C clock pessimism -0.168 1.367 SLICE_X79Y78 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 1.372 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[28] ------------------------------------------------------------------- required time -1.372 arrival time 1.553 ------------------------------------------------------------------- slack 0.181 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_30 To Clock: gtwiz_userclk_rx_srcclk_out[0]_30 Setup : 0 Failing Endpoints, Worst Slack 3.477ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.112ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.477ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 4.690ns (logic 0.377ns (8.038%) route 4.313ns (91.962%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.635ns = ( 10.952 - 8.317 ) Source Clock Delay (SCD): 2.867ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.442ns (routing 0.789ns, distribution 1.653ns) Clock Net Delay (Destination): 2.259ns (routing 0.708ns, distribution 1.551ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.442 2.867 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y180 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y180 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.006 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.646 6.652 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X60Y218 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.238 6.890 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/O net (fo=15, routed) 0.667 7.557 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X60Y214 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.259 10.952 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X60Y214 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/C clock pessimism 0.210 11.162 clock uncertainty -0.035 11.127 SLICE_X60Y214 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.034 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1] ------------------------------------------------------------------- required time 11.034 arrival time -7.557 ------------------------------------------------------------------- slack 3.477 Slack (MET) : 3.477ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 4.690ns (logic 0.377ns (8.038%) route 4.313ns (91.962%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.635ns = ( 10.952 - 8.317 ) Source Clock Delay (SCD): 2.867ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.442ns (routing 0.789ns, distribution 1.653ns) Clock Net Delay (Destination): 2.259ns (routing 0.708ns, distribution 1.551ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.442 2.867 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y180 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y180 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.006 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.646 6.652 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X60Y218 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.238 6.890 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/O net (fo=15, routed) 0.667 7.557 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X60Y214 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.259 10.952 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X60Y214 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/C clock pessimism 0.210 11.162 clock uncertainty -0.035 11.127 SLICE_X60Y214 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 11.034 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2] ------------------------------------------------------------------- required time 11.034 arrival time -7.557 ------------------------------------------------------------------- slack 3.477 Slack (MET) : 3.477ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 4.690ns (logic 0.377ns (8.038%) route 4.313ns (91.962%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.635ns = ( 10.952 - 8.317 ) Source Clock Delay (SCD): 2.867ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.442ns (routing 0.789ns, distribution 1.653ns) Clock Net Delay (Destination): 2.259ns (routing 0.708ns, distribution 1.551ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.442 2.867 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y180 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y180 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.006 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.646 6.652 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X60Y218 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.238 6.890 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/O net (fo=15, routed) 0.667 7.557 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X60Y214 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.259 10.952 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X60Y214 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/C clock pessimism 0.210 11.162 clock uncertainty -0.035 11.127 SLICE_X60Y214 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 11.034 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3] ------------------------------------------------------------------- required time 11.034 arrival time -7.557 ------------------------------------------------------------------- slack 3.477 Slack (MET) : 3.477ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 4.690ns (logic 0.377ns (8.038%) route 4.313ns (91.962%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.635ns = ( 10.952 - 8.317 ) Source Clock Delay (SCD): 2.867ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.442ns (routing 0.789ns, distribution 1.653ns) Clock Net Delay (Destination): 2.259ns (routing 0.708ns, distribution 1.551ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.442 2.867 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y180 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y180 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.006 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.646 6.652 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X60Y218 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.238 6.890 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/O net (fo=15, routed) 0.667 7.557 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X60Y214 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.259 10.952 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X60Y214 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/C clock pessimism 0.210 11.162 clock uncertainty -0.035 11.127 SLICE_X60Y214 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.034 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4] ------------------------------------------------------------------- required time 11.034 arrival time -7.557 ------------------------------------------------------------------- slack 3.477 Slack (MET) : 3.723ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 4.450ns (logic 0.377ns (8.472%) route 4.073ns (91.528%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.016ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.641ns = ( 10.958 - 8.317 ) Source Clock Delay (SCD): 2.867ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.442ns (routing 0.789ns, distribution 1.653ns) Clock Net Delay (Destination): 2.265ns (routing 0.708ns, distribution 1.557ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.442 2.867 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y180 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y180 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.006 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.646 6.652 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X60Y218 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.238 6.890 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/O net (fo=15, routed) 0.427 7.317 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X60Y219 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.265 10.958 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X60Y219 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C clock pessimism 0.210 11.168 clock uncertainty -0.035 11.133 SLICE_X60Y219 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 11.040 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2] ------------------------------------------------------------------- required time 11.040 arrival time -7.317 ------------------------------------------------------------------- slack 3.723 Slack (MET) : 3.723ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 4.450ns (logic 0.377ns (8.472%) route 4.073ns (91.528%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.016ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.641ns = ( 10.958 - 8.317 ) Source Clock Delay (SCD): 2.867ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.442ns (routing 0.789ns, distribution 1.653ns) Clock Net Delay (Destination): 2.265ns (routing 0.708ns, distribution 1.557ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.442 2.867 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y180 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y180 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.006 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.646 6.652 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X60Y218 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.238 6.890 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/O net (fo=15, routed) 0.427 7.317 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X60Y219 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.265 10.958 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X60Y219 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/C clock pessimism 0.210 11.168 clock uncertainty -0.035 11.133 SLICE_X60Y219 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.040 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3] ------------------------------------------------------------------- required time 11.040 arrival time -7.317 ------------------------------------------------------------------- slack 3.723 Slack (MET) : 3.723ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 4.450ns (logic 0.377ns (8.472%) route 4.073ns (91.528%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.016ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.641ns = ( 10.958 - 8.317 ) Source Clock Delay (SCD): 2.867ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.442ns (routing 0.789ns, distribution 1.653ns) Clock Net Delay (Destination): 2.265ns (routing 0.708ns, distribution 1.557ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.442 2.867 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y180 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y180 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.006 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.646 6.652 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X60Y218 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.238 6.890 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/O net (fo=15, routed) 0.427 7.317 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X60Y219 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.265 10.958 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X60Y219 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C clock pessimism 0.210 11.168 clock uncertainty -0.035 11.133 SLICE_X60Y219 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 11.040 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4] ------------------------------------------------------------------- required time 11.040 arrival time -7.317 ------------------------------------------------------------------- slack 3.723 Slack (MET) : 3.723ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 4.450ns (logic 0.377ns (8.472%) route 4.073ns (91.528%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.016ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.641ns = ( 10.958 - 8.317 ) Source Clock Delay (SCD): 2.867ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.442ns (routing 0.789ns, distribution 1.653ns) Clock Net Delay (Destination): 2.265ns (routing 0.708ns, distribution 1.557ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.442 2.867 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y180 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y180 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.006 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.646 6.652 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X60Y218 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.238 6.890 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/O net (fo=15, routed) 0.427 7.317 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X60Y219 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.265 10.958 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X60Y219 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/C clock pessimism 0.210 11.168 clock uncertainty -0.035 11.133 SLICE_X60Y219 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 11.040 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5] ------------------------------------------------------------------- required time 11.040 arrival time -7.317 ------------------------------------------------------------------- slack 3.723 Slack (MET) : 3.731ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 4.440ns (logic 0.377ns (8.491%) route 4.063ns (91.509%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.018ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.639ns = ( 10.956 - 8.317 ) Source Clock Delay (SCD): 2.867ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.442ns (routing 0.789ns, distribution 1.653ns) Clock Net Delay (Destination): 2.263ns (routing 0.708ns, distribution 1.555ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.442 2.867 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y180 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y180 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.006 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.646 6.652 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X60Y218 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.238 6.890 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/O net (fo=15, routed) 0.417 7.307 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X60Y219 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.263 10.956 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X60Y219 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/C clock pessimism 0.210 11.166 clock uncertainty -0.035 11.131 SLICE_X60Y219 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.038 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0] ------------------------------------------------------------------- required time 11.038 arrival time -7.307 ------------------------------------------------------------------- slack 3.731 Slack (MET) : 3.731ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 4.440ns (logic 0.377ns (8.491%) route 4.063ns (91.509%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.018ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.639ns = ( 10.956 - 8.317 ) Source Clock Delay (SCD): 2.867ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.442ns (routing 0.789ns, distribution 1.653ns) Clock Net Delay (Destination): 2.263ns (routing 0.708ns, distribution 1.555ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.442 2.867 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y180 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y180 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.006 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.646 6.652 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X60Y218 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.238 6.890 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/O net (fo=15, routed) 0.417 7.307 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X60Y219 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.263 10.956 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X60Y219 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/C clock pessimism 0.210 11.166 clock uncertainty -0.035 11.131 SLICE_X60Y219 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 11.038 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1] ------------------------------------------------------------------- required time 11.038 arrival time -7.307 ------------------------------------------------------------------- slack 3.731 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.112ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[72]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.195ns (logic 0.049ns (25.128%) route 0.146ns (74.872%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.337ns Source Clock Delay (SCD): 1.101ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 0.985ns (routing 0.376ns, distribution 0.609ns) Clock Net Delay (Destination): 1.185ns (routing 0.440ns, distribution 0.745ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.985 1.101 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK SLICE_X54Y205 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X54Y205 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.150 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.146 1.296 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X56Y205 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[72]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.185 1.337 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y205 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[72]/C clock pessimism -0.158 1.179 SLICE_X56Y205 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.184 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[72] ------------------------------------------------------------------- required time -1.184 arrival time 1.296 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.112ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[75]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.195ns (logic 0.049ns (25.128%) route 0.146ns (74.872%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.337ns Source Clock Delay (SCD): 1.101ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 0.985ns (routing 0.376ns, distribution 0.609ns) Clock Net Delay (Destination): 1.185ns (routing 0.440ns, distribution 0.745ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.985 1.101 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK SLICE_X54Y205 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X54Y205 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.150 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.146 1.296 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X56Y205 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[75]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.185 1.337 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y205 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[75]/C clock pessimism -0.158 1.179 SLICE_X56Y205 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 1.184 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[75] ------------------------------------------------------------------- required time -1.184 arrival time 1.296 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.112ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[72]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.195ns (logic 0.049ns (25.128%) route 0.146ns (74.872%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.337ns Source Clock Delay (SCD): 1.101ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 0.985ns (routing 0.376ns, distribution 0.609ns) Clock Net Delay (Destination): 1.185ns (routing 0.440ns, distribution 0.745ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.985 1.101 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK SLICE_X54Y205 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X54Y205 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.150 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.146 1.296 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X56Y205 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[72]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.185 1.337 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y205 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[72]/C clock pessimism -0.158 1.179 SLICE_X56Y205 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 1.184 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[72] ------------------------------------------------------------------- required time -1.184 arrival time 1.296 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.112ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[75]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.195ns (logic 0.049ns (25.128%) route 0.146ns (74.872%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.337ns Source Clock Delay (SCD): 1.101ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 0.985ns (routing 0.376ns, distribution 0.609ns) Clock Net Delay (Destination): 1.185ns (routing 0.440ns, distribution 0.745ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.985 1.101 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK SLICE_X54Y205 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X54Y205 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.150 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.146 1.296 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X56Y205 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[75]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.185 1.337 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y205 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[75]/C clock pessimism -0.158 1.179 SLICE_X56Y205 FDCE (Remov_GFF2_SLICEL_C_CLR) 0.005 1.184 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[75] ------------------------------------------------------------------- required time -1.184 arrival time 1.296 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.115ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[43]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.201ns (logic 0.049ns (24.378%) route 0.152ns (75.622%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.340ns Source Clock Delay (SCD): 1.101ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 0.985ns (routing 0.376ns, distribution 0.609ns) Clock Net Delay (Destination): 1.188ns (routing 0.440ns, distribution 0.748ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.985 1.101 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK SLICE_X54Y205 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X54Y205 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.150 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.152 1.302 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X56Y205 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[43]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.188 1.340 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y205 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[43]/C clock pessimism -0.158 1.182 SLICE_X56Y205 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 1.187 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[43] ------------------------------------------------------------------- required time -1.187 arrival time 1.302 ------------------------------------------------------------------- slack 0.115 Slack (MET) : 0.115ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[43]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.201ns (logic 0.049ns (24.378%) route 0.152ns (75.622%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.340ns Source Clock Delay (SCD): 1.101ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 0.985ns (routing 0.376ns, distribution 0.609ns) Clock Net Delay (Destination): 1.188ns (routing 0.440ns, distribution 0.748ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.985 1.101 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK SLICE_X54Y205 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X54Y205 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.150 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.152 1.302 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X56Y205 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[43]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.188 1.340 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y205 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[43]/C clock pessimism -0.158 1.182 SLICE_X56Y205 FDCE (Remov_DFF2_SLICEL_C_CLR) 0.005 1.187 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[43] ------------------------------------------------------------------- required time -1.187 arrival time 1.302 ------------------------------------------------------------------- slack 0.115 Slack (MET) : 0.164ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[81]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.263ns (logic 0.049ns (18.631%) route 0.214ns (81.369%)) Logic Levels: 0 Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.353ns Source Clock Delay (SCD): 1.101ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 0.985ns (routing 0.376ns, distribution 0.609ns) Clock Net Delay (Destination): 1.201ns (routing 0.440ns, distribution 0.761ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.985 1.101 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK SLICE_X54Y205 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X54Y205 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.150 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.214 1.364 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X55Y206 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[81]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.201 1.353 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X55Y206 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[81]/C clock pessimism -0.158 1.195 SLICE_X55Y206 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.200 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[81] ------------------------------------------------------------------- required time -1.200 arrival time 1.364 ------------------------------------------------------------------- slack 0.164 Slack (MET) : 0.164ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[88]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.263ns (logic 0.049ns (18.631%) route 0.214ns (81.369%)) Logic Levels: 0 Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.353ns Source Clock Delay (SCD): 1.101ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 0.985ns (routing 0.376ns, distribution 0.609ns) Clock Net Delay (Destination): 1.201ns (routing 0.440ns, distribution 0.761ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.985 1.101 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK SLICE_X54Y205 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X54Y205 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.150 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.214 1.364 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X55Y206 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[88]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.201 1.353 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X55Y206 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[88]/C clock pessimism -0.158 1.195 SLICE_X55Y206 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.200 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[88] ------------------------------------------------------------------- required time -1.200 arrival time 1.364 ------------------------------------------------------------------- slack 0.164 Slack (MET) : 0.164ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[90]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.263ns (logic 0.049ns (18.631%) route 0.214ns (81.369%)) Logic Levels: 0 Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.353ns Source Clock Delay (SCD): 1.101ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 0.985ns (routing 0.376ns, distribution 0.609ns) Clock Net Delay (Destination): 1.201ns (routing 0.440ns, distribution 0.761ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.985 1.101 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK SLICE_X54Y205 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X54Y205 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.150 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.214 1.364 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X55Y206 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[90]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.201 1.353 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X55Y206 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[90]/C clock pessimism -0.158 1.195 SLICE_X55Y206 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.200 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[90] ------------------------------------------------------------------- required time -1.200 arrival time 1.364 ------------------------------------------------------------------- slack 0.164 Slack (MET) : 0.164ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[98]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.263ns (logic 0.049ns (18.631%) route 0.214ns (81.369%)) Logic Levels: 0 Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.353ns Source Clock Delay (SCD): 1.101ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 0.985ns (routing 0.376ns, distribution 0.609ns) Clock Net Delay (Destination): 1.201ns (routing 0.440ns, distribution 0.761ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.985 1.101 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK SLICE_X54Y205 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X54Y205 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.150 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.214 1.364 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X55Y206 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[98]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y93 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.201 1.353 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X55Y206 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[98]/C clock pessimism -0.158 1.195 SLICE_X55Y206 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.200 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[98] ------------------------------------------------------------------- required time -1.200 arrival time 1.364 ------------------------------------------------------------------- slack 0.164 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_31 To Clock: gtwiz_userclk_rx_srcclk_out[0]_31 Setup : 0 Failing Endpoints, Worst Slack 3.987ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.159ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.987ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 4.183ns (logic 0.230ns (5.498%) route 3.953ns (94.502%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.019ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.649ns = ( 10.966 - 8.317 ) Source Clock Delay (SCD): 2.880ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.455ns (routing 0.794ns, distribution 1.661ns) Clock Net Delay (Destination): 2.273ns (routing 0.710ns, distribution 1.563ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.455 2.880 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y204 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y204 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.019 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.142 6.161 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X59Y199 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.091 6.252 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/O net (fo=15, routed) 0.811 7.063 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X59Y220 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.273 10.966 g_gbt_bank[2].gbtbank/CLK SLICE_X59Y220 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/C clock pessimism 0.212 11.178 clock uncertainty -0.035 11.143 SLICE_X59Y220 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.050 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5] ------------------------------------------------------------------- required time 11.050 arrival time -7.063 ------------------------------------------------------------------- slack 3.987 Slack (MET) : 3.993ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 4.176ns (logic 0.230ns (5.508%) route 3.946ns (94.492%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.020ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.648ns = ( 10.965 - 8.317 ) Source Clock Delay (SCD): 2.880ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.455ns (routing 0.794ns, distribution 1.661ns) Clock Net Delay (Destination): 2.272ns (routing 0.710ns, distribution 1.562ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.455 2.880 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y204 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y204 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.019 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.142 6.161 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X59Y199 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.091 6.252 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/O net (fo=15, routed) 0.804 7.056 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X59Y220 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.272 10.965 g_gbt_bank[2].gbtbank/CLK SLICE_X59Y220 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/C clock pessimism 0.212 11.177 clock uncertainty -0.035 11.142 SLICE_X59Y220 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 11.049 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0] ------------------------------------------------------------------- required time 11.049 arrival time -7.056 ------------------------------------------------------------------- slack 3.993 Slack (MET) : 3.993ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 4.176ns (logic 0.230ns (5.508%) route 3.946ns (94.492%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.020ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.648ns = ( 10.965 - 8.317 ) Source Clock Delay (SCD): 2.880ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.455ns (routing 0.794ns, distribution 1.661ns) Clock Net Delay (Destination): 2.272ns (routing 0.710ns, distribution 1.562ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.455 2.880 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y204 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y204 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.019 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.142 6.161 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X59Y199 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.091 6.252 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/O net (fo=15, routed) 0.804 7.056 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X59Y220 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.272 10.965 g_gbt_bank[2].gbtbank/CLK SLICE_X59Y220 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/C clock pessimism 0.212 11.177 clock uncertainty -0.035 11.142 SLICE_X59Y220 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.049 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4] ------------------------------------------------------------------- required time 11.049 arrival time -7.056 ------------------------------------------------------------------- slack 3.993 Slack (MET) : 4.060ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 4.118ns (logic 0.230ns (5.585%) route 3.888ns (94.415%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.011ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.657ns = ( 10.974 - 8.317 ) Source Clock Delay (SCD): 2.880ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.455ns (routing 0.794ns, distribution 1.661ns) Clock Net Delay (Destination): 2.281ns (routing 0.710ns, distribution 1.571ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.455 2.880 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y204 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y204 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.019 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.142 6.161 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X59Y199 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.091 6.252 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/O net (fo=15, routed) 0.746 6.998 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X59Y194 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.281 10.974 g_gbt_bank[2].gbtbank/CLK SLICE_X59Y194 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/C clock pessimism 0.212 11.186 clock uncertainty -0.035 11.151 SLICE_X59Y194 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.058 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0] ------------------------------------------------------------------- required time 11.058 arrival time -6.998 ------------------------------------------------------------------- slack 4.060 Slack (MET) : 4.159ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 4.020ns (logic 0.358ns (8.905%) route 3.662ns (91.095%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.010ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.658ns = ( 10.975 - 8.317 ) Source Clock Delay (SCD): 2.880ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.455ns (routing 0.794ns, distribution 1.661ns) Clock Net Delay (Destination): 2.282ns (routing 0.710ns, distribution 1.572ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.455 2.880 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y204 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y204 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.019 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.957 5.976 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X60Y199 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.219 6.195 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__28/O net (fo=2, routed) 0.705 6.900 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X60Y196 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.282 10.975 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK SLICE_X60Y196 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.212 11.187 clock uncertainty -0.035 11.152 SLICE_X60Y196 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.059 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 11.059 arrival time -6.900 ------------------------------------------------------------------- slack 4.159 Slack (MET) : 4.159ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 4.020ns (logic 0.358ns (8.905%) route 3.662ns (91.095%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.010ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.658ns = ( 10.975 - 8.317 ) Source Clock Delay (SCD): 2.880ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.455ns (routing 0.794ns, distribution 1.661ns) Clock Net Delay (Destination): 2.282ns (routing 0.710ns, distribution 1.572ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.455 2.880 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y204 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y204 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.019 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.957 5.976 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X60Y199 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.219 6.195 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__28/O net (fo=2, routed) 0.705 6.900 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X60Y196 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.282 10.975 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK SLICE_X60Y196 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.212 11.187 clock uncertainty -0.035 11.152 SLICE_X60Y196 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 11.059 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 11.059 arrival time -6.900 ------------------------------------------------------------------- slack 4.159 Slack (MET) : 4.236ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 3.948ns (logic 0.230ns (5.826%) route 3.718ns (94.174%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.005ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.663ns = ( 10.980 - 8.317 ) Source Clock Delay (SCD): 2.880ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.455ns (routing 0.794ns, distribution 1.661ns) Clock Net Delay (Destination): 2.287ns (routing 0.710ns, distribution 1.577ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.455 2.880 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y204 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y204 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.019 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.142 6.161 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X59Y199 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.091 6.252 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/O net (fo=15, routed) 0.576 6.828 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X58Y193 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.287 10.980 g_gbt_bank[2].gbtbank/CLK SLICE_X58Y193 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/C clock pessimism 0.212 11.192 clock uncertainty -0.035 11.157 SLICE_X58Y193 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.064 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1] ------------------------------------------------------------------- required time 11.064 arrival time -6.828 ------------------------------------------------------------------- slack 4.236 Slack (MET) : 4.236ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 3.948ns (logic 0.230ns (5.826%) route 3.718ns (94.174%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.005ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.663ns = ( 10.980 - 8.317 ) Source Clock Delay (SCD): 2.880ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.455ns (routing 0.794ns, distribution 1.661ns) Clock Net Delay (Destination): 2.287ns (routing 0.710ns, distribution 1.577ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.455 2.880 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y204 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y204 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.019 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.142 6.161 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X59Y199 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.091 6.252 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/O net (fo=15, routed) 0.576 6.828 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X58Y193 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.287 10.980 g_gbt_bank[2].gbtbank/CLK SLICE_X58Y193 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/C clock pessimism 0.212 11.192 clock uncertainty -0.035 11.157 SLICE_X58Y193 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 11.064 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2] ------------------------------------------------------------------- required time 11.064 arrival time -6.828 ------------------------------------------------------------------- slack 4.236 Slack (MET) : 4.236ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 3.948ns (logic 0.230ns (5.826%) route 3.718ns (94.174%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.005ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.663ns = ( 10.980 - 8.317 ) Source Clock Delay (SCD): 2.880ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.455ns (routing 0.794ns, distribution 1.661ns) Clock Net Delay (Destination): 2.287ns (routing 0.710ns, distribution 1.577ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.455 2.880 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y204 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y204 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.019 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.142 6.161 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X59Y199 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.091 6.252 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/O net (fo=15, routed) 0.576 6.828 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X58Y193 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.287 10.980 g_gbt_bank[2].gbtbank/CLK SLICE_X58Y193 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/C clock pessimism 0.212 11.192 clock uncertainty -0.035 11.157 SLICE_X58Y193 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.064 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3] ------------------------------------------------------------------- required time 11.064 arrival time -6.828 ------------------------------------------------------------------- slack 4.236 Slack (MET) : 4.236ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 3.948ns (logic 0.230ns (5.826%) route 3.718ns (94.174%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.005ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.663ns = ( 10.980 - 8.317 ) Source Clock Delay (SCD): 2.880ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.455ns (routing 0.794ns, distribution 1.661ns) Clock Net Delay (Destination): 2.287ns (routing 0.710ns, distribution 1.577ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.455 2.880 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y204 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y204 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.019 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.142 6.161 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X59Y199 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.091 6.252 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/O net (fo=15, routed) 0.576 6.828 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X58Y193 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.287 10.980 g_gbt_bank[2].gbtbank/CLK SLICE_X58Y193 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/C clock pessimism 0.212 11.192 clock uncertainty -0.035 11.157 SLICE_X58Y193 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 11.064 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4] ------------------------------------------------------------------- required time 11.064 arrival time -6.828 ------------------------------------------------------------------- slack 4.236 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.159ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[37]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.229ns (logic 0.049ns (21.397%) route 0.180ns (78.603%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.369ns Source Clock Delay (SCD): 1.144ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.028ns (routing 0.377ns, distribution 0.651ns) Clock Net Delay (Destination): 1.217ns (routing 0.443ns, distribution 0.774ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.028 1.144 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK SLICE_X60Y195 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y195 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.193 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.180 1.373 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X58Y194 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[37]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.217 1.369 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y194 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[37]/C clock pessimism -0.160 1.209 SLICE_X58Y194 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.214 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[37] ------------------------------------------------------------------- required time -1.214 arrival time 1.373 ------------------------------------------------------------------- slack 0.159 Slack (MET) : 0.159ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[38]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.229ns (logic 0.049ns (21.397%) route 0.180ns (78.603%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.369ns Source Clock Delay (SCD): 1.144ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.028ns (routing 0.377ns, distribution 0.651ns) Clock Net Delay (Destination): 1.217ns (routing 0.443ns, distribution 0.774ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.028 1.144 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK SLICE_X60Y195 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y195 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.193 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.180 1.373 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X58Y194 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[38]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.217 1.369 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y194 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[38]/C clock pessimism -0.160 1.209 SLICE_X58Y194 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.214 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[38] ------------------------------------------------------------------- required time -1.214 arrival time 1.373 ------------------------------------------------------------------- slack 0.159 Slack (MET) : 0.159ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[39]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.229ns (logic 0.049ns (21.397%) route 0.180ns (78.603%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.369ns Source Clock Delay (SCD): 1.144ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.028ns (routing 0.377ns, distribution 0.651ns) Clock Net Delay (Destination): 1.217ns (routing 0.443ns, distribution 0.774ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.028 1.144 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK SLICE_X60Y195 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y195 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.193 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.180 1.373 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X58Y194 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[39]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.217 1.369 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y194 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[39]/C clock pessimism -0.160 1.209 SLICE_X58Y194 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.214 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[39] ------------------------------------------------------------------- required time -1.214 arrival time 1.373 ------------------------------------------------------------------- slack 0.159 Slack (MET) : 0.160ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.232ns (logic 0.049ns (21.121%) route 0.183ns (78.879%)) Logic Levels: 0 Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.371ns Source Clock Delay (SCD): 1.144ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.028ns (routing 0.377ns, distribution 0.651ns) Clock Net Delay (Destination): 1.219ns (routing 0.443ns, distribution 0.776ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.028 1.144 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK SLICE_X60Y195 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y195 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.193 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.183 1.376 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X58Y194 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.219 1.371 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y194 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C clock pessimism -0.160 1.211 SLICE_X58Y194 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.216 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0] ------------------------------------------------------------------- required time -1.216 arrival time 1.376 ------------------------------------------------------------------- slack 0.160 Slack (MET) : 0.160ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.232ns (logic 0.049ns (21.121%) route 0.183ns (78.879%)) Logic Levels: 0 Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.371ns Source Clock Delay (SCD): 1.144ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.028ns (routing 0.377ns, distribution 0.651ns) Clock Net Delay (Destination): 1.219ns (routing 0.443ns, distribution 0.776ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.028 1.144 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK SLICE_X60Y195 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y195 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.193 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.183 1.376 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X58Y194 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.219 1.371 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y194 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C clock pessimism -0.160 1.211 SLICE_X58Y194 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 1.216 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] ------------------------------------------------------------------- required time -1.216 arrival time 1.376 ------------------------------------------------------------------- slack 0.160 Slack (MET) : 0.160ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.232ns (logic 0.049ns (21.121%) route 0.183ns (78.879%)) Logic Levels: 0 Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.371ns Source Clock Delay (SCD): 1.144ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.028ns (routing 0.377ns, distribution 0.651ns) Clock Net Delay (Destination): 1.219ns (routing 0.443ns, distribution 0.776ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.028 1.144 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK SLICE_X60Y195 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y195 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.193 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.183 1.376 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X58Y194 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.219 1.371 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y194 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C clock pessimism -0.160 1.211 SLICE_X58Y194 FDCE (Remov_BFF_SLICEM_C_CLR) 0.005 1.216 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] ------------------------------------------------------------------- required time -1.216 arrival time 1.376 ------------------------------------------------------------------- slack 0.160 Slack (MET) : 0.160ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[31]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.232ns (logic 0.049ns (21.121%) route 0.183ns (78.879%)) Logic Levels: 0 Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.371ns Source Clock Delay (SCD): 1.144ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.028ns (routing 0.377ns, distribution 0.651ns) Clock Net Delay (Destination): 1.219ns (routing 0.443ns, distribution 0.776ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.028 1.144 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK SLICE_X60Y195 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y195 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.193 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.183 1.376 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X58Y194 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[31]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.219 1.371 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y194 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[31]/C clock pessimism -0.160 1.211 SLICE_X58Y194 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 1.216 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[31] ------------------------------------------------------------------- required time -1.216 arrival time 1.376 ------------------------------------------------------------------- slack 0.160 Slack (MET) : 0.170ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.263ns (logic 0.048ns (18.251%) route 0.215ns (81.749%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.371ns Source Clock Delay (SCD): 1.123ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.007ns (routing 0.377ns, distribution 0.630ns) Clock Net Delay (Destination): 1.219ns (routing 0.443ns, distribution 0.776ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.123 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X57Y194 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X57Y194 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.171 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.215 1.386 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X60Y193 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.219 1.371 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X60Y193 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism -0.160 1.211 SLICE_X60Y193 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.216 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time -1.216 arrival time 1.386 ------------------------------------------------------------------- slack 0.170 Slack (MET) : 0.170ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.263ns (logic 0.048ns (18.251%) route 0.215ns (81.749%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.371ns Source Clock Delay (SCD): 1.123ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.007ns (routing 0.377ns, distribution 0.630ns) Clock Net Delay (Destination): 1.219ns (routing 0.443ns, distribution 0.776ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.123 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X57Y194 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X57Y194 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.171 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.215 1.386 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X60Y193 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.219 1.371 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X60Y193 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.160 1.211 SLICE_X60Y193 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.216 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -1.216 arrival time 1.386 ------------------------------------------------------------------- slack 0.170 Slack (MET) : 0.170ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.263ns (logic 0.048ns (18.251%) route 0.215ns (81.749%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.371ns Source Clock Delay (SCD): 1.123ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.007ns (routing 0.377ns, distribution 0.630ns) Clock Net Delay (Destination): 1.219ns (routing 0.443ns, distribution 0.776ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.123 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X57Y194 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X57Y194 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.171 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.215 1.386 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X60Y193 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y91 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.219 1.371 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X60Y193 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C clock pessimism -0.160 1.211 SLICE_X60Y193 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.216 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20] ------------------------------------------------------------------- required time -1.216 arrival time 1.386 ------------------------------------------------------------------- slack 0.170 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_32 To Clock: gtwiz_userclk_rx_srcclk_out[0]_32 Setup : 0 Failing Endpoints, Worst Slack 5.181ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.116ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.181ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 2.688ns (logic 0.229ns (8.519%) route 2.459ns (91.481%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.320ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.327ns = ( 10.644 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.951ns (routing 0.693ns, distribution 1.258ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y214 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y214 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.765 4.753 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X30Y218 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 4.843 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/O net (fo=15, routed) 0.694 5.537 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X28Y212 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.951 10.644 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X28Y212 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/C clock pessimism 0.202 10.846 clock uncertainty -0.035 10.811 SLICE_X28Y212 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.718 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1] ------------------------------------------------------------------- required time 10.718 arrival time -5.537 ------------------------------------------------------------------- slack 5.181 Slack (MET) : 5.181ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 2.688ns (logic 0.229ns (8.519%) route 2.459ns (91.481%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.320ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.327ns = ( 10.644 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.951ns (routing 0.693ns, distribution 1.258ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y214 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y214 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.765 4.753 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X30Y218 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 4.843 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/O net (fo=15, routed) 0.694 5.537 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X28Y212 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.951 10.644 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X28Y212 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/C clock pessimism 0.202 10.846 clock uncertainty -0.035 10.811 SLICE_X28Y212 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 10.718 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2] ------------------------------------------------------------------- required time 10.718 arrival time -5.537 ------------------------------------------------------------------- slack 5.181 Slack (MET) : 5.181ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 2.688ns (logic 0.229ns (8.519%) route 2.459ns (91.481%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.320ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.327ns = ( 10.644 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.951ns (routing 0.693ns, distribution 1.258ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y214 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y214 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.765 4.753 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X30Y218 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 4.843 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/O net (fo=15, routed) 0.694 5.537 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X28Y212 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.951 10.644 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X28Y212 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C clock pessimism 0.202 10.846 clock uncertainty -0.035 10.811 SLICE_X28Y212 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 10.718 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3] ------------------------------------------------------------------- required time 10.718 arrival time -5.537 ------------------------------------------------------------------- slack 5.181 Slack (MET) : 5.181ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 2.688ns (logic 0.229ns (8.519%) route 2.459ns (91.481%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.320ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.327ns = ( 10.644 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.951ns (routing 0.693ns, distribution 1.258ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y214 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y214 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.765 4.753 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X30Y218 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 4.843 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/O net (fo=15, routed) 0.694 5.537 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X28Y212 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.951 10.644 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X28Y212 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/C clock pessimism 0.202 10.846 clock uncertainty -0.035 10.811 SLICE_X28Y212 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.718 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4] ------------------------------------------------------------------- required time 10.718 arrival time -5.537 ------------------------------------------------------------------- slack 5.181 Slack (MET) : 5.198ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 2.676ns (logic 0.229ns (8.558%) route 2.447ns (91.442%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.315ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.332ns = ( 10.649 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.956ns (routing 0.693ns, distribution 1.263ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y214 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y214 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.765 4.753 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X30Y218 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 4.843 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/O net (fo=15, routed) 0.682 5.525 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X28Y216 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.956 10.649 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X28Y216 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/C clock pessimism 0.202 10.851 clock uncertainty -0.035 10.816 SLICE_X28Y216 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.723 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1] ------------------------------------------------------------------- required time 10.723 arrival time -5.525 ------------------------------------------------------------------- slack 5.198 Slack (MET) : 5.198ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 2.676ns (logic 0.229ns (8.558%) route 2.447ns (91.442%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.315ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.332ns = ( 10.649 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.956ns (routing 0.693ns, distribution 1.263ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y214 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y214 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.765 4.753 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X30Y218 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 4.843 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/O net (fo=15, routed) 0.682 5.525 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X28Y216 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.956 10.649 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X28Y216 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/C clock pessimism 0.202 10.851 clock uncertainty -0.035 10.816 SLICE_X28Y216 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.723 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2] ------------------------------------------------------------------- required time 10.723 arrival time -5.525 ------------------------------------------------------------------- slack 5.198 Slack (MET) : 5.198ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 2.676ns (logic 0.229ns (8.558%) route 2.447ns (91.442%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.315ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.332ns = ( 10.649 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.956ns (routing 0.693ns, distribution 1.263ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y214 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y214 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.765 4.753 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X30Y218 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 4.843 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/O net (fo=15, routed) 0.682 5.525 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X28Y216 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.956 10.649 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X28Y216 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/C clock pessimism 0.202 10.851 clock uncertainty -0.035 10.816 SLICE_X28Y216 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 10.723 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3] ------------------------------------------------------------------- required time 10.723 arrival time -5.525 ------------------------------------------------------------------- slack 5.198 Slack (MET) : 5.198ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 2.676ns (logic 0.229ns (8.558%) route 2.447ns (91.442%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.315ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.332ns = ( 10.649 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.956ns (routing 0.693ns, distribution 1.263ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y214 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y214 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.765 4.753 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X30Y218 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 4.843 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/O net (fo=15, routed) 0.682 5.525 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X28Y216 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.956 10.649 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X28Y216 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5]/C clock pessimism 0.202 10.851 clock uncertainty -0.035 10.816 SLICE_X28Y216 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 10.723 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5] ------------------------------------------------------------------- required time 10.723 arrival time -5.525 ------------------------------------------------------------------- slack 5.198 Slack (MET) : 5.267ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 2.617ns (logic 0.229ns (8.750%) route 2.388ns (91.250%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.305ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.342ns = ( 10.659 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.966ns (routing 0.693ns, distribution 1.273ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y214 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y214 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.765 4.753 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X30Y218 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 4.843 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/O net (fo=15, routed) 0.623 5.466 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X28Y217 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.966 10.659 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X28Y217 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/C clock pessimism 0.202 10.861 clock uncertainty -0.035 10.826 SLICE_X28Y217 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 10.733 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0] ------------------------------------------------------------------- required time 10.733 arrival time -5.466 ------------------------------------------------------------------- slack 5.267 Slack (MET) : 5.267ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 2.617ns (logic 0.229ns (8.750%) route 2.388ns (91.250%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.305ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.342ns = ( 10.659 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.966ns (routing 0.693ns, distribution 1.273ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y214 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y214 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.765 4.753 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X30Y218 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 4.843 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/O net (fo=15, routed) 0.623 5.466 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X28Y217 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.966 10.659 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X28Y217 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/C clock pessimism 0.202 10.861 clock uncertainty -0.035 10.826 SLICE_X28Y217 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.733 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6] ------------------------------------------------------------------- required time 10.733 arrival time -5.466 ------------------------------------------------------------------- slack 5.267 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.116ns (arrival time - required time) Source: SFP_GEN[30].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.190ns (logic 0.048ns (25.263%) route 0.142ns (74.737%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.204ns Source Clock Delay (SCD): 0.991ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.875ns (routing 0.368ns, distribution 0.507ns) Clock Net Delay (Destination): 1.052ns (routing 0.432ns, distribution 0.620ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.875 0.991 SFP_GEN[30].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X31Y203 FDPE r SFP_GEN[30].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X31Y203 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.039 f SFP_GEN[30].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.142 1.181 SFP_GEN[30].ngCCM_gbt/sync_m_reg[3][0] SLICE_X29Y203 FDCE f SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.052 1.204 SFP_GEN[30].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X29Y203 FDCE r SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[2]/C clock pessimism -0.144 1.060 SLICE_X29Y203 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.065 SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[2] ------------------------------------------------------------------- required time -1.065 arrival time 1.181 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.151ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.205ns Source Clock Delay (SCD): 0.993ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.877ns (routing 0.368ns, distribution 0.509ns) Clock Net Delay (Destination): 1.053ns (routing 0.432ns, distribution 0.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.877 0.993 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X27Y212 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X27Y212 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.042 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.175 1.217 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X30Y212 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.053 1.205 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X30Y212 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C clock pessimism -0.144 1.061 SLICE_X30Y212 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.066 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time -1.066 arrival time 1.217 ------------------------------------------------------------------- slack 0.151 Slack (MET) : 0.151ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.205ns Source Clock Delay (SCD): 0.993ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.877ns (routing 0.368ns, distribution 0.509ns) Clock Net Delay (Destination): 1.053ns (routing 0.432ns, distribution 0.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.877 0.993 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X27Y212 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X27Y212 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.042 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.175 1.217 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X30Y212 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.053 1.205 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X30Y212 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C clock pessimism -0.144 1.061 SLICE_X30Y212 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.066 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time -1.066 arrival time 1.217 ------------------------------------------------------------------- slack 0.151 Slack (MET) : 0.203ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.275ns (logic 0.049ns (17.818%) route 0.226ns (82.182%)) Logic Levels: 0 Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.205ns Source Clock Delay (SCD): 0.994ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.878ns (routing 0.368ns, distribution 0.510ns) Clock Net Delay (Destination): 1.053ns (routing 0.432ns, distribution 0.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.878 0.994 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK SLICE_X29Y217 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X29Y217 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.043 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.226 1.269 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X27Y215 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.053 1.205 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X27Y215 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.144 1.061 SLICE_X27Y215 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.066 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -1.066 arrival time 1.269 ------------------------------------------------------------------- slack 0.203 Slack (MET) : 0.219ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.300ns (logic 0.049ns (16.333%) route 0.251ns (83.667%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.213ns Source Clock Delay (SCD): 0.993ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.877ns (routing 0.368ns, distribution 0.509ns) Clock Net Delay (Destination): 1.061ns (routing 0.432ns, distribution 0.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.877 0.993 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X27Y212 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X27Y212 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.042 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.251 1.293 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X31Y212 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.061 1.213 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X31Y212 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C clock pessimism -0.144 1.069 SLICE_X31Y212 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.074 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5] ------------------------------------------------------------------- required time -1.074 arrival time 1.293 ------------------------------------------------------------------- slack 0.219 Slack (MET) : 0.219ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.300ns (logic 0.049ns (16.333%) route 0.251ns (83.667%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.213ns Source Clock Delay (SCD): 0.993ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.877ns (routing 0.368ns, distribution 0.509ns) Clock Net Delay (Destination): 1.061ns (routing 0.432ns, distribution 0.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.877 0.993 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X27Y212 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X27Y212 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.042 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.251 1.293 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X31Y212 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.061 1.213 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X31Y212 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C clock pessimism -0.144 1.069 SLICE_X31Y212 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.074 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7] ------------------------------------------------------------------- required time -1.074 arrival time 1.293 ------------------------------------------------------------------- slack 0.219 Slack (MET) : 0.219ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.300ns (logic 0.049ns (16.333%) route 0.251ns (83.667%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.213ns Source Clock Delay (SCD): 0.993ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.877ns (routing 0.368ns, distribution 0.509ns) Clock Net Delay (Destination): 1.061ns (routing 0.432ns, distribution 0.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.877 0.993 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X27Y212 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X27Y212 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.042 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.251 1.293 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X31Y212 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.061 1.213 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X31Y212 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism -0.144 1.069 SLICE_X31Y212 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.074 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time -1.074 arrival time 1.293 ------------------------------------------------------------------- slack 0.219 Slack (MET) : 0.220ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.299ns (logic 0.049ns (16.388%) route 0.250ns (83.612%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.211ns Source Clock Delay (SCD): 0.993ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.877ns (routing 0.368ns, distribution 0.509ns) Clock Net Delay (Destination): 1.059ns (routing 0.432ns, distribution 0.627ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.877 0.993 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X27Y212 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X27Y212 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.042 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.250 1.292 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X32Y212 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.059 1.211 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X32Y212 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism -0.144 1.067 SLICE_X32Y212 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.072 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time -1.072 arrival time 1.292 ------------------------------------------------------------------- slack 0.220 Slack (MET) : 0.220ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.299ns (logic 0.049ns (16.388%) route 0.250ns (83.612%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.211ns Source Clock Delay (SCD): 0.993ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.877ns (routing 0.368ns, distribution 0.509ns) Clock Net Delay (Destination): 1.059ns (routing 0.432ns, distribution 0.627ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.877 0.993 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X27Y212 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X27Y212 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.042 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.250 1.292 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X32Y212 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.059 1.211 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X32Y212 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.144 1.067 SLICE_X32Y212 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.072 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -1.072 arrival time 1.292 ------------------------------------------------------------------- slack 0.220 Slack (MET) : 0.220ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.299ns (logic 0.049ns (16.388%) route 0.250ns (83.612%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.211ns Source Clock Delay (SCD): 0.993ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.877ns (routing 0.368ns, distribution 0.509ns) Clock Net Delay (Destination): 1.059ns (routing 0.432ns, distribution 0.627ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.877 0.993 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X27Y212 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X27Y212 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.042 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.250 1.292 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X32Y212 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y88 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.059 1.211 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X32Y212 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C clock pessimism -0.144 1.067 SLICE_X32Y212 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.072 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20] ------------------------------------------------------------------- required time -1.072 arrival time 1.292 ------------------------------------------------------------------- slack 0.220 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_33 To Clock: gtwiz_userclk_rx_srcclk_out[0]_33 Setup : 0 Failing Endpoints, Worst Slack 4.472ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.142ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.472ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 3.752ns (logic 0.231ns (6.157%) route 3.521ns (93.843%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.035ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.663ns = ( 10.980 - 8.317 ) Source Clock Delay (SCD): 2.836ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.411ns (routing 0.775ns, distribution 1.636ns) Clock Net Delay (Destination): 2.287ns (routing 0.697ns, distribution 1.590ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.411 2.836 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X12Y234 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X12Y234 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.975 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.938 5.913 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X71Y233 LUT2 (Prop_D6LUT_SLICEM_I0_O) 0.092 6.005 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__30/O net (fo=2, routed) 0.583 6.588 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X70Y234 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.287 10.980 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X70Y234 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.208 11.188 clock uncertainty -0.035 11.153 SLICE_X70Y234 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 11.060 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 11.060 arrival time -6.588 ------------------------------------------------------------------- slack 4.472 Slack (MET) : 4.472ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 3.752ns (logic 0.231ns (6.157%) route 3.521ns (93.843%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.035ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.663ns = ( 10.980 - 8.317 ) Source Clock Delay (SCD): 2.836ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.411ns (routing 0.775ns, distribution 1.636ns) Clock Net Delay (Destination): 2.287ns (routing 0.697ns, distribution 1.590ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.411 2.836 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X12Y234 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X12Y234 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.975 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.938 5.913 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X71Y233 LUT2 (Prop_D6LUT_SLICEM_I0_O) 0.092 6.005 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__30/O net (fo=2, routed) 0.583 6.588 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X70Y234 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.287 10.980 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X70Y234 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.208 11.188 clock uncertainty -0.035 11.153 SLICE_X70Y234 FDCE (Recov_EFF2_SLICEM_C_CLR) -0.093 11.060 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 11.060 arrival time -6.588 ------------------------------------------------------------------- slack 4.472 Slack (MET) : 4.711ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 3.512ns (logic 0.362ns (10.308%) route 3.150ns (89.692%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.662ns = ( 10.979 - 8.317 ) Source Clock Delay (SCD): 2.836ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.411ns (routing 0.775ns, distribution 1.636ns) Clock Net Delay (Destination): 2.286ns (routing 0.697ns, distribution 1.589ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.411 2.836 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X12Y234 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X12Y234 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.975 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.561 5.536 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X72Y234 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.759 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/O net (fo=15, routed) 0.589 6.348 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X69Y229 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.286 10.979 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4 SLICE_X69Y229 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/C clock pessimism 0.208 11.187 clock uncertainty -0.035 11.152 SLICE_X69Y229 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.059 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1] ------------------------------------------------------------------- required time 11.059 arrival time -6.348 ------------------------------------------------------------------- slack 4.711 Slack (MET) : 4.711ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 3.512ns (logic 0.362ns (10.308%) route 3.150ns (89.692%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.662ns = ( 10.979 - 8.317 ) Source Clock Delay (SCD): 2.836ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.411ns (routing 0.775ns, distribution 1.636ns) Clock Net Delay (Destination): 2.286ns (routing 0.697ns, distribution 1.589ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.411 2.836 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X12Y234 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X12Y234 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.975 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.561 5.536 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X72Y234 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.759 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/O net (fo=15, routed) 0.589 6.348 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X69Y229 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.286 10.979 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4 SLICE_X69Y229 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/C clock pessimism 0.208 11.187 clock uncertainty -0.035 11.152 SLICE_X69Y229 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 11.059 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2] ------------------------------------------------------------------- required time 11.059 arrival time -6.348 ------------------------------------------------------------------- slack 4.711 Slack (MET) : 4.711ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 3.512ns (logic 0.362ns (10.308%) route 3.150ns (89.692%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.662ns = ( 10.979 - 8.317 ) Source Clock Delay (SCD): 2.836ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.411ns (routing 0.775ns, distribution 1.636ns) Clock Net Delay (Destination): 2.286ns (routing 0.697ns, distribution 1.589ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.411 2.836 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X12Y234 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X12Y234 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.975 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.561 5.536 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X72Y234 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.759 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/O net (fo=15, routed) 0.589 6.348 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X69Y229 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.286 10.979 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4 SLICE_X69Y229 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C clock pessimism 0.208 11.187 clock uncertainty -0.035 11.152 SLICE_X69Y229 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 11.059 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3] ------------------------------------------------------------------- required time 11.059 arrival time -6.348 ------------------------------------------------------------------- slack 4.711 Slack (MET) : 4.711ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 3.512ns (logic 0.362ns (10.308%) route 3.150ns (89.692%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.662ns = ( 10.979 - 8.317 ) Source Clock Delay (SCD): 2.836ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.411ns (routing 0.775ns, distribution 1.636ns) Clock Net Delay (Destination): 2.286ns (routing 0.697ns, distribution 1.589ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.411 2.836 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X12Y234 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X12Y234 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.975 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.561 5.536 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X72Y234 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.759 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/O net (fo=15, routed) 0.589 6.348 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X69Y229 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.286 10.979 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4 SLICE_X69Y229 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/C clock pessimism 0.208 11.187 clock uncertainty -0.035 11.152 SLICE_X69Y229 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.059 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4] ------------------------------------------------------------------- required time 11.059 arrival time -6.348 ------------------------------------------------------------------- slack 4.711 Slack (MET) : 4.741ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 3.483ns (logic 0.362ns (10.393%) route 3.121ns (89.607%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.035ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.663ns = ( 10.980 - 8.317 ) Source Clock Delay (SCD): 2.836ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.411ns (routing 0.775ns, distribution 1.636ns) Clock Net Delay (Destination): 2.287ns (routing 0.697ns, distribution 1.590ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.411 2.836 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X12Y234 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X12Y234 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.975 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.561 5.536 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X72Y234 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.759 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/O net (fo=15, routed) 0.560 6.319 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X69Y235 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.287 10.980 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4 SLICE_X69Y235 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/C clock pessimism 0.208 11.188 clock uncertainty -0.035 11.153 SLICE_X69Y235 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 11.060 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2] ------------------------------------------------------------------- required time 11.060 arrival time -6.319 ------------------------------------------------------------------- slack 4.741 Slack (MET) : 4.741ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 3.483ns (logic 0.362ns (10.393%) route 3.121ns (89.607%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.035ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.663ns = ( 10.980 - 8.317 ) Source Clock Delay (SCD): 2.836ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.411ns (routing 0.775ns, distribution 1.636ns) Clock Net Delay (Destination): 2.287ns (routing 0.697ns, distribution 1.590ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.411 2.836 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X12Y234 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X12Y234 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.975 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.561 5.536 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X72Y234 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.759 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/O net (fo=15, routed) 0.560 6.319 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X69Y235 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.287 10.980 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4 SLICE_X69Y235 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/C clock pessimism 0.208 11.188 clock uncertainty -0.035 11.153 SLICE_X69Y235 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.060 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6] ------------------------------------------------------------------- required time 11.060 arrival time -6.319 ------------------------------------------------------------------- slack 4.741 Slack (MET) : 4.741ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 3.483ns (logic 0.362ns (10.393%) route 3.121ns (89.607%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.035ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.663ns = ( 10.980 - 8.317 ) Source Clock Delay (SCD): 2.836ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.411ns (routing 0.775ns, distribution 1.636ns) Clock Net Delay (Destination): 2.287ns (routing 0.697ns, distribution 1.590ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.411 2.836 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X12Y234 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X12Y234 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.975 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.561 5.536 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X72Y234 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.759 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/O net (fo=15, routed) 0.560 6.319 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X69Y235 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.287 10.980 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4 SLICE_X69Y235 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/C clock pessimism 0.208 11.188 clock uncertainty -0.035 11.153 SLICE_X69Y235 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 11.060 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7] ------------------------------------------------------------------- required time 11.060 arrival time -6.319 ------------------------------------------------------------------- slack 4.741 Slack (MET) : 4.749ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 3.473ns (logic 0.362ns (10.423%) route 3.111ns (89.577%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.033ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.661ns = ( 10.978 - 8.317 ) Source Clock Delay (SCD): 2.836ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.411ns (routing 0.775ns, distribution 1.636ns) Clock Net Delay (Destination): 2.285ns (routing 0.697ns, distribution 1.588ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.411 2.836 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X12Y234 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X12Y234 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.975 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.561 5.536 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X72Y234 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.759 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/O net (fo=15, routed) 0.550 6.309 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X69Y235 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.285 10.978 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4 SLICE_X69Y235 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/C clock pessimism 0.208 11.186 clock uncertainty -0.035 11.151 SLICE_X69Y235 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 11.058 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3] ------------------------------------------------------------------- required time 11.058 arrival time -6.309 ------------------------------------------------------------------- slack 4.749 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.142ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[102]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.180ns (logic 0.049ns (27.222%) route 0.131ns (72.778%)) Logic Levels: 0 Clock Path Skew: 0.033ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.373ns Source Clock Delay (SCD): 1.141ns Clock Pessimism Removal (CPR): 0.199ns Clock Net Delay (Source): 1.025ns (routing 0.369ns, distribution 0.656ns) Clock Net Delay (Destination): 1.221ns (routing 0.431ns, distribution 0.790ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.025 1.141 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X68Y231 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y231 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.190 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.131 1.321 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X67Y231 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[102]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.221 1.373 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X67Y231 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[102]/C clock pessimism -0.199 1.174 SLICE_X67Y231 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.179 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[102] ------------------------------------------------------------------- required time -1.179 arrival time 1.321 ------------------------------------------------------------------- slack 0.142 Slack (MET) : 0.158ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[111]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.213ns (logic 0.049ns (23.005%) route 0.164ns (76.995%)) Logic Levels: 0 Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.381ns Source Clock Delay (SCD): 1.141ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 1.025ns (routing 0.369ns, distribution 0.656ns) Clock Net Delay (Destination): 1.229ns (routing 0.431ns, distribution 0.798ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.025 1.141 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X68Y231 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y231 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.190 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.164 1.354 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X67Y232 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[111]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.229 1.381 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X67Y232 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[111]/C clock pessimism -0.190 1.191 SLICE_X67Y232 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.196 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[111] ------------------------------------------------------------------- required time -1.196 arrival time 1.354 ------------------------------------------------------------------- slack 0.158 Slack (MET) : 0.182ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.261ns (logic 0.048ns (18.391%) route 0.213ns (81.609%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.375ns Source Clock Delay (SCD): 1.144ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.028ns (routing 0.369ns, distribution 0.659ns) Clock Net Delay (Destination): 1.223ns (routing 0.431ns, distribution 0.792ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.028 1.144 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X70Y229 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y229 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.192 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.213 1.405 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X69Y227 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.223 1.375 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X69Y227 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C clock pessimism -0.157 1.218 SLICE_X69Y227 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.223 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5] ------------------------------------------------------------------- required time -1.223 arrival time 1.405 ------------------------------------------------------------------- slack 0.182 Slack (MET) : 0.182ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.261ns (logic 0.048ns (18.391%) route 0.213ns (81.609%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.375ns Source Clock Delay (SCD): 1.144ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.028ns (routing 0.369ns, distribution 0.659ns) Clock Net Delay (Destination): 1.223ns (routing 0.431ns, distribution 0.792ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.028 1.144 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X70Y229 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y229 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.192 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.213 1.405 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X69Y227 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.223 1.375 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X69Y227 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C clock pessimism -0.157 1.218 SLICE_X69Y227 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.223 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7] ------------------------------------------------------------------- required time -1.223 arrival time 1.405 ------------------------------------------------------------------- slack 0.182 Slack (MET) : 0.182ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.261ns (logic 0.048ns (18.391%) route 0.213ns (81.609%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.375ns Source Clock Delay (SCD): 1.144ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.028ns (routing 0.369ns, distribution 0.659ns) Clock Net Delay (Destination): 1.223ns (routing 0.431ns, distribution 0.792ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.028 1.144 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X70Y229 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y229 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.192 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.213 1.405 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X69Y227 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.223 1.375 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X69Y227 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism -0.157 1.218 SLICE_X69Y227 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 1.223 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time -1.223 arrival time 1.405 ------------------------------------------------------------------- slack 0.182 Slack (MET) : 0.184ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[60]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.049ns (19.141%) route 0.207ns (80.859%)) Logic Levels: 0 Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.365ns Source Clock Delay (SCD): 1.141ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.025ns (routing 0.369ns, distribution 0.656ns) Clock Net Delay (Destination): 1.213ns (routing 0.431ns, distribution 0.782ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.025 1.141 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X68Y231 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y231 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.190 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.207 1.397 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X64Y229 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[60]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.213 1.365 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X64Y229 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[60]/C clock pessimism -0.157 1.208 SLICE_X64Y229 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.213 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[60] ------------------------------------------------------------------- required time -1.213 arrival time 1.397 ------------------------------------------------------------------- slack 0.184 Slack (MET) : 0.184ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[63]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.049ns (19.141%) route 0.207ns (80.859%)) Logic Levels: 0 Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.365ns Source Clock Delay (SCD): 1.141ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.025ns (routing 0.369ns, distribution 0.656ns) Clock Net Delay (Destination): 1.213ns (routing 0.431ns, distribution 0.782ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.025 1.141 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X68Y231 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y231 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.190 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.207 1.397 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X64Y229 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[63]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.213 1.365 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X64Y229 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[63]/C clock pessimism -0.157 1.208 SLICE_X64Y229 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.213 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[63] ------------------------------------------------------------------- required time -1.213 arrival time 1.397 ------------------------------------------------------------------- slack 0.184 Slack (MET) : 0.184ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[68]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.049ns (19.141%) route 0.207ns (80.859%)) Logic Levels: 0 Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.365ns Source Clock Delay (SCD): 1.141ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.025ns (routing 0.369ns, distribution 0.656ns) Clock Net Delay (Destination): 1.213ns (routing 0.431ns, distribution 0.782ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.025 1.141 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X68Y231 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y231 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.190 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.207 1.397 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X64Y229 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[68]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.213 1.365 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X64Y229 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[68]/C clock pessimism -0.157 1.208 SLICE_X64Y229 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.213 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[68] ------------------------------------------------------------------- required time -1.213 arrival time 1.397 ------------------------------------------------------------------- slack 0.184 Slack (MET) : 0.184ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[72]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.049ns (19.141%) route 0.207ns (80.859%)) Logic Levels: 0 Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.365ns Source Clock Delay (SCD): 1.141ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.025ns (routing 0.369ns, distribution 0.656ns) Clock Net Delay (Destination): 1.213ns (routing 0.431ns, distribution 0.782ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.025 1.141 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X68Y231 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y231 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.190 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.207 1.397 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X64Y229 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[72]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.213 1.365 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X64Y229 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[72]/C clock pessimism -0.157 1.208 SLICE_X64Y229 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.213 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[72] ------------------------------------------------------------------- required time -1.213 arrival time 1.397 ------------------------------------------------------------------- slack 0.184 Slack (MET) : 0.184ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[60]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.049ns (19.141%) route 0.207ns (80.859%)) Logic Levels: 0 Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.365ns Source Clock Delay (SCD): 1.141ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.025ns (routing 0.369ns, distribution 0.656ns) Clock Net Delay (Destination): 1.213ns (routing 0.431ns, distribution 0.782ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.025 1.141 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X68Y231 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y231 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.190 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.207 1.397 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X64Y229 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[60]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y89 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.213 1.365 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X64Y229 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[60]/C clock pessimism -0.157 1.208 SLICE_X64Y229 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.213 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[60] ------------------------------------------------------------------- required time -1.213 arrival time 1.397 ------------------------------------------------------------------- slack 0.184 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_34 To Clock: gtwiz_userclk_rx_srcclk_out[0]_34 Setup : 0 Failing Endpoints, Worst Slack 4.906ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.115ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.906ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 2.946ns (logic 0.285ns (9.674%) route 2.661ns (90.326%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.337ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.332ns = ( 10.649 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.446ns (routing 0.762ns, distribution 1.684ns) Clock Net Delay (Destination): 1.956ns (routing 0.684ns, distribution 1.272ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.446 2.871 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X2Y248 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X2Y248 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.727 4.737 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X35Y253 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.146 4.883 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/O net (fo=15, routed) 0.934 5.817 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X36Y255 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.956 10.649 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 SLICE_X36Y255 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/C clock pessimism 0.202 10.851 clock uncertainty -0.035 10.816 SLICE_X36Y255 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.723 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6] ------------------------------------------------------------------- required time 10.723 arrival time -5.817 ------------------------------------------------------------------- slack 4.906 Slack (MET) : 4.906ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 2.946ns (logic 0.285ns (9.674%) route 2.661ns (90.326%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.337ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.332ns = ( 10.649 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.446ns (routing 0.762ns, distribution 1.684ns) Clock Net Delay (Destination): 1.956ns (routing 0.684ns, distribution 1.272ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.446 2.871 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X2Y248 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X2Y248 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.727 4.737 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X35Y253 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.146 4.883 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/O net (fo=15, routed) 0.934 5.817 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X36Y255 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.956 10.649 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 SLICE_X36Y255 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/C clock pessimism 0.202 10.851 clock uncertainty -0.035 10.816 SLICE_X36Y255 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.723 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7] ------------------------------------------------------------------- required time 10.723 arrival time -5.817 ------------------------------------------------------------------- slack 4.906 Slack (MET) : 4.914ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 2.936ns (logic 0.285ns (9.707%) route 2.651ns (90.293%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.339ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.330ns = ( 10.647 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.446ns (routing 0.762ns, distribution 1.684ns) Clock Net Delay (Destination): 1.954ns (routing 0.684ns, distribution 1.270ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.446 2.871 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X2Y248 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X2Y248 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.727 4.737 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X35Y253 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.146 4.883 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/O net (fo=15, routed) 0.924 5.807 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X36Y255 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.954 10.647 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 SLICE_X36Y255 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/C clock pessimism 0.202 10.849 clock uncertainty -0.035 10.814 SLICE_X36Y255 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.721 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3] ------------------------------------------------------------------- required time 10.721 arrival time -5.807 ------------------------------------------------------------------- slack 4.914 Slack (MET) : 4.914ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 2.936ns (logic 0.285ns (9.707%) route 2.651ns (90.293%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.339ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.330ns = ( 10.647 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.446ns (routing 0.762ns, distribution 1.684ns) Clock Net Delay (Destination): 1.954ns (routing 0.684ns, distribution 1.270ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.446 2.871 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X2Y248 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X2Y248 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.727 4.737 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X35Y253 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.146 4.883 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/O net (fo=15, routed) 0.924 5.807 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X36Y255 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.954 10.647 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 SLICE_X36Y255 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/C clock pessimism 0.202 10.849 clock uncertainty -0.035 10.814 SLICE_X36Y255 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 10.721 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4] ------------------------------------------------------------------- required time 10.721 arrival time -5.807 ------------------------------------------------------------------- slack 4.914 Slack (MET) : 5.045ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 2.807ns (logic 0.285ns (10.153%) route 2.522ns (89.847%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.337ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.332ns = ( 10.649 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.446ns (routing 0.762ns, distribution 1.684ns) Clock Net Delay (Destination): 1.956ns (routing 0.684ns, distribution 1.272ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.446 2.871 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X2Y248 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X2Y248 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.727 4.737 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X35Y253 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.146 4.883 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/O net (fo=15, routed) 0.795 5.678 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X35Y254 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.956 10.649 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 SLICE_X35Y254 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/C clock pessimism 0.202 10.851 clock uncertainty -0.035 10.816 SLICE_X35Y254 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.723 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8] ------------------------------------------------------------------- required time 10.723 arrival time -5.678 ------------------------------------------------------------------- slack 5.045 Slack (MET) : 5.050ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 2.800ns (logic 0.285ns (10.179%) route 2.515ns (89.821%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.339ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.330ns = ( 10.647 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.446ns (routing 0.762ns, distribution 1.684ns) Clock Net Delay (Destination): 1.954ns (routing 0.684ns, distribution 1.270ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.446 2.871 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X2Y248 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X2Y248 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.727 4.737 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X35Y253 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.146 4.883 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/O net (fo=15, routed) 0.788 5.671 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X35Y254 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.954 10.647 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 SLICE_X35Y254 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/C clock pessimism 0.202 10.849 clock uncertainty -0.035 10.814 SLICE_X35Y254 FDCE (Recov_GFF_SLICEM_C_CLR) -0.093 10.721 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0] ------------------------------------------------------------------- required time 10.721 arrival time -5.671 ------------------------------------------------------------------- slack 5.050 Slack (MET) : 5.050ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 2.800ns (logic 0.285ns (10.179%) route 2.515ns (89.821%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.339ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.330ns = ( 10.647 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.446ns (routing 0.762ns, distribution 1.684ns) Clock Net Delay (Destination): 1.954ns (routing 0.684ns, distribution 1.270ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.446 2.871 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X2Y248 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X2Y248 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.727 4.737 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X35Y253 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.146 4.883 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/O net (fo=15, routed) 0.788 5.671 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X35Y254 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.954 10.647 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 SLICE_X35Y254 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/C clock pessimism 0.202 10.849 clock uncertainty -0.035 10.814 SLICE_X35Y254 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 10.721 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5] ------------------------------------------------------------------- required time 10.721 arrival time -5.671 ------------------------------------------------------------------- slack 5.050 Slack (MET) : 5.050ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 2.800ns (logic 0.285ns (10.179%) route 2.515ns (89.821%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.339ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.330ns = ( 10.647 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.446ns (routing 0.762ns, distribution 1.684ns) Clock Net Delay (Destination): 1.954ns (routing 0.684ns, distribution 1.270ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.446 2.871 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X2Y248 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X2Y248 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.727 4.737 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X35Y253 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.146 4.883 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/O net (fo=15, routed) 0.788 5.671 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X35Y254 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.954 10.647 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 SLICE_X35Y254 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0]/C clock pessimism 0.202 10.849 clock uncertainty -0.035 10.814 SLICE_X35Y254 FDCE (Recov_HFF2_SLICEM_C_CLR) -0.093 10.721 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0] ------------------------------------------------------------------- required time 10.721 arrival time -5.671 ------------------------------------------------------------------- slack 5.050 Slack (MET) : 5.157ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 2.688ns (logic 0.286ns (10.640%) route 2.402ns (89.360%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.344ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.325ns = ( 10.642 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.446ns (routing 0.762ns, distribution 1.684ns) Clock Net Delay (Destination): 1.949ns (routing 0.684ns, distribution 1.265ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.446 2.871 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X2Y248 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X2Y248 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.817 4.827 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X36Y249 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.147 4.974 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__31/O net (fo=2, routed) 0.585 5.559 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X36Y247 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.949 10.642 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK SLICE_X36Y247 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.202 10.844 clock uncertainty -0.035 10.809 SLICE_X36Y247 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 10.716 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 10.716 arrival time -5.559 ------------------------------------------------------------------- slack 5.157 Slack (MET) : 5.157ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 2.688ns (logic 0.286ns (10.640%) route 2.402ns (89.360%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.344ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.325ns = ( 10.642 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.446ns (routing 0.762ns, distribution 1.684ns) Clock Net Delay (Destination): 1.949ns (routing 0.684ns, distribution 1.265ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.446 2.871 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X2Y248 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X2Y248 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.817 4.827 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X36Y249 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.147 4.974 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__31/O net (fo=2, routed) 0.585 5.559 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X36Y247 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.949 10.642 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK SLICE_X36Y247 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.202 10.844 clock uncertainty -0.035 10.809 SLICE_X36Y247 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 10.716 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 10.716 arrival time -5.559 ------------------------------------------------------------------- slack 5.157 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.115ns (arrival time - required time) Source: SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.197ns (logic 0.048ns (24.365%) route 0.149ns (75.634%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.215ns Source Clock Delay (SCD): 0.998ns Clock Pessimism Removal (CPR): 0.140ns Clock Net Delay (Source): 0.882ns (routing 0.365ns, distribution 0.517ns) Clock Net Delay (Destination): 1.063ns (routing 0.426ns, distribution 0.637ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.882 0.998 SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y242 FDPE r SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y242 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.046 f SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.149 1.195 SFP_GEN[32].ngCCM_gbt/sync_m_reg[3][0] SLICE_X34Y242 FDCE f SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.063 1.215 SFP_GEN[32].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X34Y242 FDCE r SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[36]/C clock pessimism -0.140 1.075 SLICE_X34Y242 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.080 SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[36] ------------------------------------------------------------------- required time -1.080 arrival time 1.195 ------------------------------------------------------------------- slack 0.115 Slack (MET) : 0.115ns (arrival time - required time) Source: SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.197ns (logic 0.048ns (24.365%) route 0.149ns (75.634%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.215ns Source Clock Delay (SCD): 0.998ns Clock Pessimism Removal (CPR): 0.140ns Clock Net Delay (Source): 0.882ns (routing 0.365ns, distribution 0.517ns) Clock Net Delay (Destination): 1.063ns (routing 0.426ns, distribution 0.637ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.882 0.998 SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y242 FDPE r SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y242 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.046 f SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.149 1.195 SFP_GEN[32].ngCCM_gbt/sync_m_reg[3][0] SLICE_X34Y242 FDCE f SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.063 1.215 SFP_GEN[32].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X34Y242 FDCE r SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[38]/C clock pessimism -0.140 1.075 SLICE_X34Y242 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.080 SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[38] ------------------------------------------------------------------- required time -1.080 arrival time 1.195 ------------------------------------------------------------------- slack 0.115 Slack (MET) : 0.191ns (arrival time - required time) Source: SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[32].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.048ns (18.113%) route 0.217ns (81.887%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.207ns Source Clock Delay (SCD): 0.998ns Clock Pessimism Removal (CPR): 0.140ns Clock Net Delay (Source): 0.882ns (routing 0.365ns, distribution 0.517ns) Clock Net Delay (Destination): 1.055ns (routing 0.426ns, distribution 0.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.882 0.998 SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y242 FDPE r SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y242 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.046 f SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.217 1.263 SFP_GEN[32].ngCCM_gbt/sync_m_reg[3][0] SLICE_X34Y241 FDCE f SFP_GEN[32].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.055 1.207 SFP_GEN[32].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X34Y241 FDCE r SFP_GEN[32].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.140 1.067 SLICE_X34Y241 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.072 SFP_GEN[32].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.072 arrival time 1.263 ------------------------------------------------------------------- slack 0.191 Slack (MET) : 0.193ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.275ns (logic 0.049ns (17.818%) route 0.226ns (82.182%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.208ns Source Clock Delay (SCD): 0.991ns Clock Pessimism Removal (CPR): 0.140ns Clock Net Delay (Source): 0.875ns (routing 0.365ns, distribution 0.510ns) Clock Net Delay (Destination): 1.056ns (routing 0.426ns, distribution 0.630ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.875 0.991 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK SLICE_X37Y246 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X37Y246 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.040 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.226 1.266 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X35Y252 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.056 1.208 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y252 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.140 1.068 SLICE_X35Y252 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.073 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -1.073 arrival time 1.266 ------------------------------------------------------------------- slack 0.193 Slack (MET) : 0.202ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.049ns (18.846%) route 0.211ns (81.154%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.207ns Source Clock Delay (SCD): 1.014ns Clock Pessimism Removal (CPR): 0.140ns Clock Net Delay (Source): 0.898ns (routing 0.365ns, distribution 0.533ns) Clock Net Delay (Destination): 1.055ns (routing 0.426ns, distribution 0.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.898 1.014 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X29Y244 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X29Y244 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.063 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.211 1.274 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X33Y244 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.055 1.207 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X33Y244 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C clock pessimism -0.140 1.067 SLICE_X33Y244 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.072 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13] ------------------------------------------------------------------- required time -1.072 arrival time 1.274 ------------------------------------------------------------------- slack 0.202 Slack (MET) : 0.202ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.049ns (18.846%) route 0.211ns (81.154%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.207ns Source Clock Delay (SCD): 1.014ns Clock Pessimism Removal (CPR): 0.140ns Clock Net Delay (Source): 0.898ns (routing 0.365ns, distribution 0.533ns) Clock Net Delay (Destination): 1.055ns (routing 0.426ns, distribution 0.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.898 1.014 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X29Y244 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X29Y244 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.063 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.211 1.274 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X33Y244 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.055 1.207 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X33Y244 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C clock pessimism -0.140 1.067 SLICE_X33Y244 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.072 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time -1.072 arrival time 1.274 ------------------------------------------------------------------- slack 0.202 Slack (MET) : 0.202ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.049ns (18.846%) route 0.211ns (81.154%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.207ns Source Clock Delay (SCD): 1.014ns Clock Pessimism Removal (CPR): 0.140ns Clock Net Delay (Source): 0.898ns (routing 0.365ns, distribution 0.533ns) Clock Net Delay (Destination): 1.055ns (routing 0.426ns, distribution 0.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.898 1.014 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X29Y244 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X29Y244 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.063 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.211 1.274 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X33Y244 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.055 1.207 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X33Y244 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism -0.140 1.067 SLICE_X33Y244 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.072 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time -1.072 arrival time 1.274 ------------------------------------------------------------------- slack 0.202 Slack (MET) : 0.202ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.049ns (18.846%) route 0.211ns (81.154%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.207ns Source Clock Delay (SCD): 1.014ns Clock Pessimism Removal (CPR): 0.140ns Clock Net Delay (Source): 0.898ns (routing 0.365ns, distribution 0.533ns) Clock Net Delay (Destination): 1.055ns (routing 0.426ns, distribution 0.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.898 1.014 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X29Y244 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X29Y244 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.063 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.211 1.274 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X33Y244 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.055 1.207 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X33Y244 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C clock pessimism -0.140 1.067 SLICE_X33Y244 FDCE (Remov_FFF2_SLICEL_C_CLR) 0.005 1.072 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5] ------------------------------------------------------------------- required time -1.072 arrival time 1.274 ------------------------------------------------------------------- slack 0.202 Slack (MET) : 0.202ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.049ns (18.846%) route 0.211ns (81.154%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.207ns Source Clock Delay (SCD): 1.014ns Clock Pessimism Removal (CPR): 0.140ns Clock Net Delay (Source): 0.898ns (routing 0.365ns, distribution 0.533ns) Clock Net Delay (Destination): 1.055ns (routing 0.426ns, distribution 0.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.898 1.014 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X29Y244 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X29Y244 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.063 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.211 1.274 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X33Y244 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.055 1.207 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X33Y244 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C clock pessimism -0.140 1.067 SLICE_X33Y244 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 1.072 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7] ------------------------------------------------------------------- required time -1.072 arrival time 1.274 ------------------------------------------------------------------- slack 0.202 Slack (MET) : 0.202ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.049ns (18.846%) route 0.211ns (81.154%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.207ns Source Clock Delay (SCD): 1.014ns Clock Pessimism Removal (CPR): 0.140ns Clock Net Delay (Source): 0.898ns (routing 0.365ns, distribution 0.533ns) Clock Net Delay (Destination): 1.055ns (routing 0.426ns, distribution 0.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.898 1.014 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X29Y244 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X29Y244 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.063 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.211 1.274 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X33Y244 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y113 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.055 1.207 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X33Y244 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism -0.140 1.067 SLICE_X33Y244 FDCE (Remov_GFF2_SLICEL_C_CLR) 0.005 1.072 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time -1.072 arrival time 1.274 ------------------------------------------------------------------- slack 0.202 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_35 To Clock: gtwiz_userclk_rx_srcclk_out[0]_35 Setup : 0 Failing Endpoints, Worst Slack 4.305ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.122ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.305ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 3.907ns (logic 0.285ns (7.295%) route 3.622ns (92.705%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.023ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.668ns = ( 10.985 - 8.317 ) Source Clock Delay (SCD): 2.856ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.431ns (routing 0.777ns, distribution 1.654ns) Clock Net Delay (Destination): 2.292ns (routing 0.696ns, distribution 1.596ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.431 2.856 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y262 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y262 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.995 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.752 5.747 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X66Y254 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 5.893 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/O net (fo=15, routed) 0.870 6.763 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X70Y253 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.292 10.985 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 SLICE_X70Y253 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/C clock pessimism 0.211 11.196 clock uncertainty -0.035 11.161 SLICE_X70Y253 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.068 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6] ------------------------------------------------------------------- required time 11.068 arrival time -6.763 ------------------------------------------------------------------- slack 4.305 Slack (MET) : 4.305ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 3.907ns (logic 0.285ns (7.295%) route 3.622ns (92.705%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.023ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.668ns = ( 10.985 - 8.317 ) Source Clock Delay (SCD): 2.856ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.431ns (routing 0.777ns, distribution 1.654ns) Clock Net Delay (Destination): 2.292ns (routing 0.696ns, distribution 1.596ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.431 2.856 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y262 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y262 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.995 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.752 5.747 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X66Y254 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 5.893 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/O net (fo=15, routed) 0.870 6.763 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X70Y253 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.292 10.985 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 SLICE_X70Y253 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/C clock pessimism 0.211 11.196 clock uncertainty -0.035 11.161 SLICE_X70Y253 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.068 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7] ------------------------------------------------------------------- required time 11.068 arrival time -6.763 ------------------------------------------------------------------- slack 4.305 Slack (MET) : 4.310ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 3.900ns (logic 0.285ns (7.308%) route 3.615ns (92.692%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.666ns = ( 10.983 - 8.317 ) Source Clock Delay (SCD): 2.856ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.431ns (routing 0.777ns, distribution 1.654ns) Clock Net Delay (Destination): 2.290ns (routing 0.696ns, distribution 1.594ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.431 2.856 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y262 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y262 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.995 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.752 5.747 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X66Y254 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 5.893 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/O net (fo=15, routed) 0.863 6.756 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X70Y253 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.290 10.983 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 SLICE_X70Y253 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/C clock pessimism 0.211 11.194 clock uncertainty -0.035 11.159 SLICE_X70Y253 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.066 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4] ------------------------------------------------------------------- required time 11.066 arrival time -6.756 ------------------------------------------------------------------- slack 4.310 Slack (MET) : 4.310ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 3.900ns (logic 0.285ns (7.308%) route 3.615ns (92.692%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.666ns = ( 10.983 - 8.317 ) Source Clock Delay (SCD): 2.856ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.431ns (routing 0.777ns, distribution 1.654ns) Clock Net Delay (Destination): 2.290ns (routing 0.696ns, distribution 1.594ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.431 2.856 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y262 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y262 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.995 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.752 5.747 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X66Y254 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 5.893 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/O net (fo=15, routed) 0.863 6.756 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X70Y253 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.290 10.983 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 SLICE_X70Y253 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/C clock pessimism 0.211 11.194 clock uncertainty -0.035 11.159 SLICE_X70Y253 FDCE (Recov_GFF_SLICEM_C_CLR) -0.093 11.066 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5] ------------------------------------------------------------------- required time 11.066 arrival time -6.756 ------------------------------------------------------------------- slack 4.310 Slack (MET) : 4.353ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 3.857ns (logic 0.285ns (7.389%) route 3.572ns (92.611%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.666ns = ( 10.983 - 8.317 ) Source Clock Delay (SCD): 2.856ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.431ns (routing 0.777ns, distribution 1.654ns) Clock Net Delay (Destination): 2.290ns (routing 0.696ns, distribution 1.594ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.431 2.856 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y262 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y262 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.995 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.752 5.747 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X66Y254 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 5.893 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/O net (fo=15, routed) 0.820 6.713 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X70Y254 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.290 10.983 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 SLICE_X70Y254 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/C clock pessimism 0.211 11.194 clock uncertainty -0.035 11.159 SLICE_X70Y254 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.066 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9] ------------------------------------------------------------------- required time 11.066 arrival time -6.713 ------------------------------------------------------------------- slack 4.353 Slack (MET) : 4.353ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 3.857ns (logic 0.285ns (7.389%) route 3.572ns (92.611%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.666ns = ( 10.983 - 8.317 ) Source Clock Delay (SCD): 2.856ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.431ns (routing 0.777ns, distribution 1.654ns) Clock Net Delay (Destination): 2.290ns (routing 0.696ns, distribution 1.594ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.431 2.856 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y262 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y262 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.995 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.752 5.747 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X66Y254 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 5.893 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/O net (fo=15, routed) 0.820 6.713 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X70Y254 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.290 10.983 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 SLICE_X70Y254 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/C clock pessimism 0.211 11.194 clock uncertainty -0.035 11.159 SLICE_X70Y254 FDCE (Recov_HFF2_SLICEM_C_CLR) -0.093 11.066 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0] ------------------------------------------------------------------- required time 11.066 arrival time -6.713 ------------------------------------------------------------------- slack 4.353 Slack (MET) : 4.462ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 3.743ns (logic 0.362ns (9.671%) route 3.381ns (90.329%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.016ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.661ns = ( 10.978 - 8.317 ) Source Clock Delay (SCD): 2.856ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.431ns (routing 0.777ns, distribution 1.654ns) Clock Net Delay (Destination): 2.285ns (routing 0.696ns, distribution 1.589ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.431 2.856 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y262 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y262 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.995 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.884 5.879 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X68Y254 LUT2 (Prop_D6LUT_SLICEL_I0_O) 0.223 6.102 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__32/O net (fo=2, routed) 0.497 6.599 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X68Y253 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.285 10.978 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X68Y253 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.211 11.189 clock uncertainty -0.035 11.154 SLICE_X68Y253 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.061 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 11.061 arrival time -6.599 ------------------------------------------------------------------- slack 4.462 Slack (MET) : 4.462ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 3.743ns (logic 0.362ns (9.671%) route 3.381ns (90.329%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.016ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.661ns = ( 10.978 - 8.317 ) Source Clock Delay (SCD): 2.856ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.431ns (routing 0.777ns, distribution 1.654ns) Clock Net Delay (Destination): 2.285ns (routing 0.696ns, distribution 1.589ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.431 2.856 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y262 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y262 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.995 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.884 5.879 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X68Y254 LUT2 (Prop_D6LUT_SLICEL_I0_O) 0.223 6.102 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__32/O net (fo=2, routed) 0.497 6.599 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X68Y253 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.285 10.978 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X68Y253 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.211 11.189 clock uncertainty -0.035 11.154 SLICE_X68Y253 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 11.061 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 11.061 arrival time -6.599 ------------------------------------------------------------------- slack 4.462 Slack (MET) : 4.584ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 3.616ns (logic 0.285ns (7.882%) route 3.331ns (92.118%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.656ns = ( 10.973 - 8.317 ) Source Clock Delay (SCD): 2.856ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.431ns (routing 0.777ns, distribution 1.654ns) Clock Net Delay (Destination): 2.280ns (routing 0.696ns, distribution 1.584ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.431 2.856 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y262 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y262 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.995 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.752 5.747 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X66Y254 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 5.893 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/O net (fo=15, routed) 0.579 6.472 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X69Y253 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.280 10.973 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 SLICE_X69Y253 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/C clock pessimism 0.211 11.184 clock uncertainty -0.035 11.149 SLICE_X69Y253 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 11.056 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1] ------------------------------------------------------------------- required time 11.056 arrival time -6.472 ------------------------------------------------------------------- slack 4.584 Slack (MET) : 4.584ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 3.616ns (logic 0.285ns (7.882%) route 3.331ns (92.118%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.656ns = ( 10.973 - 8.317 ) Source Clock Delay (SCD): 2.856ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.431ns (routing 0.777ns, distribution 1.654ns) Clock Net Delay (Destination): 2.280ns (routing 0.696ns, distribution 1.584ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.431 2.856 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y262 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y262 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.995 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.752 5.747 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X66Y254 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 5.893 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/O net (fo=15, routed) 0.579 6.472 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X69Y253 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.280 10.973 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 SLICE_X69Y253 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/C clock pessimism 0.211 11.184 clock uncertainty -0.035 11.149 SLICE_X69Y253 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 11.056 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2] ------------------------------------------------------------------- required time 11.056 arrival time -6.472 ------------------------------------------------------------------- slack 4.584 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.122ns (arrival time - required time) Source: SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.201ns (logic 0.048ns (23.881%) route 0.153ns (76.119%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.378ns Source Clock Delay (SCD): 1.148ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.032ns (routing 0.372ns, distribution 0.660ns) Clock Net Delay (Destination): 1.226ns (routing 0.435ns, distribution 0.791ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.032 1.148 SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X70Y256 FDPE r SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X70Y256 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.196 f SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.153 1.349 SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] SLICE_X69Y256 FDCE f SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.226 1.378 SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y256 FDCE r SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[32]/C clock pessimism -0.156 1.222 SLICE_X69Y256 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 1.227 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[32] ------------------------------------------------------------------- required time -1.227 arrival time 1.349 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.201ns (logic 0.048ns (23.881%) route 0.153ns (76.119%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.378ns Source Clock Delay (SCD): 1.148ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.032ns (routing 0.372ns, distribution 0.660ns) Clock Net Delay (Destination): 1.226ns (routing 0.435ns, distribution 0.791ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.032 1.148 SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X70Y256 FDPE r SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X70Y256 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.196 f SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.153 1.349 SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] SLICE_X69Y256 FDCE f SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.226 1.378 SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y256 FDCE r SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[34]/C clock pessimism -0.156 1.222 SLICE_X69Y256 FDCE (Remov_DFF2_SLICEL_C_CLR) 0.005 1.227 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[34] ------------------------------------------------------------------- required time -1.227 arrival time 1.349 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.201ns (logic 0.048ns (23.881%) route 0.153ns (76.119%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.378ns Source Clock Delay (SCD): 1.148ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.032ns (routing 0.372ns, distribution 0.660ns) Clock Net Delay (Destination): 1.226ns (routing 0.435ns, distribution 0.791ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.032 1.148 SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X70Y256 FDPE r SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X70Y256 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.196 f SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.153 1.349 SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] SLICE_X69Y256 FDCE f SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.226 1.378 SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y256 FDCE r SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[36]/C clock pessimism -0.156 1.222 SLICE_X69Y256 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 1.227 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[36] ------------------------------------------------------------------- required time -1.227 arrival time 1.349 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.201ns (logic 0.048ns (23.881%) route 0.153ns (76.119%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.378ns Source Clock Delay (SCD): 1.148ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.032ns (routing 0.372ns, distribution 0.660ns) Clock Net Delay (Destination): 1.226ns (routing 0.435ns, distribution 0.791ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.032 1.148 SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X70Y256 FDPE r SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X70Y256 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.196 f SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.153 1.349 SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] SLICE_X69Y256 FDCE f SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.226 1.378 SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y256 FDCE r SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[38]/C clock pessimism -0.156 1.222 SLICE_X69Y256 FDCE (Remov_CFF2_SLICEL_C_CLR) 0.005 1.227 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[38] ------------------------------------------------------------------- required time -1.227 arrival time 1.349 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.156ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.243ns (logic 0.049ns (20.165%) route 0.194ns (79.835%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.379ns Source Clock Delay (SCD): 1.141ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.025ns (routing 0.372ns, distribution 0.653ns) Clock Net Delay (Destination): 1.227ns (routing 0.435ns, distribution 0.792ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.025 1.141 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X65Y258 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y258 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.190 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.194 1.384 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X63Y258 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.227 1.379 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X63Y258 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C clock pessimism -0.156 1.223 SLICE_X63Y258 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.228 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time -1.228 arrival time 1.384 ------------------------------------------------------------------- slack 0.156 Slack (MET) : 0.156ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.243ns (logic 0.049ns (20.165%) route 0.194ns (79.835%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.379ns Source Clock Delay (SCD): 1.141ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.025ns (routing 0.372ns, distribution 0.653ns) Clock Net Delay (Destination): 1.227ns (routing 0.435ns, distribution 0.792ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.025 1.141 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X65Y258 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y258 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.190 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.194 1.384 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X63Y258 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.227 1.379 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X63Y258 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.156 1.223 SLICE_X63Y258 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.228 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -1.228 arrival time 1.384 ------------------------------------------------------------------- slack 0.156 Slack (MET) : 0.156ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.243ns (logic 0.049ns (20.165%) route 0.194ns (79.835%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.379ns Source Clock Delay (SCD): 1.141ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.025ns (routing 0.372ns, distribution 0.653ns) Clock Net Delay (Destination): 1.227ns (routing 0.435ns, distribution 0.792ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.025 1.141 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X65Y258 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y258 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.190 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.194 1.384 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X63Y258 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.227 1.379 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X63Y258 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C clock pessimism -0.156 1.223 SLICE_X63Y258 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.228 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19] ------------------------------------------------------------------- required time -1.228 arrival time 1.384 ------------------------------------------------------------------- slack 0.156 Slack (MET) : 0.173ns (arrival time - required time) Source: SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[33].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.222ns (logic 0.048ns (21.622%) route 0.174ns (78.378%)) Logic Levels: 0 Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.383ns Source Clock Delay (SCD): 1.148ns Clock Pessimism Removal (CPR): 0.191ns Clock Net Delay (Source): 1.032ns (routing 0.372ns, distribution 0.660ns) Clock Net Delay (Destination): 1.231ns (routing 0.435ns, distribution 0.796ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.032 1.148 SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X70Y256 FDPE r SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X70Y256 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.196 f SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.174 1.370 SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] SLICE_X70Y254 FDCE f SFP_GEN[33].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.231 1.383 SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X70Y254 FDCE r SFP_GEN[33].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.191 1.192 SLICE_X70Y254 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.197 SFP_GEN[33].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.197 arrival time 1.370 ------------------------------------------------------------------- slack 0.173 Slack (MET) : 0.195ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.274ns (logic 0.049ns (17.883%) route 0.225ns (82.117%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.371ns Source Clock Delay (SCD): 1.141ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.025ns (routing 0.372ns, distribution 0.653ns) Clock Net Delay (Destination): 1.219ns (routing 0.435ns, distribution 0.784ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.025 1.141 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X65Y258 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y258 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.190 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.225 1.415 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X69Y260 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.219 1.371 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X69Y260 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C clock pessimism -0.156 1.215 SLICE_X69Y260 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.220 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time -1.220 arrival time 1.415 ------------------------------------------------------------------- slack 0.195 Slack (MET) : 0.195ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.274ns (logic 0.049ns (17.883%) route 0.225ns (82.117%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.371ns Source Clock Delay (SCD): 1.141ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.025ns (routing 0.372ns, distribution 0.653ns) Clock Net Delay (Destination): 1.219ns (routing 0.435ns, distribution 0.784ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.025 1.141 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X65Y258 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y258 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.190 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.225 1.415 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X69Y260 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y117 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.219 1.371 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X69Y260 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C clock pessimism -0.156 1.215 SLICE_X69Y260 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.220 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time -1.220 arrival time 1.415 ------------------------------------------------------------------- slack 0.195 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_36 To Clock: gtwiz_userclk_rx_srcclk_out[0]_36 Setup : 0 Failing Endpoints, Worst Slack 3.370ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.100ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.370ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 4.474ns (logic 0.382ns (8.538%) route 4.092ns (91.462%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.345ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.349ns = ( 10.666 - 8.317 ) Source Clock Delay (SCD): 2.899ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.474ns (routing 0.794ns, distribution 1.680ns) Clock Net Delay (Destination): 1.973ns (routing 0.710ns, distribution 1.263ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.474 2.899 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y423 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.038 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.908 5.946 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X49Y420 LUT2 (Prop_A6LUT_SLICEM_I0_O) 0.243 6.189 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__35/O net (fo=2, routed) 1.184 7.373 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_1 SLICE_X47Y425 FDCE f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.973 10.666 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X47Y425 FDCE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.205 10.871 clock uncertainty -0.035 10.836 SLICE_X47Y425 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 10.743 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 10.743 arrival time -7.373 ------------------------------------------------------------------- slack 3.370 Slack (MET) : 3.370ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 4.474ns (logic 0.382ns (8.538%) route 4.092ns (91.462%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.345ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.349ns = ( 10.666 - 8.317 ) Source Clock Delay (SCD): 2.899ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.474ns (routing 0.794ns, distribution 1.680ns) Clock Net Delay (Destination): 1.973ns (routing 0.710ns, distribution 1.263ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.474 2.899 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y423 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.038 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.908 5.946 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X49Y420 LUT2 (Prop_A6LUT_SLICEM_I0_O) 0.243 6.189 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__35/O net (fo=2, routed) 1.184 7.373 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_1 SLICE_X47Y425 FDCE f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.973 10.666 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X47Y425 FDCE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.205 10.871 clock uncertainty -0.035 10.836 SLICE_X47Y425 FDCE (Recov_EFF2_SLICEM_C_CLR) -0.093 10.743 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 10.743 arrival time -7.373 ------------------------------------------------------------------- slack 3.370 Slack (MET) : 3.944ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 4.201ns (logic 0.382ns (9.093%) route 3.819ns (90.907%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.044ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.643ns = ( 10.960 - 8.317 ) Source Clock Delay (SCD): 2.899ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.474ns (routing 0.794ns, distribution 1.680ns) Clock Net Delay (Destination): 2.267ns (routing 0.710ns, distribution 1.557ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.474 2.899 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y423 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.038 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.912 5.950 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X49Y420 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.243 6.193 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/O net (fo=15, routed) 0.907 7.100 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X49Y426 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.267 10.960 g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X49Y426 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/C clock pessimism 0.212 11.172 clock uncertainty -0.035 11.137 SLICE_X49Y426 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.044 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3] ------------------------------------------------------------------- required time 11.044 arrival time -7.100 ------------------------------------------------------------------- slack 3.944 Slack (MET) : 3.944ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 4.201ns (logic 0.382ns (9.093%) route 3.819ns (90.907%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.044ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.643ns = ( 10.960 - 8.317 ) Source Clock Delay (SCD): 2.899ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.474ns (routing 0.794ns, distribution 1.680ns) Clock Net Delay (Destination): 2.267ns (routing 0.710ns, distribution 1.557ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.474 2.899 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y423 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.038 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.912 5.950 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X49Y420 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.243 6.193 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/O net (fo=15, routed) 0.907 7.100 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X49Y426 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.267 10.960 g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X49Y426 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/C clock pessimism 0.212 11.172 clock uncertainty -0.035 11.137 SLICE_X49Y426 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.044 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4] ------------------------------------------------------------------- required time 11.044 arrival time -7.100 ------------------------------------------------------------------- slack 3.944 Slack (MET) : 4.406ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 3.748ns (logic 0.382ns (10.192%) route 3.366ns (89.808%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.035ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.652ns = ( 10.969 - 8.317 ) Source Clock Delay (SCD): 2.899ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.474ns (routing 0.794ns, distribution 1.680ns) Clock Net Delay (Destination): 2.276ns (routing 0.710ns, distribution 1.566ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.474 2.899 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y423 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.038 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.912 5.950 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X49Y420 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.243 6.193 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/O net (fo=15, routed) 0.454 6.647 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X49Y421 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.276 10.969 g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X49Y421 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/C clock pessimism 0.212 11.181 clock uncertainty -0.035 11.146 SLICE_X49Y421 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.053 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0] ------------------------------------------------------------------- required time 11.053 arrival time -6.647 ------------------------------------------------------------------- slack 4.406 Slack (MET) : 4.406ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 3.749ns (logic 0.382ns (10.189%) route 3.367ns (89.811%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.653ns = ( 10.970 - 8.317 ) Source Clock Delay (SCD): 2.899ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.474ns (routing 0.794ns, distribution 1.680ns) Clock Net Delay (Destination): 2.277ns (routing 0.710ns, distribution 1.567ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.474 2.899 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y423 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.038 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.912 5.950 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X49Y420 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.243 6.193 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/O net (fo=15, routed) 0.455 6.648 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X50Y421 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.277 10.970 g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X50Y421 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/C clock pessimism 0.212 11.182 clock uncertainty -0.035 11.147 SLICE_X50Y421 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.054 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1] ------------------------------------------------------------------- required time 11.054 arrival time -6.648 ------------------------------------------------------------------- slack 4.406 Slack (MET) : 4.406ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 3.749ns (logic 0.382ns (10.189%) route 3.367ns (89.811%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.653ns = ( 10.970 - 8.317 ) Source Clock Delay (SCD): 2.899ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.474ns (routing 0.794ns, distribution 1.680ns) Clock Net Delay (Destination): 2.277ns (routing 0.710ns, distribution 1.567ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.474 2.899 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y423 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.038 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.912 5.950 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X49Y420 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.243 6.193 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/O net (fo=15, routed) 0.455 6.648 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X50Y421 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.277 10.970 g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X50Y421 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/C clock pessimism 0.212 11.182 clock uncertainty -0.035 11.147 SLICE_X50Y421 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 11.054 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2] ------------------------------------------------------------------- required time 11.054 arrival time -6.648 ------------------------------------------------------------------- slack 4.406 Slack (MET) : 4.406ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 3.748ns (logic 0.382ns (10.192%) route 3.366ns (89.808%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.035ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.652ns = ( 10.969 - 8.317 ) Source Clock Delay (SCD): 2.899ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.474ns (routing 0.794ns, distribution 1.680ns) Clock Net Delay (Destination): 2.276ns (routing 0.710ns, distribution 1.566ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.474 2.899 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y423 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.038 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.912 5.950 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X49Y420 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.243 6.193 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/O net (fo=15, routed) 0.454 6.647 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X49Y421 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.276 10.969 g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X49Y421 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/C clock pessimism 0.212 11.181 clock uncertainty -0.035 11.146 SLICE_X49Y421 FDCE (Recov_AFF2_SLICEM_C_CLR) -0.093 11.053 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5] ------------------------------------------------------------------- required time 11.053 arrival time -6.647 ------------------------------------------------------------------- slack 4.406 Slack (MET) : 4.414ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 3.739ns (logic 0.382ns (10.217%) route 3.357ns (89.783%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.036ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.651ns = ( 10.968 - 8.317 ) Source Clock Delay (SCD): 2.899ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.474ns (routing 0.794ns, distribution 1.680ns) Clock Net Delay (Destination): 2.275ns (routing 0.710ns, distribution 1.565ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.474 2.899 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y423 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.038 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.912 5.950 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X49Y420 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.243 6.193 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/O net (fo=15, routed) 0.445 6.638 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X50Y421 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.275 10.968 g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X50Y421 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/C clock pessimism 0.212 11.180 clock uncertainty -0.035 11.145 SLICE_X50Y421 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 11.052 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1] ------------------------------------------------------------------- required time 11.052 arrival time -6.638 ------------------------------------------------------------------- slack 4.414 Slack (MET) : 4.451ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/shiftPsAddr_reg_inv/PRE (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 3.693ns (logic 0.139ns (3.764%) route 3.554ns (96.236%)) Logic Levels: 0 Clock Path Skew: -0.045ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.642ns = ( 10.959 - 8.317 ) Source Clock Delay (SCD): 2.899ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.474ns (routing 0.794ns, distribution 1.680ns) Clock Net Delay (Destination): 2.266ns (routing 0.710ns, distribution 1.556ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.474 2.899 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y423 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.038 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.554 6.592 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/bitslip_reset_0 SLICE_X48Y421 FDPE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/shiftPsAddr_reg_inv/PRE (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.266 10.959 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK SLICE_X48Y421 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/shiftPsAddr_reg_inv/C clock pessimism 0.212 11.171 clock uncertainty -0.035 11.136 SLICE_X48Y421 FDPE (Recov_DFF_SLICEL_C_PRE) -0.093 11.043 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/shiftPsAddr_reg_inv ------------------------------------------------------------------- required time 11.043 arrival time -6.592 ------------------------------------------------------------------- slack 4.451 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.100ns (arrival time - required time) Source: SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.189ns (logic 0.048ns (25.397%) route 0.141ns (74.603%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.377ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.017ns (routing 0.377ns, distribution 0.640ns) Clock Net Delay (Destination): 1.225ns (routing 0.443ns, distribution 0.782ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.133 SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X55Y428 FDPE r SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X55Y428 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.181 f SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.141 1.322 SFP_GEN[36].ngCCM_gbt/sync_m_reg[3][0] SLICE_X54Y428 FDCE f SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.225 1.377 SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X54Y428 FDCE r SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[32]/C clock pessimism -0.160 1.217 SLICE_X54Y428 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.222 SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[32] ------------------------------------------------------------------- required time -1.222 arrival time 1.322 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.189ns (logic 0.048ns (25.397%) route 0.141ns (74.603%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.377ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.017ns (routing 0.377ns, distribution 0.640ns) Clock Net Delay (Destination): 1.225ns (routing 0.443ns, distribution 0.782ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.133 SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X55Y428 FDPE r SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X55Y428 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.181 f SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.141 1.322 SFP_GEN[36].ngCCM_gbt/sync_m_reg[3][0] SLICE_X54Y428 FDCE f SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.225 1.377 SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X54Y428 FDCE r SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[34]/C clock pessimism -0.160 1.217 SLICE_X54Y428 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 1.222 SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[34] ------------------------------------------------------------------- required time -1.222 arrival time 1.322 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.189ns (logic 0.048ns (25.397%) route 0.141ns (74.603%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.377ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.017ns (routing 0.377ns, distribution 0.640ns) Clock Net Delay (Destination): 1.225ns (routing 0.443ns, distribution 0.782ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.133 SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X55Y428 FDPE r SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X55Y428 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.181 f SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.141 1.322 SFP_GEN[36].ngCCM_gbt/sync_m_reg[3][0] SLICE_X54Y428 FDCE f SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.225 1.377 SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X54Y428 FDCE r SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[36]/C clock pessimism -0.160 1.217 SLICE_X54Y428 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 1.222 SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[36] ------------------------------------------------------------------- required time -1.222 arrival time 1.322 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.189ns (logic 0.048ns (25.397%) route 0.141ns (74.603%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.377ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.017ns (routing 0.377ns, distribution 0.640ns) Clock Net Delay (Destination): 1.225ns (routing 0.443ns, distribution 0.782ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.133 SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X55Y428 FDPE r SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X55Y428 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.181 f SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.141 1.322 SFP_GEN[36].ngCCM_gbt/sync_m_reg[3][0] SLICE_X54Y428 FDCE f SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.225 1.377 SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X54Y428 FDCE r SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[38]/C clock pessimism -0.160 1.217 SLICE_X54Y428 FDCE (Remov_GFF2_SLICEL_C_CLR) 0.005 1.222 SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[38] ------------------------------------------------------------------- required time -1.222 arrival time 1.322 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.146ns (arrival time - required time) Source: SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.238ns (logic 0.048ns (20.168%) route 0.190ns (79.832%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.380ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.017ns (routing 0.377ns, distribution 0.640ns) Clock Net Delay (Destination): 1.228ns (routing 0.443ns, distribution 0.785ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.133 SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X55Y428 FDPE r SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X55Y428 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.181 f SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.190 1.371 SFP_GEN[36].ngCCM_gbt/sync_m_reg[3][0] SLICE_X53Y426 FDCE f SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.228 1.380 SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y426 FDCE r SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[24]/C clock pessimism -0.160 1.220 SLICE_X53Y426 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.225 SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[24] ------------------------------------------------------------------- required time -1.225 arrival time 1.371 ------------------------------------------------------------------- slack 0.146 Slack (MET) : 0.146ns (arrival time - required time) Source: SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.238ns (logic 0.048ns (20.168%) route 0.190ns (79.832%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.380ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.017ns (routing 0.377ns, distribution 0.640ns) Clock Net Delay (Destination): 1.228ns (routing 0.443ns, distribution 0.785ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.133 SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X55Y428 FDPE r SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X55Y428 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.181 f SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.190 1.371 SFP_GEN[36].ngCCM_gbt/sync_m_reg[3][0] SLICE_X53Y426 FDCE f SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.228 1.380 SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y426 FDCE r SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[25]/C clock pessimism -0.160 1.220 SLICE_X53Y426 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 1.225 SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[25] ------------------------------------------------------------------- required time -1.225 arrival time 1.371 ------------------------------------------------------------------- slack 0.146 Slack (MET) : 0.146ns (arrival time - required time) Source: SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.238ns (logic 0.048ns (20.168%) route 0.190ns (79.832%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.380ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.017ns (routing 0.377ns, distribution 0.640ns) Clock Net Delay (Destination): 1.228ns (routing 0.443ns, distribution 0.785ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.133 SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X55Y428 FDPE r SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X55Y428 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.181 f SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.190 1.371 SFP_GEN[36].ngCCM_gbt/sync_m_reg[3][0] SLICE_X53Y426 FDCE f SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.228 1.380 SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y426 FDCE r SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[26]/C clock pessimism -0.160 1.220 SLICE_X53Y426 FDCE (Remov_BFF_SLICEM_C_CLR) 0.005 1.225 SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[26] ------------------------------------------------------------------- required time -1.225 arrival time 1.371 ------------------------------------------------------------------- slack 0.146 Slack (MET) : 0.146ns (arrival time - required time) Source: SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.238ns (logic 0.048ns (20.168%) route 0.190ns (79.832%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.380ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.017ns (routing 0.377ns, distribution 0.640ns) Clock Net Delay (Destination): 1.228ns (routing 0.443ns, distribution 0.785ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.133 SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X55Y428 FDPE r SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X55Y428 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.181 f SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.190 1.371 SFP_GEN[36].ngCCM_gbt/sync_m_reg[3][0] SLICE_X53Y426 FDCE f SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.228 1.380 SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y426 FDCE r SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[27]/C clock pessimism -0.160 1.220 SLICE_X53Y426 FDCE (Remov_BFF2_SLICEM_C_CLR) 0.005 1.225 SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[27] ------------------------------------------------------------------- required time -1.225 arrival time 1.371 ------------------------------------------------------------------- slack 0.146 Slack (MET) : 0.146ns (arrival time - required time) Source: SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.238ns (logic 0.048ns (20.168%) route 0.190ns (79.832%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.380ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.017ns (routing 0.377ns, distribution 0.640ns) Clock Net Delay (Destination): 1.228ns (routing 0.443ns, distribution 0.785ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.133 SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X55Y428 FDPE r SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X55Y428 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.181 f SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.190 1.371 SFP_GEN[36].ngCCM_gbt/sync_m_reg[3][0] SLICE_X53Y426 FDCE f SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.228 1.380 SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y426 FDCE r SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[28]/C clock pessimism -0.160 1.220 SLICE_X53Y426 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 1.225 SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[28] ------------------------------------------------------------------- required time -1.225 arrival time 1.371 ------------------------------------------------------------------- slack 0.146 Slack (MET) : 0.146ns (arrival time - required time) Source: SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.238ns (logic 0.048ns (20.168%) route 0.190ns (79.832%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.380ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.017ns (routing 0.377ns, distribution 0.640ns) Clock Net Delay (Destination): 1.228ns (routing 0.443ns, distribution 0.785ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.133 SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X55Y428 FDPE r SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X55Y428 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.181 f SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.190 1.371 SFP_GEN[36].ngCCM_gbt/sync_m_reg[3][0] SLICE_X53Y426 FDCE f SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y187 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.228 1.380 SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y426 FDCE r SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[29]/C clock pessimism -0.160 1.220 SLICE_X53Y426 FDCE (Remov_CFF2_SLICEM_C_CLR) 0.005 1.225 SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[29] ------------------------------------------------------------------- required time -1.225 arrival time 1.371 ------------------------------------------------------------------- slack 0.146 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_37 To Clock: gtwiz_userclk_rx_srcclk_out[0]_37 Setup : 0 Failing Endpoints, Worst Slack 2.625ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.225ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.625ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.486ns (logic 0.229ns (4.174%) route 5.257ns (95.826%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.078ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.958ns = ( 11.275 - 8.317 ) Source Clock Delay (SCD): 3.182ns Clock Pessimism Removal (CPR): 0.146ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.757ns (routing 1.081ns, distribution 1.676ns) Clock Net Delay (Destination): 2.582ns (routing 0.984ns, distribution 1.598ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.757 3.182 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y558 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y558 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.321 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.641 6.962 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X55Y472 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 7.052 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/O net (fo=15, routed) 1.616 8.668 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X50Y539 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.582 11.275 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X50Y539 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/C clock pessimism 0.146 11.421 clock uncertainty -0.035 11.386 SLICE_X50Y539 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 11.293 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10] ------------------------------------------------------------------- required time 11.293 arrival time -8.668 ------------------------------------------------------------------- slack 2.625 Slack (MET) : 2.683ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.438ns (logic 0.229ns (4.211%) route 5.209ns (95.789%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.968ns = ( 11.285 - 8.317 ) Source Clock Delay (SCD): 3.182ns Clock Pessimism Removal (CPR): 0.146ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.757ns (routing 1.081ns, distribution 1.676ns) Clock Net Delay (Destination): 2.592ns (routing 0.984ns, distribution 1.608ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.757 3.182 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y558 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y558 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.321 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.641 6.962 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X55Y472 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 7.052 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/O net (fo=15, routed) 1.568 8.620 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X50Y538 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.592 11.285 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X50Y538 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/C clock pessimism 0.146 11.431 clock uncertainty -0.035 11.396 SLICE_X50Y538 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.303 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3] ------------------------------------------------------------------- required time 11.303 arrival time -8.620 ------------------------------------------------------------------- slack 2.683 Slack (MET) : 2.683ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.438ns (logic 0.229ns (4.211%) route 5.209ns (95.789%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.968ns = ( 11.285 - 8.317 ) Source Clock Delay (SCD): 3.182ns Clock Pessimism Removal (CPR): 0.146ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.757ns (routing 1.081ns, distribution 1.676ns) Clock Net Delay (Destination): 2.592ns (routing 0.984ns, distribution 1.608ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.757 3.182 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y558 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y558 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.321 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.641 6.962 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X55Y472 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 7.052 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/O net (fo=15, routed) 1.568 8.620 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X50Y538 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.592 11.285 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X50Y538 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/C clock pessimism 0.146 11.431 clock uncertainty -0.035 11.396 SLICE_X50Y538 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.303 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4] ------------------------------------------------------------------- required time 11.303 arrival time -8.620 ------------------------------------------------------------------- slack 2.683 Slack (MET) : 2.683ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.438ns (logic 0.229ns (4.211%) route 5.209ns (95.789%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.968ns = ( 11.285 - 8.317 ) Source Clock Delay (SCD): 3.182ns Clock Pessimism Removal (CPR): 0.146ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.757ns (routing 1.081ns, distribution 1.676ns) Clock Net Delay (Destination): 2.592ns (routing 0.984ns, distribution 1.608ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.757 3.182 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y558 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y558 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.321 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.641 6.962 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X55Y472 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 7.052 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/O net (fo=15, routed) 1.568 8.620 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X50Y538 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.592 11.285 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X50Y538 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/C clock pessimism 0.146 11.431 clock uncertainty -0.035 11.396 SLICE_X50Y538 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 11.303 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5] ------------------------------------------------------------------- required time 11.303 arrival time -8.620 ------------------------------------------------------------------- slack 2.683 Slack (MET) : 2.683ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.438ns (logic 0.229ns (4.211%) route 5.209ns (95.789%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.968ns = ( 11.285 - 8.317 ) Source Clock Delay (SCD): 3.182ns Clock Pessimism Removal (CPR): 0.146ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.757ns (routing 1.081ns, distribution 1.676ns) Clock Net Delay (Destination): 2.592ns (routing 0.984ns, distribution 1.608ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.757 3.182 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y558 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y558 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.321 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.641 6.962 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X55Y472 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 7.052 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/O net (fo=15, routed) 1.568 8.620 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X50Y538 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.592 11.285 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X50Y538 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/C clock pessimism 0.146 11.431 clock uncertainty -0.035 11.396 SLICE_X50Y538 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 11.303 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6] ------------------------------------------------------------------- required time 11.303 arrival time -8.620 ------------------------------------------------------------------- slack 2.683 Slack (MET) : 2.689ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.549ns (logic 0.229ns (4.127%) route 5.320ns (95.873%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.049ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.003ns = ( 11.320 - 8.317 ) Source Clock Delay (SCD): 3.182ns Clock Pessimism Removal (CPR): 0.228ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.757ns (routing 1.081ns, distribution 1.676ns) Clock Net Delay (Destination): 2.627ns (routing 0.984ns, distribution 1.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.757 3.182 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y558 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y558 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.321 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.641 6.962 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X55Y472 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 7.052 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/O net (fo=15, routed) 1.679 8.731 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X50Y541 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.627 11.320 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X50Y541 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/C clock pessimism 0.228 11.548 clock uncertainty -0.035 11.513 SLICE_X50Y541 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 11.420 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0] ------------------------------------------------------------------- required time 11.420 arrival time -8.731 ------------------------------------------------------------------- slack 2.689 Slack (MET) : 2.689ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.549ns (logic 0.229ns (4.127%) route 5.320ns (95.873%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.049ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.003ns = ( 11.320 - 8.317 ) Source Clock Delay (SCD): 3.182ns Clock Pessimism Removal (CPR): 0.228ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.757ns (routing 1.081ns, distribution 1.676ns) Clock Net Delay (Destination): 2.627ns (routing 0.984ns, distribution 1.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.757 3.182 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y558 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y558 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.321 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.641 6.962 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X55Y472 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 7.052 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/O net (fo=15, routed) 1.679 8.731 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X50Y541 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.627 11.320 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X50Y541 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/C clock pessimism 0.228 11.548 clock uncertainty -0.035 11.513 SLICE_X50Y541 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.420 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1] ------------------------------------------------------------------- required time 11.420 arrival time -8.731 ------------------------------------------------------------------- slack 2.689 Slack (MET) : 2.689ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.549ns (logic 0.229ns (4.127%) route 5.320ns (95.873%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.049ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.003ns = ( 11.320 - 8.317 ) Source Clock Delay (SCD): 3.182ns Clock Pessimism Removal (CPR): 0.228ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.757ns (routing 1.081ns, distribution 1.676ns) Clock Net Delay (Destination): 2.627ns (routing 0.984ns, distribution 1.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.757 3.182 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y558 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y558 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.321 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.641 6.962 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X55Y472 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 7.052 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/O net (fo=15, routed) 1.679 8.731 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X50Y541 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.627 11.320 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X50Y541 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/C clock pessimism 0.228 11.548 clock uncertainty -0.035 11.513 SLICE_X50Y541 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 11.420 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2] ------------------------------------------------------------------- required time 11.420 arrival time -8.731 ------------------------------------------------------------------- slack 2.689 Slack (MET) : 2.689ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.549ns (logic 0.229ns (4.127%) route 5.320ns (95.873%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.049ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.003ns = ( 11.320 - 8.317 ) Source Clock Delay (SCD): 3.182ns Clock Pessimism Removal (CPR): 0.228ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.757ns (routing 1.081ns, distribution 1.676ns) Clock Net Delay (Destination): 2.627ns (routing 0.984ns, distribution 1.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.757 3.182 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y558 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y558 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.321 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.641 6.962 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X55Y472 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 7.052 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/O net (fo=15, routed) 1.679 8.731 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X50Y541 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.627 11.320 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X50Y541 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C clock pessimism 0.228 11.548 clock uncertainty -0.035 11.513 SLICE_X50Y541 FDCE (Recov_AFF2_SLICEL_C_CLR) -0.093 11.420 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3] ------------------------------------------------------------------- required time 11.420 arrival time -8.731 ------------------------------------------------------------------- slack 2.689 Slack (MET) : 2.689ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.549ns (logic 0.229ns (4.127%) route 5.320ns (95.873%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.049ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.003ns = ( 11.320 - 8.317 ) Source Clock Delay (SCD): 3.182ns Clock Pessimism Removal (CPR): 0.228ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.757ns (routing 1.081ns, distribution 1.676ns) Clock Net Delay (Destination): 2.627ns (routing 0.984ns, distribution 1.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.757 3.182 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y558 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y558 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.321 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.641 6.962 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X55Y472 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 7.052 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/O net (fo=15, routed) 1.679 8.731 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X50Y541 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.627 11.320 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X50Y541 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/C clock pessimism 0.228 11.548 clock uncertainty -0.035 11.513 SLICE_X50Y541 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 11.420 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4] ------------------------------------------------------------------- required time 11.420 arrival time -8.731 ------------------------------------------------------------------- slack 2.689 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.225ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.310ns (logic 0.049ns (15.806%) route 0.261ns (84.194%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.501ns Source Clock Delay (SCD): 1.258ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 1.142ns (routing 0.463ns, distribution 0.679ns) Clock Net Delay (Destination): 1.349ns (routing 0.528ns, distribution 0.821ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.142 1.258 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X51Y562 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X51Y562 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.307 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.261 1.568 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X49Y564 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.349 1.501 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X49Y564 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism -0.163 1.338 SLICE_X49Y564 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.343 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time -1.343 arrival time 1.568 ------------------------------------------------------------------- slack 0.225 Slack (MET) : 0.225ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.310ns (logic 0.049ns (15.806%) route 0.261ns (84.194%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.501ns Source Clock Delay (SCD): 1.258ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 1.142ns (routing 0.463ns, distribution 0.679ns) Clock Net Delay (Destination): 1.349ns (routing 0.528ns, distribution 0.821ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.142 1.258 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X51Y562 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X51Y562 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.307 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.261 1.568 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X49Y564 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.349 1.501 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X49Y564 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.163 1.338 SLICE_X49Y564 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.343 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -1.343 arrival time 1.568 ------------------------------------------------------------------- slack 0.225 Slack (MET) : 0.225ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.310ns (logic 0.049ns (15.806%) route 0.261ns (84.194%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.501ns Source Clock Delay (SCD): 1.258ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 1.142ns (routing 0.463ns, distribution 0.679ns) Clock Net Delay (Destination): 1.349ns (routing 0.528ns, distribution 0.821ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.142 1.258 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X51Y562 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X51Y562 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.307 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.261 1.568 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X49Y564 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.349 1.501 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X49Y564 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C clock pessimism -0.163 1.338 SLICE_X49Y564 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.343 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11] ------------------------------------------------------------------- required time -1.343 arrival time 1.568 ------------------------------------------------------------------- slack 0.225 Slack (MET) : 0.226ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.309ns (logic 0.049ns (15.858%) route 0.260ns (84.142%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.499ns Source Clock Delay (SCD): 1.258ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 1.142ns (routing 0.463ns, distribution 0.679ns) Clock Net Delay (Destination): 1.347ns (routing 0.528ns, distribution 0.819ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.142 1.258 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X51Y562 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X51Y562 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.307 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.260 1.567 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X50Y564 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.347 1.499 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X50Y564 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C clock pessimism -0.163 1.336 SLICE_X50Y564 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.341 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13] ------------------------------------------------------------------- required time -1.341 arrival time 1.567 ------------------------------------------------------------------- slack 0.226 Slack (MET) : 0.226ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.309ns (logic 0.049ns (15.858%) route 0.260ns (84.142%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.499ns Source Clock Delay (SCD): 1.258ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 1.142ns (routing 0.463ns, distribution 0.679ns) Clock Net Delay (Destination): 1.347ns (routing 0.528ns, distribution 0.819ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.142 1.258 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X51Y562 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X51Y562 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.307 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.260 1.567 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X50Y564 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.347 1.499 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X50Y564 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C clock pessimism -0.163 1.336 SLICE_X50Y564 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.341 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15] ------------------------------------------------------------------- required time -1.341 arrival time 1.567 ------------------------------------------------------------------- slack 0.226 Slack (MET) : 0.226ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.309ns (logic 0.049ns (15.858%) route 0.260ns (84.142%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.499ns Source Clock Delay (SCD): 1.258ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 1.142ns (routing 0.463ns, distribution 0.679ns) Clock Net Delay (Destination): 1.347ns (routing 0.528ns, distribution 0.819ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.142 1.258 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X51Y562 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X51Y562 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.307 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.260 1.567 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X50Y564 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.347 1.499 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X50Y564 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism -0.163 1.336 SLICE_X50Y564 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.341 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time -1.341 arrival time 1.567 ------------------------------------------------------------------- slack 0.226 Slack (MET) : 0.226ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.309ns (logic 0.049ns (15.858%) route 0.260ns (84.142%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.499ns Source Clock Delay (SCD): 1.258ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 1.142ns (routing 0.463ns, distribution 0.679ns) Clock Net Delay (Destination): 1.347ns (routing 0.528ns, distribution 0.819ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.142 1.258 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X51Y562 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X51Y562 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.307 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.260 1.567 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X50Y564 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.347 1.499 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X50Y564 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C clock pessimism -0.163 1.336 SLICE_X50Y564 FDCE (Remov_FFF2_SLICEL_C_CLR) 0.005 1.341 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3] ------------------------------------------------------------------- required time -1.341 arrival time 1.567 ------------------------------------------------------------------- slack 0.226 Slack (MET) : 0.232ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.315ns (logic 0.049ns (15.556%) route 0.266ns (84.444%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.499ns Source Clock Delay (SCD): 1.258ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 1.142ns (routing 0.463ns, distribution 0.679ns) Clock Net Delay (Destination): 1.347ns (routing 0.528ns, distribution 0.819ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.142 1.258 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X51Y562 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X51Y562 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.307 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.266 1.573 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X49Y565 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.347 1.499 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X49Y565 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism -0.163 1.336 SLICE_X49Y565 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.341 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time -1.341 arrival time 1.573 ------------------------------------------------------------------- slack 0.232 Slack (MET) : 0.247ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.329ns (logic 0.049ns (14.894%) route 0.280ns (85.106%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.505ns Source Clock Delay (SCD): 1.265ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 1.149ns (routing 0.463ns, distribution 0.686ns) Clock Net Delay (Destination): 1.353ns (routing 0.528ns, distribution 0.825ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.149 1.265 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/CLK SLICE_X54Y542 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X54Y542 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.314 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.280 1.594 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X50Y541 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.353 1.505 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X50Y541 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.163 1.342 SLICE_X50Y541 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.347 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -1.347 arrival time 1.594 ------------------------------------------------------------------- slack 0.247 Slack (MET) : 0.265ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.354ns (logic 0.049ns (13.842%) route 0.305ns (86.158%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.505ns Source Clock Delay (SCD): 1.258ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 1.142ns (routing 0.463ns, distribution 0.679ns) Clock Net Delay (Destination): 1.353ns (routing 0.528ns, distribution 0.825ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.142 1.258 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X51Y562 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X51Y562 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.307 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.305 1.612 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X49Y566 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y216 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.353 1.505 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X49Y566 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C clock pessimism -0.163 1.342 SLICE_X49Y566 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.347 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time -1.347 arrival time 1.612 ------------------------------------------------------------------- slack 0.265 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_38 To Clock: gtwiz_userclk_rx_srcclk_out[0]_38 Setup : 0 Failing Endpoints, Worst Slack 1.785ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.153ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.785ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 6.435ns (logic 0.304ns (4.724%) route 6.131ns (95.276%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.628ns = ( 10.945 - 8.317 ) Source Clock Delay (SCD): 2.805ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.380ns (routing 0.788ns, distribution 1.592ns) Clock Net Delay (Destination): 2.252ns (routing 0.707ns, distribution 1.545ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.380 2.805 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X18Y589 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X18Y589 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.944 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 4.039 6.983 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X66Y470 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 7.148 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/O net (fo=15, routed) 2.092 9.240 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X64Y563 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.252 10.945 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X64Y563 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/C clock pessimism 0.208 11.154 clock uncertainty -0.035 11.118 SLICE_X64Y563 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.025 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4] ------------------------------------------------------------------- required time 11.025 arrival time -9.240 ------------------------------------------------------------------- slack 1.785 Slack (MET) : 1.785ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 6.435ns (logic 0.304ns (4.724%) route 6.131ns (95.276%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.628ns = ( 10.945 - 8.317 ) Source Clock Delay (SCD): 2.805ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.380ns (routing 0.788ns, distribution 1.592ns) Clock Net Delay (Destination): 2.252ns (routing 0.707ns, distribution 1.545ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.380 2.805 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X18Y589 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X18Y589 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.944 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 4.039 6.983 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X66Y470 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 7.148 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/O net (fo=15, routed) 2.092 9.240 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X64Y563 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.252 10.945 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X64Y563 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/C clock pessimism 0.208 11.154 clock uncertainty -0.035 11.118 SLICE_X64Y563 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 11.025 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7] ------------------------------------------------------------------- required time 11.025 arrival time -9.240 ------------------------------------------------------------------- slack 1.785 Slack (MET) : 1.790ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 6.428ns (logic 0.304ns (4.729%) route 6.124ns (95.271%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.029ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.626ns = ( 10.943 - 8.317 ) Source Clock Delay (SCD): 2.805ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.380ns (routing 0.788ns, distribution 1.592ns) Clock Net Delay (Destination): 2.250ns (routing 0.707ns, distribution 1.543ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.380 2.805 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X18Y589 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X18Y589 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.944 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 4.039 6.983 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X66Y470 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 7.148 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/O net (fo=15, routed) 2.085 9.233 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X64Y563 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.250 10.943 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X64Y563 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/C clock pessimism 0.208 11.152 clock uncertainty -0.035 11.116 SLICE_X64Y563 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.023 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6] ------------------------------------------------------------------- required time 11.023 arrival time -9.233 ------------------------------------------------------------------- slack 1.790 Slack (MET) : 2.063ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 6.151ns (logic 0.304ns (4.942%) route 5.847ns (95.058%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.622ns = ( 10.939 - 8.317 ) Source Clock Delay (SCD): 2.805ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.380ns (routing 0.788ns, distribution 1.592ns) Clock Net Delay (Destination): 2.246ns (routing 0.707ns, distribution 1.539ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.380 2.805 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X18Y589 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X18Y589 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.944 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 4.039 6.983 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X66Y470 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 7.148 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/O net (fo=15, routed) 1.808 8.956 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X64Y561 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.246 10.939 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X64Y561 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/C clock pessimism 0.208 11.148 clock uncertainty -0.035 11.112 SLICE_X64Y561 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.019 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1] ------------------------------------------------------------------- required time 11.019 arrival time -8.956 ------------------------------------------------------------------- slack 2.063 Slack (MET) : 2.063ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 6.151ns (logic 0.304ns (4.942%) route 5.847ns (95.058%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.622ns = ( 10.939 - 8.317 ) Source Clock Delay (SCD): 2.805ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.380ns (routing 0.788ns, distribution 1.592ns) Clock Net Delay (Destination): 2.246ns (routing 0.707ns, distribution 1.539ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.380 2.805 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X18Y589 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X18Y589 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.944 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 4.039 6.983 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X66Y470 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 7.148 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/O net (fo=15, routed) 1.808 8.956 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X64Y561 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.246 10.939 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X64Y561 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/C clock pessimism 0.208 11.148 clock uncertainty -0.035 11.112 SLICE_X64Y561 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 11.019 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2] ------------------------------------------------------------------- required time 11.019 arrival time -8.956 ------------------------------------------------------------------- slack 2.063 Slack (MET) : 2.063ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 6.151ns (logic 0.304ns (4.942%) route 5.847ns (95.058%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.622ns = ( 10.939 - 8.317 ) Source Clock Delay (SCD): 2.805ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.380ns (routing 0.788ns, distribution 1.592ns) Clock Net Delay (Destination): 2.246ns (routing 0.707ns, distribution 1.539ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.380 2.805 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X18Y589 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X18Y589 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.944 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 4.039 6.983 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X66Y470 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 7.148 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/O net (fo=15, routed) 1.808 8.956 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X64Y561 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.246 10.939 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X64Y561 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/C clock pessimism 0.208 11.148 clock uncertainty -0.035 11.112 SLICE_X64Y561 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.019 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3] ------------------------------------------------------------------- required time 11.019 arrival time -8.956 ------------------------------------------------------------------- slack 2.063 Slack (MET) : 2.063ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 6.151ns (logic 0.304ns (4.942%) route 5.847ns (95.058%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.622ns = ( 10.939 - 8.317 ) Source Clock Delay (SCD): 2.805ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.380ns (routing 0.788ns, distribution 1.592ns) Clock Net Delay (Destination): 2.246ns (routing 0.707ns, distribution 1.539ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.380 2.805 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X18Y589 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X18Y589 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.944 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 4.039 6.983 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X66Y470 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 7.148 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/O net (fo=15, routed) 1.808 8.956 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X64Y561 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.246 10.939 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X64Y561 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/C clock pessimism 0.208 11.148 clock uncertainty -0.035 11.112 SLICE_X64Y561 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.019 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4] ------------------------------------------------------------------- required time 11.019 arrival time -8.956 ------------------------------------------------------------------- slack 2.063 Slack (MET) : 2.135ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 6.086ns (logic 0.304ns (4.995%) route 5.782ns (95.005%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.629ns = ( 10.946 - 8.317 ) Source Clock Delay (SCD): 2.805ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.380ns (routing 0.788ns, distribution 1.592ns) Clock Net Delay (Destination): 2.253ns (routing 0.707ns, distribution 1.546ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.380 2.805 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X18Y589 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X18Y589 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.944 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 4.039 6.983 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X66Y470 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 7.148 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/O net (fo=15, routed) 1.743 8.891 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X64Y562 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.253 10.946 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X64Y562 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/C clock pessimism 0.208 11.155 clock uncertainty -0.035 11.119 SLICE_X64Y562 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.026 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3] ------------------------------------------------------------------- required time 11.026 arrival time -8.891 ------------------------------------------------------------------- slack 2.135 Slack (MET) : 2.135ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 6.086ns (logic 0.304ns (4.995%) route 5.782ns (95.005%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.629ns = ( 10.946 - 8.317 ) Source Clock Delay (SCD): 2.805ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.380ns (routing 0.788ns, distribution 1.592ns) Clock Net Delay (Destination): 2.253ns (routing 0.707ns, distribution 1.546ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.380 2.805 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X18Y589 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X18Y589 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.944 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 4.039 6.983 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X66Y470 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 7.148 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/O net (fo=15, routed) 1.743 8.891 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X64Y562 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.253 10.946 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X64Y562 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/C clock pessimism 0.208 11.155 clock uncertainty -0.035 11.119 SLICE_X64Y562 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 11.026 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5] ------------------------------------------------------------------- required time 11.026 arrival time -8.891 ------------------------------------------------------------------- slack 2.135 Slack (MET) : 2.140ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 6.079ns (logic 0.304ns (5.001%) route 5.775ns (94.999%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.030ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.627ns = ( 10.944 - 8.317 ) Source Clock Delay (SCD): 2.805ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.380ns (routing 0.788ns, distribution 1.592ns) Clock Net Delay (Destination): 2.251ns (routing 0.707ns, distribution 1.544ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.380 2.805 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X18Y589 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X18Y589 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.944 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 4.039 6.983 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X66Y470 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 7.148 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/O net (fo=15, routed) 1.736 8.884 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X64Y562 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.251 10.944 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X64Y562 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/C clock pessimism 0.208 11.153 clock uncertainty -0.035 11.117 SLICE_X64Y562 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.024 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1] ------------------------------------------------------------------- required time 11.024 arrival time -8.884 ------------------------------------------------------------------- slack 2.140 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.153ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.242ns (logic 0.049ns (20.248%) route 0.193ns (79.752%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.353ns Source Clock Delay (SCD): 1.112ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 0.996ns (routing 0.376ns, distribution 0.620ns) Clock Net Delay (Destination): 1.201ns (routing 0.440ns, distribution 0.761ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.996 1.112 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK SLICE_X63Y567 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X63Y567 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.161 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.193 1.354 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X65Y567 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.201 1.353 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X65Y567 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.157 1.196 SLICE_X65Y567 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.201 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -1.201 arrival time 1.354 ------------------------------------------------------------------- slack 0.153 Slack (MET) : 0.221ns (arrival time - required time) Source: SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[47].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.264ns (logic 0.048ns (18.182%) route 0.216ns (81.818%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.366ns Source Clock Delay (SCD): 1.137ns Clock Pessimism Removal (CPR): 0.191ns Clock Net Delay (Source): 1.021ns (routing 0.376ns, distribution 0.645ns) Clock Net Delay (Destination): 1.214ns (routing 0.440ns, distribution 0.774ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.021 1.137 SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y547 FDPE r SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y547 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.185 f SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.216 1.401 SFP_GEN[47].ngCCM_gbt/sync_m_reg[3][0] SLICE_X69Y546 FDCE f SFP_GEN[47].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.214 1.366 SFP_GEN[47].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X69Y546 FDCE r SFP_GEN[47].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.191 1.175 SLICE_X69Y546 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.180 SFP_GEN[47].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.180 arrival time 1.401 ------------------------------------------------------------------- slack 0.221 Slack (MET) : 0.239ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.324ns (logic 0.049ns (15.123%) route 0.275ns (84.877%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.373ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.020ns (routing 0.376ns, distribution 0.644ns) Clock Net Delay (Destination): 1.221ns (routing 0.440ns, distribution 0.781ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.136 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X63Y591 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X63Y591 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.185 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.275 1.460 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X68Y589 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.221 1.373 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X68Y589 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C clock pessimism -0.157 1.216 SLICE_X68Y589 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.221 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time -1.221 arrival time 1.460 ------------------------------------------------------------------- slack 0.239 Slack (MET) : 0.239ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.324ns (logic 0.049ns (15.123%) route 0.275ns (84.877%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.373ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.020ns (routing 0.376ns, distribution 0.644ns) Clock Net Delay (Destination): 1.221ns (routing 0.440ns, distribution 0.781ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.136 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X63Y591 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X63Y591 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.185 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.275 1.460 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X68Y589 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.221 1.373 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X68Y589 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C clock pessimism -0.157 1.216 SLICE_X68Y589 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.221 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19] ------------------------------------------------------------------- required time -1.221 arrival time 1.460 ------------------------------------------------------------------- slack 0.239 Slack (MET) : 0.243ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.318ns (logic 0.049ns (15.409%) route 0.269ns (84.591%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.363ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.020ns (routing 0.376ns, distribution 0.644ns) Clock Net Delay (Destination): 1.211ns (routing 0.440ns, distribution 0.771ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.136 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X63Y591 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X63Y591 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.185 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.269 1.454 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X61Y589 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.211 1.363 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X61Y589 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C clock pessimism -0.157 1.206 SLICE_X61Y589 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.211 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time -1.211 arrival time 1.454 ------------------------------------------------------------------- slack 0.243 Slack (MET) : 0.243ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.318ns (logic 0.049ns (15.409%) route 0.269ns (84.591%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.363ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.020ns (routing 0.376ns, distribution 0.644ns) Clock Net Delay (Destination): 1.211ns (routing 0.440ns, distribution 0.771ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.136 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X63Y591 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X63Y591 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.185 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.269 1.454 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X61Y589 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.211 1.363 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X61Y589 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C clock pessimism -0.157 1.206 SLICE_X61Y589 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.211 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time -1.211 arrival time 1.454 ------------------------------------------------------------------- slack 0.243 Slack (MET) : 0.243ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.318ns (logic 0.049ns (15.409%) route 0.269ns (84.591%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.363ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.020ns (routing 0.376ns, distribution 0.644ns) Clock Net Delay (Destination): 1.211ns (routing 0.440ns, distribution 0.771ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.136 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X63Y591 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X63Y591 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.185 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.269 1.454 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X61Y589 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.211 1.363 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X61Y589 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C clock pessimism -0.157 1.206 SLICE_X61Y589 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.211 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19] ------------------------------------------------------------------- required time -1.211 arrival time 1.454 ------------------------------------------------------------------- slack 0.243 Slack (MET) : 0.243ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.318ns (logic 0.049ns (15.409%) route 0.269ns (84.591%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.363ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.020ns (routing 0.376ns, distribution 0.644ns) Clock Net Delay (Destination): 1.211ns (routing 0.440ns, distribution 0.771ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.136 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X63Y591 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X63Y591 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.185 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.269 1.454 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X61Y589 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.211 1.363 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X61Y589 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C clock pessimism -0.157 1.206 SLICE_X61Y589 FDCE (Remov_FFF2_SLICEM_C_CLR) 0.005 1.211 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time -1.211 arrival time 1.454 ------------------------------------------------------------------- slack 0.243 Slack (MET) : 0.243ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.318ns (logic 0.049ns (15.409%) route 0.269ns (84.591%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.363ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.020ns (routing 0.376ns, distribution 0.644ns) Clock Net Delay (Destination): 1.211ns (routing 0.440ns, distribution 0.771ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.136 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X63Y591 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X63Y591 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.185 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.269 1.454 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X61Y589 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.211 1.363 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X61Y589 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C clock pessimism -0.157 1.206 SLICE_X61Y589 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.211 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4] ------------------------------------------------------------------- required time -1.211 arrival time 1.454 ------------------------------------------------------------------- slack 0.243 Slack (MET) : 0.243ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.318ns (logic 0.049ns (15.409%) route 0.269ns (84.591%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.363ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.020ns (routing 0.376ns, distribution 0.644ns) Clock Net Delay (Destination): 1.211ns (routing 0.440ns, distribution 0.771ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.136 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X63Y591 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X63Y591 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.185 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.269 1.454 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X61Y589 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y237 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.211 1.363 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X61Y589 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C clock pessimism -0.157 1.206 SLICE_X61Y589 FDCE (Remov_GFF2_SLICEM_C_CLR) 0.005 1.211 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6] ------------------------------------------------------------------- required time -1.211 arrival time 1.454 ------------------------------------------------------------------- slack 0.243 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_39 To Clock: gtwiz_userclk_rx_srcclk_out[0]_39 Setup : 0 Failing Endpoints, Worst Slack 4.385ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.133ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.385ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.466ns (logic 0.363ns (10.473%) route 3.103ns (89.527%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.338ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.332ns = ( 10.649 - 8.317 ) Source Clock Delay (SCD): 2.873ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.448ns (routing 0.789ns, distribution 1.659ns) Clock Net Delay (Destination): 1.956ns (routing 0.708ns, distribution 1.248ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.448 2.873 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y441 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.012 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.499 5.511 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X44Y419 LUT2 (Prop_A6LUT_SLICEM_I0_O) 0.224 5.735 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__36/O net (fo=2, routed) 0.604 6.339 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X44Y420 FDCE f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.956 10.649 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X44Y420 FDCE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.203 10.852 clock uncertainty -0.035 10.817 SLICE_X44Y420 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 10.724 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 10.724 arrival time -6.339 ------------------------------------------------------------------- slack 4.385 Slack (MET) : 4.385ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.466ns (logic 0.363ns (10.473%) route 3.103ns (89.527%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.338ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.332ns = ( 10.649 - 8.317 ) Source Clock Delay (SCD): 2.873ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.448ns (routing 0.789ns, distribution 1.659ns) Clock Net Delay (Destination): 1.956ns (routing 0.708ns, distribution 1.248ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.448 2.873 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y441 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.012 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.499 5.511 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X44Y419 LUT2 (Prop_A6LUT_SLICEM_I0_O) 0.224 5.735 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__36/O net (fo=2, routed) 0.604 6.339 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X44Y420 FDCE f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.956 10.649 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X44Y420 FDCE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.203 10.852 clock uncertainty -0.035 10.817 SLICE_X44Y420 FDCE (Recov_EFF2_SLICEM_C_CLR) -0.093 10.724 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 10.724 arrival time -6.339 ------------------------------------------------------------------- slack 4.385 Slack (MET) : 4.499ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.398ns (logic 0.305ns (8.976%) route 3.093ns (91.024%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.292ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.379ns = ( 10.696 - 8.317 ) Source Clock Delay (SCD): 2.873ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.448ns (routing 0.789ns, distribution 1.659ns) Clock Net Delay (Destination): 2.003ns (routing 0.708ns, distribution 1.295ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.448 2.873 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y441 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.012 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.290 5.302 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X43Y418 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.468 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/O net (fo=15, routed) 0.803 6.271 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X36Y421 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.003 10.696 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X36Y421 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/C clock pessimism 0.202 10.899 clock uncertainty -0.035 10.863 SLICE_X36Y421 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.770 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6] ------------------------------------------------------------------- required time 10.770 arrival time -6.271 ------------------------------------------------------------------- slack 4.499 Slack (MET) : 4.499ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.398ns (logic 0.305ns (8.976%) route 3.093ns (91.024%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.292ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.379ns = ( 10.696 - 8.317 ) Source Clock Delay (SCD): 2.873ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.448ns (routing 0.789ns, distribution 1.659ns) Clock Net Delay (Destination): 2.003ns (routing 0.708ns, distribution 1.295ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.448 2.873 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y441 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.012 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.290 5.302 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X43Y418 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.468 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/O net (fo=15, routed) 0.803 6.271 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X36Y421 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.003 10.696 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X36Y421 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/C clock pessimism 0.202 10.899 clock uncertainty -0.035 10.863 SLICE_X36Y421 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.770 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7] ------------------------------------------------------------------- required time 10.770 arrival time -6.271 ------------------------------------------------------------------- slack 4.499 Slack (MET) : 4.499ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.397ns (logic 0.305ns (8.979%) route 3.092ns (91.021%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.293ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.378ns = ( 10.695 - 8.317 ) Source Clock Delay (SCD): 2.873ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.448ns (routing 0.789ns, distribution 1.659ns) Clock Net Delay (Destination): 2.002ns (routing 0.708ns, distribution 1.294ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.448 2.873 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y441 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.012 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.290 5.302 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X43Y418 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.468 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/O net (fo=15, routed) 0.802 6.270 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X35Y421 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.002 10.695 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X35Y421 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/C clock pessimism 0.202 10.898 clock uncertainty -0.035 10.862 SLICE_X35Y421 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.769 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1] ------------------------------------------------------------------- required time 10.769 arrival time -6.270 ------------------------------------------------------------------- slack 4.499 Slack (MET) : 4.504ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.390ns (logic 0.305ns (8.997%) route 3.085ns (91.003%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.295ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.376ns = ( 10.693 - 8.317 ) Source Clock Delay (SCD): 2.873ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.448ns (routing 0.789ns, distribution 1.659ns) Clock Net Delay (Destination): 2.000ns (routing 0.708ns, distribution 1.292ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.448 2.873 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y441 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.012 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.290 5.302 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X43Y418 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.468 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/O net (fo=15, routed) 0.795 6.263 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X35Y421 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.000 10.693 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X35Y421 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/C clock pessimism 0.202 10.896 clock uncertainty -0.035 10.860 SLICE_X35Y421 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 10.767 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1] ------------------------------------------------------------------- required time 10.767 arrival time -6.263 ------------------------------------------------------------------- slack 4.504 Slack (MET) : 4.504ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.390ns (logic 0.305ns (8.997%) route 3.085ns (91.003%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.295ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.376ns = ( 10.693 - 8.317 ) Source Clock Delay (SCD): 2.873ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.448ns (routing 0.789ns, distribution 1.659ns) Clock Net Delay (Destination): 2.000ns (routing 0.708ns, distribution 1.292ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.448 2.873 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y441 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.012 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.290 5.302 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X43Y418 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.468 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/O net (fo=15, routed) 0.795 6.263 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X35Y421 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.000 10.693 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X35Y421 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/C clock pessimism 0.202 10.896 clock uncertainty -0.035 10.860 SLICE_X35Y421 FDCE (Recov_GFF2_SLICEM_C_CLR) -0.093 10.767 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2] ------------------------------------------------------------------- required time 10.767 arrival time -6.263 ------------------------------------------------------------------- slack 4.504 Slack (MET) : 4.504ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.390ns (logic 0.305ns (8.997%) route 3.085ns (91.003%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.295ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.376ns = ( 10.693 - 8.317 ) Source Clock Delay (SCD): 2.873ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.448ns (routing 0.789ns, distribution 1.659ns) Clock Net Delay (Destination): 2.000ns (routing 0.708ns, distribution 1.292ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.448 2.873 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y441 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.012 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.290 5.302 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X43Y418 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.468 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/O net (fo=15, routed) 0.795 6.263 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X35Y421 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.000 10.693 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X35Y421 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/C clock pessimism 0.202 10.896 clock uncertainty -0.035 10.860 SLICE_X35Y421 FDCE (Recov_FFF_SLICEM_C_CLR) -0.093 10.767 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5] ------------------------------------------------------------------- required time 10.767 arrival time -6.263 ------------------------------------------------------------------- slack 4.504 Slack (MET) : 4.507ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.388ns (logic 0.305ns (9.002%) route 3.083ns (90.998%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.294ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.377ns = ( 10.694 - 8.317 ) Source Clock Delay (SCD): 2.873ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.448ns (routing 0.789ns, distribution 1.659ns) Clock Net Delay (Destination): 2.001ns (routing 0.708ns, distribution 1.293ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.448 2.873 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y441 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.012 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.290 5.302 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X43Y418 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.468 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/O net (fo=15, routed) 0.793 6.261 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X36Y421 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.001 10.694 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X36Y421 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/C clock pessimism 0.202 10.897 clock uncertainty -0.035 10.861 SLICE_X36Y421 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.768 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3] ------------------------------------------------------------------- required time 10.768 arrival time -6.261 ------------------------------------------------------------------- slack 4.507 Slack (MET) : 4.507ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.388ns (logic 0.305ns (9.002%) route 3.083ns (90.998%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.294ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.377ns = ( 10.694 - 8.317 ) Source Clock Delay (SCD): 2.873ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.448ns (routing 0.789ns, distribution 1.659ns) Clock Net Delay (Destination): 2.001ns (routing 0.708ns, distribution 1.293ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.448 2.873 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y441 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.012 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.290 5.302 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X43Y418 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.468 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/O net (fo=15, routed) 0.793 6.261 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X36Y421 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.001 10.694 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X36Y421 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/C clock pessimism 0.202 10.897 clock uncertainty -0.035 10.861 SLICE_X36Y421 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 10.768 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4] ------------------------------------------------------------------- required time 10.768 arrival time -6.261 ------------------------------------------------------------------- slack 4.507 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.133ns (arrival time - required time) Source: SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.227ns (logic 0.048ns (21.145%) route 0.179ns (78.855%)) Logic Levels: 0 Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.236ns Source Clock Delay (SCD): 1.004ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.888ns (routing 0.376ns, distribution 0.512ns) Clock Net Delay (Destination): 1.084ns (routing 0.440ns, distribution 0.644ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.888 1.004 SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X38Y421 FDPE r SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y421 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.052 f SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.179 1.231 SFP_GEN[37].ngCCM_gbt/sync_m_reg[3][0] SLICE_X40Y421 FDCE f SFP_GEN[37].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.084 1.236 SFP_GEN[37].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X40Y421 FDCE r SFP_GEN[37].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.143 1.093 SLICE_X40Y421 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.098 SFP_GEN[37].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.098 arrival time 1.231 ------------------------------------------------------------------- slack 0.133 Slack (MET) : 0.143ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.217ns (logic 0.049ns (22.581%) route 0.168ns (77.419%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.217ns Source Clock Delay (SCD): 1.005ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.889ns (routing 0.376ns, distribution 0.513ns) Clock Net Delay (Destination): 1.065ns (routing 0.440ns, distribution 0.625ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.889 1.005 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X39Y420 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X39Y420 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.054 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.168 1.222 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X37Y420 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.065 1.217 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X37Y420 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.143 1.074 SLICE_X37Y420 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.079 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -1.079 arrival time 1.222 ------------------------------------------------------------------- slack 0.143 Slack (MET) : 0.167ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.048ns (18.462%) route 0.212ns (81.538%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.253ns Source Clock Delay (SCD): 1.022ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.906ns (routing 0.376ns, distribution 0.530ns) Clock Net Delay (Destination): 1.101ns (routing 0.440ns, distribution 0.661ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.906 1.022 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X28Y425 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X28Y425 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.070 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.212 1.282 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X30Y424 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.101 1.253 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X30Y424 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism -0.143 1.110 SLICE_X30Y424 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.115 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time -1.115 arrival time 1.282 ------------------------------------------------------------------- slack 0.167 Slack (MET) : 0.167ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.048ns (18.462%) route 0.212ns (81.538%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.253ns Source Clock Delay (SCD): 1.022ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.906ns (routing 0.376ns, distribution 0.530ns) Clock Net Delay (Destination): 1.101ns (routing 0.440ns, distribution 0.661ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.906 1.022 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X28Y425 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X28Y425 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.070 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.212 1.282 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X30Y424 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.101 1.253 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X30Y424 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.143 1.110 SLICE_X30Y424 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.115 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -1.115 arrival time 1.282 ------------------------------------------------------------------- slack 0.167 Slack (MET) : 0.203ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.253ns (logic 0.048ns (18.972%) route 0.205ns (81.028%)) Logic Levels: 0 Clock Path Skew: 0.045ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.243ns Source Clock Delay (SCD): 1.022ns Clock Pessimism Removal (CPR): 0.176ns Clock Net Delay (Source): 0.906ns (routing 0.376ns, distribution 0.530ns) Clock Net Delay (Destination): 1.091ns (routing 0.440ns, distribution 0.651ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.906 1.022 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X28Y425 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X28Y425 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.070 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.205 1.275 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X28Y424 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.091 1.243 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X28Y424 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C clock pessimism -0.176 1.067 SLICE_X28Y424 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.072 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10] ------------------------------------------------------------------- required time -1.072 arrival time 1.275 ------------------------------------------------------------------- slack 0.203 Slack (MET) : 0.203ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.253ns (logic 0.048ns (18.972%) route 0.205ns (81.028%)) Logic Levels: 0 Clock Path Skew: 0.045ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.243ns Source Clock Delay (SCD): 1.022ns Clock Pessimism Removal (CPR): 0.176ns Clock Net Delay (Source): 0.906ns (routing 0.376ns, distribution 0.530ns) Clock Net Delay (Destination): 1.091ns (routing 0.440ns, distribution 0.651ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.906 1.022 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X28Y425 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X28Y425 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.070 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.205 1.275 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X28Y424 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.091 1.243 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X28Y424 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C clock pessimism -0.176 1.067 SLICE_X28Y424 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 1.072 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8] ------------------------------------------------------------------- required time -1.072 arrival time 1.275 ------------------------------------------------------------------- slack 0.203 Slack (MET) : 0.247ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.335ns (logic 0.048ns (14.328%) route 0.287ns (85.672%)) Logic Levels: 0 Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.248ns Source Clock Delay (SCD): 1.022ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.906ns (routing 0.376ns, distribution 0.530ns) Clock Net Delay (Destination): 1.096ns (routing 0.440ns, distribution 0.656ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.906 1.022 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X28Y425 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X28Y425 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.070 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.287 1.357 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X29Y421 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.096 1.248 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X29Y421 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C clock pessimism -0.143 1.105 SLICE_X29Y421 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.110 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11] ------------------------------------------------------------------- required time -1.110 arrival time 1.357 ------------------------------------------------------------------- slack 0.247 Slack (MET) : 0.247ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.335ns (logic 0.048ns (14.328%) route 0.287ns (85.672%)) Logic Levels: 0 Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.248ns Source Clock Delay (SCD): 1.022ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.906ns (routing 0.376ns, distribution 0.530ns) Clock Net Delay (Destination): 1.096ns (routing 0.440ns, distribution 0.656ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.906 1.022 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X28Y425 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X28Y425 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.070 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.287 1.357 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X29Y421 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.096 1.248 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X29Y421 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism -0.143 1.105 SLICE_X29Y421 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.110 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time -1.110 arrival time 1.357 ------------------------------------------------------------------- slack 0.247 Slack (MET) : 0.252ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.329ns (logic 0.048ns (14.590%) route 0.281ns (85.410%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.237ns Source Clock Delay (SCD): 1.022ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.906ns (routing 0.376ns, distribution 0.530ns) Clock Net Delay (Destination): 1.085ns (routing 0.440ns, distribution 0.645ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.906 1.022 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X28Y425 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X28Y425 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.070 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.281 1.351 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X27Y422 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.085 1.237 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X27Y422 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C clock pessimism -0.143 1.094 SLICE_X27Y422 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 1.099 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8] ------------------------------------------------------------------- required time -1.099 arrival time 1.351 ------------------------------------------------------------------- slack 0.252 Slack (MET) : 0.252ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.329ns (logic 0.048ns (14.590%) route 0.281ns (85.410%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.237ns Source Clock Delay (SCD): 1.022ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.906ns (routing 0.376ns, distribution 0.530ns) Clock Net Delay (Destination): 1.085ns (routing 0.440ns, distribution 0.645ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.906 1.022 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X28Y425 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X28Y425 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.070 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.281 1.351 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X27Y422 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y189 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.085 1.237 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X27Y422 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism -0.143 1.094 SLICE_X27Y422 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 1.099 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time -1.099 arrival time 1.351 ------------------------------------------------------------------- slack 0.252 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_4 To Clock: gtwiz_userclk_rx_srcclk_out[0]_4 Setup : 0 Failing Endpoints, Worst Slack 3.469ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.142ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.469ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 4.065ns (logic 0.285ns (7.011%) route 3.780ns (92.989%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.655ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.998ns = ( 11.315 - 8.317 ) Source Clock Delay (SCD): 3.942ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.467ns (routing 1.458ns, distribution 2.009ns) Clock Net Delay (Destination): 2.600ns (routing 1.333ns, distribution 1.267ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.467 3.942 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y89 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y89 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.081 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.865 6.946 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X86Y96 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 7.092 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/O net (fo=15, routed) 0.915 8.007 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X83Y92 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.600 11.315 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] SLICE_X83Y92 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/C clock pessimism 0.289 11.605 clock uncertainty -0.035 11.569 SLICE_X83Y92 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.476 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5] ------------------------------------------------------------------- required time 11.476 arrival time -8.007 ------------------------------------------------------------------- slack 3.469 Slack (MET) : 3.610ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 3.949ns (logic 0.285ns (7.217%) route 3.664ns (92.783%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.630ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.023ns = ( 11.340 - 8.317 ) Source Clock Delay (SCD): 3.942ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.467ns (routing 1.458ns, distribution 2.009ns) Clock Net Delay (Destination): 2.625ns (routing 1.333ns, distribution 1.292ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.467 3.942 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y89 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y89 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.081 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.865 6.946 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X86Y96 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 7.092 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/O net (fo=15, routed) 0.799 7.891 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X81Y94 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.625 11.340 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] SLICE_X81Y94 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/C clock pessimism 0.289 11.629 clock uncertainty -0.035 11.594 SLICE_X81Y94 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.501 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1] ------------------------------------------------------------------- required time 11.501 arrival time -7.891 ------------------------------------------------------------------- slack 3.610 Slack (MET) : 3.610ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 3.949ns (logic 0.285ns (7.217%) route 3.664ns (92.783%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.630ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.023ns = ( 11.340 - 8.317 ) Source Clock Delay (SCD): 3.942ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.467ns (routing 1.458ns, distribution 2.009ns) Clock Net Delay (Destination): 2.625ns (routing 1.333ns, distribution 1.292ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.467 3.942 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y89 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y89 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.081 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.865 6.946 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X86Y96 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 7.092 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/O net (fo=15, routed) 0.799 7.891 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X81Y94 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.625 11.340 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] SLICE_X81Y94 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/C clock pessimism 0.289 11.629 clock uncertainty -0.035 11.594 SLICE_X81Y94 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 11.501 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2] ------------------------------------------------------------------- required time 11.501 arrival time -7.891 ------------------------------------------------------------------- slack 3.610 Slack (MET) : 3.610ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 3.949ns (logic 0.285ns (7.217%) route 3.664ns (92.783%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.630ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.023ns = ( 11.340 - 8.317 ) Source Clock Delay (SCD): 3.942ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.467ns (routing 1.458ns, distribution 2.009ns) Clock Net Delay (Destination): 2.625ns (routing 1.333ns, distribution 1.292ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.467 3.942 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y89 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y89 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.081 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.865 6.946 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X86Y96 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 7.092 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/O net (fo=15, routed) 0.799 7.891 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X81Y94 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.625 11.340 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] SLICE_X81Y94 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/C clock pessimism 0.289 11.629 clock uncertainty -0.035 11.594 SLICE_X81Y94 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.501 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4] ------------------------------------------------------------------- required time 11.501 arrival time -7.891 ------------------------------------------------------------------- slack 3.610 Slack (MET) : 3.618ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 3.939ns (logic 0.285ns (7.235%) route 3.654ns (92.765%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.632ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.021ns = ( 11.338 - 8.317 ) Source Clock Delay (SCD): 3.942ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.467ns (routing 1.458ns, distribution 2.009ns) Clock Net Delay (Destination): 2.623ns (routing 1.333ns, distribution 1.290ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.467 3.942 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y89 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y89 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.081 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.865 6.946 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X86Y96 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 7.092 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/O net (fo=15, routed) 0.789 7.881 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X81Y94 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.623 11.338 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] SLICE_X81Y94 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C clock pessimism 0.289 11.627 clock uncertainty -0.035 11.592 SLICE_X81Y94 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.499 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3] ------------------------------------------------------------------- required time 11.499 arrival time -7.881 ------------------------------------------------------------------- slack 3.618 Slack (MET) : 3.646ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 3.906ns (logic 0.285ns (7.296%) route 3.621ns (92.704%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.637ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.016ns = ( 11.333 - 8.317 ) Source Clock Delay (SCD): 3.942ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.467ns (routing 1.458ns, distribution 2.009ns) Clock Net Delay (Destination): 2.618ns (routing 1.333ns, distribution 1.285ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.467 3.942 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y89 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y89 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.081 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.865 6.946 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X86Y96 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 7.092 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/O net (fo=15, routed) 0.756 7.848 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X82Y92 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.618 11.333 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] SLICE_X82Y92 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/C clock pessimism 0.289 11.622 clock uncertainty -0.035 11.587 SLICE_X82Y92 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.494 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2] ------------------------------------------------------------------- required time 11.494 arrival time -7.848 ------------------------------------------------------------------- slack 3.646 Slack (MET) : 3.651ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 3.899ns (logic 0.285ns (7.310%) route 3.614ns (92.690%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.639ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.014ns = ( 11.331 - 8.317 ) Source Clock Delay (SCD): 3.942ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.467ns (routing 1.458ns, distribution 2.009ns) Clock Net Delay (Destination): 2.616ns (routing 1.333ns, distribution 1.283ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.467 3.942 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y89 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y89 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.081 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.865 6.946 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X86Y96 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 7.092 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/O net (fo=15, routed) 0.749 7.841 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X82Y92 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.616 11.331 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] SLICE_X82Y92 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/C clock pessimism 0.289 11.620 clock uncertainty -0.035 11.585 SLICE_X82Y92 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.492 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1] ------------------------------------------------------------------- required time 11.492 arrival time -7.841 ------------------------------------------------------------------- slack 3.651 Slack (MET) : 3.725ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 3.826ns (logic 0.285ns (7.449%) route 3.541ns (92.551%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.638ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.015ns = ( 11.332 - 8.317 ) Source Clock Delay (SCD): 3.942ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.467ns (routing 1.458ns, distribution 2.009ns) Clock Net Delay (Destination): 2.617ns (routing 1.333ns, distribution 1.284ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.467 3.942 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y89 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y89 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.081 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.865 6.946 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X86Y96 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 7.092 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/O net (fo=15, routed) 0.676 7.768 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X82Y93 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.617 11.332 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] SLICE_X82Y93 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/C clock pessimism 0.289 11.621 clock uncertainty -0.035 11.586 SLICE_X82Y93 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 11.493 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] ------------------------------------------------------------------- required time 11.493 arrival time -7.768 ------------------------------------------------------------------- slack 3.725 Slack (MET) : 3.796ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 3.746ns (logic 0.285ns (7.608%) route 3.461ns (92.392%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.647ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.006ns = ( 11.323 - 8.317 ) Source Clock Delay (SCD): 3.942ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.467ns (routing 1.458ns, distribution 2.009ns) Clock Net Delay (Destination): 2.608ns (routing 1.333ns, distribution 1.275ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.467 3.942 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y89 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y89 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.081 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.865 6.946 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X86Y96 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 7.092 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/O net (fo=15, routed) 0.596 7.688 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X82Y91 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.608 11.323 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] SLICE_X82Y91 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/C clock pessimism 0.289 11.612 clock uncertainty -0.035 11.577 SLICE_X82Y91 FDCE (Recov_BFF2_SLICEM_C_CLR) -0.093 11.484 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0] ------------------------------------------------------------------- required time 11.484 arrival time -7.688 ------------------------------------------------------------------- slack 3.796 Slack (MET) : 3.796ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 3.746ns (logic 0.285ns (7.608%) route 3.461ns (92.392%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.647ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.006ns = ( 11.323 - 8.317 ) Source Clock Delay (SCD): 3.942ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.467ns (routing 1.458ns, distribution 2.009ns) Clock Net Delay (Destination): 2.608ns (routing 1.333ns, distribution 1.275ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.467 3.942 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X127Y89 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X127Y89 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 4.081 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.865 6.946 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X86Y96 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 7.092 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/O net (fo=15, routed) 0.596 7.688 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X82Y91 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.608 11.323 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] SLICE_X82Y91 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/C clock pessimism 0.289 11.612 clock uncertainty -0.035 11.577 SLICE_X82Y91 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.484 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5] ------------------------------------------------------------------- required time 11.484 arrival time -7.688 ------------------------------------------------------------------- slack 3.796 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.142ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[88]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.049ns (22.172%) route 0.172ns (77.828%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.498ns Source Clock Delay (SCD): 1.253ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 1.135ns (routing 0.607ns, distribution 0.528ns) Clock Net Delay (Destination): 1.333ns (routing 0.684ns, distribution 0.649ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.135 1.253 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X80Y83 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y83 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.302 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.172 1.474 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X77Y83 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[88]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.333 1.498 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X77Y83 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[88]/C clock pessimism -0.171 1.327 SLICE_X77Y83 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.332 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[88] ------------------------------------------------------------------- required time -1.332 arrival time 1.474 ------------------------------------------------------------------- slack 0.142 Slack (MET) : 0.142ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[91]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.049ns (22.172%) route 0.172ns (77.828%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.498ns Source Clock Delay (SCD): 1.253ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 1.135ns (routing 0.607ns, distribution 0.528ns) Clock Net Delay (Destination): 1.333ns (routing 0.684ns, distribution 0.649ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.135 1.253 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X80Y83 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y83 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.302 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.172 1.474 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X77Y83 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[91]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.333 1.498 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X77Y83 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[91]/C clock pessimism -0.171 1.327 SLICE_X77Y83 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.332 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[91] ------------------------------------------------------------------- required time -1.332 arrival time 1.474 ------------------------------------------------------------------- slack 0.142 Slack (MET) : 0.142ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[97]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.049ns (22.172%) route 0.172ns (77.828%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.498ns Source Clock Delay (SCD): 1.253ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 1.135ns (routing 0.607ns, distribution 0.528ns) Clock Net Delay (Destination): 1.333ns (routing 0.684ns, distribution 0.649ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.135 1.253 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X80Y83 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y83 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.302 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.172 1.474 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X77Y83 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[97]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.333 1.498 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X77Y83 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[97]/C clock pessimism -0.171 1.327 SLICE_X77Y83 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.332 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[97] ------------------------------------------------------------------- required time -1.332 arrival time 1.474 ------------------------------------------------------------------- slack 0.142 Slack (MET) : 0.142ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[98]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.049ns (22.172%) route 0.172ns (77.828%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.498ns Source Clock Delay (SCD): 1.253ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 1.135ns (routing 0.607ns, distribution 0.528ns) Clock Net Delay (Destination): 1.333ns (routing 0.684ns, distribution 0.649ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.135 1.253 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X80Y83 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y83 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.302 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.172 1.474 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X77Y83 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[98]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.333 1.498 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X77Y83 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[98]/C clock pessimism -0.171 1.327 SLICE_X77Y83 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.332 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[98] ------------------------------------------------------------------- required time -1.332 arrival time 1.474 ------------------------------------------------------------------- slack 0.142 Slack (MET) : 0.142ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[88]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.049ns (22.172%) route 0.172ns (77.828%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.498ns Source Clock Delay (SCD): 1.253ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 1.135ns (routing 0.607ns, distribution 0.528ns) Clock Net Delay (Destination): 1.333ns (routing 0.684ns, distribution 0.649ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.135 1.253 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X80Y83 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y83 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.302 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.172 1.474 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X77Y83 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[88]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.333 1.498 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X77Y83 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[88]/C clock pessimism -0.171 1.327 SLICE_X77Y83 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.332 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[88] ------------------------------------------------------------------- required time -1.332 arrival time 1.474 ------------------------------------------------------------------- slack 0.142 Slack (MET) : 0.142ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[91]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.049ns (22.172%) route 0.172ns (77.828%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.498ns Source Clock Delay (SCD): 1.253ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 1.135ns (routing 0.607ns, distribution 0.528ns) Clock Net Delay (Destination): 1.333ns (routing 0.684ns, distribution 0.649ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.135 1.253 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X80Y83 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y83 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.302 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.172 1.474 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X77Y83 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[91]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.333 1.498 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X77Y83 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[91]/C clock pessimism -0.171 1.327 SLICE_X77Y83 FDCE (Remov_GFF2_SLICEM_C_CLR) 0.005 1.332 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[91] ------------------------------------------------------------------- required time -1.332 arrival time 1.474 ------------------------------------------------------------------- slack 0.142 Slack (MET) : 0.142ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[97]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.049ns (22.172%) route 0.172ns (77.828%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.498ns Source Clock Delay (SCD): 1.253ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 1.135ns (routing 0.607ns, distribution 0.528ns) Clock Net Delay (Destination): 1.333ns (routing 0.684ns, distribution 0.649ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.135 1.253 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X80Y83 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y83 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.302 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.172 1.474 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X77Y83 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[97]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.333 1.498 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X77Y83 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[97]/C clock pessimism -0.171 1.327 SLICE_X77Y83 FDCE (Remov_FFF2_SLICEM_C_CLR) 0.005 1.332 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[97] ------------------------------------------------------------------- required time -1.332 arrival time 1.474 ------------------------------------------------------------------- slack 0.142 Slack (MET) : 0.142ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[98]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.049ns (22.172%) route 0.172ns (77.828%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.498ns Source Clock Delay (SCD): 1.253ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 1.135ns (routing 0.607ns, distribution 0.528ns) Clock Net Delay (Destination): 1.333ns (routing 0.684ns, distribution 0.649ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.135 1.253 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X80Y83 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y83 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.302 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.172 1.474 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X77Y83 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[98]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.333 1.498 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X77Y83 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[98]/C clock pessimism -0.171 1.327 SLICE_X77Y83 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.332 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[98] ------------------------------------------------------------------- required time -1.332 arrival time 1.474 ------------------------------------------------------------------- slack 0.142 Slack (MET) : 0.143ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[11]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.500ns Source Clock Delay (SCD): 1.253ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 1.135ns (routing 0.607ns, distribution 0.528ns) Clock Net Delay (Destination): 1.335ns (routing 0.684ns, distribution 0.651ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.135 1.253 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X80Y83 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y83 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.302 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.175 1.477 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X77Y83 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[11]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.335 1.500 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X77Y83 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[11]/C clock pessimism -0.171 1.329 SLICE_X77Y83 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.334 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[11] ------------------------------------------------------------------- required time -1.334 arrival time 1.477 ------------------------------------------------------------------- slack 0.143 Slack (MET) : 0.143ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.500ns Source Clock Delay (SCD): 1.253ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 1.135ns (routing 0.607ns, distribution 0.528ns) Clock Net Delay (Destination): 1.335ns (routing 0.684ns, distribution 0.651ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.135 1.253 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X80Y83 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y83 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.302 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.175 1.477 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X77Y83 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y41 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.335 1.500 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X77Y83 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[17]/C clock pessimism -0.171 1.329 SLICE_X77Y83 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 1.334 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[17] ------------------------------------------------------------------- required time -1.334 arrival time 1.477 ------------------------------------------------------------------- slack 0.143 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_40 To Clock: gtwiz_userclk_rx_srcclk_out[0]_40 Setup : 0 Failing Endpoints, Worst Slack 5.554ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.146ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.554ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 2.523ns (logic 0.139ns (5.509%) route 2.384ns (94.491%)) Logic Levels: 0 Clock Path Skew: -0.112ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.351ns = ( 10.668 - 8.317 ) Source Clock Delay (SCD): 2.666ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.241ns (routing 0.775ns, distribution 1.466ns) Clock Net Delay (Destination): 1.975ns (routing 0.697ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.241 2.666 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X36Y458 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X36Y458 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.805 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 2.384 5.189 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X38Y470 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.975 10.668 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X38Y470 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C clock pessimism 0.203 10.871 clock uncertainty -0.035 10.836 SLICE_X38Y470 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.743 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12] ------------------------------------------------------------------- required time 10.743 arrival time -5.189 ------------------------------------------------------------------- slack 5.554 Slack (MET) : 5.554ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 2.523ns (logic 0.139ns (5.509%) route 2.384ns (94.491%)) Logic Levels: 0 Clock Path Skew: -0.112ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.351ns = ( 10.668 - 8.317 ) Source Clock Delay (SCD): 2.666ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.241ns (routing 0.775ns, distribution 1.466ns) Clock Net Delay (Destination): 1.975ns (routing 0.697ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.241 2.666 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X36Y458 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X36Y458 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.805 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 2.384 5.189 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X38Y470 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.975 10.668 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X38Y470 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C clock pessimism 0.203 10.871 clock uncertainty -0.035 10.836 SLICE_X38Y470 FDCE (Recov_AFF2_SLICEL_C_CLR) -0.093 10.743 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14] ------------------------------------------------------------------- required time 10.743 arrival time -5.189 ------------------------------------------------------------------- slack 5.554 Slack (MET) : 5.554ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 2.523ns (logic 0.139ns (5.509%) route 2.384ns (94.491%)) Logic Levels: 0 Clock Path Skew: -0.112ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.351ns = ( 10.668 - 8.317 ) Source Clock Delay (SCD): 2.666ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.241ns (routing 0.775ns, distribution 1.466ns) Clock Net Delay (Destination): 1.975ns (routing 0.697ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.241 2.666 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X36Y458 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X36Y458 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.805 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 2.384 5.189 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X38Y470 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.975 10.668 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X38Y470 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism 0.203 10.871 clock uncertainty -0.035 10.836 SLICE_X38Y470 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.743 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time 10.743 arrival time -5.189 ------------------------------------------------------------------- slack 5.554 Slack (MET) : 5.554ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 2.523ns (logic 0.139ns (5.509%) route 2.384ns (94.491%)) Logic Levels: 0 Clock Path Skew: -0.112ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.351ns = ( 10.668 - 8.317 ) Source Clock Delay (SCD): 2.666ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.241ns (routing 0.775ns, distribution 1.466ns) Clock Net Delay (Destination): 1.975ns (routing 0.697ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.241 2.666 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X36Y458 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X36Y458 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.805 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 2.384 5.189 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X38Y470 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.975 10.668 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X38Y470 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C clock pessimism 0.203 10.871 clock uncertainty -0.035 10.836 SLICE_X38Y470 FDCE (Recov_BFF2_SLICEL_C_CLR) -0.093 10.743 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time 10.743 arrival time -5.189 ------------------------------------------------------------------- slack 5.554 Slack (MET) : 5.554ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 2.523ns (logic 0.139ns (5.509%) route 2.384ns (94.491%)) Logic Levels: 0 Clock Path Skew: -0.112ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.351ns = ( 10.668 - 8.317 ) Source Clock Delay (SCD): 2.666ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.241ns (routing 0.775ns, distribution 1.466ns) Clock Net Delay (Destination): 1.975ns (routing 0.697ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.241 2.666 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X36Y458 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X36Y458 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.805 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 2.384 5.189 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X38Y470 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.975 10.668 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X38Y470 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism 0.203 10.871 clock uncertainty -0.035 10.836 SLICE_X38Y470 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.743 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time 10.743 arrival time -5.189 ------------------------------------------------------------------- slack 5.554 Slack (MET) : 5.554ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 2.523ns (logic 0.139ns (5.509%) route 2.384ns (94.491%)) Logic Levels: 0 Clock Path Skew: -0.112ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.351ns = ( 10.668 - 8.317 ) Source Clock Delay (SCD): 2.666ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.241ns (routing 0.775ns, distribution 1.466ns) Clock Net Delay (Destination): 1.975ns (routing 0.697ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.241 2.666 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X36Y458 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X36Y458 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.805 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 2.384 5.189 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X38Y470 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.975 10.668 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X38Y470 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C clock pessimism 0.203 10.871 clock uncertainty -0.035 10.836 SLICE_X38Y470 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 10.743 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time 10.743 arrival time -5.189 ------------------------------------------------------------------- slack 5.554 Slack (MET) : 5.554ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 2.523ns (logic 0.139ns (5.509%) route 2.384ns (94.491%)) Logic Levels: 0 Clock Path Skew: -0.112ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.351ns = ( 10.668 - 8.317 ) Source Clock Delay (SCD): 2.666ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.241ns (routing 0.775ns, distribution 1.466ns) Clock Net Delay (Destination): 1.975ns (routing 0.697ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.241 2.666 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X36Y458 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X36Y458 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.805 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 2.384 5.189 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X38Y470 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.975 10.668 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X38Y470 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C clock pessimism 0.203 10.871 clock uncertainty -0.035 10.836 SLICE_X38Y470 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.743 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3] ------------------------------------------------------------------- required time 10.743 arrival time -5.189 ------------------------------------------------------------------- slack 5.554 Slack (MET) : 5.767ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[60]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 2.281ns (logic 0.140ns (6.138%) route 2.141ns (93.862%)) Logic Levels: 0 Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.339ns = ( 10.656 - 8.317 ) Source Clock Delay (SCD): 2.683ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.258ns (routing 0.775ns, distribution 1.483ns) Clock Net Delay (Destination): 1.963ns (routing 0.697ns, distribution 1.266ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.258 2.683 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X41Y427 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y427 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 2.823 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 2.141 4.964 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X33Y458 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[60]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.963 10.656 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X33Y458 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[60]/C clock pessimism 0.203 10.859 clock uncertainty -0.035 10.824 SLICE_X33Y458 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.731 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[60] ------------------------------------------------------------------- required time 10.731 arrival time -4.964 ------------------------------------------------------------------- slack 5.767 Slack (MET) : 5.767ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[79]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 2.281ns (logic 0.140ns (6.138%) route 2.141ns (93.862%)) Logic Levels: 0 Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.339ns = ( 10.656 - 8.317 ) Source Clock Delay (SCD): 2.683ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.258ns (routing 0.775ns, distribution 1.483ns) Clock Net Delay (Destination): 1.963ns (routing 0.697ns, distribution 1.266ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.258 2.683 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X41Y427 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y427 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 2.823 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 2.141 4.964 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X33Y458 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[79]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.963 10.656 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X33Y458 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[79]/C clock pessimism 0.203 10.859 clock uncertainty -0.035 10.824 SLICE_X33Y458 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.731 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[79] ------------------------------------------------------------------- required time 10.731 arrival time -4.964 ------------------------------------------------------------------- slack 5.767 Slack (MET) : 5.767ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[100]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 2.281ns (logic 0.140ns (6.138%) route 2.141ns (93.862%)) Logic Levels: 0 Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.339ns = ( 10.656 - 8.317 ) Source Clock Delay (SCD): 2.683ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.258ns (routing 0.775ns, distribution 1.483ns) Clock Net Delay (Destination): 1.963ns (routing 0.697ns, distribution 1.266ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.258 2.683 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X41Y427 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y427 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 2.823 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 2.141 4.964 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X33Y458 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[100]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.963 10.656 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X33Y458 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[100]/C clock pessimism 0.203 10.859 clock uncertainty -0.035 10.824 SLICE_X33Y458 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 10.731 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[100] ------------------------------------------------------------------- required time 10.731 arrival time -4.964 ------------------------------------------------------------------- slack 5.767 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.146ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.181ns (logic 0.049ns (27.072%) route 0.132ns (72.928%)) Logic Levels: 0 Clock Path Skew: 0.030ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.201ns Source Clock Delay (SCD): 0.991ns Clock Pessimism Removal (CPR): 0.180ns Clock Net Delay (Source): 0.875ns (routing 0.369ns, distribution 0.506ns) Clock Net Delay (Destination): 1.049ns (routing 0.431ns, distribution 0.618ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.875 0.991 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X41Y427 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y427 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.040 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.132 1.172 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X41Y427 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.049 1.201 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X41Y427 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.180 1.021 SLICE_X41Y427 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.026 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -1.026 arrival time 1.172 ------------------------------------------------------------------- slack 0.146 Slack (MET) : 0.149ns (arrival time - required time) Source: SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.230ns (logic 0.048ns (20.870%) route 0.182ns (79.130%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.195ns Source Clock Delay (SCD): 0.976ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.860ns (routing 0.369ns, distribution 0.491ns) Clock Net Delay (Destination): 1.043ns (routing 0.431ns, distribution 0.612ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.860 0.976 SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y455 FDPE r SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y455 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.024 f SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.182 1.206 SFP_GEN[38].ngCCM_gbt/sync_m_reg[3][0] SLICE_X40Y456 FDCE f SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.043 1.195 SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X40Y456 FDCE r SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[25]/C clock pessimism -0.143 1.052 SLICE_X40Y456 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.057 SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[25] ------------------------------------------------------------------- required time -1.057 arrival time 1.206 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.149ns (arrival time - required time) Source: SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.230ns (logic 0.048ns (20.870%) route 0.182ns (79.130%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.195ns Source Clock Delay (SCD): 0.976ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.860ns (routing 0.369ns, distribution 0.491ns) Clock Net Delay (Destination): 1.043ns (routing 0.431ns, distribution 0.612ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.860 0.976 SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y455 FDPE r SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y455 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.024 f SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.182 1.206 SFP_GEN[38].ngCCM_gbt/sync_m_reg[3][0] SLICE_X40Y456 FDCE f SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.043 1.195 SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X40Y456 FDCE r SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[30]/C clock pessimism -0.143 1.052 SLICE_X40Y456 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.057 SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[30] ------------------------------------------------------------------- required time -1.057 arrival time 1.206 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.204ns (arrival time - required time) Source: SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.254ns (logic 0.048ns (18.898%) route 0.206ns (81.102%)) Logic Levels: 0 Clock Path Skew: 0.045ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.192ns Source Clock Delay (SCD): 0.976ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.860ns (routing 0.369ns, distribution 0.491ns) Clock Net Delay (Destination): 1.040ns (routing 0.431ns, distribution 0.609ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.860 0.976 SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y455 FDPE r SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y455 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.024 f SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.206 1.230 SFP_GEN[38].ngCCM_gbt/sync_m_reg[3][0] SLICE_X41Y456 FDCE f SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.040 1.192 SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y456 FDCE r SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[21]/C clock pessimism -0.171 1.021 SLICE_X41Y456 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.026 SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[21] ------------------------------------------------------------------- required time -1.026 arrival time 1.230 ------------------------------------------------------------------- slack 0.204 Slack (MET) : 0.204ns (arrival time - required time) Source: SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.254ns (logic 0.048ns (18.898%) route 0.206ns (81.102%)) Logic Levels: 0 Clock Path Skew: 0.045ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.192ns Source Clock Delay (SCD): 0.976ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.860ns (routing 0.369ns, distribution 0.491ns) Clock Net Delay (Destination): 1.040ns (routing 0.431ns, distribution 0.609ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.860 0.976 SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y455 FDPE r SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y455 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.024 f SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.206 1.230 SFP_GEN[38].ngCCM_gbt/sync_m_reg[3][0] SLICE_X41Y456 FDCE f SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.040 1.192 SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y456 FDCE r SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[23]/C clock pessimism -0.171 1.021 SLICE_X41Y456 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.026 SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[23] ------------------------------------------------------------------- required time -1.026 arrival time 1.230 ------------------------------------------------------------------- slack 0.204 Slack (MET) : 0.204ns (arrival time - required time) Source: SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.254ns (logic 0.048ns (18.898%) route 0.206ns (81.102%)) Logic Levels: 0 Clock Path Skew: 0.045ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.192ns Source Clock Delay (SCD): 0.976ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.860ns (routing 0.369ns, distribution 0.491ns) Clock Net Delay (Destination): 1.040ns (routing 0.431ns, distribution 0.609ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.860 0.976 SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y455 FDPE r SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y455 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.024 f SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.206 1.230 SFP_GEN[38].ngCCM_gbt/sync_m_reg[3][0] SLICE_X41Y456 FDCE f SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.040 1.192 SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y456 FDCE r SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[32]/C clock pessimism -0.171 1.021 SLICE_X41Y456 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.026 SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[32] ------------------------------------------------------------------- required time -1.026 arrival time 1.230 ------------------------------------------------------------------- slack 0.204 Slack (MET) : 0.204ns (arrival time - required time) Source: SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.254ns (logic 0.048ns (18.898%) route 0.206ns (81.102%)) Logic Levels: 0 Clock Path Skew: 0.045ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.192ns Source Clock Delay (SCD): 0.976ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.860ns (routing 0.369ns, distribution 0.491ns) Clock Net Delay (Destination): 1.040ns (routing 0.431ns, distribution 0.609ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.860 0.976 SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y455 FDPE r SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y455 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.024 f SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.206 1.230 SFP_GEN[38].ngCCM_gbt/sync_m_reg[3][0] SLICE_X41Y456 FDCE f SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.040 1.192 SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y456 FDCE r SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[34]/C clock pessimism -0.171 1.021 SLICE_X41Y456 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.026 SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[34] ------------------------------------------------------------------- required time -1.026 arrival time 1.230 ------------------------------------------------------------------- slack 0.204 Slack (MET) : 0.204ns (arrival time - required time) Source: SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.254ns (logic 0.048ns (18.898%) route 0.206ns (81.102%)) Logic Levels: 0 Clock Path Skew: 0.045ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.192ns Source Clock Delay (SCD): 0.976ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.860ns (routing 0.369ns, distribution 0.491ns) Clock Net Delay (Destination): 1.040ns (routing 0.431ns, distribution 0.609ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.860 0.976 SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y455 FDPE r SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y455 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.024 f SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.206 1.230 SFP_GEN[38].ngCCM_gbt/sync_m_reg[3][0] SLICE_X41Y456 FDCE f SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.040 1.192 SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y456 FDCE r SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[36]/C clock pessimism -0.171 1.021 SLICE_X41Y456 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.026 SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[36] ------------------------------------------------------------------- required time -1.026 arrival time 1.230 ------------------------------------------------------------------- slack 0.204 Slack (MET) : 0.204ns (arrival time - required time) Source: SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.254ns (logic 0.048ns (18.898%) route 0.206ns (81.102%)) Logic Levels: 0 Clock Path Skew: 0.045ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.192ns Source Clock Delay (SCD): 0.976ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.860ns (routing 0.369ns, distribution 0.491ns) Clock Net Delay (Destination): 1.040ns (routing 0.431ns, distribution 0.609ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.860 0.976 SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y455 FDPE r SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y455 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.024 f SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.206 1.230 SFP_GEN[38].ngCCM_gbt/sync_m_reg[3][0] SLICE_X41Y456 FDCE f SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.040 1.192 SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y456 FDCE r SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[38]/C clock pessimism -0.171 1.021 SLICE_X41Y456 FDCE (Remov_GFF2_SLICEM_C_CLR) 0.005 1.026 SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[38] ------------------------------------------------------------------- required time -1.026 arrival time 1.230 ------------------------------------------------------------------- slack 0.204 Slack (MET) : 0.205ns (arrival time - required time) Source: SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.257ns (logic 0.048ns (18.677%) route 0.209ns (81.323%)) Logic Levels: 0 Clock Path Skew: 0.047ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.194ns Source Clock Delay (SCD): 0.976ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.860ns (routing 0.369ns, distribution 0.491ns) Clock Net Delay (Destination): 1.042ns (routing 0.431ns, distribution 0.611ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.860 0.976 SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y455 FDPE r SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y455 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.024 f SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.209 1.233 SFP_GEN[38].ngCCM_gbt/sync_m_reg[3][0] SLICE_X41Y456 FDCE f SFP_GEN[38].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y185 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.042 1.194 SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y456 FDCE r SFP_GEN[38].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.171 1.023 SLICE_X41Y456 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.028 SFP_GEN[38].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.028 arrival time 1.233 ------------------------------------------------------------------- slack 0.205 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_41 To Clock: gtwiz_userclk_rx_srcclk_out[0]_41 Setup : 0 Failing Endpoints, Worst Slack 5.115ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.163ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.115ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 2.839ns (logic 0.304ns (10.708%) route 2.535ns (89.292%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.235ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.699ns = ( 11.016 - 8.317 ) Source Clock Delay (SCD): 3.155ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.730ns (routing 1.081ns, distribution 1.649ns) Clock Net Delay (Destination): 2.323ns (routing 0.984ns, distribution 1.339ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.730 3.155 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X15Y464 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X15Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.294 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.799 5.093 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X45Y439 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 5.258 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/O net (fo=15, routed) 0.736 5.994 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X46Y448 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.323 11.016 g_gbt_bank[3].gbtbank/CLK SLICE_X46Y448 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/C clock pessimism 0.221 11.237 clock uncertainty -0.035 11.202 SLICE_X46Y448 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.109 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3] ------------------------------------------------------------------- required time 11.109 arrival time -5.994 ------------------------------------------------------------------- slack 5.115 Slack (MET) : 5.115ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 2.839ns (logic 0.304ns (10.708%) route 2.535ns (89.292%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.235ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.699ns = ( 11.016 - 8.317 ) Source Clock Delay (SCD): 3.155ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.730ns (routing 1.081ns, distribution 1.649ns) Clock Net Delay (Destination): 2.323ns (routing 0.984ns, distribution 1.339ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.730 3.155 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X15Y464 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X15Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.294 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.799 5.093 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X45Y439 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 5.258 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/O net (fo=15, routed) 0.736 5.994 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X46Y448 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.323 11.016 g_gbt_bank[3].gbtbank/CLK SLICE_X46Y448 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/C clock pessimism 0.221 11.237 clock uncertainty -0.035 11.202 SLICE_X46Y448 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 11.109 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0] ------------------------------------------------------------------- required time 11.109 arrival time -5.994 ------------------------------------------------------------------- slack 5.115 Slack (MET) : 5.123ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 2.829ns (logic 0.304ns (10.746%) route 2.525ns (89.254%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.237ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.697ns = ( 11.014 - 8.317 ) Source Clock Delay (SCD): 3.155ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.730ns (routing 1.081ns, distribution 1.649ns) Clock Net Delay (Destination): 2.321ns (routing 0.984ns, distribution 1.337ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.730 3.155 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X15Y464 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X15Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.294 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.799 5.093 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X45Y439 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 5.258 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/O net (fo=15, routed) 0.726 5.984 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X46Y448 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.321 11.014 g_gbt_bank[3].gbtbank/CLK SLICE_X46Y448 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/C clock pessimism 0.221 11.235 clock uncertainty -0.035 11.200 SLICE_X46Y448 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 11.107 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2] ------------------------------------------------------------------- required time 11.107 arrival time -5.984 ------------------------------------------------------------------- slack 5.123 Slack (MET) : 5.123ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 2.829ns (logic 0.304ns (10.746%) route 2.525ns (89.254%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.237ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.697ns = ( 11.014 - 8.317 ) Source Clock Delay (SCD): 3.155ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.730ns (routing 1.081ns, distribution 1.649ns) Clock Net Delay (Destination): 2.321ns (routing 0.984ns, distribution 1.337ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.730 3.155 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X15Y464 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X15Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.294 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.799 5.093 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X45Y439 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 5.258 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/O net (fo=15, routed) 0.726 5.984 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X46Y448 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.321 11.014 g_gbt_bank[3].gbtbank/CLK SLICE_X46Y448 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C clock pessimism 0.221 11.235 clock uncertainty -0.035 11.200 SLICE_X46Y448 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 11.107 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3] ------------------------------------------------------------------- required time 11.107 arrival time -5.984 ------------------------------------------------------------------- slack 5.123 Slack (MET) : 5.123ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 2.829ns (logic 0.304ns (10.746%) route 2.525ns (89.254%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.237ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.697ns = ( 11.014 - 8.317 ) Source Clock Delay (SCD): 3.155ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.730ns (routing 1.081ns, distribution 1.649ns) Clock Net Delay (Destination): 2.321ns (routing 0.984ns, distribution 1.337ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.730 3.155 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X15Y464 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X15Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.294 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.799 5.093 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X45Y439 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 5.258 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/O net (fo=15, routed) 0.726 5.984 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X46Y448 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.321 11.014 g_gbt_bank[3].gbtbank/CLK SLICE_X46Y448 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/C clock pessimism 0.221 11.235 clock uncertainty -0.035 11.200 SLICE_X46Y448 FDCE (Recov_FFF_SLICEL_C_CLR) -0.093 11.107 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4] ------------------------------------------------------------------- required time 11.107 arrival time -5.984 ------------------------------------------------------------------- slack 5.123 Slack (MET) : 5.123ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 2.829ns (logic 0.304ns (10.746%) route 2.525ns (89.254%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.237ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.697ns = ( 11.014 - 8.317 ) Source Clock Delay (SCD): 3.155ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.730ns (routing 1.081ns, distribution 1.649ns) Clock Net Delay (Destination): 2.321ns (routing 0.984ns, distribution 1.337ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.730 3.155 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X15Y464 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X15Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.294 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.799 5.093 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X45Y439 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 5.258 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/O net (fo=15, routed) 0.726 5.984 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X46Y448 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.321 11.014 g_gbt_bank[3].gbtbank/CLK SLICE_X46Y448 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/C clock pessimism 0.221 11.235 clock uncertainty -0.035 11.200 SLICE_X46Y448 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.107 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5] ------------------------------------------------------------------- required time 11.107 arrival time -5.984 ------------------------------------------------------------------- slack 5.123 Slack (MET) : 5.123ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 2.829ns (logic 0.304ns (10.746%) route 2.525ns (89.254%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.237ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.697ns = ( 11.014 - 8.317 ) Source Clock Delay (SCD): 3.155ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.730ns (routing 1.081ns, distribution 1.649ns) Clock Net Delay (Destination): 2.321ns (routing 0.984ns, distribution 1.337ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.730 3.155 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X15Y464 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X15Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.294 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.799 5.093 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X45Y439 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 5.258 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/O net (fo=15, routed) 0.726 5.984 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X46Y448 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.321 11.014 g_gbt_bank[3].gbtbank/CLK SLICE_X46Y448 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/C clock pessimism 0.221 11.235 clock uncertainty -0.035 11.200 SLICE_X46Y448 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 11.107 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0] ------------------------------------------------------------------- required time 11.107 arrival time -5.984 ------------------------------------------------------------------- slack 5.123 Slack (MET) : 5.199ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 2.760ns (logic 0.305ns (11.051%) route 2.455ns (88.949%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.704ns = ( 11.021 - 8.317 ) Source Clock Delay (SCD): 3.155ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.730ns (routing 1.081ns, distribution 1.649ns) Clock Net Delay (Destination): 2.328ns (routing 0.984ns, distribution 1.344ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.730 3.155 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X15Y464 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X15Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.294 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.011 5.305 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X46Y438 LUT2 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.471 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__38/O net (fo=2, routed) 0.444 5.915 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X46Y443 FDCE f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.328 11.021 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK SLICE_X46Y443 FDCE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.221 11.242 clock uncertainty -0.035 11.207 SLICE_X46Y443 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.114 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 11.114 arrival time -5.915 ------------------------------------------------------------------- slack 5.199 Slack (MET) : 5.199ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 2.760ns (logic 0.305ns (11.051%) route 2.455ns (88.949%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.704ns = ( 11.021 - 8.317 ) Source Clock Delay (SCD): 3.155ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.730ns (routing 1.081ns, distribution 1.649ns) Clock Net Delay (Destination): 2.328ns (routing 0.984ns, distribution 1.344ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.730 3.155 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X15Y464 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X15Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.294 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.011 5.305 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X46Y438 LUT2 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.471 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__38/O net (fo=2, routed) 0.444 5.915 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X46Y443 FDCE f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.328 11.021 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK SLICE_X46Y443 FDCE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.221 11.242 clock uncertainty -0.035 11.207 SLICE_X46Y443 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 11.114 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 11.114 arrival time -5.915 ------------------------------------------------------------------- slack 5.199 Slack (MET) : 5.214ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 2.743ns (logic 0.304ns (11.083%) route 2.439ns (88.917%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.702ns = ( 11.019 - 8.317 ) Source Clock Delay (SCD): 3.155ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.730ns (routing 1.081ns, distribution 1.649ns) Clock Net Delay (Destination): 2.326ns (routing 0.984ns, distribution 1.342ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.730 3.155 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X15Y464 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X15Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.294 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.799 5.093 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X45Y439 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 5.258 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/O net (fo=15, routed) 0.640 5.898 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X46Y446 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.326 11.019 g_gbt_bank[3].gbtbank/CLK SLICE_X46Y446 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/C clock pessimism 0.221 11.240 clock uncertainty -0.035 11.205 SLICE_X46Y446 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.112 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1] ------------------------------------------------------------------- required time 11.112 arrival time -5.898 ------------------------------------------------------------------- slack 5.214 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.163ns (arrival time - required time) Source: SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.236ns (logic 0.048ns (20.339%) route 0.188ns (79.661%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.494ns Source Clock Delay (SCD): 1.263ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 1.147ns (routing 0.463ns, distribution 0.684ns) Clock Net Delay (Destination): 1.342ns (routing 0.528ns, distribution 0.814ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.147 1.263 SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X49Y440 FDPE r SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y440 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.311 f SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.188 1.499 SFP_GEN[39].ngCCM_gbt/sync_m_reg[3][0] SLICE_X48Y439 FDCE f SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.342 1.494 SFP_GEN[39].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y439 FDCE r SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[16]/C clock pessimism -0.163 1.331 SLICE_X48Y439 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.336 SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[16] ------------------------------------------------------------------- required time -1.336 arrival time 1.499 ------------------------------------------------------------------- slack 0.163 Slack (MET) : 0.163ns (arrival time - required time) Source: SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.236ns (logic 0.048ns (20.339%) route 0.188ns (79.661%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.494ns Source Clock Delay (SCD): 1.263ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 1.147ns (routing 0.463ns, distribution 0.684ns) Clock Net Delay (Destination): 1.342ns (routing 0.528ns, distribution 0.814ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.147 1.263 SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X49Y440 FDPE r SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y440 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.311 f SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.188 1.499 SFP_GEN[39].ngCCM_gbt/sync_m_reg[3][0] SLICE_X48Y439 FDCE f SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.342 1.494 SFP_GEN[39].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y439 FDCE r SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[21]/C clock pessimism -0.163 1.331 SLICE_X48Y439 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.336 SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[21] ------------------------------------------------------------------- required time -1.336 arrival time 1.499 ------------------------------------------------------------------- slack 0.163 Slack (MET) : 0.163ns (arrival time - required time) Source: SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[22]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.236ns (logic 0.048ns (20.339%) route 0.188ns (79.661%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.494ns Source Clock Delay (SCD): 1.263ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 1.147ns (routing 0.463ns, distribution 0.684ns) Clock Net Delay (Destination): 1.342ns (routing 0.528ns, distribution 0.814ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.147 1.263 SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X49Y440 FDPE r SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y440 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.311 f SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.188 1.499 SFP_GEN[39].ngCCM_gbt/sync_m_reg[3][0] SLICE_X48Y439 FDCE f SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[22]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.342 1.494 SFP_GEN[39].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y439 FDCE r SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[22]/C clock pessimism -0.163 1.331 SLICE_X48Y439 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 1.336 SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[22] ------------------------------------------------------------------- required time -1.336 arrival time 1.499 ------------------------------------------------------------------- slack 0.163 Slack (MET) : 0.163ns (arrival time - required time) Source: SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.236ns (logic 0.048ns (20.339%) route 0.188ns (79.661%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.494ns Source Clock Delay (SCD): 1.263ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 1.147ns (routing 0.463ns, distribution 0.684ns) Clock Net Delay (Destination): 1.342ns (routing 0.528ns, distribution 0.814ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.147 1.263 SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X49Y440 FDPE r SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y440 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.311 f SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.188 1.499 SFP_GEN[39].ngCCM_gbt/sync_m_reg[3][0] SLICE_X48Y439 FDCE f SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.342 1.494 SFP_GEN[39].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y439 FDCE r SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[23]/C clock pessimism -0.163 1.331 SLICE_X48Y439 FDCE (Remov_BFF2_SLICEL_C_CLR) 0.005 1.336 SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[23] ------------------------------------------------------------------- required time -1.336 arrival time 1.499 ------------------------------------------------------------------- slack 0.163 Slack (MET) : 0.163ns (arrival time - required time) Source: SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.236ns (logic 0.048ns (20.339%) route 0.188ns (79.661%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.494ns Source Clock Delay (SCD): 1.263ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 1.147ns (routing 0.463ns, distribution 0.684ns) Clock Net Delay (Destination): 1.342ns (routing 0.528ns, distribution 0.814ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.147 1.263 SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X49Y440 FDPE r SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y440 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.311 f SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.188 1.499 SFP_GEN[39].ngCCM_gbt/sync_m_reg[3][0] SLICE_X48Y439 FDCE f SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.342 1.494 SFP_GEN[39].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y439 FDCE r SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[24]/C clock pessimism -0.163 1.331 SLICE_X48Y439 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 1.336 SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[24] ------------------------------------------------------------------- required time -1.336 arrival time 1.499 ------------------------------------------------------------------- slack 0.163 Slack (MET) : 0.163ns (arrival time - required time) Source: SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.236ns (logic 0.048ns (20.339%) route 0.188ns (79.661%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.494ns Source Clock Delay (SCD): 1.263ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 1.147ns (routing 0.463ns, distribution 0.684ns) Clock Net Delay (Destination): 1.342ns (routing 0.528ns, distribution 0.814ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.147 1.263 SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X49Y440 FDPE r SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y440 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.311 f SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.188 1.499 SFP_GEN[39].ngCCM_gbt/sync_m_reg[3][0] SLICE_X48Y439 FDCE f SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.342 1.494 SFP_GEN[39].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y439 FDCE r SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[26]/C clock pessimism -0.163 1.331 SLICE_X48Y439 FDCE (Remov_CFF2_SLICEL_C_CLR) 0.005 1.336 SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[26] ------------------------------------------------------------------- required time -1.336 arrival time 1.499 ------------------------------------------------------------------- slack 0.163 Slack (MET) : 0.163ns (arrival time - required time) Source: SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.236ns (logic 0.048ns (20.339%) route 0.188ns (79.661%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.494ns Source Clock Delay (SCD): 1.263ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 1.147ns (routing 0.463ns, distribution 0.684ns) Clock Net Delay (Destination): 1.342ns (routing 0.528ns, distribution 0.814ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.147 1.263 SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X49Y440 FDPE r SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y440 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.311 f SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.188 1.499 SFP_GEN[39].ngCCM_gbt/sync_m_reg[3][0] SLICE_X48Y439 FDCE f SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.342 1.494 SFP_GEN[39].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y439 FDCE r SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[28]/C clock pessimism -0.163 1.331 SLICE_X48Y439 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 1.336 SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[28] ------------------------------------------------------------------- required time -1.336 arrival time 1.499 ------------------------------------------------------------------- slack 0.163 Slack (MET) : 0.163ns (arrival time - required time) Source: SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.236ns (logic 0.048ns (20.339%) route 0.188ns (79.661%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.494ns Source Clock Delay (SCD): 1.263ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 1.147ns (routing 0.463ns, distribution 0.684ns) Clock Net Delay (Destination): 1.342ns (routing 0.528ns, distribution 0.814ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.147 1.263 SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X49Y440 FDPE r SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y440 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.311 f SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.188 1.499 SFP_GEN[39].ngCCM_gbt/sync_m_reg[3][0] SLICE_X48Y439 FDCE f SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.342 1.494 SFP_GEN[39].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y439 FDCE r SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[30]/C clock pessimism -0.163 1.331 SLICE_X48Y439 FDCE (Remov_DFF2_SLICEL_C_CLR) 0.005 1.336 SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[30] ------------------------------------------------------------------- required time -1.336 arrival time 1.499 ------------------------------------------------------------------- slack 0.163 Slack (MET) : 0.166ns (arrival time - required time) Source: SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.048ns (21.429%) route 0.176ns (78.571%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.510ns Source Clock Delay (SCD): 1.263ns Clock Pessimism Removal (CPR): 0.194ns Clock Net Delay (Source): 1.147ns (routing 0.463ns, distribution 0.684ns) Clock Net Delay (Destination): 1.358ns (routing 0.528ns, distribution 0.830ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.147 1.263 SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X49Y440 FDPE r SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y440 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.311 f SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.176 1.487 SFP_GEN[39].ngCCM_gbt/sync_m_reg[3][0] SLICE_X50Y442 FDCE f SFP_GEN[39].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.358 1.510 SFP_GEN[39].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X50Y442 FDCE r SFP_GEN[39].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.194 1.316 SLICE_X50Y442 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.321 SFP_GEN[39].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.321 arrival time 1.487 ------------------------------------------------------------------- slack 0.166 Slack (MET) : 0.185ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[47]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.262ns (logic 0.049ns (18.702%) route 0.213ns (81.298%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.141ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 1.025ns (routing 0.463ns, distribution 0.562ns) Clock Net Delay (Destination): 1.207ns (routing 0.528ns, distribution 0.679ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.025 1.141 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK SLICE_X42Y446 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X42Y446 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.190 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.213 1.403 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X45Y445 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[47]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y168 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.207 1.359 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X45Y445 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[47]/C clock pessimism -0.146 1.213 SLICE_X45Y445 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.218 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[47] ------------------------------------------------------------------- required time -1.218 arrival time 1.403 ------------------------------------------------------------------- slack 0.185 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_42 To Clock: gtwiz_userclk_rx_srcclk_out[0]_42 Setup : 0 Failing Endpoints, Worst Slack 4.363ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.093ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.363ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 3.846ns (logic 0.306ns (7.956%) route 3.540ns (92.044%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.020ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.652ns = ( 10.969 - 8.317 ) Source Clock Delay (SCD): 2.840ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.415ns (routing 0.775ns, distribution 1.640ns) Clock Net Delay (Destination): 2.276ns (routing 0.697ns, distribution 1.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.415 2.840 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X11Y486 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y486 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.979 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.546 5.525 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X59Y464 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.167 5.692 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/O net (fo=15, routed) 0.994 6.686 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X61Y481 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.276 10.969 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X61Y481 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/C clock pessimism 0.208 11.177 clock uncertainty -0.035 11.142 SLICE_X61Y481 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.049 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6] ------------------------------------------------------------------- required time 11.049 arrival time -6.686 ------------------------------------------------------------------- slack 4.363 Slack (MET) : 4.369ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 3.839ns (logic 0.306ns (7.971%) route 3.533ns (92.029%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.019ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.651ns = ( 10.968 - 8.317 ) Source Clock Delay (SCD): 2.840ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.415ns (routing 0.775ns, distribution 1.640ns) Clock Net Delay (Destination): 2.275ns (routing 0.697ns, distribution 1.578ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.415 2.840 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X11Y486 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y486 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.979 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.546 5.525 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X59Y464 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.167 5.692 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/O net (fo=15, routed) 0.987 6.679 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X61Y481 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.275 10.968 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X61Y481 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/C clock pessimism 0.208 11.176 clock uncertainty -0.035 11.141 SLICE_X61Y481 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.048 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7] ------------------------------------------------------------------- required time 11.048 arrival time -6.679 ------------------------------------------------------------------- slack 4.369 Slack (MET) : 4.438ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 3.771ns (logic 0.306ns (8.115%) route 3.465ns (91.885%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.020ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.652ns = ( 10.969 - 8.317 ) Source Clock Delay (SCD): 2.840ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.415ns (routing 0.775ns, distribution 1.640ns) Clock Net Delay (Destination): 2.276ns (routing 0.697ns, distribution 1.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.415 2.840 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X11Y486 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y486 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.979 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.546 5.525 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X59Y464 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.167 5.692 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/O net (fo=15, routed) 0.919 6.611 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X61Y480 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.276 10.969 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X61Y480 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/C clock pessimism 0.208 11.177 clock uncertainty -0.035 11.142 SLICE_X61Y480 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.049 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0] ------------------------------------------------------------------- required time 11.049 arrival time -6.611 ------------------------------------------------------------------- slack 4.438 Slack (MET) : 4.438ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 3.771ns (logic 0.306ns (8.115%) route 3.465ns (91.885%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.020ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.652ns = ( 10.969 - 8.317 ) Source Clock Delay (SCD): 2.840ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.415ns (routing 0.775ns, distribution 1.640ns) Clock Net Delay (Destination): 2.276ns (routing 0.697ns, distribution 1.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.415 2.840 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X11Y486 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y486 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.979 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.546 5.525 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X59Y464 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.167 5.692 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/O net (fo=15, routed) 0.919 6.611 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X61Y480 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.276 10.969 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X61Y480 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C clock pessimism 0.208 11.177 clock uncertainty -0.035 11.142 SLICE_X61Y480 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 11.049 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2] ------------------------------------------------------------------- required time 11.049 arrival time -6.611 ------------------------------------------------------------------- slack 4.438 Slack (MET) : 4.444ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 3.764ns (logic 0.306ns (8.130%) route 3.458ns (91.870%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.019ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.651ns = ( 10.968 - 8.317 ) Source Clock Delay (SCD): 2.840ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.415ns (routing 0.775ns, distribution 1.640ns) Clock Net Delay (Destination): 2.275ns (routing 0.697ns, distribution 1.578ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.415 2.840 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X11Y486 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y486 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.979 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.546 5.525 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X59Y464 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.167 5.692 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/O net (fo=15, routed) 0.912 6.604 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X61Y480 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.275 10.968 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X61Y480 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/C clock pessimism 0.208 11.176 clock uncertainty -0.035 11.141 SLICE_X61Y480 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.048 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1] ------------------------------------------------------------------- required time 11.048 arrival time -6.604 ------------------------------------------------------------------- slack 4.444 Slack (MET) : 4.444ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 3.764ns (logic 0.306ns (8.130%) route 3.458ns (91.870%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.019ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.651ns = ( 10.968 - 8.317 ) Source Clock Delay (SCD): 2.840ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.415ns (routing 0.775ns, distribution 1.640ns) Clock Net Delay (Destination): 2.275ns (routing 0.697ns, distribution 1.578ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.415 2.840 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X11Y486 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y486 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.979 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.546 5.525 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X59Y464 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.167 5.692 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/O net (fo=15, routed) 0.912 6.604 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X61Y480 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.275 10.968 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X61Y480 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/C clock pessimism 0.208 11.176 clock uncertainty -0.035 11.141 SLICE_X61Y480 FDCE (Recov_GFF_SLICEM_C_CLR) -0.093 11.048 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3] ------------------------------------------------------------------- required time 11.048 arrival time -6.604 ------------------------------------------------------------------- slack 4.444 Slack (MET) : 4.444ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 3.764ns (logic 0.306ns (8.130%) route 3.458ns (91.870%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.019ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.651ns = ( 10.968 - 8.317 ) Source Clock Delay (SCD): 2.840ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.415ns (routing 0.775ns, distribution 1.640ns) Clock Net Delay (Destination): 2.275ns (routing 0.697ns, distribution 1.578ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.415 2.840 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X11Y486 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y486 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.979 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.546 5.525 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X59Y464 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.167 5.692 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/O net (fo=15, routed) 0.912 6.604 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X61Y480 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.275 10.968 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X61Y480 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C clock pessimism 0.208 11.176 clock uncertainty -0.035 11.141 SLICE_X61Y480 FDCE (Recov_FFF_SLICEM_C_CLR) -0.093 11.048 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4] ------------------------------------------------------------------- required time 11.048 arrival time -6.604 ------------------------------------------------------------------- slack 4.444 Slack (MET) : 4.444ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 3.764ns (logic 0.306ns (8.130%) route 3.458ns (91.870%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.019ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.651ns = ( 10.968 - 8.317 ) Source Clock Delay (SCD): 2.840ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.415ns (routing 0.775ns, distribution 1.640ns) Clock Net Delay (Destination): 2.275ns (routing 0.697ns, distribution 1.578ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.415 2.840 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X11Y486 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y486 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.979 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.546 5.525 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X59Y464 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.167 5.692 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/O net (fo=15, routed) 0.912 6.604 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X61Y480 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.275 10.968 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X61Y480 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/C clock pessimism 0.208 11.176 clock uncertainty -0.035 11.141 SLICE_X61Y480 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 11.048 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5] ------------------------------------------------------------------- required time 11.048 arrival time -6.604 ------------------------------------------------------------------- slack 4.444 Slack (MET) : 4.533ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 3.660ns (logic 0.306ns (8.361%) route 3.354ns (91.639%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.004ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.636ns = ( 10.953 - 8.317 ) Source Clock Delay (SCD): 2.840ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.415ns (routing 0.775ns, distribution 1.640ns) Clock Net Delay (Destination): 2.260ns (routing 0.697ns, distribution 1.563ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.415 2.840 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X11Y486 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y486 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.979 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.546 5.525 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X59Y464 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.167 5.692 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/O net (fo=15, routed) 0.808 6.500 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X60Y480 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.260 10.953 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X60Y480 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/C clock pessimism 0.208 11.161 clock uncertainty -0.035 11.126 SLICE_X60Y480 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.033 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4] ------------------------------------------------------------------- required time 11.033 arrival time -6.500 ------------------------------------------------------------------- slack 4.533 Slack (MET) : 4.533ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 3.660ns (logic 0.306ns (8.361%) route 3.354ns (91.639%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.004ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.636ns = ( 10.953 - 8.317 ) Source Clock Delay (SCD): 2.840ns Clock Pessimism Removal (CPR): 0.208ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.415ns (routing 0.775ns, distribution 1.640ns) Clock Net Delay (Destination): 2.260ns (routing 0.697ns, distribution 1.563ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.415 2.840 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X11Y486 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y486 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.979 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.546 5.525 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X59Y464 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.167 5.692 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/O net (fo=15, routed) 0.808 6.500 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X60Y480 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.260 10.953 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X60Y480 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/C clock pessimism 0.208 11.161 clock uncertainty -0.035 11.126 SLICE_X60Y480 FDCE (Recov_AFF2_SLICEL_C_CLR) -0.093 11.033 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0] ------------------------------------------------------------------- required time 11.033 arrival time -6.500 ------------------------------------------------------------------- slack 4.533 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.093ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.188ns (logic 0.049ns (26.064%) route 0.139ns (73.936%)) Logic Levels: 0 Clock Path Skew: 0.090ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.374ns Source Clock Delay (SCD): 1.127ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.011ns (routing 0.369ns, distribution 0.642ns) Clock Net Delay (Destination): 1.222ns (routing 0.431ns, distribution 0.791ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.011 1.127 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X54Y485 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X54Y485 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.176 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.139 1.315 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X55Y485 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.222 1.374 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X55Y485 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C clock pessimism -0.157 1.217 SLICE_X55Y485 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.222 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time -1.222 arrival time 1.315 ------------------------------------------------------------------- slack 0.093 Slack (MET) : 0.093ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.188ns (logic 0.049ns (26.064%) route 0.139ns (73.936%)) Logic Levels: 0 Clock Path Skew: 0.090ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.374ns Source Clock Delay (SCD): 1.127ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.011ns (routing 0.369ns, distribution 0.642ns) Clock Net Delay (Destination): 1.222ns (routing 0.431ns, distribution 0.791ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.011 1.127 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X54Y485 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X54Y485 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.176 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.139 1.315 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X55Y485 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.222 1.374 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X55Y485 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C clock pessimism -0.157 1.217 SLICE_X55Y485 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.222 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time -1.222 arrival time 1.315 ------------------------------------------------------------------- slack 0.093 Slack (MET) : 0.144ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.357ns Source Clock Delay (SCD): 1.125ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.009ns (routing 0.369ns, distribution 0.640ns) Clock Net Delay (Destination): 1.205ns (routing 0.431ns, distribution 0.774ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.009 1.125 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK SLICE_X58Y480 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X58Y480 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.174 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.175 1.349 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X60Y480 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.205 1.357 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X60Y480 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.157 1.200 SLICE_X60Y480 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.205 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -1.205 arrival time 1.349 ------------------------------------------------------------------- slack 0.144 Slack (MET) : 0.161ns (arrival time - required time) Source: SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[22]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.258ns (logic 0.048ns (18.605%) route 0.210ns (81.395%)) Logic Levels: 0 Clock Path Skew: 0.092ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.366ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.001ns (routing 0.369ns, distribution 0.632ns) Clock Net Delay (Destination): 1.214ns (routing 0.431ns, distribution 0.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.001 1.117 SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y484 FDPE r SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y484 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.165 f SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.210 1.375 SFP_GEN[40].ngCCM_gbt/sync_m_reg[3][0] SLICE_X61Y486 FDCE f SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[22]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.214 1.366 SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X61Y486 FDCE r SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[22]/C clock pessimism -0.157 1.209 SLICE_X61Y486 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.214 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[22] ------------------------------------------------------------------- required time -1.214 arrival time 1.375 ------------------------------------------------------------------- slack 0.161 Slack (MET) : 0.161ns (arrival time - required time) Source: SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[80]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.258ns (logic 0.048ns (18.605%) route 0.210ns (81.395%)) Logic Levels: 0 Clock Path Skew: 0.092ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.366ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.001ns (routing 0.369ns, distribution 0.632ns) Clock Net Delay (Destination): 1.214ns (routing 0.431ns, distribution 0.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.001 1.117 SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y484 FDPE r SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y484 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.165 f SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.210 1.375 SFP_GEN[40].ngCCM_gbt/sync_m_reg[3][0] SLICE_X61Y486 FDCE f SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[80]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.214 1.366 SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X61Y486 FDCE r SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[80]/C clock pessimism -0.157 1.209 SLICE_X61Y486 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.214 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[80] ------------------------------------------------------------------- required time -1.214 arrival time 1.375 ------------------------------------------------------------------- slack 0.161 Slack (MET) : 0.161ns (arrival time - required time) Source: SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.258ns (logic 0.048ns (18.605%) route 0.210ns (81.395%)) Logic Levels: 0 Clock Path Skew: 0.092ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.366ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.001ns (routing 0.369ns, distribution 0.632ns) Clock Net Delay (Destination): 1.214ns (routing 0.431ns, distribution 0.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.001 1.117 SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y484 FDPE r SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y484 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.165 f SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.210 1.375 SFP_GEN[40].ngCCM_gbt/sync_m_reg[3][0] SLICE_X61Y486 FDCE f SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.214 1.366 SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X61Y486 FDCE r SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[83]/C clock pessimism -0.157 1.209 SLICE_X61Y486 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.214 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[83] ------------------------------------------------------------------- required time -1.214 arrival time 1.375 ------------------------------------------------------------------- slack 0.161 Slack (MET) : 0.192ns (arrival time - required time) Source: SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[72]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.257ns (logic 0.048ns (18.677%) route 0.209ns (81.323%)) Logic Levels: 0 Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.365ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.188ns Clock Net Delay (Source): 1.001ns (routing 0.369ns, distribution 0.632ns) Clock Net Delay (Destination): 1.213ns (routing 0.431ns, distribution 0.782ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.001 1.117 SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y484 FDPE r SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y484 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.165 f SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.209 1.374 SFP_GEN[40].ngCCM_gbt/sync_m_reg[3][0] SLICE_X59Y482 FDCE f SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[72]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.213 1.365 SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y482 FDCE r SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[72]/C clock pessimism -0.188 1.177 SLICE_X59Y482 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.182 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[72] ------------------------------------------------------------------- required time -1.182 arrival time 1.374 ------------------------------------------------------------------- slack 0.192 Slack (MET) : 0.192ns (arrival time - required time) Source: SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[74]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.257ns (logic 0.048ns (18.677%) route 0.209ns (81.323%)) Logic Levels: 0 Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.365ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.188ns Clock Net Delay (Source): 1.001ns (routing 0.369ns, distribution 0.632ns) Clock Net Delay (Destination): 1.213ns (routing 0.431ns, distribution 0.782ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.001 1.117 SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y484 FDPE r SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y484 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.165 f SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.209 1.374 SFP_GEN[40].ngCCM_gbt/sync_m_reg[3][0] SLICE_X59Y482 FDCE f SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[74]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.213 1.365 SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y482 FDCE r SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[74]/C clock pessimism -0.188 1.177 SLICE_X59Y482 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.182 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[74] ------------------------------------------------------------------- required time -1.182 arrival time 1.374 ------------------------------------------------------------------- slack 0.192 Slack (MET) : 0.192ns (arrival time - required time) Source: SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[76]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.257ns (logic 0.048ns (18.677%) route 0.209ns (81.323%)) Logic Levels: 0 Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.365ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.188ns Clock Net Delay (Source): 1.001ns (routing 0.369ns, distribution 0.632ns) Clock Net Delay (Destination): 1.213ns (routing 0.431ns, distribution 0.782ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.001 1.117 SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y484 FDPE r SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y484 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.165 f SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.209 1.374 SFP_GEN[40].ngCCM_gbt/sync_m_reg[3][0] SLICE_X59Y482 FDCE f SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[76]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.213 1.365 SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y482 FDCE r SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[76]/C clock pessimism -0.188 1.177 SLICE_X59Y482 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.182 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[76] ------------------------------------------------------------------- required time -1.182 arrival time 1.374 ------------------------------------------------------------------- slack 0.192 Slack (MET) : 0.192ns (arrival time - required time) Source: SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[78]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.257ns (logic 0.048ns (18.677%) route 0.209ns (81.323%)) Logic Levels: 0 Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.365ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.188ns Clock Net Delay (Source): 1.001ns (routing 0.369ns, distribution 0.632ns) Clock Net Delay (Destination): 1.213ns (routing 0.431ns, distribution 0.782ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.001 1.117 SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y484 FDPE r SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y484 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.165 f SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.209 1.374 SFP_GEN[40].ngCCM_gbt/sync_m_reg[3][0] SLICE_X59Y482 FDCE f SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[78]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y209 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.213 1.365 SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y482 FDCE r SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[78]/C clock pessimism -0.188 1.177 SLICE_X59Y482 FDCE (Remov_GFF2_SLICEM_C_CLR) 0.005 1.182 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[78] ------------------------------------------------------------------- required time -1.182 arrival time 1.374 ------------------------------------------------------------------- slack 0.192 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_43 To Clock: gtwiz_userclk_rx_srcclk_out[0]_43 Setup : 0 Failing Endpoints, Worst Slack 2.867ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.222ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.867ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 5.017ns (logic 0.288ns (5.740%) route 4.729ns (94.260%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.305ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.342ns = ( 10.659 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.966ns (routing 0.693ns, distribution 1.273ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y503 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y503 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.940 5.928 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X42Y416 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.077 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/O net (fo=15, routed) 1.789 7.866 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X40Y497 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.966 10.659 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X40Y497 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/C clock pessimism 0.202 10.861 clock uncertainty -0.035 10.826 SLICE_X40Y497 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.733 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3] ------------------------------------------------------------------- required time 10.733 arrival time -7.866 ------------------------------------------------------------------- slack 2.867 Slack (MET) : 2.867ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 5.017ns (logic 0.288ns (5.740%) route 4.729ns (94.260%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.305ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.342ns = ( 10.659 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.966ns (routing 0.693ns, distribution 1.273ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y503 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y503 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.940 5.928 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X42Y416 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.077 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/O net (fo=15, routed) 1.789 7.866 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X40Y497 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.966 10.659 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X40Y497 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/C clock pessimism 0.202 10.861 clock uncertainty -0.035 10.826 SLICE_X40Y497 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.733 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6] ------------------------------------------------------------------- required time 10.733 arrival time -7.866 ------------------------------------------------------------------- slack 2.867 Slack (MET) : 2.867ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 5.017ns (logic 0.288ns (5.740%) route 4.729ns (94.260%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.305ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.342ns = ( 10.659 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.966ns (routing 0.693ns, distribution 1.273ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y503 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y503 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.940 5.928 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X42Y416 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.077 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/O net (fo=15, routed) 1.789 7.866 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X40Y497 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.966 10.659 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X40Y497 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/C clock pessimism 0.202 10.861 clock uncertainty -0.035 10.826 SLICE_X40Y497 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.733 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7] ------------------------------------------------------------------- required time 10.733 arrival time -7.866 ------------------------------------------------------------------- slack 2.867 Slack (MET) : 2.875ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 5.007ns (logic 0.288ns (5.752%) route 4.719ns (94.248%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.307ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.340ns = ( 10.657 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.964ns (routing 0.693ns, distribution 1.271ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y503 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y503 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.940 5.928 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X42Y416 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.077 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/O net (fo=15, routed) 1.779 7.856 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X40Y497 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.964 10.657 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X40Y497 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/C clock pessimism 0.202 10.859 clock uncertainty -0.035 10.824 SLICE_X40Y497 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 10.731 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0] ------------------------------------------------------------------- required time 10.731 arrival time -7.856 ------------------------------------------------------------------- slack 2.875 Slack (MET) : 2.875ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 5.007ns (logic 0.288ns (5.752%) route 4.719ns (94.248%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.307ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.340ns = ( 10.657 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.964ns (routing 0.693ns, distribution 1.271ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y503 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y503 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.940 5.928 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X42Y416 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.077 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/O net (fo=15, routed) 1.779 7.856 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X40Y497 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.964 10.657 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X40Y497 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/C clock pessimism 0.202 10.859 clock uncertainty -0.035 10.824 SLICE_X40Y497 FDCE (Recov_GFF2_SLICEL_C_CLR) -0.093 10.731 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2] ------------------------------------------------------------------- required time 10.731 arrival time -7.856 ------------------------------------------------------------------- slack 2.875 Slack (MET) : 2.906ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 4.956ns (logic 0.288ns (5.811%) route 4.668ns (94.189%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.327ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.320ns = ( 10.637 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.944ns (routing 0.693ns, distribution 1.251ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y503 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y503 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.940 5.928 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X42Y416 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.077 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/O net (fo=15, routed) 1.728 7.805 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X41Y499 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.944 10.637 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X41Y499 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/C clock pessimism 0.202 10.839 clock uncertainty -0.035 10.804 SLICE_X41Y499 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.711 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1] ------------------------------------------------------------------- required time 10.711 arrival time -7.805 ------------------------------------------------------------------- slack 2.906 Slack (MET) : 2.906ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 4.956ns (logic 0.288ns (5.811%) route 4.668ns (94.189%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.327ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.320ns = ( 10.637 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.944ns (routing 0.693ns, distribution 1.251ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y503 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y503 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.940 5.928 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X42Y416 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.077 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/O net (fo=15, routed) 1.728 7.805 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X41Y499 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.944 10.637 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X41Y499 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/C clock pessimism 0.202 10.839 clock uncertainty -0.035 10.804 SLICE_X41Y499 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 10.711 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2] ------------------------------------------------------------------- required time 10.711 arrival time -7.805 ------------------------------------------------------------------- slack 2.906 Slack (MET) : 2.906ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 4.956ns (logic 0.288ns (5.811%) route 4.668ns (94.189%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.327ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.320ns = ( 10.637 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.944ns (routing 0.693ns, distribution 1.251ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y503 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y503 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.940 5.928 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X42Y416 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.077 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/O net (fo=15, routed) 1.728 7.805 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X41Y499 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.944 10.637 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X41Y499 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/C clock pessimism 0.202 10.839 clock uncertainty -0.035 10.804 SLICE_X41Y499 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 10.711 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3] ------------------------------------------------------------------- required time 10.711 arrival time -7.805 ------------------------------------------------------------------- slack 2.906 Slack (MET) : 2.906ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 4.956ns (logic 0.288ns (5.811%) route 4.668ns (94.189%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.327ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.320ns = ( 10.637 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.944ns (routing 0.693ns, distribution 1.251ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y503 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y503 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.940 5.928 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X42Y416 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.077 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/O net (fo=15, routed) 1.728 7.805 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X41Y499 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.944 10.637 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X41Y499 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/C clock pessimism 0.202 10.839 clock uncertainty -0.035 10.804 SLICE_X41Y499 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.711 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4] ------------------------------------------------------------------- required time 10.711 arrival time -7.805 ------------------------------------------------------------------- slack 2.906 Slack (MET) : 3.000ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 4.864ns (logic 0.288ns (5.921%) route 4.576ns (94.079%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.325ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.322ns = ( 10.639 - 8.317 ) Source Clock Delay (SCD): 2.849ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.424ns (routing 0.772ns, distribution 1.652ns) Clock Net Delay (Destination): 1.946ns (routing 0.693ns, distribution 1.253ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.424 2.849 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y503 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y503 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.988 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.940 5.928 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X42Y416 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.077 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/O net (fo=15, routed) 1.636 7.713 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X40Y499 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.946 10.639 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X40Y499 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/C clock pessimism 0.202 10.841 clock uncertainty -0.035 10.806 SLICE_X40Y499 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 10.713 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0] ------------------------------------------------------------------- required time 10.713 arrival time -7.713 ------------------------------------------------------------------- slack 3.000 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.222ns (arrival time - required time) Source: SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.262ns (logic 0.048ns (18.321%) route 0.214ns (81.679%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.197ns Source Clock Delay (SCD): 0.990ns Clock Pessimism Removal (CPR): 0.172ns Clock Net Delay (Source): 0.874ns (routing 0.368ns, distribution 0.506ns) Clock Net Delay (Destination): 1.045ns (routing 0.432ns, distribution 0.613ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.874 0.990 SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y499 FDPE r SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y499 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.038 f SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.214 1.252 SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] SLICE_X42Y498 FDCE f SFP_GEN[41].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.045 1.197 SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y498 FDCE r SFP_GEN[41].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.172 1.025 SLICE_X42Y498 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.030 SFP_GEN[41].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.030 arrival time 1.252 ------------------------------------------------------------------- slack 0.222 Slack (MET) : 0.223ns (arrival time - required time) Source: SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.312ns (logic 0.048ns (15.385%) route 0.264ns (84.615%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.218ns Source Clock Delay (SCD): 0.990ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.874ns (routing 0.368ns, distribution 0.506ns) Clock Net Delay (Destination): 1.066ns (routing 0.432ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.874 0.990 SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y499 FDPE r SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y499 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.038 f SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.264 1.302 SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] SLICE_X39Y497 FDCE f SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.066 1.218 SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y497 FDCE r SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[16]/C clock pessimism -0.144 1.074 SLICE_X39Y497 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.079 SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[16] ------------------------------------------------------------------- required time -1.079 arrival time 1.302 ------------------------------------------------------------------- slack 0.223 Slack (MET) : 0.223ns (arrival time - required time) Source: SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.312ns (logic 0.048ns (15.385%) route 0.264ns (84.615%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.218ns Source Clock Delay (SCD): 0.990ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.874ns (routing 0.368ns, distribution 0.506ns) Clock Net Delay (Destination): 1.066ns (routing 0.432ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.874 0.990 SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y499 FDPE r SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y499 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.038 f SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.264 1.302 SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] SLICE_X39Y497 FDCE f SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.066 1.218 SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y497 FDCE r SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[17]/C clock pessimism -0.144 1.074 SLICE_X39Y497 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 1.079 SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[17] ------------------------------------------------------------------- required time -1.079 arrival time 1.302 ------------------------------------------------------------------- slack 0.223 Slack (MET) : 0.223ns (arrival time - required time) Source: SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.312ns (logic 0.048ns (15.385%) route 0.264ns (84.615%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.218ns Source Clock Delay (SCD): 0.990ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.874ns (routing 0.368ns, distribution 0.506ns) Clock Net Delay (Destination): 1.066ns (routing 0.432ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.874 0.990 SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y499 FDPE r SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y499 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.038 f SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.264 1.302 SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] SLICE_X39Y497 FDCE f SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.066 1.218 SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y497 FDCE r SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[19]/C clock pessimism -0.144 1.074 SLICE_X39Y497 FDCE (Remov_BFF_SLICEM_C_CLR) 0.005 1.079 SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[19] ------------------------------------------------------------------- required time -1.079 arrival time 1.302 ------------------------------------------------------------------- slack 0.223 Slack (MET) : 0.223ns (arrival time - required time) Source: SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.312ns (logic 0.048ns (15.385%) route 0.264ns (84.615%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.218ns Source Clock Delay (SCD): 0.990ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.874ns (routing 0.368ns, distribution 0.506ns) Clock Net Delay (Destination): 1.066ns (routing 0.432ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.874 0.990 SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y499 FDPE r SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y499 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.038 f SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.264 1.302 SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] SLICE_X39Y497 FDCE f SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.066 1.218 SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y497 FDCE r SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[21]/C clock pessimism -0.144 1.074 SLICE_X39Y497 FDCE (Remov_BFF2_SLICEM_C_CLR) 0.005 1.079 SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[21] ------------------------------------------------------------------- required time -1.079 arrival time 1.302 ------------------------------------------------------------------- slack 0.223 Slack (MET) : 0.223ns (arrival time - required time) Source: SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[22]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.312ns (logic 0.048ns (15.385%) route 0.264ns (84.615%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.218ns Source Clock Delay (SCD): 0.990ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.874ns (routing 0.368ns, distribution 0.506ns) Clock Net Delay (Destination): 1.066ns (routing 0.432ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.874 0.990 SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y499 FDPE r SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y499 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.038 f SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.264 1.302 SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] SLICE_X39Y497 FDCE f SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[22]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.066 1.218 SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y497 FDCE r SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[22]/C clock pessimism -0.144 1.074 SLICE_X39Y497 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 1.079 SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[22] ------------------------------------------------------------------- required time -1.079 arrival time 1.302 ------------------------------------------------------------------- slack 0.223 Slack (MET) : 0.223ns (arrival time - required time) Source: SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.312ns (logic 0.048ns (15.385%) route 0.264ns (84.615%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.218ns Source Clock Delay (SCD): 0.990ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.874ns (routing 0.368ns, distribution 0.506ns) Clock Net Delay (Destination): 1.066ns (routing 0.432ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.874 0.990 SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y499 FDPE r SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y499 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.038 f SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.264 1.302 SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] SLICE_X39Y497 FDCE f SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.066 1.218 SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y497 FDCE r SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[23]/C clock pessimism -0.144 1.074 SLICE_X39Y497 FDCE (Remov_CFF2_SLICEM_C_CLR) 0.005 1.079 SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[23] ------------------------------------------------------------------- required time -1.079 arrival time 1.302 ------------------------------------------------------------------- slack 0.223 Slack (MET) : 0.223ns (arrival time - required time) Source: SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.312ns (logic 0.048ns (15.385%) route 0.264ns (84.615%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.218ns Source Clock Delay (SCD): 0.990ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.874ns (routing 0.368ns, distribution 0.506ns) Clock Net Delay (Destination): 1.066ns (routing 0.432ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.874 0.990 SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y499 FDPE r SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y499 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.038 f SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.264 1.302 SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] SLICE_X39Y497 FDCE f SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.066 1.218 SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y497 FDCE r SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[27]/C clock pessimism -0.144 1.074 SLICE_X39Y497 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.079 SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[27] ------------------------------------------------------------------- required time -1.079 arrival time 1.302 ------------------------------------------------------------------- slack 0.223 Slack (MET) : 0.223ns (arrival time - required time) Source: SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[31]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.312ns (logic 0.048ns (15.385%) route 0.264ns (84.615%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.218ns Source Clock Delay (SCD): 0.990ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.874ns (routing 0.368ns, distribution 0.506ns) Clock Net Delay (Destination): 1.066ns (routing 0.432ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.874 0.990 SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y499 FDPE r SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y499 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.038 f SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.264 1.302 SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] SLICE_X39Y497 FDCE f SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[31]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.066 1.218 SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y497 FDCE r SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[31]/C clock pessimism -0.144 1.074 SLICE_X39Y497 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 1.079 SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[31] ------------------------------------------------------------------- required time -1.079 arrival time 1.302 ------------------------------------------------------------------- slack 0.223 Slack (MET) : 0.226ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.268ns (logic 0.048ns (17.910%) route 0.220ns (82.090%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.201ns Source Clock Delay (SCD): 0.990ns Clock Pessimism Removal (CPR): 0.174ns Clock Net Delay (Source): 0.874ns (routing 0.368ns, distribution 0.506ns) Clock Net Delay (Destination): 1.049ns (routing 0.432ns, distribution 0.617ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.874 0.990 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X35Y501 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X35Y501 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.038 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.220 1.258 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X36Y500 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y208 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.049 1.201 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X36Y500 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism -0.174 1.027 SLICE_X36Y500 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.032 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time -1.032 arrival time 1.258 ------------------------------------------------------------------- slack 0.226 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_44 To Clock: gtwiz_userclk_rx_srcclk_out[0]_44 Setup : 0 Failing Endpoints, Worst Slack 2.878ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.096ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.878ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.317ns (logic 0.374ns (7.034%) route 4.943ns (92.966%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.006ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.664ns = ( 10.981 - 8.317 ) Source Clock Delay (SCD): 2.870ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.445ns (routing 0.794ns, distribution 1.651ns) Clock Net Delay (Destination): 2.288ns (routing 0.710ns, distribution 1.578ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.445 2.870 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y508 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y508 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.009 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.551 6.560 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X60Y454 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 6.795 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/O net (fo=15, routed) 1.392 8.187 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X61Y501 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.288 10.981 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X61Y501 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/C clock pessimism 0.212 11.193 clock uncertainty -0.035 11.158 SLICE_X61Y501 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 11.065 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2] ------------------------------------------------------------------- required time 11.065 arrival time -8.187 ------------------------------------------------------------------- slack 2.878 Slack (MET) : 2.878ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.317ns (logic 0.374ns (7.034%) route 4.943ns (92.966%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.006ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.664ns = ( 10.981 - 8.317 ) Source Clock Delay (SCD): 2.870ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.445ns (routing 0.794ns, distribution 1.651ns) Clock Net Delay (Destination): 2.288ns (routing 0.710ns, distribution 1.578ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.445 2.870 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y508 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y508 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.009 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.551 6.560 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X60Y454 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 6.795 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/O net (fo=15, routed) 1.392 8.187 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X61Y501 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.288 10.981 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X61Y501 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/C clock pessimism 0.212 11.193 clock uncertainty -0.035 11.158 SLICE_X61Y501 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.065 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5] ------------------------------------------------------------------- required time 11.065 arrival time -8.187 ------------------------------------------------------------------- slack 2.878 Slack (MET) : 2.878ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.317ns (logic 0.374ns (7.034%) route 4.943ns (92.966%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.006ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.664ns = ( 10.981 - 8.317 ) Source Clock Delay (SCD): 2.870ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.445ns (routing 0.794ns, distribution 1.651ns) Clock Net Delay (Destination): 2.288ns (routing 0.710ns, distribution 1.578ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.445 2.870 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y508 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y508 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.009 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.551 6.560 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X60Y454 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 6.795 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/O net (fo=15, routed) 1.392 8.187 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X61Y501 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.288 10.981 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X61Y501 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/C clock pessimism 0.212 11.193 clock uncertainty -0.035 11.158 SLICE_X61Y501 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 11.065 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6] ------------------------------------------------------------------- required time 11.065 arrival time -8.187 ------------------------------------------------------------------- slack 2.878 Slack (MET) : 2.878ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.317ns (logic 0.374ns (7.034%) route 4.943ns (92.966%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.006ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.664ns = ( 10.981 - 8.317 ) Source Clock Delay (SCD): 2.870ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.445ns (routing 0.794ns, distribution 1.651ns) Clock Net Delay (Destination): 2.288ns (routing 0.710ns, distribution 1.578ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.445 2.870 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y508 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y508 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.009 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.551 6.560 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X60Y454 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 6.795 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/O net (fo=15, routed) 1.392 8.187 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X61Y501 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.288 10.981 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X61Y501 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/C clock pessimism 0.212 11.193 clock uncertainty -0.035 11.158 SLICE_X61Y501 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.065 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7] ------------------------------------------------------------------- required time 11.065 arrival time -8.187 ------------------------------------------------------------------- slack 2.878 Slack (MET) : 3.032ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.160ns (logic 0.374ns (7.248%) route 4.786ns (92.752%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.003ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.661ns = ( 10.978 - 8.317 ) Source Clock Delay (SCD): 2.870ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.445ns (routing 0.794ns, distribution 1.651ns) Clock Net Delay (Destination): 2.285ns (routing 0.710ns, distribution 1.575ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.445 2.870 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y508 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y508 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.009 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.551 6.560 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X60Y454 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 6.795 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/O net (fo=15, routed) 1.235 8.030 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X61Y503 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.285 10.978 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X61Y503 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/C clock pessimism 0.212 11.190 clock uncertainty -0.035 11.155 SLICE_X61Y503 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.062 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1] ------------------------------------------------------------------- required time 11.062 arrival time -8.030 ------------------------------------------------------------------- slack 3.032 Slack (MET) : 3.032ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.160ns (logic 0.374ns (7.248%) route 4.786ns (92.752%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.003ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.661ns = ( 10.978 - 8.317 ) Source Clock Delay (SCD): 2.870ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.445ns (routing 0.794ns, distribution 1.651ns) Clock Net Delay (Destination): 2.285ns (routing 0.710ns, distribution 1.575ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.445 2.870 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y508 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y508 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.009 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.551 6.560 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X60Y454 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 6.795 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/O net (fo=15, routed) 1.235 8.030 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X61Y503 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.285 10.978 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X61Y503 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/C clock pessimism 0.212 11.190 clock uncertainty -0.035 11.155 SLICE_X61Y503 FDCE (Recov_HFF2_SLICEM_C_CLR) -0.093 11.062 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2] ------------------------------------------------------------------- required time 11.062 arrival time -8.030 ------------------------------------------------------------------- slack 3.032 Slack (MET) : 3.032ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.160ns (logic 0.374ns (7.248%) route 4.786ns (92.752%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.003ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.661ns = ( 10.978 - 8.317 ) Source Clock Delay (SCD): 2.870ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.445ns (routing 0.794ns, distribution 1.651ns) Clock Net Delay (Destination): 2.285ns (routing 0.710ns, distribution 1.575ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.445 2.870 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y508 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y508 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.009 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.551 6.560 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X60Y454 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 6.795 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/O net (fo=15, routed) 1.235 8.030 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X61Y503 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.285 10.978 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X61Y503 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C clock pessimism 0.212 11.190 clock uncertainty -0.035 11.155 SLICE_X61Y503 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 11.062 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3] ------------------------------------------------------------------- required time 11.062 arrival time -8.030 ------------------------------------------------------------------- slack 3.032 Slack (MET) : 3.032ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.160ns (logic 0.374ns (7.248%) route 4.786ns (92.752%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.003ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.661ns = ( 10.978 - 8.317 ) Source Clock Delay (SCD): 2.870ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.445ns (routing 0.794ns, distribution 1.651ns) Clock Net Delay (Destination): 2.285ns (routing 0.710ns, distribution 1.575ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.445 2.870 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y508 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y508 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.009 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.551 6.560 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X60Y454 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 6.795 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/O net (fo=15, routed) 1.235 8.030 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X61Y503 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.285 10.978 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X61Y503 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/C clock pessimism 0.212 11.190 clock uncertainty -0.035 11.155 SLICE_X61Y503 FDCE (Recov_GFF_SLICEM_C_CLR) -0.093 11.062 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4] ------------------------------------------------------------------- required time 11.062 arrival time -8.030 ------------------------------------------------------------------- slack 3.032 Slack (MET) : 3.032ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.160ns (logic 0.374ns (7.248%) route 4.786ns (92.752%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.003ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.661ns = ( 10.978 - 8.317 ) Source Clock Delay (SCD): 2.870ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.445ns (routing 0.794ns, distribution 1.651ns) Clock Net Delay (Destination): 2.285ns (routing 0.710ns, distribution 1.575ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.445 2.870 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y508 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y508 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.009 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.551 6.560 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X60Y454 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 6.795 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/O net (fo=15, routed) 1.235 8.030 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X61Y503 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.285 10.978 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X61Y503 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5]/C clock pessimism 0.212 11.190 clock uncertainty -0.035 11.155 SLICE_X61Y503 FDCE (Recov_EFF2_SLICEM_C_CLR) -0.093 11.062 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5] ------------------------------------------------------------------- required time 11.062 arrival time -8.030 ------------------------------------------------------------------- slack 3.032 Slack (MET) : 3.039ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.127ns (logic 0.374ns (7.295%) route 4.753ns (92.705%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.023ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.635ns = ( 10.952 - 8.317 ) Source Clock Delay (SCD): 2.870ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.445ns (routing 0.794ns, distribution 1.651ns) Clock Net Delay (Destination): 2.259ns (routing 0.710ns, distribution 1.549ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.445 2.870 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y508 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y508 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.009 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.551 6.560 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X60Y454 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 6.795 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/O net (fo=15, routed) 1.202 7.997 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X60Y503 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.259 10.952 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X60Y503 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/C clock pessimism 0.212 11.164 clock uncertainty -0.035 11.129 SLICE_X60Y503 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.036 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0] ------------------------------------------------------------------- required time 11.036 arrival time -7.997 ------------------------------------------------------------------- slack 3.039 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.096ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.193ns (logic 0.049ns (25.389%) route 0.144ns (74.611%)) Logic Levels: 0 Clock Path Skew: 0.092ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.367ns Source Clock Delay (SCD): 1.115ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.999ns (routing 0.377ns, distribution 0.622ns) Clock Net Delay (Destination): 1.215ns (routing 0.443ns, distribution 0.772ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.115 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK SLICE_X60Y504 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y504 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.164 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.144 1.308 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X61Y504 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.215 1.367 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X61Y504 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.160 1.207 SLICE_X61Y504 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 1.212 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -1.212 arrival time 1.308 ------------------------------------------------------------------- slack 0.096 Slack (MET) : 0.196ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.298ns (logic 0.049ns (16.443%) route 0.249ns (83.557%)) Logic Levels: 0 Clock Path Skew: 0.097ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.367ns Source Clock Delay (SCD): 1.110ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.994ns (routing 0.377ns, distribution 0.617ns) Clock Net Delay (Destination): 1.215ns (routing 0.443ns, distribution 0.772ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.994 1.110 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y510 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X58Y510 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.159 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.249 1.408 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X61Y509 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.215 1.367 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X61Y509 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism -0.160 1.207 SLICE_X61Y509 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.212 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time -1.212 arrival time 1.408 ------------------------------------------------------------------- slack 0.196 Slack (MET) : 0.196ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.298ns (logic 0.049ns (16.443%) route 0.249ns (83.557%)) Logic Levels: 0 Clock Path Skew: 0.097ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.367ns Source Clock Delay (SCD): 1.110ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.994ns (routing 0.377ns, distribution 0.617ns) Clock Net Delay (Destination): 1.215ns (routing 0.443ns, distribution 0.772ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.994 1.110 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y510 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X58Y510 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.159 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.249 1.408 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X61Y509 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.215 1.367 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X61Y509 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C clock pessimism -0.160 1.207 SLICE_X61Y509 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 1.212 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3] ------------------------------------------------------------------- required time -1.212 arrival time 1.408 ------------------------------------------------------------------- slack 0.196 Slack (MET) : 0.196ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.298ns (logic 0.049ns (16.443%) route 0.249ns (83.557%)) Logic Levels: 0 Clock Path Skew: 0.097ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.367ns Source Clock Delay (SCD): 1.110ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.994ns (routing 0.377ns, distribution 0.617ns) Clock Net Delay (Destination): 1.215ns (routing 0.443ns, distribution 0.772ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.994 1.110 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y510 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X58Y510 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.159 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.249 1.408 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X61Y509 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.215 1.367 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X61Y509 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C clock pessimism -0.160 1.207 SLICE_X61Y509 FDCE (Remov_BFF_SLICEM_C_CLR) 0.005 1.212 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7] ------------------------------------------------------------------- required time -1.212 arrival time 1.408 ------------------------------------------------------------------- slack 0.196 Slack (MET) : 0.196ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.298ns (logic 0.049ns (16.443%) route 0.249ns (83.557%)) Logic Levels: 0 Clock Path Skew: 0.097ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.367ns Source Clock Delay (SCD): 1.110ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.994ns (routing 0.377ns, distribution 0.617ns) Clock Net Delay (Destination): 1.215ns (routing 0.443ns, distribution 0.772ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.994 1.110 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y510 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X58Y510 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.159 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.249 1.408 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X61Y509 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.215 1.367 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X61Y509 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C clock pessimism -0.160 1.207 SLICE_X61Y509 FDCE (Remov_BFF2_SLICEM_C_CLR) 0.005 1.212 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10] ------------------------------------------------------------------- required time -1.212 arrival time 1.408 ------------------------------------------------------------------- slack 0.196 Slack (MET) : 0.196ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.298ns (logic 0.049ns (16.443%) route 0.249ns (83.557%)) Logic Levels: 0 Clock Path Skew: 0.097ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.367ns Source Clock Delay (SCD): 1.110ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.994ns (routing 0.377ns, distribution 0.617ns) Clock Net Delay (Destination): 1.215ns (routing 0.443ns, distribution 0.772ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.994 1.110 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y510 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X58Y510 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.159 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.249 1.408 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X61Y509 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.215 1.367 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X61Y509 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C clock pessimism -0.160 1.207 SLICE_X61Y509 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 1.212 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12] ------------------------------------------------------------------- required time -1.212 arrival time 1.408 ------------------------------------------------------------------- slack 0.196 Slack (MET) : 0.196ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.298ns (logic 0.049ns (16.443%) route 0.249ns (83.557%)) Logic Levels: 0 Clock Path Skew: 0.097ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.367ns Source Clock Delay (SCD): 1.110ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.994ns (routing 0.377ns, distribution 0.617ns) Clock Net Delay (Destination): 1.215ns (routing 0.443ns, distribution 0.772ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.994 1.110 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y510 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X58Y510 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.159 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.249 1.408 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X61Y509 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.215 1.367 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X61Y509 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism -0.160 1.207 SLICE_X61Y509 FDCE (Remov_CFF2_SLICEM_C_CLR) 0.005 1.212 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time -1.212 arrival time 1.408 ------------------------------------------------------------------- slack 0.196 Slack (MET) : 0.196ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.298ns (logic 0.049ns (16.443%) route 0.249ns (83.557%)) Logic Levels: 0 Clock Path Skew: 0.097ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.367ns Source Clock Delay (SCD): 1.110ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.994ns (routing 0.377ns, distribution 0.617ns) Clock Net Delay (Destination): 1.215ns (routing 0.443ns, distribution 0.772ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.994 1.110 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y510 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X58Y510 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.159 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.249 1.408 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X61Y509 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.215 1.367 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X61Y509 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C clock pessimism -0.160 1.207 SLICE_X61Y509 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.212 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20] ------------------------------------------------------------------- required time -1.212 arrival time 1.408 ------------------------------------------------------------------- slack 0.196 Slack (MET) : 0.196ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.298ns (logic 0.049ns (16.443%) route 0.249ns (83.557%)) Logic Levels: 0 Clock Path Skew: 0.097ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.367ns Source Clock Delay (SCD): 1.110ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.994ns (routing 0.377ns, distribution 0.617ns) Clock Net Delay (Destination): 1.215ns (routing 0.443ns, distribution 0.772ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.994 1.110 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y510 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X58Y510 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.159 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.249 1.408 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X61Y509 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.215 1.367 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X61Y509 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C clock pessimism -0.160 1.207 SLICE_X61Y509 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 1.212 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8] ------------------------------------------------------------------- required time -1.212 arrival time 1.408 ------------------------------------------------------------------- slack 0.196 Slack (MET) : 0.213ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.299ns (logic 0.049ns (16.388%) route 0.250ns (83.612%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.351ns Source Clock Delay (SCD): 1.110ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.994ns (routing 0.377ns, distribution 0.617ns) Clock Net Delay (Destination): 1.199ns (routing 0.443ns, distribution 0.756ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.994 1.110 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y510 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X58Y510 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.159 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.250 1.409 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X60Y509 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y211 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.199 1.351 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X60Y509 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C clock pessimism -0.160 1.191 SLICE_X60Y509 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.196 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time -1.196 arrival time 1.409 ------------------------------------------------------------------- slack 0.213 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_45 To Clock: gtwiz_userclk_rx_srcclk_out[0]_45 Setup : 0 Failing Endpoints, Worst Slack 1.481ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.140ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.481ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 6.700ns (logic 0.362ns (5.403%) route 6.338ns (94.597%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.008ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.661ns = ( 10.978 - 8.317 ) Source Clock Delay (SCD): 2.879ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.454ns (routing 0.789ns, distribution 1.665ns) Clock Net Delay (Destination): 2.285ns (routing 0.708ns, distribution 1.577ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.454 2.879 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y534 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y534 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.018 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 4.788 7.806 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y427 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 8.029 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/O net (fo=15, routed) 1.550 9.579 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X62Y505 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.285 10.978 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X62Y505 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/C clock pessimism 0.210 11.188 clock uncertainty -0.035 11.153 SLICE_X62Y505 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.060 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1] ------------------------------------------------------------------- required time 11.060 arrival time -9.579 ------------------------------------------------------------------- slack 1.481 Slack (MET) : 1.481ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 6.701ns (logic 0.362ns (5.402%) route 6.339ns (94.598%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.007ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.662ns = ( 10.979 - 8.317 ) Source Clock Delay (SCD): 2.879ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.454ns (routing 0.789ns, distribution 1.665ns) Clock Net Delay (Destination): 2.286ns (routing 0.708ns, distribution 1.578ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.454 2.879 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y534 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y534 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.018 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 4.788 7.806 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y427 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 8.029 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/O net (fo=15, routed) 1.551 9.580 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X63Y505 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.286 10.979 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X63Y505 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/C clock pessimism 0.210 11.189 clock uncertainty -0.035 11.154 SLICE_X63Y505 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.061 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3] ------------------------------------------------------------------- required time 11.061 arrival time -9.580 ------------------------------------------------------------------- slack 1.481 Slack (MET) : 1.481ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 6.701ns (logic 0.362ns (5.402%) route 6.339ns (94.598%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.007ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.662ns = ( 10.979 - 8.317 ) Source Clock Delay (SCD): 2.879ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.454ns (routing 0.789ns, distribution 1.665ns) Clock Net Delay (Destination): 2.286ns (routing 0.708ns, distribution 1.578ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.454 2.879 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y534 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y534 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.018 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 4.788 7.806 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y427 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 8.029 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/O net (fo=15, routed) 1.551 9.580 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X63Y505 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.286 10.979 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X63Y505 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/C clock pessimism 0.210 11.189 clock uncertainty -0.035 11.154 SLICE_X63Y505 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.061 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4] ------------------------------------------------------------------- required time 11.061 arrival time -9.580 ------------------------------------------------------------------- slack 1.481 Slack (MET) : 1.481ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 6.701ns (logic 0.362ns (5.402%) route 6.339ns (94.598%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.007ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.662ns = ( 10.979 - 8.317 ) Source Clock Delay (SCD): 2.879ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.454ns (routing 0.789ns, distribution 1.665ns) Clock Net Delay (Destination): 2.286ns (routing 0.708ns, distribution 1.578ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.454 2.879 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y534 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y534 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.018 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 4.788 7.806 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y427 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 8.029 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/O net (fo=15, routed) 1.551 9.580 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X63Y505 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.286 10.979 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X63Y505 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/C clock pessimism 0.210 11.189 clock uncertainty -0.035 11.154 SLICE_X63Y505 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 11.061 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6] ------------------------------------------------------------------- required time 11.061 arrival time -9.580 ------------------------------------------------------------------- slack 1.481 Slack (MET) : 1.481ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 6.701ns (logic 0.362ns (5.402%) route 6.339ns (94.598%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.007ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.662ns = ( 10.979 - 8.317 ) Source Clock Delay (SCD): 2.879ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.454ns (routing 0.789ns, distribution 1.665ns) Clock Net Delay (Destination): 2.286ns (routing 0.708ns, distribution 1.578ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.454 2.879 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y534 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y534 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.018 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 4.788 7.806 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y427 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 8.029 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/O net (fo=15, routed) 1.551 9.580 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X63Y505 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.286 10.979 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X63Y505 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/C clock pessimism 0.210 11.189 clock uncertainty -0.035 11.154 SLICE_X63Y505 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 11.061 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7] ------------------------------------------------------------------- required time 11.061 arrival time -9.580 ------------------------------------------------------------------- slack 1.481 Slack (MET) : 1.486ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 6.693ns (logic 0.362ns (5.409%) route 6.331ns (94.591%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.010ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.659ns = ( 10.976 - 8.317 ) Source Clock Delay (SCD): 2.879ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.454ns (routing 0.789ns, distribution 1.665ns) Clock Net Delay (Destination): 2.283ns (routing 0.708ns, distribution 1.575ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.454 2.879 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y534 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y534 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.018 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 4.788 7.806 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y427 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 8.029 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/O net (fo=15, routed) 1.543 9.572 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X62Y505 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.283 10.976 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X62Y505 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/C clock pessimism 0.210 11.186 clock uncertainty -0.035 11.151 SLICE_X62Y505 FDCE (Recov_GFF_SLICEM_C_CLR) -0.093 11.058 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0] ------------------------------------------------------------------- required time 11.058 arrival time -9.572 ------------------------------------------------------------------- slack 1.486 Slack (MET) : 1.486ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 6.693ns (logic 0.362ns (5.409%) route 6.331ns (94.591%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.010ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.659ns = ( 10.976 - 8.317 ) Source Clock Delay (SCD): 2.879ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.454ns (routing 0.789ns, distribution 1.665ns) Clock Net Delay (Destination): 2.283ns (routing 0.708ns, distribution 1.575ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.454 2.879 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y534 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y534 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.018 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 4.788 7.806 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y427 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 8.029 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/O net (fo=15, routed) 1.543 9.572 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X62Y505 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.283 10.976 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X62Y505 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/C clock pessimism 0.210 11.186 clock uncertainty -0.035 11.151 SLICE_X62Y505 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.058 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5] ------------------------------------------------------------------- required time 11.058 arrival time -9.572 ------------------------------------------------------------------- slack 1.486 Slack (MET) : 1.486ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 6.693ns (logic 0.362ns (5.409%) route 6.331ns (94.591%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.010ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.659ns = ( 10.976 - 8.317 ) Source Clock Delay (SCD): 2.879ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.454ns (routing 0.789ns, distribution 1.665ns) Clock Net Delay (Destination): 2.283ns (routing 0.708ns, distribution 1.575ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.454 2.879 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y534 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y534 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.018 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 4.788 7.806 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y427 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 8.029 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/O net (fo=15, routed) 1.543 9.572 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X62Y505 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.283 10.976 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X62Y505 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][5]/C clock pessimism 0.210 11.186 clock uncertainty -0.035 11.151 SLICE_X62Y505 FDCE (Recov_HFF2_SLICEM_C_CLR) -0.093 11.058 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][5] ------------------------------------------------------------------- required time 11.058 arrival time -9.572 ------------------------------------------------------------------- slack 1.486 Slack (MET) : 1.489ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 6.691ns (logic 0.362ns (5.410%) route 6.329ns (94.590%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.009ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.660ns = ( 10.977 - 8.317 ) Source Clock Delay (SCD): 2.879ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.454ns (routing 0.789ns, distribution 1.665ns) Clock Net Delay (Destination): 2.284ns (routing 0.708ns, distribution 1.576ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.454 2.879 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y534 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y534 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.018 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 4.788 7.806 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y427 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 8.029 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/O net (fo=15, routed) 1.541 9.570 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X63Y505 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.284 10.977 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X63Y505 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/C clock pessimism 0.210 11.187 clock uncertainty -0.035 11.152 SLICE_X63Y505 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 11.059 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2] ------------------------------------------------------------------- required time 11.059 arrival time -9.570 ------------------------------------------------------------------- slack 1.489 Slack (MET) : 1.618ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 6.537ns (logic 0.362ns (5.538%) route 6.175ns (94.462%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.635ns = ( 10.952 - 8.317 ) Source Clock Delay (SCD): 2.879ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.454ns (routing 0.789ns, distribution 1.665ns) Clock Net Delay (Destination): 2.259ns (routing 0.708ns, distribution 1.551ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.454 2.879 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y534 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y534 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.018 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 4.788 7.806 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y427 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 8.029 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/O net (fo=15, routed) 1.387 9.416 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X61Y503 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.259 10.952 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X61Y503 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/C clock pessimism 0.210 11.162 clock uncertainty -0.035 11.127 SLICE_X61Y503 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.034 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1] ------------------------------------------------------------------- required time 11.034 arrival time -9.416 ------------------------------------------------------------------- slack 1.618 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.140ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.233ns (logic 0.049ns (21.030%) route 0.184ns (78.970%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.381ns Source Clock Delay (SCD): 1.135ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.019ns (routing 0.376ns, distribution 0.643ns) Clock Net Delay (Destination): 1.229ns (routing 0.440ns, distribution 0.789ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.019 1.135 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X61Y530 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X61Y530 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.184 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.184 1.368 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X62Y530 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.229 1.381 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X62Y530 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C clock pessimism -0.158 1.223 SLICE_X62Y530 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.228 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time -1.228 arrival time 1.368 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.140ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.233ns (logic 0.049ns (21.030%) route 0.184ns (78.970%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.381ns Source Clock Delay (SCD): 1.135ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.019ns (routing 0.376ns, distribution 0.643ns) Clock Net Delay (Destination): 1.229ns (routing 0.440ns, distribution 0.789ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.019 1.135 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X61Y530 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X61Y530 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.184 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.184 1.368 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X62Y530 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.229 1.381 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X62Y530 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C clock pessimism -0.158 1.223 SLICE_X62Y530 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.228 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13] ------------------------------------------------------------------- required time -1.228 arrival time 1.368 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.140ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.233ns (logic 0.049ns (21.030%) route 0.184ns (78.970%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.381ns Source Clock Delay (SCD): 1.135ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.019ns (routing 0.376ns, distribution 0.643ns) Clock Net Delay (Destination): 1.229ns (routing 0.440ns, distribution 0.789ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.019 1.135 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X61Y530 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X61Y530 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.184 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.184 1.368 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X62Y530 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.229 1.381 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X62Y530 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C clock pessimism -0.158 1.223 SLICE_X62Y530 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.228 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20] ------------------------------------------------------------------- required time -1.228 arrival time 1.368 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.140ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.233ns (logic 0.049ns (21.030%) route 0.184ns (78.970%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.381ns Source Clock Delay (SCD): 1.135ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.019ns (routing 0.376ns, distribution 0.643ns) Clock Net Delay (Destination): 1.229ns (routing 0.440ns, distribution 0.789ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.019 1.135 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X61Y530 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X61Y530 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.184 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.184 1.368 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X62Y530 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.229 1.381 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X62Y530 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C clock pessimism -0.158 1.223 SLICE_X62Y530 FDCE (Remov_FFF2_SLICEM_C_CLR) 0.005 1.228 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3] ------------------------------------------------------------------- required time -1.228 arrival time 1.368 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.232ns (logic 0.049ns (21.121%) route 0.183ns (78.879%)) Logic Levels: 0 Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.379ns Source Clock Delay (SCD): 1.135ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.019ns (routing 0.376ns, distribution 0.643ns) Clock Net Delay (Destination): 1.227ns (routing 0.440ns, distribution 0.787ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.019 1.135 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X61Y530 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X61Y530 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.184 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.183 1.367 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X63Y530 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.227 1.379 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X63Y530 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism -0.158 1.221 SLICE_X63Y530 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.226 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time -1.226 arrival time 1.367 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.232ns (logic 0.049ns (21.121%) route 0.183ns (78.879%)) Logic Levels: 0 Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.379ns Source Clock Delay (SCD): 1.135ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.019ns (routing 0.376ns, distribution 0.643ns) Clock Net Delay (Destination): 1.227ns (routing 0.440ns, distribution 0.787ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.019 1.135 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X61Y530 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X61Y530 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.184 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.183 1.367 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X63Y530 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.227 1.379 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X63Y530 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C clock pessimism -0.158 1.221 SLICE_X63Y530 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.226 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3] ------------------------------------------------------------------- required time -1.226 arrival time 1.367 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.152ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.229ns (logic 0.049ns (21.397%) route 0.180ns (78.603%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.349ns Source Clock Delay (SCD): 1.119ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.003ns (routing 0.376ns, distribution 0.627ns) Clock Net Delay (Destination): 1.197ns (routing 0.440ns, distribution 0.757ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.003 1.119 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X62Y507 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X62Y507 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.168 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.180 1.348 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X61Y505 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.197 1.349 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X61Y505 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.158 1.191 SLICE_X61Y505 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 1.196 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -1.196 arrival time 1.348 ------------------------------------------------------------------- slack 0.152 Slack (MET) : 0.153ns (arrival time - required time) Source: SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.048ns (20.779%) route 0.183ns (79.221%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.374ns Source Clock Delay (SCD): 1.143ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.027ns (routing 0.376ns, distribution 0.651ns) Clock Net Delay (Destination): 1.222ns (routing 0.440ns, distribution 0.782ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.027 1.143 SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X66Y528 FDPE r SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y528 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.191 f SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.183 1.374 SFP_GEN[43].ngCCM_gbt/sync_m_reg[3][0] SLICE_X64Y528 FDCE f SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.222 1.374 SFP_GEN[43].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X64Y528 FDCE r SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[28]/C clock pessimism -0.158 1.216 SLICE_X64Y528 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.221 SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[28] ------------------------------------------------------------------- required time -1.221 arrival time 1.374 ------------------------------------------------------------------- slack 0.153 Slack (MET) : 0.153ns (arrival time - required time) Source: SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.048ns (20.779%) route 0.183ns (79.221%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.374ns Source Clock Delay (SCD): 1.143ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.027ns (routing 0.376ns, distribution 0.651ns) Clock Net Delay (Destination): 1.222ns (routing 0.440ns, distribution 0.782ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.027 1.143 SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X66Y528 FDPE r SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y528 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.191 f SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.183 1.374 SFP_GEN[43].ngCCM_gbt/sync_m_reg[3][0] SLICE_X64Y528 FDCE f SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.222 1.374 SFP_GEN[43].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X64Y528 FDCE r SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[29]/C clock pessimism -0.158 1.216 SLICE_X64Y528 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 1.221 SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[29] ------------------------------------------------------------------- required time -1.221 arrival time 1.374 ------------------------------------------------------------------- slack 0.153 Slack (MET) : 0.153ns (arrival time - required time) Source: SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.048ns (20.779%) route 0.183ns (79.221%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.374ns Source Clock Delay (SCD): 1.143ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 1.027ns (routing 0.376ns, distribution 0.651ns) Clock Net Delay (Destination): 1.222ns (routing 0.440ns, distribution 0.782ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.027 1.143 SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X66Y528 FDPE r SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y528 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.191 f SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.183 1.374 SFP_GEN[43].ngCCM_gbt/sync_m_reg[3][0] SLICE_X64Y528 FDCE f SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y213 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.222 1.374 SFP_GEN[43].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X64Y528 FDCE r SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[36]/C clock pessimism -0.158 1.216 SLICE_X64Y528 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.221 SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[36] ------------------------------------------------------------------- required time -1.221 arrival time 1.374 ------------------------------------------------------------------- slack 0.153 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_46 To Clock: gtwiz_userclk_rx_srcclk_out[0]_46 Setup : 0 Failing Endpoints, Worst Slack 2.839ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.136ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.839ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 5.351ns (logic 0.285ns (5.326%) route 5.066ns (94.674%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.001ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.641ns = ( 10.958 - 8.317 ) Source Clock Delay (SCD): 2.851ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.426ns (routing 0.793ns, distribution 1.633ns) Clock Net Delay (Destination): 2.265ns (routing 0.709ns, distribution 1.556ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.426 2.851 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X10Y545 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X10Y545 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.990 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.464 6.454 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y479 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 6.600 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/O net (fo=15, routed) 1.602 8.202 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X63Y544 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.265 10.958 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X63Y544 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/C clock pessimism 0.211 11.169 clock uncertainty -0.035 11.134 SLICE_X63Y544 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.041 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1] ------------------------------------------------------------------- required time 11.041 arrival time -8.202 ------------------------------------------------------------------- slack 2.839 Slack (MET) : 2.839ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 5.351ns (logic 0.285ns (5.326%) route 5.066ns (94.674%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.001ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.641ns = ( 10.958 - 8.317 ) Source Clock Delay (SCD): 2.851ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.426ns (routing 0.793ns, distribution 1.633ns) Clock Net Delay (Destination): 2.265ns (routing 0.709ns, distribution 1.556ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.426 2.851 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X10Y545 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X10Y545 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.990 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.464 6.454 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y479 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 6.600 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/O net (fo=15, routed) 1.602 8.202 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X63Y544 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.265 10.958 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X63Y544 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/C clock pessimism 0.211 11.169 clock uncertainty -0.035 11.134 SLICE_X63Y544 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 11.041 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2] ------------------------------------------------------------------- required time 11.041 arrival time -8.202 ------------------------------------------------------------------- slack 2.839 Slack (MET) : 2.839ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 5.351ns (logic 0.285ns (5.326%) route 5.066ns (94.674%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.001ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.641ns = ( 10.958 - 8.317 ) Source Clock Delay (SCD): 2.851ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.426ns (routing 0.793ns, distribution 1.633ns) Clock Net Delay (Destination): 2.265ns (routing 0.709ns, distribution 1.556ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.426 2.851 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X10Y545 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X10Y545 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.990 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.464 6.454 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y479 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 6.600 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/O net (fo=15, routed) 1.602 8.202 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X63Y544 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.265 10.958 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X63Y544 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/C clock pessimism 0.211 11.169 clock uncertainty -0.035 11.134 SLICE_X63Y544 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 11.041 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3] ------------------------------------------------------------------- required time 11.041 arrival time -8.202 ------------------------------------------------------------------- slack 2.839 Slack (MET) : 2.839ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 5.351ns (logic 0.285ns (5.326%) route 5.066ns (94.674%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.001ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.641ns = ( 10.958 - 8.317 ) Source Clock Delay (SCD): 2.851ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.426ns (routing 0.793ns, distribution 1.633ns) Clock Net Delay (Destination): 2.265ns (routing 0.709ns, distribution 1.556ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.426 2.851 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X10Y545 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X10Y545 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.990 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.464 6.454 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y479 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 6.600 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/O net (fo=15, routed) 1.602 8.202 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X63Y544 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.265 10.958 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X63Y544 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/C clock pessimism 0.211 11.169 clock uncertainty -0.035 11.134 SLICE_X63Y544 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.041 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4] ------------------------------------------------------------------- required time 11.041 arrival time -8.202 ------------------------------------------------------------------- slack 2.839 Slack (MET) : 3.037ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 5.160ns (logic 0.285ns (5.523%) route 4.875ns (94.477%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.008ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.648ns = ( 10.965 - 8.317 ) Source Clock Delay (SCD): 2.851ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.426ns (routing 0.793ns, distribution 1.633ns) Clock Net Delay (Destination): 2.272ns (routing 0.709ns, distribution 1.563ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.426 2.851 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X10Y545 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X10Y545 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.990 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.464 6.454 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y479 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 6.600 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/O net (fo=15, routed) 1.411 8.011 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X63Y546 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.272 10.965 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X63Y546 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/C clock pessimism 0.211 11.176 clock uncertainty -0.035 11.141 SLICE_X63Y546 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.048 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1] ------------------------------------------------------------------- required time 11.048 arrival time -8.011 ------------------------------------------------------------------- slack 3.037 Slack (MET) : 3.037ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 5.160ns (logic 0.285ns (5.523%) route 4.875ns (94.477%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.008ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.648ns = ( 10.965 - 8.317 ) Source Clock Delay (SCD): 2.851ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.426ns (routing 0.793ns, distribution 1.633ns) Clock Net Delay (Destination): 2.272ns (routing 0.709ns, distribution 1.563ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.426 2.851 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X10Y545 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X10Y545 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.990 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.464 6.454 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y479 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 6.600 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/O net (fo=15, routed) 1.411 8.011 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X63Y546 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.272 10.965 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X63Y546 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/C clock pessimism 0.211 11.176 clock uncertainty -0.035 11.141 SLICE_X63Y546 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 11.048 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2] ------------------------------------------------------------------- required time 11.048 arrival time -8.011 ------------------------------------------------------------------- slack 3.037 Slack (MET) : 3.042ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 5.152ns (logic 0.285ns (5.532%) route 4.867ns (94.468%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.005ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.645ns = ( 10.962 - 8.317 ) Source Clock Delay (SCD): 2.851ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.426ns (routing 0.793ns, distribution 1.633ns) Clock Net Delay (Destination): 2.269ns (routing 0.709ns, distribution 1.560ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.426 2.851 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X10Y545 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X10Y545 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.990 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.464 6.454 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y479 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 6.600 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/O net (fo=15, routed) 1.403 8.003 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X64Y546 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.269 10.962 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X64Y546 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/C clock pessimism 0.211 11.173 clock uncertainty -0.035 11.138 SLICE_X64Y546 FDCE (Recov_BFF2_SLICEM_C_CLR) -0.093 11.045 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0] ------------------------------------------------------------------- required time 11.045 arrival time -8.003 ------------------------------------------------------------------- slack 3.042 Slack (MET) : 3.042ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 5.152ns (logic 0.285ns (5.532%) route 4.867ns (94.468%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.005ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.645ns = ( 10.962 - 8.317 ) Source Clock Delay (SCD): 2.851ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.426ns (routing 0.793ns, distribution 1.633ns) Clock Net Delay (Destination): 2.269ns (routing 0.709ns, distribution 1.560ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.426 2.851 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X10Y545 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X10Y545 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.990 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.464 6.454 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y479 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 6.600 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/O net (fo=15, routed) 1.403 8.003 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X64Y546 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.269 10.962 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X64Y546 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5]/C clock pessimism 0.211 11.173 clock uncertainty -0.035 11.138 SLICE_X64Y546 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.045 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5] ------------------------------------------------------------------- required time 11.045 arrival time -8.003 ------------------------------------------------------------------- slack 3.042 Slack (MET) : 3.045ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 5.150ns (logic 0.285ns (5.534%) route 4.865ns (94.466%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.006ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.646ns = ( 10.963 - 8.317 ) Source Clock Delay (SCD): 2.851ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.426ns (routing 0.793ns, distribution 1.633ns) Clock Net Delay (Destination): 2.270ns (routing 0.709ns, distribution 1.561ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.426 2.851 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X10Y545 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X10Y545 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.990 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.464 6.454 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y479 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 6.600 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/O net (fo=15, routed) 1.401 8.001 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X63Y546 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.270 10.963 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X63Y546 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/C clock pessimism 0.211 11.174 clock uncertainty -0.035 11.139 SLICE_X63Y546 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 11.046 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8] ------------------------------------------------------------------- required time 11.046 arrival time -8.001 ------------------------------------------------------------------- slack 3.045 Slack (MET) : 3.045ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 5.150ns (logic 0.285ns (5.534%) route 4.865ns (94.466%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.006ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.646ns = ( 10.963 - 8.317 ) Source Clock Delay (SCD): 2.851ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.426ns (routing 0.793ns, distribution 1.633ns) Clock Net Delay (Destination): 2.270ns (routing 0.709ns, distribution 1.561ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.426 2.851 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X10Y545 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X10Y545 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.990 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.464 6.454 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X63Y479 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.146 6.600 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/O net (fo=15, routed) 1.401 8.001 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X63Y546 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.270 10.963 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X63Y546 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0]/C clock pessimism 0.211 11.174 clock uncertainty -0.035 11.139 SLICE_X63Y546 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.046 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0] ------------------------------------------------------------------- required time 11.046 arrival time -8.001 ------------------------------------------------------------------- slack 3.045 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.136ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.242ns (logic 0.049ns (20.248%) route 0.193ns (79.752%)) Logic Levels: 0 Clock Path Skew: 0.101ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.369ns Source Clock Delay (SCD): 1.109ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.993ns (routing 0.377ns, distribution 0.616ns) Clock Net Delay (Destination): 1.217ns (routing 0.443ns, distribution 0.774ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.993 1.109 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X60Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y569 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.158 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.193 1.351 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X63Y569 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.217 1.369 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X63Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C clock pessimism -0.159 1.210 SLICE_X63Y569 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.215 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10] ------------------------------------------------------------------- required time -1.215 arrival time 1.351 ------------------------------------------------------------------- slack 0.136 Slack (MET) : 0.136ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.242ns (logic 0.049ns (20.248%) route 0.193ns (79.752%)) Logic Levels: 0 Clock Path Skew: 0.101ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.369ns Source Clock Delay (SCD): 1.109ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.993ns (routing 0.377ns, distribution 0.616ns) Clock Net Delay (Destination): 1.217ns (routing 0.443ns, distribution 0.774ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.993 1.109 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X60Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y569 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.158 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.193 1.351 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X63Y569 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.217 1.369 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X63Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C clock pessimism -0.159 1.210 SLICE_X63Y569 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.215 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11] ------------------------------------------------------------------- required time -1.215 arrival time 1.351 ------------------------------------------------------------------- slack 0.136 Slack (MET) : 0.136ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.242ns (logic 0.049ns (20.248%) route 0.193ns (79.752%)) Logic Levels: 0 Clock Path Skew: 0.101ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.369ns Source Clock Delay (SCD): 1.109ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.993ns (routing 0.377ns, distribution 0.616ns) Clock Net Delay (Destination): 1.217ns (routing 0.443ns, distribution 0.774ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.993 1.109 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X60Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y569 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.158 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.193 1.351 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X63Y569 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.217 1.369 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X63Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C clock pessimism -0.159 1.210 SLICE_X63Y569 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.215 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13] ------------------------------------------------------------------- required time -1.215 arrival time 1.351 ------------------------------------------------------------------- slack 0.136 Slack (MET) : 0.136ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.242ns (logic 0.049ns (20.248%) route 0.193ns (79.752%)) Logic Levels: 0 Clock Path Skew: 0.101ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.369ns Source Clock Delay (SCD): 1.109ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.993ns (routing 0.377ns, distribution 0.616ns) Clock Net Delay (Destination): 1.217ns (routing 0.443ns, distribution 0.774ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.993 1.109 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X60Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y569 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.158 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.193 1.351 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X63Y569 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.217 1.369 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X63Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C clock pessimism -0.159 1.210 SLICE_X63Y569 FDCE (Remov_FFF2_SLICEL_C_CLR) 0.005 1.215 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15] ------------------------------------------------------------------- required time -1.215 arrival time 1.351 ------------------------------------------------------------------- slack 0.136 Slack (MET) : 0.136ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.242ns (logic 0.049ns (20.248%) route 0.193ns (79.752%)) Logic Levels: 0 Clock Path Skew: 0.101ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.369ns Source Clock Delay (SCD): 1.109ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.993ns (routing 0.377ns, distribution 0.616ns) Clock Net Delay (Destination): 1.217ns (routing 0.443ns, distribution 0.774ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.993 1.109 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X60Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y569 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.158 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.193 1.351 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X63Y569 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.217 1.369 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X63Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C clock pessimism -0.159 1.210 SLICE_X63Y569 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 1.215 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time -1.215 arrival time 1.351 ------------------------------------------------------------------- slack 0.136 Slack (MET) : 0.136ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.242ns (logic 0.049ns (20.248%) route 0.193ns (79.752%)) Logic Levels: 0 Clock Path Skew: 0.101ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.369ns Source Clock Delay (SCD): 1.109ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.993ns (routing 0.377ns, distribution 0.616ns) Clock Net Delay (Destination): 1.217ns (routing 0.443ns, distribution 0.774ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.993 1.109 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X60Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y569 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.158 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.193 1.351 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X63Y569 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.217 1.369 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X63Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C clock pessimism -0.159 1.210 SLICE_X63Y569 FDCE (Remov_GFF2_SLICEL_C_CLR) 0.005 1.215 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4] ------------------------------------------------------------------- required time -1.215 arrival time 1.351 ------------------------------------------------------------------- slack 0.136 Slack (MET) : 0.136ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.242ns (logic 0.049ns (20.248%) route 0.193ns (79.752%)) Logic Levels: 0 Clock Path Skew: 0.101ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.369ns Source Clock Delay (SCD): 1.109ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.993ns (routing 0.377ns, distribution 0.616ns) Clock Net Delay (Destination): 1.217ns (routing 0.443ns, distribution 0.774ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.993 1.109 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X60Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y569 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.158 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.193 1.351 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X63Y569 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.217 1.369 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X63Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C clock pessimism -0.159 1.210 SLICE_X63Y569 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.215 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6] ------------------------------------------------------------------- required time -1.215 arrival time 1.351 ------------------------------------------------------------------- slack 0.136 Slack (MET) : 0.136ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.242ns (logic 0.049ns (20.248%) route 0.193ns (79.752%)) Logic Levels: 0 Clock Path Skew: 0.101ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.369ns Source Clock Delay (SCD): 1.109ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.993ns (routing 0.377ns, distribution 0.616ns) Clock Net Delay (Destination): 1.217ns (routing 0.443ns, distribution 0.774ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.993 1.109 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X60Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y569 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.158 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.193 1.351 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X63Y569 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.217 1.369 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X63Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C clock pessimism -0.159 1.210 SLICE_X63Y569 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 1.215 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8] ------------------------------------------------------------------- required time -1.215 arrival time 1.351 ------------------------------------------------------------------- slack 0.136 Slack (MET) : 0.137ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.243ns (logic 0.049ns (20.165%) route 0.194ns (79.835%)) Logic Levels: 0 Clock Path Skew: 0.101ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.369ns Source Clock Delay (SCD): 1.109ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.993ns (routing 0.377ns, distribution 0.616ns) Clock Net Delay (Destination): 1.217ns (routing 0.443ns, distribution 0.774ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.993 1.109 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X60Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y569 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.158 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.194 1.352 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X62Y569 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.217 1.369 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X62Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism -0.159 1.210 SLICE_X62Y569 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.215 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time -1.215 arrival time 1.352 ------------------------------------------------------------------- slack 0.137 Slack (MET) : 0.137ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.243ns (logic 0.049ns (20.165%) route 0.194ns (79.835%)) Logic Levels: 0 Clock Path Skew: 0.101ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.369ns Source Clock Delay (SCD): 1.109ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.993ns (routing 0.377ns, distribution 0.616ns) Clock Net Delay (Destination): 1.217ns (routing 0.443ns, distribution 0.774ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.993 1.109 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X60Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y569 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.158 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.194 1.352 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X62Y569 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y235 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.217 1.369 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X62Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.159 1.210 SLICE_X62Y569 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.215 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -1.215 arrival time 1.352 ------------------------------------------------------------------- slack 0.137 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_47 To Clock: gtwiz_userclk_rx_srcclk_out[0]_47 Setup : 0 Failing Endpoints, Worst Slack 5.042ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.170ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.042ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 2.987ns (logic 0.383ns (12.822%) route 2.604ns (87.178%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.160ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.313ns = ( 10.630 - 8.317 ) Source Clock Delay (SCD): 2.673ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.248ns (routing 0.773ns, distribution 1.475ns) Clock Net Delay (Destination): 1.937ns (routing 0.695ns, distribution 1.242ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.248 2.673 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X35Y544 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X35Y544 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.812 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.168 3.980 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X44Y500 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 4.224 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/O net (fo=15, routed) 1.436 5.660 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X47Y540 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.937 10.630 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X47Y540 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/C clock pessimism 0.200 10.831 clock uncertainty -0.035 10.795 SLICE_X47Y540 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.702 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6] ------------------------------------------------------------------- required time 10.702 arrival time -5.660 ------------------------------------------------------------------- slack 5.042 Slack (MET) : 5.042ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 2.987ns (logic 0.383ns (12.822%) route 2.604ns (87.178%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.160ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.313ns = ( 10.630 - 8.317 ) Source Clock Delay (SCD): 2.673ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.248ns (routing 0.773ns, distribution 1.475ns) Clock Net Delay (Destination): 1.937ns (routing 0.695ns, distribution 1.242ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.248 2.673 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X35Y544 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X35Y544 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.812 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.168 3.980 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X44Y500 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 4.224 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/O net (fo=15, routed) 1.436 5.660 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X47Y540 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.937 10.630 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X47Y540 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/C clock pessimism 0.200 10.831 clock uncertainty -0.035 10.795 SLICE_X47Y540 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 10.702 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7] ------------------------------------------------------------------- required time 10.702 arrival time -5.660 ------------------------------------------------------------------- slack 5.042 Slack (MET) : 5.047ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 2.980ns (logic 0.383ns (12.852%) route 2.597ns (87.148%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.311ns = ( 10.628 - 8.317 ) Source Clock Delay (SCD): 2.673ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.248ns (routing 0.773ns, distribution 1.475ns) Clock Net Delay (Destination): 1.935ns (routing 0.695ns, distribution 1.240ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.248 2.673 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X35Y544 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X35Y544 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.812 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.168 3.980 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X44Y500 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 4.224 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/O net (fo=15, routed) 1.429 5.653 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X47Y540 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.935 10.628 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X47Y540 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/C clock pessimism 0.200 10.829 clock uncertainty -0.035 10.793 SLICE_X47Y540 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 10.700 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4] ------------------------------------------------------------------- required time 10.700 arrival time -5.653 ------------------------------------------------------------------- slack 5.047 Slack (MET) : 5.047ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 2.980ns (logic 0.383ns (12.852%) route 2.597ns (87.148%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.311ns = ( 10.628 - 8.317 ) Source Clock Delay (SCD): 2.673ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.248ns (routing 0.773ns, distribution 1.475ns) Clock Net Delay (Destination): 1.935ns (routing 0.695ns, distribution 1.240ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.248 2.673 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X35Y544 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X35Y544 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.812 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.168 3.980 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X44Y500 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 4.224 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/O net (fo=15, routed) 1.429 5.653 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X47Y540 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.935 10.628 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X47Y540 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/C clock pessimism 0.200 10.829 clock uncertainty -0.035 10.793 SLICE_X47Y540 FDCE (Recov_GFF_SLICEM_C_CLR) -0.093 10.700 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5] ------------------------------------------------------------------- required time 10.700 arrival time -5.653 ------------------------------------------------------------------- slack 5.047 Slack (MET) : 5.121ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 2.898ns (logic 0.383ns (13.216%) route 2.515ns (86.784%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.170ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.302ns = ( 10.619 - 8.317 ) Source Clock Delay (SCD): 2.673ns Clock Pessimism Removal (CPR): 0.201ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.248ns (routing 0.773ns, distribution 1.475ns) Clock Net Delay (Destination): 1.926ns (routing 0.695ns, distribution 1.231ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.248 2.673 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X35Y544 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X35Y544 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.812 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.168 3.980 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X44Y500 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 4.224 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/O net (fo=15, routed) 1.347 5.571 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X47Y542 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.926 10.619 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X47Y542 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/C clock pessimism 0.201 10.820 clock uncertainty -0.035 10.785 SLICE_X47Y542 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 10.692 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5] ------------------------------------------------------------------- required time 10.692 arrival time -5.571 ------------------------------------------------------------------- slack 5.121 Slack (MET) : 5.274ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 2.756ns (logic 0.383ns (13.897%) route 2.373ns (86.103%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.314ns = ( 10.631 - 8.317 ) Source Clock Delay (SCD): 2.673ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.248ns (routing 0.773ns, distribution 1.475ns) Clock Net Delay (Destination): 1.938ns (routing 0.695ns, distribution 1.243ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.248 2.673 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X35Y544 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X35Y544 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.812 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.168 3.980 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X44Y500 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 4.224 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/O net (fo=15, routed) 1.205 5.429 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X46Y541 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.938 10.631 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X46Y541 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]/C clock pessimism 0.200 10.832 clock uncertainty -0.035 10.796 SLICE_X46Y541 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.703 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1] ------------------------------------------------------------------- required time 10.703 arrival time -5.429 ------------------------------------------------------------------- slack 5.274 Slack (MET) : 5.274ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 2.756ns (logic 0.383ns (13.897%) route 2.373ns (86.103%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.314ns = ( 10.631 - 8.317 ) Source Clock Delay (SCD): 2.673ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.248ns (routing 0.773ns, distribution 1.475ns) Clock Net Delay (Destination): 1.938ns (routing 0.695ns, distribution 1.243ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.248 2.673 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X35Y544 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X35Y544 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.812 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.168 3.980 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X44Y500 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 4.224 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/O net (fo=15, routed) 1.205 5.429 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X46Y541 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.938 10.631 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X46Y541 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]/C clock pessimism 0.200 10.832 clock uncertainty -0.035 10.796 SLICE_X46Y541 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 10.703 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2] ------------------------------------------------------------------- required time 10.703 arrival time -5.429 ------------------------------------------------------------------- slack 5.274 Slack (MET) : 5.274ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 2.756ns (logic 0.383ns (13.897%) route 2.373ns (86.103%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.314ns = ( 10.631 - 8.317 ) Source Clock Delay (SCD): 2.673ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.248ns (routing 0.773ns, distribution 1.475ns) Clock Net Delay (Destination): 1.938ns (routing 0.695ns, distribution 1.243ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.248 2.673 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X35Y544 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X35Y544 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.812 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.168 3.980 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X44Y500 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 4.224 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/O net (fo=15, routed) 1.205 5.429 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X46Y541 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.938 10.631 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X46Y541 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/C clock pessimism 0.200 10.832 clock uncertainty -0.035 10.796 SLICE_X46Y541 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.703 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4] ------------------------------------------------------------------- required time 10.703 arrival time -5.429 ------------------------------------------------------------------- slack 5.274 Slack (MET) : 5.282ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 2.746ns (logic 0.383ns (13.948%) route 2.363ns (86.052%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.161ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.312ns = ( 10.629 - 8.317 ) Source Clock Delay (SCD): 2.673ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.248ns (routing 0.773ns, distribution 1.475ns) Clock Net Delay (Destination): 1.936ns (routing 0.695ns, distribution 1.241ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.248 2.673 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X35Y544 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X35Y544 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.812 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.168 3.980 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X44Y500 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 4.224 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/O net (fo=15, routed) 1.195 5.419 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X46Y541 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.936 10.629 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X46Y541 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/C clock pessimism 0.200 10.830 clock uncertainty -0.035 10.794 SLICE_X46Y541 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 10.701 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0] ------------------------------------------------------------------- required time 10.701 arrival time -5.419 ------------------------------------------------------------------- slack 5.282 Slack (MET) : 5.282ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 2.746ns (logic 0.383ns (13.948%) route 2.363ns (86.052%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.161ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.312ns = ( 10.629 - 8.317 ) Source Clock Delay (SCD): 2.673ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.248ns (routing 0.773ns, distribution 1.475ns) Clock Net Delay (Destination): 1.936ns (routing 0.695ns, distribution 1.241ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.248 2.673 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X35Y544 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X35Y544 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.812 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.168 3.980 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X44Y500 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 4.224 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/O net (fo=15, routed) 1.195 5.419 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X46Y541 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.936 10.629 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X46Y541 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C clock pessimism 0.200 10.830 clock uncertainty -0.035 10.794 SLICE_X46Y541 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 10.701 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3] ------------------------------------------------------------------- required time 10.701 arrival time -5.419 ------------------------------------------------------------------- slack 5.282 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.170ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.210ns (logic 0.049ns (23.333%) route 0.161ns (76.667%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.187ns Source Clock Delay (SCD): 0.982ns Clock Pessimism Removal (CPR): 0.170ns Clock Net Delay (Source): 0.866ns (routing 0.368ns, distribution 0.498ns) Clock Net Delay (Destination): 1.035ns (routing 0.430ns, distribution 0.605ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.866 0.982 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X45Y541 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X45Y541 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.031 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.161 1.192 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X45Y542 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.035 1.187 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X45Y542 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.170 1.017 SLICE_X45Y542 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.022 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -1.022 arrival time 1.192 ------------------------------------------------------------------- slack 0.170 Slack (MET) : 0.176ns (arrival time - required time) Source: SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.271ns (logic 0.048ns (17.712%) route 0.223ns (82.288%)) Logic Levels: 0 Clock Path Skew: 0.090ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.211ns Source Clock Delay (SCD): 0.980ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 0.864ns (routing 0.368ns, distribution 0.496ns) Clock Net Delay (Destination): 1.059ns (routing 0.430ns, distribution 0.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.864 0.980 SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X46Y550 FDPE r SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X46Y550 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.028 f SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.223 1.251 SFP_GEN[45].ngCCM_gbt/sync_m_reg[3][0] SLICE_X43Y549 FDCE f SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.059 1.211 SFP_GEN[45].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y549 FDCE r SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[32]/C clock pessimism -0.141 1.070 SLICE_X43Y549 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 1.075 SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[32] ------------------------------------------------------------------- required time -1.075 arrival time 1.251 ------------------------------------------------------------------- slack 0.176 Slack (MET) : 0.176ns (arrival time - required time) Source: SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.271ns (logic 0.048ns (17.712%) route 0.223ns (82.288%)) Logic Levels: 0 Clock Path Skew: 0.090ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.211ns Source Clock Delay (SCD): 0.980ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 0.864ns (routing 0.368ns, distribution 0.496ns) Clock Net Delay (Destination): 1.059ns (routing 0.430ns, distribution 0.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.864 0.980 SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X46Y550 FDPE r SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X46Y550 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.028 f SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.223 1.251 SFP_GEN[45].ngCCM_gbt/sync_m_reg[3][0] SLICE_X43Y549 FDCE f SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.059 1.211 SFP_GEN[45].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y549 FDCE r SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[34]/C clock pessimism -0.141 1.070 SLICE_X43Y549 FDCE (Remov_DFF2_SLICEL_C_CLR) 0.005 1.075 SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[34] ------------------------------------------------------------------- required time -1.075 arrival time 1.251 ------------------------------------------------------------------- slack 0.176 Slack (MET) : 0.197ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/RX_HEADER_LOCKED_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.262ns (logic 0.049ns (18.702%) route 0.213ns (81.298%)) Logic Levels: 0 Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.190ns Source Clock Delay (SCD): 0.989ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 0.873ns (routing 0.368ns, distribution 0.505ns) Clock Net Delay (Destination): 1.038ns (routing 0.430ns, distribution 0.608ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.873 0.989 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X35Y544 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X35Y544 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.038 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 0.213 1.251 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/bitslip_reset_9 SLICE_X38Y546 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/RX_HEADER_LOCKED_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.038 1.190 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X38Y546 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/RX_HEADER_LOCKED_O_reg/C clock pessimism -0.141 1.049 SLICE_X38Y546 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.054 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/RX_HEADER_LOCKED_O_reg ------------------------------------------------------------------- required time -1.054 arrival time 1.251 ------------------------------------------------------------------- slack 0.197 Slack (MET) : 0.207ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.280ns (logic 0.048ns (17.143%) route 0.232ns (82.857%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.188ns Source Clock Delay (SCD): 0.979ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 0.863ns (routing 0.368ns, distribution 0.495ns) Clock Net Delay (Destination): 1.036ns (routing 0.430ns, distribution 0.606ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.863 0.979 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X42Y556 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X42Y556 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.027 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.232 1.259 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X45Y560 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.036 1.188 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/CLK SLICE_X45Y560 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/READY_O_reg/C clock pessimism -0.141 1.047 SLICE_X45Y560 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.052 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/READY_O_reg ------------------------------------------------------------------- required time -1.052 arrival time 1.259 ------------------------------------------------------------------- slack 0.207 Slack (MET) : 0.207ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.280ns (logic 0.048ns (17.143%) route 0.232ns (82.857%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.188ns Source Clock Delay (SCD): 0.979ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 0.863ns (routing 0.368ns, distribution 0.495ns) Clock Net Delay (Destination): 1.036ns (routing 0.430ns, distribution 0.606ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.863 0.979 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X42Y556 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X42Y556 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.027 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.232 1.259 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X45Y560 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.036 1.188 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/CLK SLICE_X45Y560 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C clock pessimism -0.141 1.047 SLICE_X45Y560 FDCE (Remov_DFF2_SLICEL_C_CLR) 0.005 1.052 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg ------------------------------------------------------------------- required time -1.052 arrival time 1.259 ------------------------------------------------------------------- slack 0.207 Slack (MET) : 0.226ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.290ns (logic 0.048ns (16.552%) route 0.242ns (83.448%)) Logic Levels: 0 Clock Path Skew: 0.059ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.180ns Source Clock Delay (SCD): 0.979ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.863ns (routing 0.368ns, distribution 0.495ns) Clock Net Delay (Destination): 1.028ns (routing 0.430ns, distribution 0.598ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.863 0.979 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X42Y556 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X42Y556 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.027 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.242 1.269 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X41Y558 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.028 1.180 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X41Y558 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C clock pessimism -0.142 1.038 SLICE_X41Y558 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.043 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15] ------------------------------------------------------------------- required time -1.043 arrival time 1.269 ------------------------------------------------------------------- slack 0.226 Slack (MET) : 0.237ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.284ns (logic 0.048ns (16.901%) route 0.236ns (83.099%)) Logic Levels: 0 Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.190ns Source Clock Delay (SCD): 0.979ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 0.863ns (routing 0.368ns, distribution 0.495ns) Clock Net Delay (Destination): 1.038ns (routing 0.430ns, distribution 0.608ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.863 0.979 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X42Y556 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X42Y556 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.027 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.236 1.263 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X43Y553 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.038 1.190 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X43Y553 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C clock pessimism -0.169 1.021 SLICE_X43Y553 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.026 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7] ------------------------------------------------------------------- required time -1.026 arrival time 1.263 ------------------------------------------------------------------- slack 0.237 Slack (MET) : 0.238ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.310ns (logic 0.048ns (15.484%) route 0.262ns (84.516%)) Logic Levels: 0 Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.187ns Source Clock Delay (SCD): 0.979ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 0.863ns (routing 0.368ns, distribution 0.495ns) Clock Net Delay (Destination): 1.035ns (routing 0.430ns, distribution 0.605ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.863 0.979 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X42Y556 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X42Y556 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.027 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.262 1.289 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X40Y559 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.035 1.187 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X40Y559 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C clock pessimism -0.141 1.046 SLICE_X40Y559 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.051 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11] ------------------------------------------------------------------- required time -1.051 arrival time 1.289 ------------------------------------------------------------------- slack 0.238 Slack (MET) : 0.238ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.310ns (logic 0.048ns (15.484%) route 0.262ns (84.516%)) Logic Levels: 0 Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.187ns Source Clock Delay (SCD): 0.979ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 0.863ns (routing 0.368ns, distribution 0.495ns) Clock Net Delay (Destination): 1.035ns (routing 0.430ns, distribution 0.605ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.863 0.979 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X42Y556 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X42Y556 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.027 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.262 1.289 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X40Y559 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y233 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.035 1.187 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X40Y559 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism -0.141 1.046 SLICE_X40Y559 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.051 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time -1.051 arrival time 1.289 ------------------------------------------------------------------- slack 0.238 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_5 To Clock: gtwiz_userclk_rx_srcclk_out[0]_5 Setup : 0 Failing Endpoints, Worst Slack 3.889ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.180ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.889ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 3.688ns (logic 0.286ns (7.755%) route 3.402ns (92.245%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.612ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.679ns = ( 10.996 - 8.317 ) Source Clock Delay (SCD): 3.552ns Clock Pessimism Removal (CPR): 0.261ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.077ns (routing 1.103ns, distribution 1.974ns) Clock Net Delay (Destination): 2.281ns (routing 1.003ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.077 3.552 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X125Y97 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y97 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.691 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.710 6.401 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X80Y107 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.147 6.548 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__2/O net (fo=2, routed) 0.692 7.240 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X78Y100 FDCE f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.281 10.996 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X78Y100 FDCE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.261 11.257 clock uncertainty -0.035 11.222 SLICE_X78Y100 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.129 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 11.129 arrival time -7.240 ------------------------------------------------------------------- slack 3.889 Slack (MET) : 3.889ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 3.688ns (logic 0.286ns (7.755%) route 3.402ns (92.245%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.612ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.679ns = ( 10.996 - 8.317 ) Source Clock Delay (SCD): 3.552ns Clock Pessimism Removal (CPR): 0.261ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.077ns (routing 1.103ns, distribution 1.974ns) Clock Net Delay (Destination): 2.281ns (routing 1.003ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.077 3.552 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X125Y97 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y97 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.691 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.710 6.401 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X80Y107 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.147 6.548 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__2/O net (fo=2, routed) 0.692 7.240 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X78Y100 FDCE f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.281 10.996 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X78Y100 FDCE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.261 11.257 clock uncertainty -0.035 11.222 SLICE_X78Y100 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 11.129 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 11.129 arrival time -7.240 ------------------------------------------------------------------- slack 3.889 Slack (MET) : 3.906ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 3.671ns (logic 0.305ns (8.308%) route 3.366ns (91.692%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.612ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.679ns = ( 10.996 - 8.317 ) Source Clock Delay (SCD): 3.552ns Clock Pessimism Removal (CPR): 0.261ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.077ns (routing 1.103ns, distribution 1.974ns) Clock Net Delay (Destination): 2.281ns (routing 1.003ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.077 3.552 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X125Y97 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y97 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.691 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.880 5.571 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y109 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.166 5.737 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/O net (fo=15, routed) 1.486 7.223 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X75Y108 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.281 10.996 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] SLICE_X75Y108 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/C clock pessimism 0.261 11.257 clock uncertainty -0.035 11.222 SLICE_X75Y108 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 11.129 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3] ------------------------------------------------------------------- required time 11.129 arrival time -7.223 ------------------------------------------------------------------- slack 3.906 Slack (MET) : 3.906ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 3.671ns (logic 0.305ns (8.308%) route 3.366ns (91.692%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.612ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.679ns = ( 10.996 - 8.317 ) Source Clock Delay (SCD): 3.552ns Clock Pessimism Removal (CPR): 0.261ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.077ns (routing 1.103ns, distribution 1.974ns) Clock Net Delay (Destination): 2.281ns (routing 1.003ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.077 3.552 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X125Y97 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y97 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.691 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.880 5.571 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y109 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.166 5.737 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/O net (fo=15, routed) 1.486 7.223 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X75Y108 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.281 10.996 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] SLICE_X75Y108 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/C clock pessimism 0.261 11.257 clock uncertainty -0.035 11.222 SLICE_X75Y108 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 11.129 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0] ------------------------------------------------------------------- required time 11.129 arrival time -7.223 ------------------------------------------------------------------- slack 3.906 Slack (MET) : 4.041ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 3.531ns (logic 0.305ns (8.638%) route 3.226ns (91.362%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.617ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.674ns = ( 10.991 - 8.317 ) Source Clock Delay (SCD): 3.552ns Clock Pessimism Removal (CPR): 0.261ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.077ns (routing 1.103ns, distribution 1.974ns) Clock Net Delay (Destination): 2.276ns (routing 1.003ns, distribution 1.273ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.077 3.552 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X125Y97 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y97 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.691 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.880 5.571 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y109 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.166 5.737 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/O net (fo=15, routed) 1.346 7.083 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X75Y110 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.276 10.991 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] SLICE_X75Y110 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/C clock pessimism 0.261 11.252 clock uncertainty -0.035 11.217 SLICE_X75Y110 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 11.124 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2] ------------------------------------------------------------------- required time 11.124 arrival time -7.083 ------------------------------------------------------------------- slack 4.041 Slack (MET) : 4.041ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 3.531ns (logic 0.305ns (8.638%) route 3.226ns (91.362%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.617ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.674ns = ( 10.991 - 8.317 ) Source Clock Delay (SCD): 3.552ns Clock Pessimism Removal (CPR): 0.261ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.077ns (routing 1.103ns, distribution 1.974ns) Clock Net Delay (Destination): 2.276ns (routing 1.003ns, distribution 1.273ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.077 3.552 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X125Y97 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y97 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.691 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.880 5.571 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y109 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.166 5.737 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/O net (fo=15, routed) 1.346 7.083 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X75Y110 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.276 10.991 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] SLICE_X75Y110 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/C clock pessimism 0.261 11.252 clock uncertainty -0.035 11.217 SLICE_X75Y110 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 11.124 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5] ------------------------------------------------------------------- required time 11.124 arrival time -7.083 ------------------------------------------------------------------- slack 4.041 Slack (MET) : 4.115ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 3.465ns (logic 0.305ns (8.802%) route 3.160ns (91.198%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.609ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.682ns = ( 10.999 - 8.317 ) Source Clock Delay (SCD): 3.552ns Clock Pessimism Removal (CPR): 0.261ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.077ns (routing 1.103ns, distribution 1.974ns) Clock Net Delay (Destination): 2.284ns (routing 1.003ns, distribution 1.281ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.077 3.552 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X125Y97 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y97 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.691 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.880 5.571 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y109 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.166 5.737 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/O net (fo=15, routed) 1.280 7.017 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X75Y109 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.284 10.999 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] SLICE_X75Y109 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/C clock pessimism 0.261 11.260 clock uncertainty -0.035 11.225 SLICE_X75Y109 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.132 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1] ------------------------------------------------------------------- required time 11.132 arrival time -7.017 ------------------------------------------------------------------- slack 4.115 Slack (MET) : 4.115ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 3.465ns (logic 0.305ns (8.802%) route 3.160ns (91.198%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.609ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.682ns = ( 10.999 - 8.317 ) Source Clock Delay (SCD): 3.552ns Clock Pessimism Removal (CPR): 0.261ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.077ns (routing 1.103ns, distribution 1.974ns) Clock Net Delay (Destination): 2.284ns (routing 1.003ns, distribution 1.281ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.077 3.552 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X125Y97 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y97 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.691 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.880 5.571 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y109 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.166 5.737 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/O net (fo=15, routed) 1.280 7.017 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X75Y109 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.284 10.999 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] SLICE_X75Y109 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/C clock pessimism 0.261 11.260 clock uncertainty -0.035 11.225 SLICE_X75Y109 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.132 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4] ------------------------------------------------------------------- required time 11.132 arrival time -7.017 ------------------------------------------------------------------- slack 4.115 Slack (MET) : 4.115ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 3.465ns (logic 0.305ns (8.802%) route 3.160ns (91.198%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.609ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.682ns = ( 10.999 - 8.317 ) Source Clock Delay (SCD): 3.552ns Clock Pessimism Removal (CPR): 0.261ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.077ns (routing 1.103ns, distribution 1.974ns) Clock Net Delay (Destination): 2.284ns (routing 1.003ns, distribution 1.281ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.077 3.552 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X125Y97 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y97 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.691 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.880 5.571 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y109 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.166 5.737 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/O net (fo=15, routed) 1.280 7.017 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X75Y109 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.284 10.999 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] SLICE_X75Y109 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/C clock pessimism 0.261 11.260 clock uncertainty -0.035 11.225 SLICE_X75Y109 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 11.132 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6] ------------------------------------------------------------------- required time 11.132 arrival time -7.017 ------------------------------------------------------------------- slack 4.115 Slack (MET) : 4.115ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 3.465ns (logic 0.305ns (8.802%) route 3.160ns (91.198%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.609ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.682ns = ( 10.999 - 8.317 ) Source Clock Delay (SCD): 3.552ns Clock Pessimism Removal (CPR): 0.261ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.077ns (routing 1.103ns, distribution 1.974ns) Clock Net Delay (Destination): 2.284ns (routing 1.003ns, distribution 1.281ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.077 3.552 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X125Y97 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y97 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.691 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.880 5.571 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y109 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.166 5.737 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/O net (fo=15, routed) 1.280 7.017 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X75Y109 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.284 10.999 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] SLICE_X75Y109 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/C clock pessimism 0.261 11.260 clock uncertainty -0.035 11.225 SLICE_X75Y109 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 11.132 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7] ------------------------------------------------------------------- required time 11.132 arrival time -7.017 ------------------------------------------------------------------- slack 4.115 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.180ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.261ns (logic 0.048ns (18.391%) route 0.213ns (81.609%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.336ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 0.989ns (routing 0.471ns, distribution 0.518ns) Clock Net Delay (Destination): 1.171ns (routing 0.533ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X76Y105 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X76Y105 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.155 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.213 1.368 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X75Y107 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.171 1.336 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X75Y107 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism -0.153 1.183 SLICE_X75Y107 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.188 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time -1.188 arrival time 1.368 ------------------------------------------------------------------- slack 0.180 Slack (MET) : 0.180ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.261ns (logic 0.048ns (18.391%) route 0.213ns (81.609%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.336ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 0.989ns (routing 0.471ns, distribution 0.518ns) Clock Net Delay (Destination): 1.171ns (routing 0.533ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X76Y105 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X76Y105 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.155 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.213 1.368 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X75Y107 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.171 1.336 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X75Y107 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.153 1.183 SLICE_X75Y107 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.188 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -1.188 arrival time 1.368 ------------------------------------------------------------------- slack 0.180 Slack (MET) : 0.180ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.261ns (logic 0.048ns (18.391%) route 0.213ns (81.609%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.336ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 0.989ns (routing 0.471ns, distribution 0.518ns) Clock Net Delay (Destination): 1.171ns (routing 0.533ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X76Y105 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X76Y105 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.155 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.213 1.368 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X75Y107 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.171 1.336 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X75Y107 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism -0.153 1.183 SLICE_X75Y107 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 1.188 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time -1.188 arrival time 1.368 ------------------------------------------------------------------- slack 0.180 Slack (MET) : 0.180ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.261ns (logic 0.048ns (18.391%) route 0.213ns (81.609%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.336ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 0.989ns (routing 0.471ns, distribution 0.518ns) Clock Net Delay (Destination): 1.171ns (routing 0.533ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X76Y105 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X76Y105 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.155 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.213 1.368 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X75Y107 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.171 1.336 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X75Y107 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C clock pessimism -0.153 1.183 SLICE_X75Y107 FDCE (Remov_BFF2_SLICEL_C_CLR) 0.005 1.188 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3] ------------------------------------------------------------------- required time -1.188 arrival time 1.368 ------------------------------------------------------------------- slack 0.180 Slack (MET) : 0.180ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.261ns (logic 0.048ns (18.391%) route 0.213ns (81.609%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.336ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 0.989ns (routing 0.471ns, distribution 0.518ns) Clock Net Delay (Destination): 1.171ns (routing 0.533ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X76Y105 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X76Y105 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.155 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.213 1.368 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X75Y107 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.171 1.336 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X75Y107 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C clock pessimism -0.153 1.183 SLICE_X75Y107 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 1.188 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5] ------------------------------------------------------------------- required time -1.188 arrival time 1.368 ------------------------------------------------------------------- slack 0.180 Slack (MET) : 0.180ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.261ns (logic 0.048ns (18.391%) route 0.213ns (81.609%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.336ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 0.989ns (routing 0.471ns, distribution 0.518ns) Clock Net Delay (Destination): 1.171ns (routing 0.533ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X76Y105 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X76Y105 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.155 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.213 1.368 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X75Y107 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.171 1.336 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X75Y107 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C clock pessimism -0.153 1.183 SLICE_X75Y107 FDCE (Remov_CFF2_SLICEL_C_CLR) 0.005 1.188 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7] ------------------------------------------------------------------- required time -1.188 arrival time 1.368 ------------------------------------------------------------------- slack 0.180 Slack (MET) : 0.187ns (arrival time - required time) Source: SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.048ns (18.462%) route 0.212ns (81.538%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.336ns Source Clock Delay (SCD): 1.115ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 0.997ns (routing 0.471ns, distribution 0.526ns) Clock Net Delay (Destination): 1.171ns (routing 0.533ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.115 SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X72Y109 FDPE r SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y109 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.163 f SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.212 1.375 SFP_GEN[3].ngCCM_gbt/sync_m_reg[3][0] SLICE_X73Y108 FDCE f SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.171 1.336 SFP_GEN[3].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X73Y108 FDCE r SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[32]/C clock pessimism -0.153 1.183 SLICE_X73Y108 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.188 SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[32] ------------------------------------------------------------------- required time -1.188 arrival time 1.375 ------------------------------------------------------------------- slack 0.187 Slack (MET) : 0.187ns (arrival time - required time) Source: SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.048ns (18.462%) route 0.212ns (81.538%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.336ns Source Clock Delay (SCD): 1.115ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 0.997ns (routing 0.471ns, distribution 0.526ns) Clock Net Delay (Destination): 1.171ns (routing 0.533ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.115 SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X72Y109 FDPE r SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y109 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.163 f SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.212 1.375 SFP_GEN[3].ngCCM_gbt/sync_m_reg[3][0] SLICE_X73Y108 FDCE f SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.171 1.336 SFP_GEN[3].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X73Y108 FDCE r SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[34]/C clock pessimism -0.153 1.183 SLICE_X73Y108 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.188 SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[34] ------------------------------------------------------------------- required time -1.188 arrival time 1.375 ------------------------------------------------------------------- slack 0.187 Slack (MET) : 0.187ns (arrival time - required time) Source: SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.048ns (18.462%) route 0.212ns (81.538%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.336ns Source Clock Delay (SCD): 1.115ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 0.997ns (routing 0.471ns, distribution 0.526ns) Clock Net Delay (Destination): 1.171ns (routing 0.533ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.115 SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X72Y109 FDPE r SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y109 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.163 f SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.212 1.375 SFP_GEN[3].ngCCM_gbt/sync_m_reg[3][0] SLICE_X73Y108 FDCE f SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.171 1.336 SFP_GEN[3].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X73Y108 FDCE r SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[36]/C clock pessimism -0.153 1.183 SLICE_X73Y108 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.188 SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[36] ------------------------------------------------------------------- required time -1.188 arrival time 1.375 ------------------------------------------------------------------- slack 0.187 Slack (MET) : 0.187ns (arrival time - required time) Source: SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.048ns (18.462%) route 0.212ns (81.538%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.336ns Source Clock Delay (SCD): 1.115ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 0.997ns (routing 0.471ns, distribution 0.526ns) Clock Net Delay (Destination): 1.171ns (routing 0.533ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.115 SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X72Y109 FDPE r SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y109 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.163 f SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.212 1.375 SFP_GEN[3].ngCCM_gbt/sync_m_reg[3][0] SLICE_X73Y108 FDCE f SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y40 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.171 1.336 SFP_GEN[3].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X73Y108 FDCE r SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[38]/C clock pessimism -0.153 1.183 SLICE_X73Y108 FDCE (Remov_GFF2_SLICEM_C_CLR) 0.005 1.188 SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[38] ------------------------------------------------------------------- required time -1.188 arrival time 1.375 ------------------------------------------------------------------- slack 0.187 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_6 To Clock: gtwiz_userclk_rx_srcclk_out[0]_6 Setup : 0 Failing Endpoints, Worst Slack 5.036ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.217ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.036ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 3.175ns (logic 0.364ns (11.465%) route 2.811ns (88.535%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.598ns = ( 10.915 - 8.317 ) Source Clock Delay (SCD): 2.799ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.324ns (routing 0.667ns, distribution 1.657ns) Clock Net Delay (Destination): 2.200ns (routing 0.604ns, distribution 1.596ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.324 2.799 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X129Y120 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X129Y120 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.938 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.053 4.991 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y129 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.225 5.216 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/O net (fo=15, routed) 0.758 5.974 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X90Y132 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.200 10.915 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] SLICE_X90Y132 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/C clock pessimism 0.223 11.138 clock uncertainty -0.035 11.103 SLICE_X90Y132 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.010 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1] ------------------------------------------------------------------- required time 11.010 arrival time -5.974 ------------------------------------------------------------------- slack 5.036 Slack (MET) : 5.036ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 3.175ns (logic 0.364ns (11.465%) route 2.811ns (88.535%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.598ns = ( 10.915 - 8.317 ) Source Clock Delay (SCD): 2.799ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.324ns (routing 0.667ns, distribution 1.657ns) Clock Net Delay (Destination): 2.200ns (routing 0.604ns, distribution 1.596ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.324 2.799 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X129Y120 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X129Y120 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.938 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.053 4.991 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y129 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.225 5.216 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/O net (fo=15, routed) 0.758 5.974 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X90Y132 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.200 10.915 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] SLICE_X90Y132 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/C clock pessimism 0.223 11.138 clock uncertainty -0.035 11.103 SLICE_X90Y132 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 11.010 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2] ------------------------------------------------------------------- required time 11.010 arrival time -5.974 ------------------------------------------------------------------- slack 5.036 Slack (MET) : 5.036ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 3.175ns (logic 0.364ns (11.465%) route 2.811ns (88.535%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.598ns = ( 10.915 - 8.317 ) Source Clock Delay (SCD): 2.799ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.324ns (routing 0.667ns, distribution 1.657ns) Clock Net Delay (Destination): 2.200ns (routing 0.604ns, distribution 1.596ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.324 2.799 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X129Y120 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X129Y120 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.938 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.053 4.991 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y129 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.225 5.216 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/O net (fo=15, routed) 0.758 5.974 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X90Y132 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.200 10.915 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] SLICE_X90Y132 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/C clock pessimism 0.223 11.138 clock uncertainty -0.035 11.103 SLICE_X90Y132 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.010 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3] ------------------------------------------------------------------- required time 11.010 arrival time -5.974 ------------------------------------------------------------------- slack 5.036 Slack (MET) : 5.036ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 3.175ns (logic 0.364ns (11.465%) route 2.811ns (88.535%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.598ns = ( 10.915 - 8.317 ) Source Clock Delay (SCD): 2.799ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.324ns (routing 0.667ns, distribution 1.657ns) Clock Net Delay (Destination): 2.200ns (routing 0.604ns, distribution 1.596ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.324 2.799 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X129Y120 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X129Y120 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.938 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.053 4.991 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y129 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.225 5.216 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/O net (fo=15, routed) 0.758 5.974 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X90Y132 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.200 10.915 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] SLICE_X90Y132 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/C clock pessimism 0.223 11.138 clock uncertainty -0.035 11.103 SLICE_X90Y132 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.010 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4] ------------------------------------------------------------------- required time 11.010 arrival time -5.974 ------------------------------------------------------------------- slack 5.036 Slack (MET) : 5.109ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 3.102ns (logic 0.364ns (11.734%) route 2.738ns (88.266%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.598ns = ( 10.915 - 8.317 ) Source Clock Delay (SCD): 2.799ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.324ns (routing 0.667ns, distribution 1.657ns) Clock Net Delay (Destination): 2.200ns (routing 0.604ns, distribution 1.596ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.324 2.799 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X129Y120 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X129Y120 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.938 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.053 4.991 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y129 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.225 5.216 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/O net (fo=15, routed) 0.685 5.901 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X93Y131 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.200 10.915 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] SLICE_X93Y131 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/C clock pessimism 0.223 11.138 clock uncertainty -0.035 11.103 SLICE_X93Y131 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 11.010 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0] ------------------------------------------------------------------- required time 11.010 arrival time -5.901 ------------------------------------------------------------------- slack 5.109 Slack (MET) : 5.109ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 3.102ns (logic 0.364ns (11.734%) route 2.738ns (88.266%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.598ns = ( 10.915 - 8.317 ) Source Clock Delay (SCD): 2.799ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.324ns (routing 0.667ns, distribution 1.657ns) Clock Net Delay (Destination): 2.200ns (routing 0.604ns, distribution 1.596ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.324 2.799 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X129Y120 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X129Y120 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.938 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.053 4.991 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y129 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.225 5.216 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/O net (fo=15, routed) 0.685 5.901 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X93Y131 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.200 10.915 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] SLICE_X93Y131 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/C clock pessimism 0.223 11.138 clock uncertainty -0.035 11.103 SLICE_X93Y131 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.010 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1] ------------------------------------------------------------------- required time 11.010 arrival time -5.901 ------------------------------------------------------------------- slack 5.109 Slack (MET) : 5.109ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 3.102ns (logic 0.364ns (11.734%) route 2.738ns (88.266%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.598ns = ( 10.915 - 8.317 ) Source Clock Delay (SCD): 2.799ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.324ns (routing 0.667ns, distribution 1.657ns) Clock Net Delay (Destination): 2.200ns (routing 0.604ns, distribution 1.596ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.324 2.799 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X129Y120 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X129Y120 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.938 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.053 4.991 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y129 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.225 5.216 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/O net (fo=15, routed) 0.685 5.901 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X93Y131 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.200 10.915 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] SLICE_X93Y131 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C clock pessimism 0.223 11.138 clock uncertainty -0.035 11.103 SLICE_X93Y131 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 11.010 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2] ------------------------------------------------------------------- required time 11.010 arrival time -5.901 ------------------------------------------------------------------- slack 5.109 Slack (MET) : 5.113ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 3.069ns (logic 0.229ns (7.462%) route 2.840ns (92.538%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.007ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.569ns = ( 10.886 - 8.317 ) Source Clock Delay (SCD): 2.799ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.324ns (routing 0.667ns, distribution 1.657ns) Clock Net Delay (Destination): 2.171ns (routing 0.604ns, distribution 1.567ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.324 2.799 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X129Y120 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X129Y120 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.938 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.235 5.173 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X94Y129 LUT2 (Prop_D6LUT_SLICEL_I0_O) 0.090 5.263 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__3/O net (fo=2, routed) 0.605 5.868 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X94Y121 FDCE f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.171 10.886 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X94Y121 FDCE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.223 11.109 clock uncertainty -0.035 11.074 SLICE_X94Y121 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 10.981 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 10.981 arrival time -5.868 ------------------------------------------------------------------- slack 5.113 Slack (MET) : 5.113ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 3.069ns (logic 0.229ns (7.462%) route 2.840ns (92.538%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.007ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.569ns = ( 10.886 - 8.317 ) Source Clock Delay (SCD): 2.799ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.324ns (routing 0.667ns, distribution 1.657ns) Clock Net Delay (Destination): 2.171ns (routing 0.604ns, distribution 1.567ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.324 2.799 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X129Y120 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X129Y120 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.938 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.235 5.173 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X94Y129 LUT2 (Prop_D6LUT_SLICEL_I0_O) 0.090 5.263 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__3/O net (fo=2, routed) 0.605 5.868 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X94Y121 FDCE f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.171 10.886 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X94Y121 FDCE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.223 11.109 clock uncertainty -0.035 11.074 SLICE_X94Y121 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 10.981 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 10.981 arrival time -5.868 ------------------------------------------------------------------- slack 5.113 Slack (MET) : 5.117ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 3.092ns (logic 0.364ns (11.772%) route 2.728ns (88.228%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.020ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.596ns = ( 10.913 - 8.317 ) Source Clock Delay (SCD): 2.799ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.324ns (routing 0.667ns, distribution 1.657ns) Clock Net Delay (Destination): 2.198ns (routing 0.604ns, distribution 1.594ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.324 2.799 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X129Y120 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X129Y120 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.938 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.053 4.991 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y129 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.225 5.216 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/O net (fo=15, routed) 0.675 5.891 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X93Y131 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.198 10.913 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] SLICE_X93Y131 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/C clock pessimism 0.223 11.136 clock uncertainty -0.035 11.101 SLICE_X93Y131 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 11.008 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4] ------------------------------------------------------------------- required time 11.008 arrival time -5.891 ------------------------------------------------------------------- slack 5.117 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.217ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[80]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.309ns (logic 0.049ns (15.858%) route 0.260ns (84.142%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.307ns Source Clock Delay (SCD): 1.069ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.951ns (routing 0.303ns, distribution 0.648ns) Clock Net Delay (Destination): 1.142ns (routing 0.344ns, distribution 0.798ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.951 1.069 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X93Y123 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y123 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.118 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.260 1.378 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X89Y125 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[80]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.142 1.307 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X89Y125 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[80]/C clock pessimism -0.151 1.156 SLICE_X89Y125 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.161 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[80] ------------------------------------------------------------------- required time -1.161 arrival time 1.378 ------------------------------------------------------------------- slack 0.217 Slack (MET) : 0.217ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[89]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.309ns (logic 0.049ns (15.858%) route 0.260ns (84.142%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.307ns Source Clock Delay (SCD): 1.069ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.951ns (routing 0.303ns, distribution 0.648ns) Clock Net Delay (Destination): 1.142ns (routing 0.344ns, distribution 0.798ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.951 1.069 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X93Y123 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y123 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.118 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.260 1.378 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X89Y125 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[89]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.142 1.307 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X89Y125 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[89]/C clock pessimism -0.151 1.156 SLICE_X89Y125 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.161 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[89] ------------------------------------------------------------------- required time -1.161 arrival time 1.378 ------------------------------------------------------------------- slack 0.217 Slack (MET) : 0.217ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[91]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.309ns (logic 0.049ns (15.858%) route 0.260ns (84.142%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.307ns Source Clock Delay (SCD): 1.069ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.951ns (routing 0.303ns, distribution 0.648ns) Clock Net Delay (Destination): 1.142ns (routing 0.344ns, distribution 0.798ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.951 1.069 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X93Y123 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y123 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.118 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.260 1.378 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X89Y125 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[91]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.142 1.307 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X89Y125 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[91]/C clock pessimism -0.151 1.156 SLICE_X89Y125 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.161 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[91] ------------------------------------------------------------------- required time -1.161 arrival time 1.378 ------------------------------------------------------------------- slack 0.217 Slack (MET) : 0.217ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[96]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.309ns (logic 0.049ns (15.858%) route 0.260ns (84.142%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.307ns Source Clock Delay (SCD): 1.069ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.951ns (routing 0.303ns, distribution 0.648ns) Clock Net Delay (Destination): 1.142ns (routing 0.344ns, distribution 0.798ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.951 1.069 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X93Y123 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y123 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.118 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.260 1.378 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X89Y125 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[96]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.142 1.307 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X89Y125 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[96]/C clock pessimism -0.151 1.156 SLICE_X89Y125 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.161 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[96] ------------------------------------------------------------------- required time -1.161 arrival time 1.378 ------------------------------------------------------------------- slack 0.217 Slack (MET) : 0.217ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[80]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.309ns (logic 0.049ns (15.858%) route 0.260ns (84.142%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.307ns Source Clock Delay (SCD): 1.069ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.951ns (routing 0.303ns, distribution 0.648ns) Clock Net Delay (Destination): 1.142ns (routing 0.344ns, distribution 0.798ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.951 1.069 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X93Y123 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y123 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.118 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.260 1.378 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X89Y125 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[80]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.142 1.307 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X89Y125 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[80]/C clock pessimism -0.151 1.156 SLICE_X89Y125 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.161 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[80] ------------------------------------------------------------------- required time -1.161 arrival time 1.378 ------------------------------------------------------------------- slack 0.217 Slack (MET) : 0.217ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[89]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.309ns (logic 0.049ns (15.858%) route 0.260ns (84.142%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.307ns Source Clock Delay (SCD): 1.069ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.951ns (routing 0.303ns, distribution 0.648ns) Clock Net Delay (Destination): 1.142ns (routing 0.344ns, distribution 0.798ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.951 1.069 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X93Y123 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y123 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.118 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.260 1.378 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X89Y125 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[89]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.142 1.307 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X89Y125 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[89]/C clock pessimism -0.151 1.156 SLICE_X89Y125 FDCE (Remov_GFF2_SLICEM_C_CLR) 0.005 1.161 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[89] ------------------------------------------------------------------- required time -1.161 arrival time 1.378 ------------------------------------------------------------------- slack 0.217 Slack (MET) : 0.217ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[91]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.309ns (logic 0.049ns (15.858%) route 0.260ns (84.142%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.307ns Source Clock Delay (SCD): 1.069ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.951ns (routing 0.303ns, distribution 0.648ns) Clock Net Delay (Destination): 1.142ns (routing 0.344ns, distribution 0.798ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.951 1.069 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X93Y123 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y123 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.118 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.260 1.378 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X89Y125 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[91]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.142 1.307 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X89Y125 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[91]/C clock pessimism -0.151 1.156 SLICE_X89Y125 FDCE (Remov_FFF2_SLICEM_C_CLR) 0.005 1.161 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[91] ------------------------------------------------------------------- required time -1.161 arrival time 1.378 ------------------------------------------------------------------- slack 0.217 Slack (MET) : 0.217ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[96]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.309ns (logic 0.049ns (15.858%) route 0.260ns (84.142%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.307ns Source Clock Delay (SCD): 1.069ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.951ns (routing 0.303ns, distribution 0.648ns) Clock Net Delay (Destination): 1.142ns (routing 0.344ns, distribution 0.798ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.951 1.069 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X93Y123 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y123 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.118 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.260 1.378 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X89Y125 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[96]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.142 1.307 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X89Y125 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[96]/C clock pessimism -0.151 1.156 SLICE_X89Y125 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.161 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[96] ------------------------------------------------------------------- required time -1.161 arrival time 1.378 ------------------------------------------------------------------- slack 0.217 Slack (MET) : 0.218ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[40]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.312ns (logic 0.049ns (15.705%) route 0.263ns (84.295%)) Logic Levels: 0 Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.309ns Source Clock Delay (SCD): 1.069ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.951ns (routing 0.303ns, distribution 0.648ns) Clock Net Delay (Destination): 1.144ns (routing 0.344ns, distribution 0.800ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.951 1.069 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X93Y123 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y123 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.118 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.263 1.381 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X89Y125 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[40]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.144 1.309 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X89Y125 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[40]/C clock pessimism -0.151 1.158 SLICE_X89Y125 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.163 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[40] ------------------------------------------------------------------- required time -1.163 arrival time 1.381 ------------------------------------------------------------------- slack 0.218 Slack (MET) : 0.218ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[49]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.312ns (logic 0.049ns (15.705%) route 0.263ns (84.295%)) Logic Levels: 0 Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.309ns Source Clock Delay (SCD): 1.069ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.951ns (routing 0.303ns, distribution 0.648ns) Clock Net Delay (Destination): 1.144ns (routing 0.344ns, distribution 0.800ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.951 1.069 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X93Y123 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y123 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.118 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.263 1.381 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X89Y125 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[49]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y65 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.144 1.309 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X89Y125 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[49]/C clock pessimism -0.151 1.158 SLICE_X89Y125 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 1.163 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[49] ------------------------------------------------------------------- required time -1.163 arrival time 1.381 ------------------------------------------------------------------- slack 0.218 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_7 To Clock: gtwiz_userclk_rx_srcclk_out[0]_7 Setup : 0 Failing Endpoints, Worst Slack 4.078ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.183ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.078ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 4.165ns (logic 0.228ns (5.474%) route 3.937ns (94.526%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.642ns = ( 10.959 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.665ns, distribution 1.668ns) Clock Net Delay (Destination): 2.244ns (routing 0.604ns, distribution 1.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y141 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.060 6.007 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y144 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.089 6.096 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/O net (fo=15, routed) 0.877 6.973 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X85Y140 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.244 10.959 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] SLICE_X85Y140 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/C clock pessimism 0.220 11.179 clock uncertainty -0.035 11.144 SLICE_X85Y140 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.051 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1] ------------------------------------------------------------------- required time 11.051 arrival time -6.973 ------------------------------------------------------------------- slack 4.078 Slack (MET) : 4.078ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 4.165ns (logic 0.228ns (5.474%) route 3.937ns (94.526%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.642ns = ( 10.959 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.665ns, distribution 1.668ns) Clock Net Delay (Destination): 2.244ns (routing 0.604ns, distribution 1.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y141 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.060 6.007 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y144 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.089 6.096 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/O net (fo=15, routed) 0.877 6.973 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X85Y140 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.244 10.959 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] SLICE_X85Y140 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/C clock pessimism 0.220 11.179 clock uncertainty -0.035 11.144 SLICE_X85Y140 FDCE (Recov_HFF2_SLICEM_C_CLR) -0.093 11.051 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2] ------------------------------------------------------------------- required time 11.051 arrival time -6.973 ------------------------------------------------------------------- slack 4.078 Slack (MET) : 4.078ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 4.165ns (logic 0.228ns (5.474%) route 3.937ns (94.526%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.642ns = ( 10.959 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.665ns, distribution 1.668ns) Clock Net Delay (Destination): 2.244ns (routing 0.604ns, distribution 1.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y141 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.060 6.007 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y144 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.089 6.096 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/O net (fo=15, routed) 0.877 6.973 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X85Y140 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.244 10.959 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] SLICE_X85Y140 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/C clock pessimism 0.220 11.179 clock uncertainty -0.035 11.144 SLICE_X85Y140 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 11.051 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3] ------------------------------------------------------------------- required time 11.051 arrival time -6.973 ------------------------------------------------------------------- slack 4.078 Slack (MET) : 4.078ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 4.165ns (logic 0.228ns (5.474%) route 3.937ns (94.526%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.642ns = ( 10.959 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.665ns, distribution 1.668ns) Clock Net Delay (Destination): 2.244ns (routing 0.604ns, distribution 1.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y141 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.060 6.007 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y144 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.089 6.096 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/O net (fo=15, routed) 0.877 6.973 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X85Y140 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.244 10.959 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] SLICE_X85Y140 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/C clock pessimism 0.220 11.179 clock uncertainty -0.035 11.144 SLICE_X85Y140 FDCE (Recov_GFF_SLICEM_C_CLR) -0.093 11.051 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4] ------------------------------------------------------------------- required time 11.051 arrival time -6.973 ------------------------------------------------------------------- slack 4.078 Slack (MET) : 4.217ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 4.035ns (logic 0.228ns (5.651%) route 3.807ns (94.349%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.063ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.651ns = ( 10.968 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.665ns, distribution 1.668ns) Clock Net Delay (Destination): 2.253ns (routing 0.604ns, distribution 1.649ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y141 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.060 6.007 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y144 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.089 6.096 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/O net (fo=15, routed) 0.747 6.843 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X85Y141 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.253 10.968 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] SLICE_X85Y141 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/C clock pessimism 0.220 11.188 clock uncertainty -0.035 11.153 SLICE_X85Y141 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.060 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5] ------------------------------------------------------------------- required time 11.060 arrival time -6.843 ------------------------------------------------------------------- slack 4.217 Slack (MET) : 4.222ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 4.028ns (logic 0.228ns (5.660%) route 3.800ns (94.340%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.649ns = ( 10.966 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.665ns, distribution 1.668ns) Clock Net Delay (Destination): 2.251ns (routing 0.604ns, distribution 1.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y141 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.060 6.007 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y144 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.089 6.096 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/O net (fo=15, routed) 0.740 6.836 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X85Y141 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.251 10.966 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] SLICE_X85Y141 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/C clock pessimism 0.220 11.186 clock uncertainty -0.035 11.151 SLICE_X85Y141 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.058 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1] ------------------------------------------------------------------- required time 11.058 arrival time -6.836 ------------------------------------------------------------------- slack 4.222 Slack (MET) : 4.222ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 4.028ns (logic 0.228ns (5.660%) route 3.800ns (94.340%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.649ns = ( 10.966 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.665ns, distribution 1.668ns) Clock Net Delay (Destination): 2.251ns (routing 0.604ns, distribution 1.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y141 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.060 6.007 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y144 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.089 6.096 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/O net (fo=15, routed) 0.740 6.836 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X85Y141 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.251 10.966 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] SLICE_X85Y141 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/C clock pessimism 0.220 11.186 clock uncertainty -0.035 11.151 SLICE_X85Y141 FDCE (Recov_GFF_SLICEM_C_CLR) -0.093 11.058 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2] ------------------------------------------------------------------- required time 11.058 arrival time -6.836 ------------------------------------------------------------------- slack 4.222 Slack (MET) : 4.222ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 4.028ns (logic 0.228ns (5.660%) route 3.800ns (94.340%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.649ns = ( 10.966 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.665ns, distribution 1.668ns) Clock Net Delay (Destination): 2.251ns (routing 0.604ns, distribution 1.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y141 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.060 6.007 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y144 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.089 6.096 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/O net (fo=15, routed) 0.740 6.836 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X85Y141 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.251 10.966 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] SLICE_X85Y141 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/C clock pessimism 0.220 11.186 clock uncertainty -0.035 11.151 SLICE_X85Y141 FDCE (Recov_FFF_SLICEM_C_CLR) -0.093 11.058 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3] ------------------------------------------------------------------- required time 11.058 arrival time -6.836 ------------------------------------------------------------------- slack 4.222 Slack (MET) : 4.222ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 4.028ns (logic 0.228ns (5.660%) route 3.800ns (94.340%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.649ns = ( 10.966 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.665ns, distribution 1.668ns) Clock Net Delay (Destination): 2.251ns (routing 0.604ns, distribution 1.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y141 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.060 6.007 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y144 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.089 6.096 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/O net (fo=15, routed) 0.740 6.836 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X85Y141 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.251 10.966 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] SLICE_X85Y141 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/C clock pessimism 0.220 11.186 clock uncertainty -0.035 11.151 SLICE_X85Y141 FDCE (Recov_HFF2_SLICEM_C_CLR) -0.093 11.058 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0] ------------------------------------------------------------------- required time 11.058 arrival time -6.836 ------------------------------------------------------------------- slack 4.222 Slack (MET) : 4.222ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 4.028ns (logic 0.228ns (5.660%) route 3.800ns (94.340%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.649ns = ( 10.966 - 8.317 ) Source Clock Delay (SCD): 2.808ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.333ns (routing 0.665ns, distribution 1.668ns) Clock Net Delay (Destination): 2.251ns (routing 0.604ns, distribution 1.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.333 2.808 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y141 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.947 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.060 6.007 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y144 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.089 6.096 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/O net (fo=15, routed) 0.740 6.836 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X85Y141 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.251 10.966 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] SLICE_X85Y141 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]/C clock pessimism 0.220 11.186 clock uncertainty -0.035 11.151 SLICE_X85Y141 FDCE (Recov_GFF2_SLICEM_C_CLR) -0.093 11.058 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5] ------------------------------------------------------------------- required time 11.058 arrival time -6.836 ------------------------------------------------------------------- slack 4.222 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.183ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.222ns (logic 0.049ns (22.072%) route 0.173ns (77.928%)) Logic Levels: 0 Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.319ns Source Clock Delay (SCD): 1.100ns Clock Pessimism Removal (CPR): 0.185ns Clock Net Delay (Source): 0.982ns (routing 0.300ns, distribution 0.682ns) Clock Net Delay (Destination): 1.154ns (routing 0.344ns, distribution 0.810ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.982 1.100 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X84Y139 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y139 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.149 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.173 1.322 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X84Y141 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.154 1.319 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X84Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.185 1.134 SLICE_X84Y141 FDCE (Remov_DFF2_SLICEL_C_CLR) 0.005 1.139 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -1.139 arrival time 1.322 ------------------------------------------------------------------- slack 0.183 Slack (MET) : 0.204ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.311ns (logic 0.049ns (15.756%) route 0.262ns (84.244%)) Logic Levels: 0 Clock Path Skew: 0.102ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.356ns Source Clock Delay (SCD): 1.100ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.982ns (routing 0.300ns, distribution 0.682ns) Clock Net Delay (Destination): 1.191ns (routing 0.344ns, distribution 0.847ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.982 1.100 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X84Y139 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y139 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.149 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.262 1.411 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X79Y139 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[20]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.191 1.356 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X79Y139 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[20]/C clock pessimism -0.154 1.202 SLICE_X79Y139 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.207 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[20] ------------------------------------------------------------------- required time -1.207 arrival time 1.411 ------------------------------------------------------------------- slack 0.204 Slack (MET) : 0.204ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[21]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.311ns (logic 0.049ns (15.756%) route 0.262ns (84.244%)) Logic Levels: 0 Clock Path Skew: 0.102ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.356ns Source Clock Delay (SCD): 1.100ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.982ns (routing 0.300ns, distribution 0.682ns) Clock Net Delay (Destination): 1.191ns (routing 0.344ns, distribution 0.847ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.982 1.100 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X84Y139 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y139 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.149 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.262 1.411 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X79Y139 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[21]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.191 1.356 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X79Y139 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[21]/C clock pessimism -0.154 1.202 SLICE_X79Y139 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.207 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[21] ------------------------------------------------------------------- required time -1.207 arrival time 1.411 ------------------------------------------------------------------- slack 0.204 Slack (MET) : 0.204ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[22]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.311ns (logic 0.049ns (15.756%) route 0.262ns (84.244%)) Logic Levels: 0 Clock Path Skew: 0.102ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.356ns Source Clock Delay (SCD): 1.100ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.982ns (routing 0.300ns, distribution 0.682ns) Clock Net Delay (Destination): 1.191ns (routing 0.344ns, distribution 0.847ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.982 1.100 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X84Y139 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y139 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.149 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.262 1.411 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X79Y139 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[22]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.191 1.356 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X79Y139 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[22]/C clock pessimism -0.154 1.202 SLICE_X79Y139 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.207 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[22] ------------------------------------------------------------------- required time -1.207 arrival time 1.411 ------------------------------------------------------------------- slack 0.204 Slack (MET) : 0.204ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[21]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.311ns (logic 0.049ns (15.756%) route 0.262ns (84.244%)) Logic Levels: 0 Clock Path Skew: 0.102ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.356ns Source Clock Delay (SCD): 1.100ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.982ns (routing 0.300ns, distribution 0.682ns) Clock Net Delay (Destination): 1.191ns (routing 0.344ns, distribution 0.847ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.982 1.100 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X84Y139 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y139 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.149 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.262 1.411 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X79Y139 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[21]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.191 1.356 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X79Y139 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[21]/C clock pessimism -0.154 1.202 SLICE_X79Y139 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.207 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[21] ------------------------------------------------------------------- required time -1.207 arrival time 1.411 ------------------------------------------------------------------- slack 0.204 Slack (MET) : 0.204ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[22]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.311ns (logic 0.049ns (15.756%) route 0.262ns (84.244%)) Logic Levels: 0 Clock Path Skew: 0.102ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.356ns Source Clock Delay (SCD): 1.100ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.982ns (routing 0.300ns, distribution 0.682ns) Clock Net Delay (Destination): 1.191ns (routing 0.344ns, distribution 0.847ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.982 1.100 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X84Y139 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y139 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.149 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.262 1.411 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X79Y139 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[22]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.191 1.356 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X79Y139 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[22]/C clock pessimism -0.154 1.202 SLICE_X79Y139 FDCE (Remov_GFF2_SLICEM_C_CLR) 0.005 1.207 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[22] ------------------------------------------------------------------- required time -1.207 arrival time 1.411 ------------------------------------------------------------------- slack 0.204 Slack (MET) : 0.204ns (arrival time - required time) Source: SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[40]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.288ns (logic 0.048ns (16.667%) route 0.240ns (83.333%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.342ns Source Clock Delay (SCD): 1.109ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.991ns (routing 0.300ns, distribution 0.691ns) Clock Net Delay (Destination): 1.177ns (routing 0.344ns, distribution 0.833ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.991 1.109 SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X76Y140 FDPE r SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X76Y140 FDPE (Prop_GFF2_SLICEM_C_Q) 0.048 1.157 f SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.240 1.397 SFP_GEN[5].ngCCM_gbt/sync_m_reg[3][0] SLICE_X74Y141 FDCE f SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[40]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.177 1.342 SFP_GEN[5].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X74Y141 FDCE r SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[40]/C clock pessimism -0.154 1.188 SLICE_X74Y141 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.193 SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[40] ------------------------------------------------------------------- required time -1.193 arrival time 1.397 ------------------------------------------------------------------- slack 0.204 Slack (MET) : 0.204ns (arrival time - required time) Source: SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[42]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.288ns (logic 0.048ns (16.667%) route 0.240ns (83.333%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.342ns Source Clock Delay (SCD): 1.109ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.991ns (routing 0.300ns, distribution 0.691ns) Clock Net Delay (Destination): 1.177ns (routing 0.344ns, distribution 0.833ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.991 1.109 SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X76Y140 FDPE r SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X76Y140 FDPE (Prop_GFF2_SLICEM_C_Q) 0.048 1.157 f SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.240 1.397 SFP_GEN[5].ngCCM_gbt/sync_m_reg[3][0] SLICE_X74Y141 FDCE f SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[42]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.177 1.342 SFP_GEN[5].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X74Y141 FDCE r SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[42]/C clock pessimism -0.154 1.188 SLICE_X74Y141 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 1.193 SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[42] ------------------------------------------------------------------- required time -1.193 arrival time 1.397 ------------------------------------------------------------------- slack 0.204 Slack (MET) : 0.205ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[60]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.314ns (logic 0.049ns (15.605%) route 0.265ns (84.395%)) Logic Levels: 0 Clock Path Skew: 0.104ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.358ns Source Clock Delay (SCD): 1.100ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.982ns (routing 0.300ns, distribution 0.682ns) Clock Net Delay (Destination): 1.193ns (routing 0.344ns, distribution 0.849ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.982 1.100 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X84Y139 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y139 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.149 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.265 1.414 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X79Y139 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[60]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.193 1.358 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X79Y139 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[60]/C clock pessimism -0.154 1.204 SLICE_X79Y139 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.209 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[60] ------------------------------------------------------------------- required time -1.209 arrival time 1.414 ------------------------------------------------------------------- slack 0.205 Slack (MET) : 0.205ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[78]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.314ns (logic 0.049ns (15.605%) route 0.265ns (84.395%)) Logic Levels: 0 Clock Path Skew: 0.104ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.358ns Source Clock Delay (SCD): 1.100ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.982ns (routing 0.300ns, distribution 0.682ns) Clock Net Delay (Destination): 1.193ns (routing 0.344ns, distribution 0.849ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.982 1.100 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X84Y139 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y139 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.149 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.265 1.414 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X79Y139 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[78]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y69 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.193 1.358 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X79Y139 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[78]/C clock pessimism -0.154 1.204 SLICE_X79Y139 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 1.209 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[78] ------------------------------------------------------------------- required time -1.209 arrival time 1.414 ------------------------------------------------------------------- slack 0.205 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_8 To Clock: gtwiz_userclk_rx_srcclk_out[0]_8 Setup : 0 Failing Endpoints, Worst Slack 5.154ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.172ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.154ns (required time - arrival time) Source: SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 2.560ns (logic 0.139ns (5.430%) route 2.421ns (94.570%)) Logic Levels: 0 Clock Path Skew: -0.475ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.279ns = ( 10.596 - 8.317 ) Source Clock Delay (SCD): 2.979ns Clock Pessimism Removal (CPR): 0.225ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.504ns (routing 0.664ns, distribution 1.840ns) Clock Net Delay (Destination): 1.881ns (routing 0.602ns, distribution 1.279ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.504 2.979 SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y140 FDPE r SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y140 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.118 f SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.421 5.539 SFP_GEN[6].ngCCM_gbt/sync_m_reg[3][0] SLICE_X99Y124 FDCE f SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.881 10.596 SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X99Y124 FDCE r SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[52]/C clock pessimism 0.225 10.821 clock uncertainty -0.035 10.786 SLICE_X99Y124 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.693 SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[52] ------------------------------------------------------------------- required time 10.693 arrival time -5.539 ------------------------------------------------------------------- slack 5.154 Slack (MET) : 5.154ns (required time - arrival time) Source: SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[54]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 2.560ns (logic 0.139ns (5.430%) route 2.421ns (94.570%)) Logic Levels: 0 Clock Path Skew: -0.475ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.279ns = ( 10.596 - 8.317 ) Source Clock Delay (SCD): 2.979ns Clock Pessimism Removal (CPR): 0.225ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.504ns (routing 0.664ns, distribution 1.840ns) Clock Net Delay (Destination): 1.881ns (routing 0.602ns, distribution 1.279ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.504 2.979 SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y140 FDPE r SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y140 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.118 f SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.421 5.539 SFP_GEN[6].ngCCM_gbt/sync_m_reg[3][0] SLICE_X99Y124 FDCE f SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[54]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.881 10.596 SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X99Y124 FDCE r SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[54]/C clock pessimism 0.225 10.821 clock uncertainty -0.035 10.786 SLICE_X99Y124 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 10.693 SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[54] ------------------------------------------------------------------- required time 10.693 arrival time -5.539 ------------------------------------------------------------------- slack 5.154 Slack (MET) : 5.154ns (required time - arrival time) Source: SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[60]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 2.560ns (logic 0.139ns (5.430%) route 2.421ns (94.570%)) Logic Levels: 0 Clock Path Skew: -0.475ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.279ns = ( 10.596 - 8.317 ) Source Clock Delay (SCD): 2.979ns Clock Pessimism Removal (CPR): 0.225ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.504ns (routing 0.664ns, distribution 1.840ns) Clock Net Delay (Destination): 1.881ns (routing 0.602ns, distribution 1.279ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.504 2.979 SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y140 FDPE r SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y140 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.118 f SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.421 5.539 SFP_GEN[6].ngCCM_gbt/sync_m_reg[3][0] SLICE_X99Y124 FDCE f SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[60]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.881 10.596 SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X99Y124 FDCE r SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[60]/C clock pessimism 0.225 10.821 clock uncertainty -0.035 10.786 SLICE_X99Y124 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.693 SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[60] ------------------------------------------------------------------- required time 10.693 arrival time -5.539 ------------------------------------------------------------------- slack 5.154 Slack (MET) : 5.154ns (required time - arrival time) Source: SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[62]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 2.560ns (logic 0.139ns (5.430%) route 2.421ns (94.570%)) Logic Levels: 0 Clock Path Skew: -0.475ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.279ns = ( 10.596 - 8.317 ) Source Clock Delay (SCD): 2.979ns Clock Pessimism Removal (CPR): 0.225ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.504ns (routing 0.664ns, distribution 1.840ns) Clock Net Delay (Destination): 1.881ns (routing 0.602ns, distribution 1.279ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.504 2.979 SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y140 FDPE r SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y140 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.118 f SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.421 5.539 SFP_GEN[6].ngCCM_gbt/sync_m_reg[3][0] SLICE_X99Y124 FDCE f SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[62]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.881 10.596 SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X99Y124 FDCE r SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[62]/C clock pessimism 0.225 10.821 clock uncertainty -0.035 10.786 SLICE_X99Y124 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 10.693 SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[62] ------------------------------------------------------------------- required time 10.693 arrival time -5.539 ------------------------------------------------------------------- slack 5.154 Slack (MET) : 5.154ns (required time - arrival time) Source: SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[64]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 2.560ns (logic 0.139ns (5.430%) route 2.421ns (94.570%)) Logic Levels: 0 Clock Path Skew: -0.475ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.279ns = ( 10.596 - 8.317 ) Source Clock Delay (SCD): 2.979ns Clock Pessimism Removal (CPR): 0.225ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.504ns (routing 0.664ns, distribution 1.840ns) Clock Net Delay (Destination): 1.881ns (routing 0.602ns, distribution 1.279ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.504 2.979 SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y140 FDPE r SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y140 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.118 f SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.421 5.539 SFP_GEN[6].ngCCM_gbt/sync_m_reg[3][0] SLICE_X99Y124 FDCE f SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[64]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.881 10.596 SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X99Y124 FDCE r SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[64]/C clock pessimism 0.225 10.821 clock uncertainty -0.035 10.786 SLICE_X99Y124 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.693 SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[64] ------------------------------------------------------------------- required time 10.693 arrival time -5.539 ------------------------------------------------------------------- slack 5.154 Slack (MET) : 5.154ns (required time - arrival time) Source: SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[66]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 2.560ns (logic 0.139ns (5.430%) route 2.421ns (94.570%)) Logic Levels: 0 Clock Path Skew: -0.475ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.279ns = ( 10.596 - 8.317 ) Source Clock Delay (SCD): 2.979ns Clock Pessimism Removal (CPR): 0.225ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.504ns (routing 0.664ns, distribution 1.840ns) Clock Net Delay (Destination): 1.881ns (routing 0.602ns, distribution 1.279ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.504 2.979 SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y140 FDPE r SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y140 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.118 f SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.421 5.539 SFP_GEN[6].ngCCM_gbt/sync_m_reg[3][0] SLICE_X99Y124 FDCE f SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[66]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.881 10.596 SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X99Y124 FDCE r SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[66]/C clock pessimism 0.225 10.821 clock uncertainty -0.035 10.786 SLICE_X99Y124 FDCE (Recov_BFF2_SLICEL_C_CLR) -0.093 10.693 SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[66] ------------------------------------------------------------------- required time 10.693 arrival time -5.539 ------------------------------------------------------------------- slack 5.154 Slack (MET) : 5.154ns (required time - arrival time) Source: SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[68]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 2.560ns (logic 0.139ns (5.430%) route 2.421ns (94.570%)) Logic Levels: 0 Clock Path Skew: -0.475ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.279ns = ( 10.596 - 8.317 ) Source Clock Delay (SCD): 2.979ns Clock Pessimism Removal (CPR): 0.225ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.504ns (routing 0.664ns, distribution 1.840ns) Clock Net Delay (Destination): 1.881ns (routing 0.602ns, distribution 1.279ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.504 2.979 SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y140 FDPE r SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y140 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.118 f SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.421 5.539 SFP_GEN[6].ngCCM_gbt/sync_m_reg[3][0] SLICE_X99Y124 FDCE f SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[68]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.881 10.596 SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X99Y124 FDCE r SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[68]/C clock pessimism 0.225 10.821 clock uncertainty -0.035 10.786 SLICE_X99Y124 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.693 SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[68] ------------------------------------------------------------------- required time 10.693 arrival time -5.539 ------------------------------------------------------------------- slack 5.154 Slack (MET) : 5.154ns (required time - arrival time) Source: SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[70]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 2.560ns (logic 0.139ns (5.430%) route 2.421ns (94.570%)) Logic Levels: 0 Clock Path Skew: -0.475ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.279ns = ( 10.596 - 8.317 ) Source Clock Delay (SCD): 2.979ns Clock Pessimism Removal (CPR): 0.225ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.504ns (routing 0.664ns, distribution 1.840ns) Clock Net Delay (Destination): 1.881ns (routing 0.602ns, distribution 1.279ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.504 2.979 SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y140 FDPE r SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y140 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.118 f SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.421 5.539 SFP_GEN[6].ngCCM_gbt/sync_m_reg[3][0] SLICE_X99Y124 FDCE f SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[70]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.881 10.596 SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X99Y124 FDCE r SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[70]/C clock pessimism 0.225 10.821 clock uncertainty -0.035 10.786 SLICE_X99Y124 FDCE (Recov_AFF2_SLICEL_C_CLR) -0.093 10.693 SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[70] ------------------------------------------------------------------- required time 10.693 arrival time -5.539 ------------------------------------------------------------------- slack 5.154 Slack (MET) : 5.306ns (required time - arrival time) Source: SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[56]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 2.415ns (logic 0.139ns (5.756%) route 2.276ns (94.244%)) Logic Levels: 0 Clock Path Skew: -0.468ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.286ns = ( 10.603 - 8.317 ) Source Clock Delay (SCD): 2.979ns Clock Pessimism Removal (CPR): 0.225ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.504ns (routing 0.664ns, distribution 1.840ns) Clock Net Delay (Destination): 1.888ns (routing 0.602ns, distribution 1.286ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.504 2.979 SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y140 FDPE r SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y140 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.118 f SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.276 5.394 SFP_GEN[6].ngCCM_gbt/sync_m_reg[3][0] SLICE_X99Y127 FDCE f SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[56]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.888 10.603 SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X99Y127 FDCE r SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[56]/C clock pessimism 0.225 10.828 clock uncertainty -0.035 10.793 SLICE_X99Y127 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.700 SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[56] ------------------------------------------------------------------- required time 10.700 arrival time -5.394 ------------------------------------------------------------------- slack 5.306 Slack (MET) : 5.306ns (required time - arrival time) Source: SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[58]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 2.415ns (logic 0.139ns (5.756%) route 2.276ns (94.244%)) Logic Levels: 0 Clock Path Skew: -0.468ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.286ns = ( 10.603 - 8.317 ) Source Clock Delay (SCD): 2.979ns Clock Pessimism Removal (CPR): 0.225ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.504ns (routing 0.664ns, distribution 1.840ns) Clock Net Delay (Destination): 1.888ns (routing 0.602ns, distribution 1.286ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.504 2.979 SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y140 FDPE r SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y140 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.118 f SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.276 5.394 SFP_GEN[6].ngCCM_gbt/sync_m_reg[3][0] SLICE_X99Y127 FDCE f SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[58]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.888 10.603 SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X99Y127 FDCE r SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[58]/C clock pessimism 0.225 10.828 clock uncertainty -0.035 10.793 SLICE_X99Y127 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 10.700 SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[58] ------------------------------------------------------------------- required time 10.700 arrival time -5.394 ------------------------------------------------------------------- slack 5.306 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.172ns (arrival time - required time) Source: SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[6].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.048ns (18.462%) route 0.212ns (81.538%)) Logic Levels: 0 Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.299ns Source Clock Delay (SCD): 1.065ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.947ns (routing 0.301ns, distribution 0.646ns) Clock Net Delay (Destination): 1.134ns (routing 0.342ns, distribution 0.792ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.947 1.065 SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y140 FDPE r SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y140 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.113 f SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.212 1.325 SFP_GEN[6].ngCCM_gbt/sync_m_reg[3][0] SLICE_X92Y141 FDCE f SFP_GEN[6].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.134 1.299 SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X92Y141 FDCE r SFP_GEN[6].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.151 1.148 SLICE_X92Y141 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.153 SFP_GEN[6].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.153 arrival time 1.325 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.183ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.276ns (logic 0.049ns (17.754%) route 0.227ns (82.246%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.153ns Source Clock Delay (SCD): 0.933ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.815ns (routing 0.301ns, distribution 0.514ns) Clock Net Delay (Destination): 0.988ns (routing 0.342ns, distribution 0.646ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.815 0.933 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X102Y142 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y142 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 0.982 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.227 1.209 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X97Y142 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.988 1.153 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X97Y142 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C clock pessimism -0.132 1.021 SLICE_X97Y142 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.026 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4] ------------------------------------------------------------------- required time -1.026 arrival time 1.209 ------------------------------------------------------------------- slack 0.183 Slack (MET) : 0.192ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[93]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.049ns (19.141%) route 0.207ns (80.859%)) Logic Levels: 0 Clock Path Skew: 0.059ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.125ns Source Clock Delay (SCD): 0.934ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.816ns (routing 0.301ns, distribution 0.515ns) Clock Net Delay (Destination): 0.960ns (routing 0.342ns, distribution 0.618ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.816 0.934 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X102Y143 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y143 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 0.983 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.207 1.190 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X103Y141 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[93]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.960 1.125 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X103Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[93]/C clock pessimism -0.132 0.993 SLICE_X103Y141 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 0.998 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[93] ------------------------------------------------------------------- required time -0.998 arrival time 1.190 ------------------------------------------------------------------- slack 0.192 Slack (MET) : 0.192ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[93]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.049ns (19.141%) route 0.207ns (80.859%)) Logic Levels: 0 Clock Path Skew: 0.059ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.125ns Source Clock Delay (SCD): 0.934ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.816ns (routing 0.301ns, distribution 0.515ns) Clock Net Delay (Destination): 0.960ns (routing 0.342ns, distribution 0.618ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.816 0.934 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X102Y143 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y143 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 0.983 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.207 1.190 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X103Y141 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[93]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.960 1.125 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X103Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[93]/C clock pessimism -0.132 0.993 SLICE_X103Y141 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 0.998 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[93] ------------------------------------------------------------------- required time -0.998 arrival time 1.190 ------------------------------------------------------------------- slack 0.192 Slack (MET) : 0.217ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.049ns (18.148%) route 0.221ns (81.852%)) Logic Levels: 0 Clock Path Skew: 0.048ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.144ns Source Clock Delay (SCD): 0.933ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 0.815ns (routing 0.301ns, distribution 0.514ns) Clock Net Delay (Destination): 0.979ns (routing 0.342ns, distribution 0.637ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.815 0.933 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X102Y142 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y142 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 0.982 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.221 1.203 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X102Y136 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.979 1.144 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/CLK SLICE_X102Y136 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/READY_O_reg/C clock pessimism -0.163 0.981 SLICE_X102Y136 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 0.986 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/READY_O_reg ------------------------------------------------------------------- required time -0.986 arrival time 1.203 ------------------------------------------------------------------- slack 0.217 Slack (MET) : 0.225ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.296ns (logic 0.049ns (16.554%) route 0.247ns (83.446%)) Logic Levels: 0 Clock Path Skew: 0.066ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.131ns Source Clock Delay (SCD): 0.933ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.815ns (routing 0.301ns, distribution 0.514ns) Clock Net Delay (Destination): 0.966ns (routing 0.342ns, distribution 0.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.815 0.933 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X102Y142 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y142 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 0.982 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.247 1.229 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X99Y144 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.966 1.131 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X99Y144 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C clock pessimism -0.132 0.999 SLICE_X99Y144 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.004 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time -1.004 arrival time 1.229 ------------------------------------------------------------------- slack 0.225 Slack (MET) : 0.225ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.296ns (logic 0.049ns (16.554%) route 0.247ns (83.446%)) Logic Levels: 0 Clock Path Skew: 0.066ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.131ns Source Clock Delay (SCD): 0.933ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.815ns (routing 0.301ns, distribution 0.514ns) Clock Net Delay (Destination): 0.966ns (routing 0.342ns, distribution 0.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.815 0.933 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X102Y142 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y142 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 0.982 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.247 1.229 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X99Y144 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.966 1.131 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X99Y144 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C clock pessimism -0.132 0.999 SLICE_X99Y144 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.004 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8] ------------------------------------------------------------------- required time -1.004 arrival time 1.229 ------------------------------------------------------------------- slack 0.225 Slack (MET) : 0.226ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[61]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.049ns (18.148%) route 0.221ns (81.852%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.147ns Source Clock Delay (SCD): 0.934ns Clock Pessimism Removal (CPR): 0.174ns Clock Net Delay (Source): 0.816ns (routing 0.301ns, distribution 0.515ns) Clock Net Delay (Destination): 0.982ns (routing 0.342ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.816 0.934 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X102Y143 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y143 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 0.983 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.221 1.204 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X101Y143 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[61]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.982 1.147 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X101Y143 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[61]/C clock pessimism -0.174 0.973 SLICE_X101Y143 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 0.978 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[61] ------------------------------------------------------------------- required time -0.978 arrival time 1.204 ------------------------------------------------------------------- slack 0.226 Slack (MET) : 0.226ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[63]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.049ns (18.148%) route 0.221ns (81.852%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.147ns Source Clock Delay (SCD): 0.934ns Clock Pessimism Removal (CPR): 0.174ns Clock Net Delay (Source): 0.816ns (routing 0.301ns, distribution 0.515ns) Clock Net Delay (Destination): 0.982ns (routing 0.342ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.816 0.934 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X102Y143 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y143 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 0.983 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.221 1.204 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X101Y143 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[63]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.982 1.147 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X101Y143 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[63]/C clock pessimism -0.174 0.973 SLICE_X101Y143 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 0.978 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[63] ------------------------------------------------------------------- required time -0.978 arrival time 1.204 ------------------------------------------------------------------- slack 0.226 Slack (MET) : 0.226ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[103]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.049ns (18.148%) route 0.221ns (81.852%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.147ns Source Clock Delay (SCD): 0.934ns Clock Pessimism Removal (CPR): 0.174ns Clock Net Delay (Source): 0.816ns (routing 0.301ns, distribution 0.515ns) Clock Net Delay (Destination): 0.982ns (routing 0.342ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.816 0.934 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X102Y143 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y143 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 0.983 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.221 1.204 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X101Y143 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[103]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y64 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.982 1.147 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X101Y143 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[103]/C clock pessimism -0.174 0.973 SLICE_X101Y143 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 0.978 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[103] ------------------------------------------------------------------- required time -0.978 arrival time 1.204 ------------------------------------------------------------------- slack 0.226 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_9 To Clock: gtwiz_userclk_rx_srcclk_out[0]_9 Setup : 0 Failing Endpoints, Worst Slack 4.243ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.137ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.243ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 3.977ns (logic 0.229ns (5.758%) route 3.748ns (94.242%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.669ns = ( 10.986 - 8.317 ) Source Clock Delay (SCD): 2.860ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.385ns (routing 0.683ns, distribution 1.702ns) Clock Net Delay (Destination): 2.271ns (routing 0.619ns, distribution 1.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.385 2.860 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y171 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.999 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.433 5.432 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y158 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 5.522 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/O net (fo=15, routed) 1.315 6.837 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X84Y157 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.271 10.986 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] SLICE_X84Y157 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/C clock pessimism 0.223 11.209 clock uncertainty -0.035 11.173 SLICE_X84Y157 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.080 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1] ------------------------------------------------------------------- required time 11.080 arrival time -6.837 ------------------------------------------------------------------- slack 4.243 Slack (MET) : 4.243ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 3.977ns (logic 0.229ns (5.758%) route 3.748ns (94.242%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.669ns = ( 10.986 - 8.317 ) Source Clock Delay (SCD): 2.860ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.385ns (routing 0.683ns, distribution 1.702ns) Clock Net Delay (Destination): 2.271ns (routing 0.619ns, distribution 1.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.385 2.860 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y171 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.999 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.433 5.432 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y158 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 5.522 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/O net (fo=15, routed) 1.315 6.837 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X84Y157 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.271 10.986 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] SLICE_X84Y157 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/C clock pessimism 0.223 11.209 clock uncertainty -0.035 11.173 SLICE_X84Y157 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 11.080 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3] ------------------------------------------------------------------- required time 11.080 arrival time -6.837 ------------------------------------------------------------------- slack 4.243 Slack (MET) : 4.243ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 3.977ns (logic 0.229ns (5.758%) route 3.748ns (94.242%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.669ns = ( 10.986 - 8.317 ) Source Clock Delay (SCD): 2.860ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.385ns (routing 0.683ns, distribution 1.702ns) Clock Net Delay (Destination): 2.271ns (routing 0.619ns, distribution 1.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.385 2.860 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y171 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.999 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.433 5.432 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y158 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 5.522 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/O net (fo=15, routed) 1.315 6.837 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X84Y157 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.271 10.986 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] SLICE_X84Y157 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/C clock pessimism 0.223 11.209 clock uncertainty -0.035 11.173 SLICE_X84Y157 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 11.080 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5] ------------------------------------------------------------------- required time 11.080 arrival time -6.837 ------------------------------------------------------------------- slack 4.243 Slack (MET) : 4.251ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 3.967ns (logic 0.229ns (5.773%) route 3.738ns (94.227%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.029ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.667ns = ( 10.984 - 8.317 ) Source Clock Delay (SCD): 2.860ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.385ns (routing 0.683ns, distribution 1.702ns) Clock Net Delay (Destination): 2.269ns (routing 0.619ns, distribution 1.650ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.385 2.860 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y171 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.999 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.433 5.432 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y158 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 5.522 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/O net (fo=15, routed) 1.305 6.827 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X84Y157 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.269 10.984 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] SLICE_X84Y157 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/C clock pessimism 0.223 11.207 clock uncertainty -0.035 11.171 SLICE_X84Y157 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.078 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0] ------------------------------------------------------------------- required time 11.078 arrival time -6.827 ------------------------------------------------------------------- slack 4.251 Slack (MET) : 4.251ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 3.967ns (logic 0.229ns (5.773%) route 3.738ns (94.227%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.029ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.667ns = ( 10.984 - 8.317 ) Source Clock Delay (SCD): 2.860ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.385ns (routing 0.683ns, distribution 1.702ns) Clock Net Delay (Destination): 2.269ns (routing 0.619ns, distribution 1.650ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.385 2.860 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y171 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.999 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.433 5.432 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y158 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 5.522 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/O net (fo=15, routed) 1.305 6.827 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X84Y157 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.269 10.984 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] SLICE_X84Y157 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/C clock pessimism 0.223 11.207 clock uncertainty -0.035 11.171 SLICE_X84Y157 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 11.078 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2] ------------------------------------------------------------------- required time 11.078 arrival time -6.827 ------------------------------------------------------------------- slack 4.251 Slack (MET) : 4.251ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 3.967ns (logic 0.229ns (5.773%) route 3.738ns (94.227%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.029ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.667ns = ( 10.984 - 8.317 ) Source Clock Delay (SCD): 2.860ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.385ns (routing 0.683ns, distribution 1.702ns) Clock Net Delay (Destination): 2.269ns (routing 0.619ns, distribution 1.650ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.385 2.860 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y171 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.999 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.433 5.432 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y158 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 5.522 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/O net (fo=15, routed) 1.305 6.827 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X84Y157 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.269 10.984 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] SLICE_X84Y157 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/C clock pessimism 0.223 11.207 clock uncertainty -0.035 11.171 SLICE_X84Y157 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 11.078 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4] ------------------------------------------------------------------- required time 11.078 arrival time -6.827 ------------------------------------------------------------------- slack 4.251 Slack (MET) : 4.678ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 3.540ns (logic 0.229ns (6.469%) route 3.311ns (93.531%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.029ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.667ns = ( 10.984 - 8.317 ) Source Clock Delay (SCD): 2.860ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.385ns (routing 0.683ns, distribution 1.702ns) Clock Net Delay (Destination): 2.269ns (routing 0.619ns, distribution 1.650ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.385 2.860 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y171 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.999 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.433 5.432 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y158 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 5.522 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/O net (fo=15, routed) 0.878 6.400 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X83Y156 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.269 10.984 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] SLICE_X83Y156 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/C clock pessimism 0.223 11.207 clock uncertainty -0.035 11.171 SLICE_X83Y156 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.078 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1] ------------------------------------------------------------------- required time 11.078 arrival time -6.400 ------------------------------------------------------------------- slack 4.678 Slack (MET) : 4.678ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 3.540ns (logic 0.229ns (6.469%) route 3.311ns (93.531%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.029ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.667ns = ( 10.984 - 8.317 ) Source Clock Delay (SCD): 2.860ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.385ns (routing 0.683ns, distribution 1.702ns) Clock Net Delay (Destination): 2.269ns (routing 0.619ns, distribution 1.650ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.385 2.860 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y171 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.999 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.433 5.432 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y158 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 5.522 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/O net (fo=15, routed) 0.878 6.400 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X83Y156 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.269 10.984 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] SLICE_X83Y156 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/C clock pessimism 0.223 11.207 clock uncertainty -0.035 11.171 SLICE_X83Y156 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 11.078 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2] ------------------------------------------------------------------- required time 11.078 arrival time -6.400 ------------------------------------------------------------------- slack 4.678 Slack (MET) : 4.678ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 3.540ns (logic 0.229ns (6.469%) route 3.311ns (93.531%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.029ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.667ns = ( 10.984 - 8.317 ) Source Clock Delay (SCD): 2.860ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.385ns (routing 0.683ns, distribution 1.702ns) Clock Net Delay (Destination): 2.269ns (routing 0.619ns, distribution 1.650ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.385 2.860 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y171 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.999 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.433 5.432 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y158 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 5.522 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/O net (fo=15, routed) 0.878 6.400 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X83Y156 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.269 10.984 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] SLICE_X83Y156 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/C clock pessimism 0.223 11.207 clock uncertainty -0.035 11.171 SLICE_X83Y156 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 11.078 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4] ------------------------------------------------------------------- required time 11.078 arrival time -6.400 ------------------------------------------------------------------- slack 4.678 Slack (MET) : 4.683ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 3.533ns (logic 0.229ns (6.482%) route 3.304ns (93.518%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.028ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.665ns = ( 10.982 - 8.317 ) Source Clock Delay (SCD): 2.860ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.385ns (routing 0.683ns, distribution 1.702ns) Clock Net Delay (Destination): 2.267ns (routing 0.619ns, distribution 1.648ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.385 2.860 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y171 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.999 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.433 5.432 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X95Y158 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 5.522 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/O net (fo=15, routed) 0.871 6.393 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X83Y156 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.267 10.982 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] SLICE_X83Y156 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/C clock pessimism 0.223 11.205 clock uncertainty -0.035 11.169 SLICE_X83Y156 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 11.076 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0] ------------------------------------------------------------------- required time 11.076 arrival time -6.393 ------------------------------------------------------------------- slack 4.683 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.137ns (arrival time - required time) Source: SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.215ns (logic 0.048ns (22.326%) route 0.167ns (77.674%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.354ns Source Clock Delay (SCD): 1.125ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.007ns (routing 0.306ns, distribution 0.701ns) Clock Net Delay (Destination): 1.189ns (routing 0.352ns, distribution 0.837ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.125 SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y153 FDPE r SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X77Y153 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.173 f SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.167 1.340 SFP_GEN[7].ngCCM_gbt/sync_m_reg[3][0] SLICE_X75Y153 FDCE f SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.189 1.354 SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X75Y153 FDCE r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[0]/C clock pessimism -0.156 1.198 SLICE_X75Y153 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.203 SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[0] ------------------------------------------------------------------- required time -1.203 arrival time 1.340 ------------------------------------------------------------------- slack 0.137 Slack (MET) : 0.137ns (arrival time - required time) Source: SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.215ns (logic 0.048ns (22.326%) route 0.167ns (77.674%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.354ns Source Clock Delay (SCD): 1.125ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.007ns (routing 0.306ns, distribution 0.701ns) Clock Net Delay (Destination): 1.189ns (routing 0.352ns, distribution 0.837ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.125 SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y153 FDPE r SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X77Y153 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.173 f SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.167 1.340 SFP_GEN[7].ngCCM_gbt/sync_m_reg[3][0] SLICE_X75Y153 FDCE f SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.189 1.354 SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X75Y153 FDCE r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[2]/C clock pessimism -0.156 1.198 SLICE_X75Y153 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 1.203 SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[2] ------------------------------------------------------------------- required time -1.203 arrival time 1.340 ------------------------------------------------------------------- slack 0.137 Slack (MET) : 0.137ns (arrival time - required time) Source: SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[4]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.215ns (logic 0.048ns (22.326%) route 0.167ns (77.674%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.354ns Source Clock Delay (SCD): 1.125ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.007ns (routing 0.306ns, distribution 0.701ns) Clock Net Delay (Destination): 1.189ns (routing 0.352ns, distribution 0.837ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.125 SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y153 FDPE r SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X77Y153 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.173 f SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.167 1.340 SFP_GEN[7].ngCCM_gbt/sync_m_reg[3][0] SLICE_X75Y153 FDCE f SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.189 1.354 SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X75Y153 FDCE r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[4]/C clock pessimism -0.156 1.198 SLICE_X75Y153 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 1.203 SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[4] ------------------------------------------------------------------- required time -1.203 arrival time 1.340 ------------------------------------------------------------------- slack 0.137 Slack (MET) : 0.137ns (arrival time - required time) Source: SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[6]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.215ns (logic 0.048ns (22.326%) route 0.167ns (77.674%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.354ns Source Clock Delay (SCD): 1.125ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.007ns (routing 0.306ns, distribution 0.701ns) Clock Net Delay (Destination): 1.189ns (routing 0.352ns, distribution 0.837ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.125 SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y153 FDPE r SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X77Y153 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.173 f SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.167 1.340 SFP_GEN[7].ngCCM_gbt/sync_m_reg[3][0] SLICE_X75Y153 FDCE f SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.189 1.354 SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X75Y153 FDCE r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[6]/C clock pessimism -0.156 1.198 SLICE_X75Y153 FDCE (Remov_GFF2_SLICEL_C_CLR) 0.005 1.203 SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[6] ------------------------------------------------------------------- required time -1.203 arrival time 1.340 ------------------------------------------------------------------- slack 0.137 Slack (MET) : 0.150ns (arrival time - required time) Source: SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[40]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.233ns (logic 0.048ns (20.601%) route 0.185ns (79.399%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.125ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.007ns (routing 0.306ns, distribution 0.701ns) Clock Net Delay (Destination): 1.194ns (routing 0.352ns, distribution 0.842ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.125 SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y153 FDPE r SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X77Y153 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.173 f SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.185 1.358 SFP_GEN[7].ngCCM_gbt/sync_m_reg[3][0] SLICE_X76Y154 FDCE f SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[40]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.194 1.359 SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X76Y154 FDCE r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[40]/C clock pessimism -0.156 1.203 SLICE_X76Y154 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.208 SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[40] ------------------------------------------------------------------- required time -1.208 arrival time 1.358 ------------------------------------------------------------------- slack 0.150 Slack (MET) : 0.150ns (arrival time - required time) Source: SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[42]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.233ns (logic 0.048ns (20.601%) route 0.185ns (79.399%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.125ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.007ns (routing 0.306ns, distribution 0.701ns) Clock Net Delay (Destination): 1.194ns (routing 0.352ns, distribution 0.842ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.125 SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y153 FDPE r SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X77Y153 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.173 f SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.185 1.358 SFP_GEN[7].ngCCM_gbt/sync_m_reg[3][0] SLICE_X76Y154 FDCE f SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[42]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.194 1.359 SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X76Y154 FDCE r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[42]/C clock pessimism -0.156 1.203 SLICE_X76Y154 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 1.208 SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[42] ------------------------------------------------------------------- required time -1.208 arrival time 1.358 ------------------------------------------------------------------- slack 0.150 Slack (MET) : 0.154ns (arrival time - required time) Source: SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.239ns (logic 0.048ns (20.084%) route 0.191ns (79.916%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.361ns Source Clock Delay (SCD): 1.125ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.007ns (routing 0.306ns, distribution 0.701ns) Clock Net Delay (Destination): 1.196ns (routing 0.352ns, distribution 0.844ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.125 SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y153 FDPE r SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X77Y153 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.173 f SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.191 1.364 SFP_GEN[7].ngCCM_gbt/sync_m_reg[3][0] SLICE_X76Y155 FDCE f SFP_GEN[7].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.196 1.361 SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X76Y155 FDCE r SFP_GEN[7].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.156 1.205 SLICE_X76Y155 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.210 SFP_GEN[7].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.210 arrival time 1.364 ------------------------------------------------------------------- slack 0.154 Slack (MET) : 0.208ns (arrival time - required time) Source: SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.285ns (logic 0.048ns (16.842%) route 0.237ns (83.158%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.353ns Source Clock Delay (SCD): 1.125ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.007ns (routing 0.306ns, distribution 0.701ns) Clock Net Delay (Destination): 1.188ns (routing 0.352ns, distribution 0.836ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.125 SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y153 FDPE r SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X77Y153 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.173 f SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.237 1.410 SFP_GEN[7].ngCCM_gbt/sync_m_reg[3][0] SLICE_X79Y158 FDCE f SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.188 1.353 SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X79Y158 FDCE r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[16]/C clock pessimism -0.156 1.197 SLICE_X79Y158 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.202 SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[16] ------------------------------------------------------------------- required time -1.202 arrival time 1.410 ------------------------------------------------------------------- slack 0.208 Slack (MET) : 0.208ns (arrival time - required time) Source: SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.285ns (logic 0.048ns (16.842%) route 0.237ns (83.158%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.353ns Source Clock Delay (SCD): 1.125ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.007ns (routing 0.306ns, distribution 0.701ns) Clock Net Delay (Destination): 1.188ns (routing 0.352ns, distribution 0.836ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.125 SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y153 FDPE r SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X77Y153 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.173 f SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.237 1.410 SFP_GEN[7].ngCCM_gbt/sync_m_reg[3][0] SLICE_X79Y158 FDCE f SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.188 1.353 SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X79Y158 FDCE r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[18]/C clock pessimism -0.156 1.197 SLICE_X79Y158 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 1.202 SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[18] ------------------------------------------------------------------- required time -1.202 arrival time 1.410 ------------------------------------------------------------------- slack 0.208 Slack (MET) : 0.208ns (arrival time - required time) Source: SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.285ns (logic 0.048ns (16.842%) route 0.237ns (83.158%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.353ns Source Clock Delay (SCD): 1.125ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.007ns (routing 0.306ns, distribution 0.701ns) Clock Net Delay (Destination): 1.188ns (routing 0.352ns, distribution 0.836ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.125 SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y153 FDPE r SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X77Y153 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.173 f SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.237 1.410 SFP_GEN[7].ngCCM_gbt/sync_m_reg[3][0] SLICE_X79Y158 FDCE f SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y67 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.188 1.353 SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X79Y158 FDCE r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[19]/C clock pessimism -0.156 1.197 SLICE_X79Y158 FDCE (Remov_BFF_SLICEM_C_CLR) 0.005 1.202 SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[19] ------------------------------------------------------------------- required time -1.202 arrival time 1.410 ------------------------------------------------------------------- slack 0.208 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: ipb_clk To Clock: ipb_clk Setup : 0 Failing Endpoints, Worst Slack 29.209ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.772ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 29.209ns (required time - arrival time) Source: i_pwrup_rst/CLK (rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: rst_reg/PRE (recovery check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 2.551ns (logic 0.779ns (30.537%) route 1.772ns (69.463%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.062ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.288ns = ( 35.288 - 32.000 ) Source Clock Delay (SCD): 3.592ns Clock Pessimism Removal (CPR): 0.242ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.592ns (routing 0.594ns, distribution 2.998ns) Clock Net Delay (Destination): 3.288ns (routing 0.546ns, distribution 2.742ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.592 3.592 CLK SLICE_X119Y4 SRL16E r i_pwrup_rst/CLK ------------------------------------------------------------------- ------------------- SLICE_X119Y4 SRL16E (Prop_A6LUT_SLICEM_CLK_Q) 0.666 4.258 f i_pwrup_rst/Q net (fo=1, routed) 0.977 5.235 pwrup_rst SLICE_X131Y4 LUT2 (Prop_H5LUT_SLICEL_I0_O) 0.113 5.348 f rst_i_2/O net (fo=34, routed) 0.795 6.143 rst_dbl0 SLICE_X131Y5 FDPE f rst_reg/PRE ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.288 35.288 CLK SLICE_X131Y5 FDPE r rst_reg/C clock pessimism 0.242 35.530 clock uncertainty -0.085 35.445 SLICE_X131Y5 FDPE (Recov_AFF2_SLICEL_C_PRE) -0.093 35.352 rst_reg ------------------------------------------------------------------- required time 35.352 arrival time -6.143 ------------------------------------------------------------------- slack 29.209 Slack (MET) : 29.274ns (required time - arrival time) Source: i_pwrup_rst/CLK (rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: timer_reg[24]/CLR (recovery check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 2.483ns (logic 0.779ns (31.373%) route 1.704ns (68.627%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.285ns = ( 35.285 - 32.000 ) Source Clock Delay (SCD): 3.592ns Clock Pessimism Removal (CPR): 0.242ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.592ns (routing 0.594ns, distribution 2.998ns) Clock Net Delay (Destination): 3.285ns (routing 0.546ns, distribution 2.739ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.592 3.592 CLK SLICE_X119Y4 SRL16E r i_pwrup_rst/CLK ------------------------------------------------------------------- ------------------- SLICE_X119Y4 SRL16E (Prop_A6LUT_SLICEM_CLK_Q) 0.666 4.258 f i_pwrup_rst/Q net (fo=1, routed) 0.977 5.235 pwrup_rst SLICE_X131Y4 LUT2 (Prop_H5LUT_SLICEL_I0_O) 0.113 5.348 f rst_i_2/O net (fo=34, routed) 0.727 6.075 rst_dbl0 SLICE_X132Y3 FDCE f timer_reg[24]/CLR ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.285 35.285 CLK SLICE_X132Y3 FDCE r timer_reg[24]/C clock pessimism 0.242 35.527 clock uncertainty -0.085 35.442 SLICE_X132Y3 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 35.349 timer_reg[24] ------------------------------------------------------------------- required time 35.349 arrival time -6.075 ------------------------------------------------------------------- slack 29.274 Slack (MET) : 29.274ns (required time - arrival time) Source: i_pwrup_rst/CLK (rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: timer_reg[25]/CLR (recovery check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 2.483ns (logic 0.779ns (31.373%) route 1.704ns (68.627%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.285ns = ( 35.285 - 32.000 ) Source Clock Delay (SCD): 3.592ns Clock Pessimism Removal (CPR): 0.242ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.592ns (routing 0.594ns, distribution 2.998ns) Clock Net Delay (Destination): 3.285ns (routing 0.546ns, distribution 2.739ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.592 3.592 CLK SLICE_X119Y4 SRL16E r i_pwrup_rst/CLK ------------------------------------------------------------------- ------------------- SLICE_X119Y4 SRL16E (Prop_A6LUT_SLICEM_CLK_Q) 0.666 4.258 f i_pwrup_rst/Q net (fo=1, routed) 0.977 5.235 pwrup_rst SLICE_X131Y4 LUT2 (Prop_H5LUT_SLICEL_I0_O) 0.113 5.348 f rst_i_2/O net (fo=34, routed) 0.727 6.075 rst_dbl0 SLICE_X132Y3 FDCE f timer_reg[25]/CLR ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.285 35.285 CLK SLICE_X132Y3 FDCE r timer_reg[25]/C clock pessimism 0.242 35.527 clock uncertainty -0.085 35.442 SLICE_X132Y3 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 35.349 timer_reg[25] ------------------------------------------------------------------- required time 35.349 arrival time -6.075 ------------------------------------------------------------------- slack 29.274 Slack (MET) : 29.274ns (required time - arrival time) Source: i_pwrup_rst/CLK (rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: timer_reg[26]/CLR (recovery check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 2.483ns (logic 0.779ns (31.373%) route 1.704ns (68.627%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.285ns = ( 35.285 - 32.000 ) Source Clock Delay (SCD): 3.592ns Clock Pessimism Removal (CPR): 0.242ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.592ns (routing 0.594ns, distribution 2.998ns) Clock Net Delay (Destination): 3.285ns (routing 0.546ns, distribution 2.739ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.592 3.592 CLK SLICE_X119Y4 SRL16E r i_pwrup_rst/CLK ------------------------------------------------------------------- ------------------- SLICE_X119Y4 SRL16E (Prop_A6LUT_SLICEM_CLK_Q) 0.666 4.258 f i_pwrup_rst/Q net (fo=1, routed) 0.977 5.235 pwrup_rst SLICE_X131Y4 LUT2 (Prop_H5LUT_SLICEL_I0_O) 0.113 5.348 f rst_i_2/O net (fo=34, routed) 0.727 6.075 rst_dbl0 SLICE_X132Y3 FDCE f timer_reg[26]/CLR ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.285 35.285 CLK SLICE_X132Y3 FDCE r timer_reg[26]/C clock pessimism 0.242 35.527 clock uncertainty -0.085 35.442 SLICE_X132Y3 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 35.349 timer_reg[26] ------------------------------------------------------------------- required time 35.349 arrival time -6.075 ------------------------------------------------------------------- slack 29.274 Slack (MET) : 29.274ns (required time - arrival time) Source: i_pwrup_rst/CLK (rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: timer_reg[27]/CLR (recovery check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 2.483ns (logic 0.779ns (31.373%) route 1.704ns (68.627%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.285ns = ( 35.285 - 32.000 ) Source Clock Delay (SCD): 3.592ns Clock Pessimism Removal (CPR): 0.242ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.592ns (routing 0.594ns, distribution 2.998ns) Clock Net Delay (Destination): 3.285ns (routing 0.546ns, distribution 2.739ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.592 3.592 CLK SLICE_X119Y4 SRL16E r i_pwrup_rst/CLK ------------------------------------------------------------------- ------------------- SLICE_X119Y4 SRL16E (Prop_A6LUT_SLICEM_CLK_Q) 0.666 4.258 f i_pwrup_rst/Q net (fo=1, routed) 0.977 5.235 pwrup_rst SLICE_X131Y4 LUT2 (Prop_H5LUT_SLICEL_I0_O) 0.113 5.348 f rst_i_2/O net (fo=34, routed) 0.727 6.075 rst_dbl0 SLICE_X132Y3 FDCE f timer_reg[27]/CLR ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.285 35.285 CLK SLICE_X132Y3 FDCE r timer_reg[27]/C clock pessimism 0.242 35.527 clock uncertainty -0.085 35.442 SLICE_X132Y3 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 35.349 timer_reg[27] ------------------------------------------------------------------- required time 35.349 arrival time -6.075 ------------------------------------------------------------------- slack 29.274 Slack (MET) : 29.282ns (required time - arrival time) Source: i_pwrup_rst/CLK (rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: timer_reg[28]/CLR (recovery check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 2.473ns (logic 0.779ns (31.500%) route 1.694ns (68.500%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.067ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.283ns = ( 35.283 - 32.000 ) Source Clock Delay (SCD): 3.592ns Clock Pessimism Removal (CPR): 0.242ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.592ns (routing 0.594ns, distribution 2.998ns) Clock Net Delay (Destination): 3.283ns (routing 0.546ns, distribution 2.737ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.592 3.592 CLK SLICE_X119Y4 SRL16E r i_pwrup_rst/CLK ------------------------------------------------------------------- ------------------- SLICE_X119Y4 SRL16E (Prop_A6LUT_SLICEM_CLK_Q) 0.666 4.258 f i_pwrup_rst/Q net (fo=1, routed) 0.977 5.235 pwrup_rst SLICE_X131Y4 LUT2 (Prop_H5LUT_SLICEL_I0_O) 0.113 5.348 f rst_i_2/O net (fo=34, routed) 0.717 6.065 rst_dbl0 SLICE_X132Y3 FDCE f timer_reg[28]/CLR ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.283 35.283 CLK SLICE_X132Y3 FDCE r timer_reg[28]/C clock pessimism 0.242 35.525 clock uncertainty -0.085 35.440 SLICE_X132Y3 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 35.347 timer_reg[28] ------------------------------------------------------------------- required time 35.347 arrival time -6.065 ------------------------------------------------------------------- slack 29.282 Slack (MET) : 29.282ns (required time - arrival time) Source: i_pwrup_rst/CLK (rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: timer_reg[29]/CLR (recovery check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 2.473ns (logic 0.779ns (31.500%) route 1.694ns (68.500%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.067ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.283ns = ( 35.283 - 32.000 ) Source Clock Delay (SCD): 3.592ns Clock Pessimism Removal (CPR): 0.242ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.592ns (routing 0.594ns, distribution 2.998ns) Clock Net Delay (Destination): 3.283ns (routing 0.546ns, distribution 2.737ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.592 3.592 CLK SLICE_X119Y4 SRL16E r i_pwrup_rst/CLK ------------------------------------------------------------------- ------------------- SLICE_X119Y4 SRL16E (Prop_A6LUT_SLICEM_CLK_Q) 0.666 4.258 f i_pwrup_rst/Q net (fo=1, routed) 0.977 5.235 pwrup_rst SLICE_X131Y4 LUT2 (Prop_H5LUT_SLICEL_I0_O) 0.113 5.348 f rst_i_2/O net (fo=34, routed) 0.717 6.065 rst_dbl0 SLICE_X132Y3 FDCE f timer_reg[29]/CLR ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.283 35.283 CLK SLICE_X132Y3 FDCE r timer_reg[29]/C clock pessimism 0.242 35.525 clock uncertainty -0.085 35.440 SLICE_X132Y3 FDCE (Recov_FFF_SLICEL_C_CLR) -0.093 35.347 timer_reg[29] ------------------------------------------------------------------- required time 35.347 arrival time -6.065 ------------------------------------------------------------------- slack 29.282 Slack (MET) : 29.282ns (required time - arrival time) Source: i_pwrup_rst/CLK (rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: timer_reg[30]/CLR (recovery check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 2.473ns (logic 0.779ns (31.500%) route 1.694ns (68.500%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.067ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.283ns = ( 35.283 - 32.000 ) Source Clock Delay (SCD): 3.592ns Clock Pessimism Removal (CPR): 0.242ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.592ns (routing 0.594ns, distribution 2.998ns) Clock Net Delay (Destination): 3.283ns (routing 0.546ns, distribution 2.737ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.592 3.592 CLK SLICE_X119Y4 SRL16E r i_pwrup_rst/CLK ------------------------------------------------------------------- ------------------- SLICE_X119Y4 SRL16E (Prop_A6LUT_SLICEM_CLK_Q) 0.666 4.258 f i_pwrup_rst/Q net (fo=1, routed) 0.977 5.235 pwrup_rst SLICE_X131Y4 LUT2 (Prop_H5LUT_SLICEL_I0_O) 0.113 5.348 f rst_i_2/O net (fo=34, routed) 0.717 6.065 rst_dbl0 SLICE_X132Y3 FDCE f timer_reg[30]/CLR ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.283 35.283 CLK SLICE_X132Y3 FDCE r timer_reg[30]/C clock pessimism 0.242 35.525 clock uncertainty -0.085 35.440 SLICE_X132Y3 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 35.347 timer_reg[30] ------------------------------------------------------------------- required time 35.347 arrival time -6.065 ------------------------------------------------------------------- slack 29.282 Slack (MET) : 29.282ns (required time - arrival time) Source: i_pwrup_rst/CLK (rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: timer_reg[31]/CLR (recovery check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 2.473ns (logic 0.779ns (31.500%) route 1.694ns (68.500%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.067ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.283ns = ( 35.283 - 32.000 ) Source Clock Delay (SCD): 3.592ns Clock Pessimism Removal (CPR): 0.242ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.592ns (routing 0.594ns, distribution 2.998ns) Clock Net Delay (Destination): 3.283ns (routing 0.546ns, distribution 2.737ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.592 3.592 CLK SLICE_X119Y4 SRL16E r i_pwrup_rst/CLK ------------------------------------------------------------------- ------------------- SLICE_X119Y4 SRL16E (Prop_A6LUT_SLICEM_CLK_Q) 0.666 4.258 f i_pwrup_rst/Q net (fo=1, routed) 0.977 5.235 pwrup_rst SLICE_X131Y4 LUT2 (Prop_H5LUT_SLICEL_I0_O) 0.113 5.348 f rst_i_2/O net (fo=34, routed) 0.717 6.065 rst_dbl0 SLICE_X132Y3 FDCE f timer_reg[31]/CLR ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.283 35.283 CLK SLICE_X132Y3 FDCE r timer_reg[31]/C clock pessimism 0.242 35.525 clock uncertainty -0.085 35.440 SLICE_X132Y3 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 35.347 timer_reg[31] ------------------------------------------------------------------- required time 35.347 arrival time -6.065 ------------------------------------------------------------------- slack 29.282 Slack (MET) : 29.359ns (required time - arrival time) Source: i_pwrup_rst/CLK (rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: timer_reg[16]/PRE (recovery check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 2.398ns (logic 0.779ns (32.485%) route 1.619ns (67.515%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.285ns = ( 35.285 - 32.000 ) Source Clock Delay (SCD): 3.592ns Clock Pessimism Removal (CPR): 0.242ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.592ns (routing 0.594ns, distribution 2.998ns) Clock Net Delay (Destination): 3.285ns (routing 0.546ns, distribution 2.739ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.592 3.592 CLK SLICE_X119Y4 SRL16E r i_pwrup_rst/CLK ------------------------------------------------------------------- ------------------- SLICE_X119Y4 SRL16E (Prop_A6LUT_SLICEM_CLK_Q) 0.666 4.258 f i_pwrup_rst/Q net (fo=1, routed) 0.977 5.235 pwrup_rst SLICE_X131Y4 LUT2 (Prop_H5LUT_SLICEL_I0_O) 0.113 5.348 f rst_i_2/O net (fo=34, routed) 0.642 5.990 rst_dbl0 SLICE_X132Y2 FDPE f timer_reg[16]/PRE ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y106 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 3.285 35.285 CLK SLICE_X132Y2 FDPE r timer_reg[16]/C clock pessimism 0.242 35.527 clock uncertainty -0.085 35.442 SLICE_X132Y2 FDPE (Recov_AFF_SLICEL_C_PRE) -0.093 35.349 timer_reg[16] ------------------------------------------------------------------- required time 35.349 arrival time -5.990 ------------------------------------------------------------------- slack 29.359 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.772ns (arrival time - required time) Source: i_pwrup_rst/CLK (rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: timer_reg[4]/CLR (removal check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.900ns (logic 0.243ns (27.000%) route 0.657ns (73.000%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.123ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.557ns Source Clock Delay (SCD): 1.298ns Clock Pessimism Removal (CPR): 0.136ns Clock Net Delay (Source): 1.298ns (routing 0.203ns, distribution 1.095ns) Clock Net Delay (Destination): 1.557ns (routing 0.225ns, distribution 1.332ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.298 1.298 CLK SLICE_X119Y4 SRL16E r i_pwrup_rst/CLK ------------------------------------------------------------------- ------------------- SLICE_X119Y4 SRL16E (Prop_A6LUT_SLICEM_CLK_Q) 0.204 1.502 f i_pwrup_rst/Q net (fo=1, routed) 0.441 1.943 pwrup_rst SLICE_X131Y4 LUT2 (Prop_H5LUT_SLICEL_I0_O) 0.039 1.982 f rst_i_2/O net (fo=34, routed) 0.216 2.198 rst_dbl0 SLICE_X132Y0 FDCE f timer_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.557 1.557 CLK SLICE_X132Y0 FDCE r timer_reg[4]/C clock pessimism -0.136 1.421 SLICE_X132Y0 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.426 timer_reg[4] ------------------------------------------------------------------- required time -1.426 arrival time 2.198 ------------------------------------------------------------------- slack 0.772 Slack (MET) : 0.772ns (arrival time - required time) Source: i_pwrup_rst/CLK (rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: timer_reg[5]/CLR (removal check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.900ns (logic 0.243ns (27.000%) route 0.657ns (73.000%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.123ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.557ns Source Clock Delay (SCD): 1.298ns Clock Pessimism Removal (CPR): 0.136ns Clock Net Delay (Source): 1.298ns (routing 0.203ns, distribution 1.095ns) Clock Net Delay (Destination): 1.557ns (routing 0.225ns, distribution 1.332ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.298 1.298 CLK SLICE_X119Y4 SRL16E r i_pwrup_rst/CLK ------------------------------------------------------------------- ------------------- SLICE_X119Y4 SRL16E (Prop_A6LUT_SLICEM_CLK_Q) 0.204 1.502 f i_pwrup_rst/Q net (fo=1, routed) 0.441 1.943 pwrup_rst SLICE_X131Y4 LUT2 (Prop_H5LUT_SLICEL_I0_O) 0.039 1.982 f rst_i_2/O net (fo=34, routed) 0.216 2.198 rst_dbl0 SLICE_X132Y0 FDCE f timer_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.557 1.557 CLK SLICE_X132Y0 FDCE r timer_reg[5]/C clock pessimism -0.136 1.421 SLICE_X132Y0 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.426 timer_reg[5] ------------------------------------------------------------------- required time -1.426 arrival time 2.198 ------------------------------------------------------------------- slack 0.772 Slack (MET) : 0.772ns (arrival time - required time) Source: i_pwrup_rst/CLK (rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: timer_reg[6]/CLR (removal check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.900ns (logic 0.243ns (27.000%) route 0.657ns (73.000%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.123ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.557ns Source Clock Delay (SCD): 1.298ns Clock Pessimism Removal (CPR): 0.136ns Clock Net Delay (Source): 1.298ns (routing 0.203ns, distribution 1.095ns) Clock Net Delay (Destination): 1.557ns (routing 0.225ns, distribution 1.332ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.298 1.298 CLK SLICE_X119Y4 SRL16E r i_pwrup_rst/CLK ------------------------------------------------------------------- ------------------- SLICE_X119Y4 SRL16E (Prop_A6LUT_SLICEM_CLK_Q) 0.204 1.502 f i_pwrup_rst/Q net (fo=1, routed) 0.441 1.943 pwrup_rst SLICE_X131Y4 LUT2 (Prop_H5LUT_SLICEL_I0_O) 0.039 1.982 f rst_i_2/O net (fo=34, routed) 0.216 2.198 rst_dbl0 SLICE_X132Y0 FDCE f timer_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.557 1.557 CLK SLICE_X132Y0 FDCE r timer_reg[6]/C clock pessimism -0.136 1.421 SLICE_X132Y0 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 1.426 timer_reg[6] ------------------------------------------------------------------- required time -1.426 arrival time 2.198 ------------------------------------------------------------------- slack 0.772 Slack (MET) : 0.772ns (arrival time - required time) Source: i_pwrup_rst/CLK (rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: timer_reg[7]/CLR (removal check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.900ns (logic 0.243ns (27.000%) route 0.657ns (73.000%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.123ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.557ns Source Clock Delay (SCD): 1.298ns Clock Pessimism Removal (CPR): 0.136ns Clock Net Delay (Source): 1.298ns (routing 0.203ns, distribution 1.095ns) Clock Net Delay (Destination): 1.557ns (routing 0.225ns, distribution 1.332ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.298 1.298 CLK SLICE_X119Y4 SRL16E r i_pwrup_rst/CLK ------------------------------------------------------------------- ------------------- SLICE_X119Y4 SRL16E (Prop_A6LUT_SLICEM_CLK_Q) 0.204 1.502 f i_pwrup_rst/Q net (fo=1, routed) 0.441 1.943 pwrup_rst SLICE_X131Y4 LUT2 (Prop_H5LUT_SLICEL_I0_O) 0.039 1.982 f rst_i_2/O net (fo=34, routed) 0.216 2.198 rst_dbl0 SLICE_X132Y0 FDCE f timer_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.557 1.557 CLK SLICE_X132Y0 FDCE r timer_reg[7]/C clock pessimism -0.136 1.421 SLICE_X132Y0 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.426 timer_reg[7] ------------------------------------------------------------------- required time -1.426 arrival time 2.198 ------------------------------------------------------------------- slack 0.772 Slack (MET) : 0.775ns (arrival time - required time) Source: i_pwrup_rst/CLK (rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: timer_reg[0]/CLR (removal check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.906ns (logic 0.243ns (26.821%) route 0.663ns (73.179%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.126ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.560ns Source Clock Delay (SCD): 1.298ns Clock Pessimism Removal (CPR): 0.136ns Clock Net Delay (Source): 1.298ns (routing 0.203ns, distribution 1.095ns) Clock Net Delay (Destination): 1.560ns (routing 0.225ns, distribution 1.335ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.298 1.298 CLK SLICE_X119Y4 SRL16E r i_pwrup_rst/CLK ------------------------------------------------------------------- ------------------- SLICE_X119Y4 SRL16E (Prop_A6LUT_SLICEM_CLK_Q) 0.204 1.502 f i_pwrup_rst/Q net (fo=1, routed) 0.441 1.943 pwrup_rst SLICE_X131Y4 LUT2 (Prop_H5LUT_SLICEL_I0_O) 0.039 1.982 f rst_i_2/O net (fo=34, routed) 0.222 2.204 rst_dbl0 SLICE_X132Y0 FDCE f timer_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.560 1.560 CLK SLICE_X132Y0 FDCE r timer_reg[0]/C clock pessimism -0.136 1.424 SLICE_X132Y0 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.429 timer_reg[0] ------------------------------------------------------------------- required time -1.429 arrival time 2.204 ------------------------------------------------------------------- slack 0.775 Slack (MET) : 0.775ns (arrival time - required time) Source: i_pwrup_rst/CLK (rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: timer_reg[1]/CLR (removal check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.906ns (logic 0.243ns (26.821%) route 0.663ns (73.179%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.126ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.560ns Source Clock Delay (SCD): 1.298ns Clock Pessimism Removal (CPR): 0.136ns Clock Net Delay (Source): 1.298ns (routing 0.203ns, distribution 1.095ns) Clock Net Delay (Destination): 1.560ns (routing 0.225ns, distribution 1.335ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.298 1.298 CLK SLICE_X119Y4 SRL16E r i_pwrup_rst/CLK ------------------------------------------------------------------- ------------------- SLICE_X119Y4 SRL16E (Prop_A6LUT_SLICEM_CLK_Q) 0.204 1.502 f i_pwrup_rst/Q net (fo=1, routed) 0.441 1.943 pwrup_rst SLICE_X131Y4 LUT2 (Prop_H5LUT_SLICEL_I0_O) 0.039 1.982 f rst_i_2/O net (fo=34, routed) 0.222 2.204 rst_dbl0 SLICE_X132Y0 FDCE f timer_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.560 1.560 CLK SLICE_X132Y0 FDCE r timer_reg[1]/C clock pessimism -0.136 1.424 SLICE_X132Y0 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 1.429 timer_reg[1] ------------------------------------------------------------------- required time -1.429 arrival time 2.204 ------------------------------------------------------------------- slack 0.775 Slack (MET) : 0.775ns (arrival time - required time) Source: i_pwrup_rst/CLK (rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: timer_reg[2]/CLR (removal check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.906ns (logic 0.243ns (26.821%) route 0.663ns (73.179%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.126ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.560ns Source Clock Delay (SCD): 1.298ns Clock Pessimism Removal (CPR): 0.136ns Clock Net Delay (Source): 1.298ns (routing 0.203ns, distribution 1.095ns) Clock Net Delay (Destination): 1.560ns (routing 0.225ns, distribution 1.335ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.298 1.298 CLK SLICE_X119Y4 SRL16E r i_pwrup_rst/CLK ------------------------------------------------------------------- ------------------- SLICE_X119Y4 SRL16E (Prop_A6LUT_SLICEM_CLK_Q) 0.204 1.502 f i_pwrup_rst/Q net (fo=1, routed) 0.441 1.943 pwrup_rst SLICE_X131Y4 LUT2 (Prop_H5LUT_SLICEL_I0_O) 0.039 1.982 f rst_i_2/O net (fo=34, routed) 0.222 2.204 rst_dbl0 SLICE_X132Y0 FDCE f timer_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.560 1.560 CLK SLICE_X132Y0 FDCE r timer_reg[2]/C clock pessimism -0.136 1.424 SLICE_X132Y0 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 1.429 timer_reg[2] ------------------------------------------------------------------- required time -1.429 arrival time 2.204 ------------------------------------------------------------------- slack 0.775 Slack (MET) : 0.775ns (arrival time - required time) Source: i_pwrup_rst/CLK (rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: timer_reg[3]/PRE (removal check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.906ns (logic 0.243ns (26.821%) route 0.663ns (73.179%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.126ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.560ns Source Clock Delay (SCD): 1.298ns Clock Pessimism Removal (CPR): 0.136ns Clock Net Delay (Source): 1.298ns (routing 0.203ns, distribution 1.095ns) Clock Net Delay (Destination): 1.560ns (routing 0.225ns, distribution 1.335ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.298 1.298 CLK SLICE_X119Y4 SRL16E r i_pwrup_rst/CLK ------------------------------------------------------------------- ------------------- SLICE_X119Y4 SRL16E (Prop_A6LUT_SLICEM_CLK_Q) 0.204 1.502 f i_pwrup_rst/Q net (fo=1, routed) 0.441 1.943 pwrup_rst SLICE_X131Y4 LUT2 (Prop_H5LUT_SLICEL_I0_O) 0.039 1.982 f rst_i_2/O net (fo=34, routed) 0.222 2.204 rst_dbl0 SLICE_X132Y0 FDPE f timer_reg[3]/PRE ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.560 1.560 CLK SLICE_X132Y0 FDPE r timer_reg[3]/C clock pessimism -0.136 1.424 SLICE_X132Y0 FDPE (Remov_DFF_SLICEL_C_PRE) 0.005 1.429 timer_reg[3] ------------------------------------------------------------------- required time -1.429 arrival time 2.204 ------------------------------------------------------------------- slack 0.775 Slack (MET) : 0.799ns (arrival time - required time) Source: i_pwrup_rst/CLK (rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: timer_reg[12]/CLR (removal check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.935ns (logic 0.243ns (25.989%) route 0.692ns (74.011%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.131ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.565ns Source Clock Delay (SCD): 1.298ns Clock Pessimism Removal (CPR): 0.136ns Clock Net Delay (Source): 1.298ns (routing 0.203ns, distribution 1.095ns) Clock Net Delay (Destination): 1.565ns (routing 0.225ns, distribution 1.340ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.298 1.298 CLK SLICE_X119Y4 SRL16E r i_pwrup_rst/CLK ------------------------------------------------------------------- ------------------- SLICE_X119Y4 SRL16E (Prop_A6LUT_SLICEM_CLK_Q) 0.204 1.502 f i_pwrup_rst/Q net (fo=1, routed) 0.441 1.943 pwrup_rst SLICE_X131Y4 LUT2 (Prop_H5LUT_SLICEL_I0_O) 0.039 1.982 f rst_i_2/O net (fo=34, routed) 0.251 2.233 rst_dbl0 SLICE_X132Y1 FDCE f timer_reg[12]/CLR ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.565 1.565 CLK SLICE_X132Y1 FDCE r timer_reg[12]/C clock pessimism -0.136 1.429 SLICE_X132Y1 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.434 timer_reg[12] ------------------------------------------------------------------- required time -1.434 arrival time 2.233 ------------------------------------------------------------------- slack 0.799 Slack (MET) : 0.799ns (arrival time - required time) Source: i_pwrup_rst/CLK (rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: timer_reg[13]/PRE (removal check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.935ns (logic 0.243ns (25.989%) route 0.692ns (74.011%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.131ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.565ns Source Clock Delay (SCD): 1.298ns Clock Pessimism Removal (CPR): 0.136ns Clock Net Delay (Source): 1.298ns (routing 0.203ns, distribution 1.095ns) Clock Net Delay (Destination): 1.565ns (routing 0.225ns, distribution 1.340ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.298 1.298 CLK SLICE_X119Y4 SRL16E r i_pwrup_rst/CLK ------------------------------------------------------------------- ------------------- SLICE_X119Y4 SRL16E (Prop_A6LUT_SLICEM_CLK_Q) 0.204 1.502 f i_pwrup_rst/Q net (fo=1, routed) 0.441 1.943 pwrup_rst SLICE_X131Y4 LUT2 (Prop_H5LUT_SLICEL_I0_O) 0.039 1.982 f rst_i_2/O net (fo=34, routed) 0.251 2.233 rst_dbl0 SLICE_X132Y1 FDPE f timer_reg[13]/PRE ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y106 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204776, routed) 1.565 1.565 CLK SLICE_X132Y1 FDPE r timer_reg[13]/C clock pessimism -0.136 1.429 SLICE_X132Y1 FDPE (Remov_FFF_SLICEL_C_PRE) 0.005 1.434 timer_reg[13] ------------------------------------------------------------------- required time -1.434 arrival time 2.233 ------------------------------------------------------------------- slack 0.799 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: tx_wordclk To Clock: tx_wordclk Setup : 0 Failing Endpoints, Worst Slack 1.657ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.117ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.657ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genTxRstMgtClk_sync_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE (recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 5.885ns (logic 0.327ns (5.556%) route 5.558ns (94.443%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.261ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.997ns = ( 11.314 - 8.317 ) Source Clock Delay (SCD): 3.341ns Clock Pessimism Removal (CPR): 0.083ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.314ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 2.997ns Common Clock Delay (CCD): 0.903ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.341ns (routing 0.986ns, distribution 2.355ns) Clock Net Delay (Destination): 2.997ns (routing 0.903ns, distribution 2.094ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.341 3.341 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/tx_wordclk SLICE_X58Y263 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genTxRstMgtClk_sync_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X58Y263 FDPE (Prop_EFF2_SLICEM_C_Q) 0.138 3.479 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genTxRstMgtClk_sync_s_reg/Q net (fo=1, routed) 5.106 8.585 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genTxRstMgtClk_sync_s SLR Crossing[0->1] SLICE_X50Y494 LUT2 (Prop_G5LUT_SLICEL_I1_O) 0.189 8.774 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_i_1__2/O net (fo=1, routed) 0.452 9.226 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s0 SLICE_X50Y493 FDPE f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 2.997 11.314 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X50Y493 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_reg/C clock pessimism 0.083 11.397 inter-SLR compensation -0.314 11.083 clock uncertainty -0.107 10.976 SLICE_X50Y493 FDPE (Recov_EFF_SLICEL_C_PRE) -0.093 10.883 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_reg ------------------------------------------------------------------- required time 10.883 arrival time -9.226 ------------------------------------------------------------------- slack 1.657 Slack (MET) : 2.043ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[108]/CLR (recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 5.384ns (logic 0.140ns (2.600%) route 5.244ns (97.400%)) Logic Levels: 0 Clock Path Skew: -0.690ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.089ns = ( 11.406 - 8.317 ) Source Clock Delay (SCD): 3.862ns Clock Pessimism Removal (CPR): 0.083ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.862ns (routing 0.986ns, distribution 2.876ns) Clock Net Delay (Destination): 3.089ns (routing 0.903ns, distribution 2.186ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.862 3.862 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X112Y537 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X112Y537 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 4.002 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 5.244 9.246 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/gbt_txreset_s[0] SLICE_X80Y308 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[108]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.089 11.406 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/tx_wordclk SLR Crossing[0->1] SLICE_X80Y308 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[108]/C clock pessimism 0.083 11.489 clock uncertainty -0.107 11.382 SLICE_X80Y308 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.289 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[108] ------------------------------------------------------------------- required time 11.289 arrival time -9.246 ------------------------------------------------------------------- slack 2.043 Slack (MET) : 2.051ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/TX_WORD_O_reg[3]/CLR (recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 5.374ns (logic 0.140ns (2.605%) route 5.234ns (97.395%)) Logic Levels: 0 Clock Path Skew: -0.692ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.087ns = ( 11.404 - 8.317 ) Source Clock Delay (SCD): 3.862ns Clock Pessimism Removal (CPR): 0.083ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.862ns (routing 0.986ns, distribution 2.876ns) Clock Net Delay (Destination): 3.087ns (routing 0.903ns, distribution 2.184ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.862 3.862 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X112Y537 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X112Y537 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 4.002 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 5.234 9.236 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/gbt_txreset_s[0] SLICE_X80Y308 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/TX_WORD_O_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.087 11.404 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/tx_wordclk SLR Crossing[0->1] SLICE_X80Y308 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/TX_WORD_O_reg[3]/C clock pessimism 0.083 11.487 clock uncertainty -0.107 11.380 SLICE_X80Y308 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 11.287 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/TX_WORD_O_reg[3] ------------------------------------------------------------------- required time 11.287 arrival time -9.236 ------------------------------------------------------------------- slack 2.051 Slack (MET) : 2.051ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[23]/CLR (recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 5.374ns (logic 0.140ns (2.605%) route 5.234ns (97.395%)) Logic Levels: 0 Clock Path Skew: -0.692ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.087ns = ( 11.404 - 8.317 ) Source Clock Delay (SCD): 3.862ns Clock Pessimism Removal (CPR): 0.083ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.862ns (routing 0.986ns, distribution 2.876ns) Clock Net Delay (Destination): 3.087ns (routing 0.903ns, distribution 2.184ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.862 3.862 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X112Y537 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X112Y537 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 4.002 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 5.234 9.236 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/gbt_txreset_s[0] SLICE_X80Y308 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[23]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.087 11.404 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/tx_wordclk SLR Crossing[0->1] SLICE_X80Y308 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[23]/C clock pessimism 0.083 11.487 clock uncertainty -0.107 11.380 SLICE_X80Y308 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 11.287 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[23] ------------------------------------------------------------------- required time 11.287 arrival time -9.236 ------------------------------------------------------------------- slack 2.051 Slack (MET) : 2.051ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[63]/CLR (recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 5.374ns (logic 0.140ns (2.605%) route 5.234ns (97.395%)) Logic Levels: 0 Clock Path Skew: -0.692ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.087ns = ( 11.404 - 8.317 ) Source Clock Delay (SCD): 3.862ns Clock Pessimism Removal (CPR): 0.083ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.862ns (routing 0.986ns, distribution 2.876ns) Clock Net Delay (Destination): 3.087ns (routing 0.903ns, distribution 2.184ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.862 3.862 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X112Y537 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X112Y537 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 4.002 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 5.234 9.236 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/gbt_txreset_s[0] SLICE_X80Y308 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[63]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.087 11.404 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/tx_wordclk SLR Crossing[0->1] SLICE_X80Y308 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[63]/C clock pessimism 0.083 11.487 clock uncertainty -0.107 11.380 SLICE_X80Y308 FDCE (Recov_GFF2_SLICEL_C_CLR) -0.093 11.287 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[63] ------------------------------------------------------------------- required time 11.287 arrival time -9.236 ------------------------------------------------------------------- slack 2.051 Slack (MET) : 2.068ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[2]/CLR (recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 5.955ns (logic 0.139ns (2.334%) route 5.816ns (97.666%)) Logic Levels: 0 Clock Path Skew: 0.295ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.496ns = ( 11.813 - 8.317 ) Source Clock Delay (SCD): 3.284ns Clock Pessimism Removal (CPR): 0.083ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.389ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.496ns Common Clock Delay (CCD): 0.903ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.284ns (routing 0.986ns, distribution 2.298ns) Clock Net Delay (Destination): 3.496ns (routing 0.903ns, distribution 2.593ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.284 3.284 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/tx_wordclk SLICE_X61Y159 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X61Y159 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 3.423 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 5.816 9.239 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/gbt_txreset_s[0] SLR Crossing[0->1] SLICE_X6Y309 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.496 11.813 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X6Y309 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[2]/C clock pessimism 0.083 11.896 inter-SLR compensation -0.389 11.507 clock uncertainty -0.107 11.400 SLICE_X6Y309 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.307 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time 11.307 arrival time -9.239 ------------------------------------------------------------------- slack 2.068 Slack (MET) : 2.128ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[118]/CLR (recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 5.282ns (logic 0.140ns (2.651%) route 5.142ns (97.350%)) Logic Levels: 0 Clock Path Skew: -0.707ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.072ns = ( 11.389 - 8.317 ) Source Clock Delay (SCD): 3.862ns Clock Pessimism Removal (CPR): 0.083ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.862ns (routing 0.986ns, distribution 2.876ns) Clock Net Delay (Destination): 3.072ns (routing 0.903ns, distribution 2.169ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.862 3.862 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X112Y537 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X112Y537 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 4.002 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 5.142 9.144 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/gbt_txreset_s[0] SLICE_X78Y310 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[118]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.072 11.389 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/tx_wordclk SLR Crossing[0->1] SLICE_X78Y310 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[118]/C clock pessimism 0.083 11.472 clock uncertainty -0.107 11.365 SLICE_X78Y310 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.272 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[118] ------------------------------------------------------------------- required time 11.272 arrival time -9.144 ------------------------------------------------------------------- slack 2.128 Slack (MET) : 2.131ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/tx_aligned_o_reg/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtTxReady_s_reg/CLR (recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 5.059ns (logic 0.138ns (2.728%) route 4.921ns (97.272%)) Logic Levels: 0 Clock Path Skew: -0.927ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.077ns = ( 11.394 - 8.317 ) Source Clock Delay (SCD): 4.105ns Clock Pessimism Removal (CPR): 0.101ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 4.105ns (routing 0.986ns, distribution 3.119ns) Clock Net Delay (Destination): 3.077ns (routing 0.903ns, distribution 2.174ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 4.105 4.105 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/tx_wordclk SLR Crossing[0->1] SLICE_X141Y569 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/tx_aligned_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y569 FDRE (Prop_HFF_SLICEL_C_Q) 0.138 4.243 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/tx_aligned_o_reg/Q net (fo=15, routed) 4.921 9.164 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtTxReady_sync_s_reg_0 SLICE_X88Y395 FDCE f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtTxReady_s_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.077 11.394 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X88Y395 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtTxReady_s_reg/C clock pessimism 0.101 11.495 clock uncertainty -0.107 11.388 SLICE_X88Y395 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.295 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtTxReady_s_reg ------------------------------------------------------------------- required time 11.295 arrival time -9.164 ------------------------------------------------------------------- slack 2.131 Slack (MET) : 2.131ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/tx_aligned_o_reg/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtTxReady_sync_s_reg/CLR (recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 5.059ns (logic 0.138ns (2.728%) route 4.921ns (97.272%)) Logic Levels: 0 Clock Path Skew: -0.927ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.077ns = ( 11.394 - 8.317 ) Source Clock Delay (SCD): 4.105ns Clock Pessimism Removal (CPR): 0.101ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 4.105ns (routing 0.986ns, distribution 3.119ns) Clock Net Delay (Destination): 3.077ns (routing 0.903ns, distribution 2.174ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 4.105 4.105 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/tx_wordclk SLR Crossing[0->1] SLICE_X141Y569 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/tx_aligned_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y569 FDRE (Prop_HFF_SLICEL_C_Q) 0.138 4.243 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/tx_aligned_o_reg/Q net (fo=15, routed) 4.921 9.164 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtTxReady_sync_s_reg_0 SLICE_X88Y395 FDCE f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtTxReady_sync_s_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.077 11.394 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X88Y395 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtTxReady_sync_s_reg/C clock pessimism 0.101 11.495 clock uncertainty -0.107 11.388 SLICE_X88Y395 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 11.295 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtTxReady_sync_s_reg ------------------------------------------------------------------- required time 11.295 arrival time -9.164 ------------------------------------------------------------------- slack 2.131 Slack (MET) : 2.133ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[92]/CLR (recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 5.292ns (logic 0.140ns (2.646%) route 5.152ns (97.354%)) Logic Levels: 0 Clock Path Skew: -0.692ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.087ns = ( 11.404 - 8.317 ) Source Clock Delay (SCD): 3.862ns Clock Pessimism Removal (CPR): 0.083ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.862ns (routing 0.986ns, distribution 2.876ns) Clock Net Delay (Destination): 3.087ns (routing 0.903ns, distribution 2.184ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.862 3.862 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X112Y537 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X112Y537 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 4.002 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 5.152 9.154 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/gbt_txreset_s[0] SLICE_X78Y311 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[92]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y118 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 3.087 11.404 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/tx_wordclk SLR Crossing[0->1] SLICE_X78Y311 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[92]/C clock pessimism 0.083 11.487 clock uncertainty -0.107 11.380 SLICE_X78Y311 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.287 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[92] ------------------------------------------------------------------- required time 11.287 arrival time -9.154 ------------------------------------------------------------------- slack 2.133 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.117ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE (removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.265ns (logic 0.064ns (24.151%) route 0.201ns (75.849%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.143ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.666ns Source Clock Delay (SCD): 1.457ns Clock Pessimism Removal (CPR): 0.066ns Clock Net Delay (Source): 1.457ns (routing 0.373ns, distribution 1.084ns) Clock Net Delay (Destination): 1.666ns (routing 0.411ns, distribution 1.255ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.457 1.457 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X113Y541 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X113Y541 FDPE (Prop_EFF2_SLICEM_C_Q) 0.048 1.505 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/Q net (fo=1, routed) 0.036 1.541 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRstMgtClk_sync_s SLICE_X113Y541 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.016 1.557 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s0/O net (fo=1, routed) 0.165 1.722 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s0__0 SLICE_X113Y539 FDPE f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.666 1.666 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X113Y539 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg/C clock pessimism -0.066 1.600 SLICE_X113Y539 FDPE (Remov_EFF_SLICEM_C_PRE) 0.005 1.605 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg ------------------------------------------------------------------- required time -1.605 arrival time 1.722 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.188ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE (removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.223ns (logic 0.064ns (28.700%) route 0.159ns (71.300%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.030ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.583ns Source Clock Delay (SCD): 1.367ns Clock Pessimism Removal (CPR): 0.186ns Clock Net Delay (Source): 1.367ns (routing 0.373ns, distribution 0.994ns) Clock Net Delay (Destination): 1.583ns (routing 0.411ns, distribution 1.172ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.367 1.367 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/tx_wordclk SLICE_X112Y151 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X112Y151 FDPE (Prop_AFF2_SLICEM_C_Q) 0.049 1.416 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/Q net (fo=1, routed) 0.033 1.449 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s SLICE_X112Y151 LUT3 (Prop_C6LUT_SLICEM_I1_O) 0.015 1.464 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s0/O net (fo=1, routed) 0.126 1.590 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s0__0 SLICE_X112Y151 FDPE f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.583 1.583 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/tx_wordclk SLICE_X112Y151 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s_reg/C clock pessimism -0.186 1.397 SLICE_X112Y151 FDPE (Remov_EFF_SLICEM_C_PRE) 0.005 1.402 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s_reg ------------------------------------------------------------------- required time -1.402 arrival time 1.590 ------------------------------------------------------------------- slack 0.188 Slack (MET) : 0.196ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE (removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.269ns (logic 0.063ns (23.420%) route 0.206ns (76.580%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.507ns Source Clock Delay (SCD): 1.302ns Clock Pessimism Removal (CPR): 0.137ns Clock Net Delay (Source): 1.302ns (routing 0.373ns, distribution 0.929ns) Clock Net Delay (Destination): 1.507ns (routing 0.411ns, distribution 1.096ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.302 1.302 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X94Y432 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X94Y432 FDPE (Prop_EFF2_SLICEL_C_Q) 0.048 1.350 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/Q net (fo=1, routed) 0.031 1.381 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRstMgtClk_sync_s SLICE_X94Y432 LUT3 (Prop_G6LUT_SLICEL_I0_O) 0.015 1.396 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0/O net (fo=1, routed) 0.175 1.571 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0__0 SLICE_X95Y433 FDPE f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.507 1.507 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X95Y433 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/C clock pessimism -0.137 1.370 SLICE_X95Y433 FDPE (Remov_AFF_SLICEM_C_PRE) 0.005 1.375 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg ------------------------------------------------------------------- required time -1.375 arrival time 1.571 ------------------------------------------------------------------- slack 0.196 Slack (MET) : 0.197ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE (removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.368ns (logic 0.100ns (27.174%) route 0.268ns (72.826%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.166ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.627ns Source Clock Delay (SCD): 1.395ns Clock Pessimism Removal (CPR): 0.066ns Clock Net Delay (Source): 1.395ns (routing 0.373ns, distribution 1.022ns) Clock Net Delay (Destination): 1.627ns (routing 0.411ns, distribution 1.216ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.395 1.395 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X46Y537 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X46Y537 FDPE (Prop_EFF2_SLICEL_C_Q) 0.048 1.443 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/Q net (fo=1, routed) 0.115 1.558 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRstMgtClk_sync_s SLICE_X46Y542 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.052 1.610 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s0/O net (fo=1, routed) 0.153 1.763 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s0__0 SLICE_X46Y542 FDPE f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.627 1.627 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X46Y542 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s_reg/C clock pessimism -0.066 1.561 SLICE_X46Y542 FDPE (Remov_EFF_SLICEL_C_PRE) 0.005 1.566 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s_reg ------------------------------------------------------------------- required time -1.566 arrival time 1.763 ------------------------------------------------------------------- slack 0.197 Slack (MET) : 0.203ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE (removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.272ns (logic 0.064ns (23.529%) route 0.208ns (76.471%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.064ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.412ns Source Clock Delay (SCD): 1.219ns Clock Pessimism Removal (CPR): 0.129ns Clock Net Delay (Source): 1.219ns (routing 0.373ns, distribution 0.846ns) Clock Net Delay (Destination): 1.412ns (routing 0.411ns, distribution 1.001ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.219 1.219 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/tx_wordclk SLICE_X71Y78 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X71Y78 FDPE (Prop_EFF2_SLICEM_C_Q) 0.048 1.267 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/Q net (fo=1, routed) 0.036 1.303 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRstMgtClk_sync_s SLICE_X71Y78 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.016 1.319 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0/O net (fo=1, routed) 0.172 1.491 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0__0 SLICE_X73Y78 FDPE f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.412 1.412 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/tx_wordclk SLICE_X73Y78 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/C clock pessimism -0.129 1.283 SLICE_X73Y78 FDPE (Remov_EFF_SLICEM_C_PRE) 0.005 1.288 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg ------------------------------------------------------------------- required time -1.288 arrival time 1.491 ------------------------------------------------------------------- slack 0.203 Slack (MET) : 0.204ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[10]/PRE (removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.367ns (logic 0.049ns (13.351%) route 0.318ns (86.649%)) Logic Levels: 0 Clock Path Skew: 0.158ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.417ns Source Clock Delay (SCD): 1.214ns Clock Pessimism Removal (CPR): 0.045ns Clock Net Delay (Source): 1.214ns (routing 0.373ns, distribution 0.841ns) Clock Net Delay (Destination): 1.417ns (routing 0.411ns, distribution 1.006ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.214 1.214 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/tx_wordclk SLICE_X71Y173 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X71Y173 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.263 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 0.318 1.581 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/gbt_txreset_s[0] SLICE_X75Y180 FDPE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[10]/PRE ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.417 1.417 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk SLICE_X75Y180 FDPE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[10]/C clock pessimism -0.045 1.372 SLICE_X75Y180 FDPE (Remov_HFF_SLICEL_C_PRE) 0.005 1.377 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[10] ------------------------------------------------------------------- required time -1.377 arrival time 1.581 ------------------------------------------------------------------- slack 0.204 Slack (MET) : 0.209ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[12]/CLR (removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.375ns (logic 0.049ns (13.067%) route 0.326ns (86.933%)) Logic Levels: 0 Clock Path Skew: 0.161ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.420ns Source Clock Delay (SCD): 1.214ns Clock Pessimism Removal (CPR): 0.045ns Clock Net Delay (Source): 1.214ns (routing 0.373ns, distribution 0.841ns) Clock Net Delay (Destination): 1.420ns (routing 0.411ns, distribution 1.009ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.214 1.214 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/tx_wordclk SLICE_X71Y173 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X71Y173 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.263 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 0.326 1.589 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/gbt_txreset_s[0] SLICE_X75Y181 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[12]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.420 1.420 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk SLICE_X75Y181 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[12]/C clock pessimism -0.045 1.375 SLICE_X75Y181 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 1.380 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[12] ------------------------------------------------------------------- required time -1.380 arrival time 1.589 ------------------------------------------------------------------- slack 0.209 Slack (MET) : 0.209ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[14]/CLR (removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.375ns (logic 0.049ns (13.067%) route 0.326ns (86.933%)) Logic Levels: 0 Clock Path Skew: 0.161ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.420ns Source Clock Delay (SCD): 1.214ns Clock Pessimism Removal (CPR): 0.045ns Clock Net Delay (Source): 1.214ns (routing 0.373ns, distribution 0.841ns) Clock Net Delay (Destination): 1.420ns (routing 0.411ns, distribution 1.009ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.214 1.214 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/tx_wordclk SLICE_X71Y173 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X71Y173 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.263 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 0.326 1.589 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/gbt_txreset_s[0] SLICE_X75Y181 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[14]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.420 1.420 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk SLICE_X75Y181 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[14]/C clock pessimism -0.045 1.375 SLICE_X75Y181 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 1.380 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[14] ------------------------------------------------------------------- required time -1.380 arrival time 1.589 ------------------------------------------------------------------- slack 0.209 Slack (MET) : 0.214ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE (removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.296ns (logic 0.063ns (21.284%) route 0.233ns (78.716%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.470ns Source Clock Delay (SCD): 1.273ns Clock Pessimism Removal (CPR): 0.120ns Clock Net Delay (Source): 1.273ns (routing 0.373ns, distribution 0.900ns) Clock Net Delay (Destination): 1.470ns (routing 0.411ns, distribution 1.059ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.273 1.273 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X50Y540 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X50Y540 FDPE (Prop_EFF2_SLICEL_C_Q) 0.048 1.321 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/Q net (fo=1, routed) 0.031 1.352 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s SLICE_X50Y540 LUT3 (Prop_G6LUT_SLICEL_I1_O) 0.015 1.367 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s0/O net (fo=1, routed) 0.202 1.569 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s0__0 SLICE_X48Y541 FDPE f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.470 1.470 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X48Y541 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg/C clock pessimism -0.120 1.350 SLICE_X48Y541 FDPE (Remov_AFF_SLICEL_C_PRE) 0.005 1.355 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg ------------------------------------------------------------------- required time -1.355 arrival time 1.569 ------------------------------------------------------------------- slack 0.214 Slack (MET) : 0.214ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE (removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.254ns (logic 0.094ns (37.008%) route 0.160ns (62.992%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.602ns Source Clock Delay (SCD): 1.383ns Clock Pessimism Removal (CPR): 0.184ns Clock Net Delay (Source): 1.383ns (routing 0.373ns, distribution 1.010ns) Clock Net Delay (Destination): 1.602ns (routing 0.411ns, distribution 1.191ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.383 1.383 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/tx_wordclk SLICE_X32Y170 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X32Y170 FDPE (Prop_AFF2_SLICEL_C_Q) 0.049 1.432 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/Q net (fo=1, routed) 0.034 1.466 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRstMgtClk_sync_s SLICE_X32Y170 LUT3 (Prop_G6LUT_SLICEL_I0_O) 0.045 1.511 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0/O net (fo=1, routed) 0.126 1.637 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0__0 SLICE_X32Y170 FDPE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y118 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27439, routed) 1.602 1.602 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/tx_wordclk SLICE_X32Y170 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/C clock pessimism -0.184 1.418 SLICE_X32Y170 FDPE (Remov_EFF_SLICEL_C_PRE) 0.005 1.423 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg ------------------------------------------------------------------- required time -1.423 arrival time 1.637 ------------------------------------------------------------------- slack 0.214